mcip.h 2.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103
  1. /*
  2. * ARConnect IP Support (Multi core enabler: Cross core IPI, RTC ...)
  3. *
  4. * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #ifndef __SOC_ARC_MCIP_H
  11. #define __SOC_ARC_MCIP_H
  12. #include <soc/arc/aux.h>
  13. #define ARC_REG_MCIP_BCR 0x0d0
  14. #define ARC_REG_MCIP_CMD 0x600
  15. #define ARC_REG_MCIP_WDATA 0x601
  16. #define ARC_REG_MCIP_READBACK 0x602
  17. struct mcip_cmd {
  18. #ifdef CONFIG_CPU_BIG_ENDIAN
  19. unsigned int pad:8, param:16, cmd:8;
  20. #else
  21. unsigned int cmd:8, param:16, pad:8;
  22. #endif
  23. #define CMD_INTRPT_GENERATE_IRQ 0x01
  24. #define CMD_INTRPT_GENERATE_ACK 0x02
  25. #define CMD_INTRPT_READ_STATUS 0x03
  26. #define CMD_INTRPT_CHECK_SOURCE 0x04
  27. /* Semaphore Commands */
  28. #define CMD_SEMA_CLAIM_AND_READ 0x11
  29. #define CMD_SEMA_RELEASE 0x12
  30. #define CMD_DEBUG_SET_MASK 0x34
  31. #define CMD_DEBUG_SET_SELECT 0x36
  32. #define CMD_GFRC_READ_LO 0x42
  33. #define CMD_GFRC_READ_HI 0x43
  34. #define CMD_IDU_ENABLE 0x71
  35. #define CMD_IDU_DISABLE 0x72
  36. #define CMD_IDU_SET_MODE 0x74
  37. #define CMD_IDU_SET_DEST 0x76
  38. #define CMD_IDU_SET_MASK 0x7C
  39. #define IDU_M_TRIG_LEVEL 0x0
  40. #define IDU_M_TRIG_EDGE 0x1
  41. #define IDU_M_DISTRI_RR 0x0
  42. #define IDU_M_DISTRI_DEST 0x2
  43. };
  44. struct mcip_bcr {
  45. #ifdef CONFIG_CPU_BIG_ENDIAN
  46. unsigned int pad3:8,
  47. idu:1, llm:1, num_cores:6,
  48. iocoh:1, gfrc:1, dbg:1, pad2:1,
  49. msg:1, sem:1, ipi:1, pad:1,
  50. ver:8;
  51. #else
  52. unsigned int ver:8,
  53. pad:1, ipi:1, sem:1, msg:1,
  54. pad2:1, dbg:1, gfrc:1, iocoh:1,
  55. num_cores:6, llm:1, idu:1,
  56. pad3:8;
  57. #endif
  58. };
  59. /*
  60. * MCIP programming model
  61. *
  62. * - Simple commands write {cmd:8,param:16} to MCIP_CMD aux reg
  63. * (param could be irq, common_irq, core_id ...)
  64. * - More involved commands setup MCIP_WDATA with cmd specific data
  65. * before invoking the simple command
  66. */
  67. static inline void __mcip_cmd(unsigned int cmd, unsigned int param)
  68. {
  69. struct mcip_cmd buf;
  70. buf.pad = 0;
  71. buf.cmd = cmd;
  72. buf.param = param;
  73. WRITE_AUX(ARC_REG_MCIP_CMD, buf);
  74. }
  75. /*
  76. * Setup additional data for a cmd
  77. * Callers need to lock to ensure atomicity
  78. */
  79. static inline void __mcip_cmd_data(unsigned int cmd, unsigned int param,
  80. unsigned int data)
  81. {
  82. write_aux_reg(ARC_REG_MCIP_WDATA, data);
  83. __mcip_cmd(cmd, param);
  84. }
  85. #endif