mtu3_qmu.c 14 KB

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  1. /*
  2. * mtu3_qmu.c - Queue Management Unit driver for device controller
  3. *
  4. * Copyright (C) 2016 MediaTek Inc.
  5. *
  6. * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
  7. *
  8. * This software is licensed under the terms of the GNU General Public
  9. * License version 2, as published by the Free Software Foundation, and
  10. * may be copied, distributed, and modified under those terms.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. */
  18. /*
  19. * Queue Management Unit (QMU) is designed to unload SW effort
  20. * to serve DMA interrupts.
  21. * By preparing General Purpose Descriptor (GPD) and Buffer Descriptor (BD),
  22. * SW links data buffers and triggers QMU to send / receive data to
  23. * host / from device at a time.
  24. * And now only GPD is supported.
  25. *
  26. * For more detailed information, please refer to QMU Programming Guide
  27. */
  28. #include <linux/dmapool.h>
  29. #include <linux/iopoll.h>
  30. #include "mtu3.h"
  31. #define QMU_CHECKSUM_LEN 16
  32. #define GPD_FLAGS_HWO BIT(0)
  33. #define GPD_FLAGS_BDP BIT(1)
  34. #define GPD_FLAGS_BPS BIT(2)
  35. #define GPD_FLAGS_IOC BIT(7)
  36. #define GPD_EXT_FLAG_ZLP BIT(5)
  37. static struct qmu_gpd *gpd_dma_to_virt(struct mtu3_gpd_ring *ring,
  38. dma_addr_t dma_addr)
  39. {
  40. dma_addr_t dma_base = ring->dma;
  41. struct qmu_gpd *gpd_head = ring->start;
  42. u32 offset = (dma_addr - dma_base) / sizeof(*gpd_head);
  43. if (offset >= MAX_GPD_NUM)
  44. return NULL;
  45. return gpd_head + offset;
  46. }
  47. static dma_addr_t gpd_virt_to_dma(struct mtu3_gpd_ring *ring,
  48. struct qmu_gpd *gpd)
  49. {
  50. dma_addr_t dma_base = ring->dma;
  51. struct qmu_gpd *gpd_head = ring->start;
  52. u32 offset;
  53. offset = gpd - gpd_head;
  54. if (offset >= MAX_GPD_NUM)
  55. return 0;
  56. return dma_base + (offset * sizeof(*gpd));
  57. }
  58. static void gpd_ring_init(struct mtu3_gpd_ring *ring, struct qmu_gpd *gpd)
  59. {
  60. ring->start = gpd;
  61. ring->enqueue = gpd;
  62. ring->dequeue = gpd;
  63. ring->end = gpd + MAX_GPD_NUM - 1;
  64. }
  65. static void reset_gpd_list(struct mtu3_ep *mep)
  66. {
  67. struct mtu3_gpd_ring *ring = &mep->gpd_ring;
  68. struct qmu_gpd *gpd = ring->start;
  69. if (gpd) {
  70. gpd->flag &= ~GPD_FLAGS_HWO;
  71. gpd_ring_init(ring, gpd);
  72. }
  73. }
  74. int mtu3_gpd_ring_alloc(struct mtu3_ep *mep)
  75. {
  76. struct qmu_gpd *gpd;
  77. struct mtu3_gpd_ring *ring = &mep->gpd_ring;
  78. /* software own all gpds as default */
  79. gpd = dma_pool_zalloc(mep->mtu->qmu_gpd_pool, GFP_ATOMIC, &ring->dma);
  80. if (gpd == NULL)
  81. return -ENOMEM;
  82. gpd_ring_init(ring, gpd);
  83. return 0;
  84. }
  85. void mtu3_gpd_ring_free(struct mtu3_ep *mep)
  86. {
  87. struct mtu3_gpd_ring *ring = &mep->gpd_ring;
  88. dma_pool_free(mep->mtu->qmu_gpd_pool,
  89. ring->start, ring->dma);
  90. memset(ring, 0, sizeof(*ring));
  91. }
  92. /*
  93. * calculate check sum of a gpd or bd
  94. * add "noinline" and "mb" to prevent wrong calculation
  95. */
  96. static noinline u8 qmu_calc_checksum(u8 *data)
  97. {
  98. u8 chksum = 0;
  99. int i;
  100. data[1] = 0x0; /* set checksum to 0 */
  101. mb(); /* ensure the gpd/bd is really up-to-date */
  102. for (i = 0; i < QMU_CHECKSUM_LEN; i++)
  103. chksum += data[i];
  104. /* Default: HWO=1, @flag[bit0] */
  105. chksum += 1;
  106. return 0xFF - chksum;
  107. }
  108. void mtu3_qmu_resume(struct mtu3_ep *mep)
  109. {
  110. struct mtu3 *mtu = mep->mtu;
  111. void __iomem *mbase = mtu->mac_base;
  112. int epnum = mep->epnum;
  113. u32 offset;
  114. offset = mep->is_in ? USB_QMU_TQCSR(epnum) : USB_QMU_RQCSR(epnum);
  115. mtu3_writel(mbase, offset, QMU_Q_RESUME);
  116. if (!(mtu3_readl(mbase, offset) & QMU_Q_ACTIVE))
  117. mtu3_writel(mbase, offset, QMU_Q_RESUME);
  118. }
  119. static struct qmu_gpd *advance_enq_gpd(struct mtu3_gpd_ring *ring)
  120. {
  121. if (ring->enqueue < ring->end)
  122. ring->enqueue++;
  123. else
  124. ring->enqueue = ring->start;
  125. return ring->enqueue;
  126. }
  127. static struct qmu_gpd *advance_deq_gpd(struct mtu3_gpd_ring *ring)
  128. {
  129. if (ring->dequeue < ring->end)
  130. ring->dequeue++;
  131. else
  132. ring->dequeue = ring->start;
  133. return ring->dequeue;
  134. }
  135. /* check if a ring is emtpy */
  136. static int gpd_ring_empty(struct mtu3_gpd_ring *ring)
  137. {
  138. struct qmu_gpd *enq = ring->enqueue;
  139. struct qmu_gpd *next;
  140. if (ring->enqueue < ring->end)
  141. next = enq + 1;
  142. else
  143. next = ring->start;
  144. /* one gpd is reserved to simplify gpd preparation */
  145. return next == ring->dequeue;
  146. }
  147. int mtu3_prepare_transfer(struct mtu3_ep *mep)
  148. {
  149. return gpd_ring_empty(&mep->gpd_ring);
  150. }
  151. static int mtu3_prepare_tx_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq)
  152. {
  153. struct qmu_gpd *enq;
  154. struct mtu3_gpd_ring *ring = &mep->gpd_ring;
  155. struct qmu_gpd *gpd = ring->enqueue;
  156. struct usb_request *req = &mreq->request;
  157. /* set all fields to zero as default value */
  158. memset(gpd, 0, sizeof(*gpd));
  159. gpd->buffer = cpu_to_le32((u32)req->dma);
  160. gpd->buf_len = cpu_to_le16(req->length);
  161. gpd->flag |= GPD_FLAGS_IOC;
  162. /* get the next GPD */
  163. enq = advance_enq_gpd(ring);
  164. dev_dbg(mep->mtu->dev, "TX-EP%d queue gpd=%p, enq=%p\n",
  165. mep->epnum, gpd, enq);
  166. enq->flag &= ~GPD_FLAGS_HWO;
  167. gpd->next_gpd = cpu_to_le32((u32)gpd_virt_to_dma(ring, enq));
  168. if (req->zero)
  169. gpd->ext_flag |= GPD_EXT_FLAG_ZLP;
  170. gpd->chksum = qmu_calc_checksum((u8 *)gpd);
  171. gpd->flag |= GPD_FLAGS_HWO;
  172. mreq->gpd = gpd;
  173. return 0;
  174. }
  175. static int mtu3_prepare_rx_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq)
  176. {
  177. struct qmu_gpd *enq;
  178. struct mtu3_gpd_ring *ring = &mep->gpd_ring;
  179. struct qmu_gpd *gpd = ring->enqueue;
  180. struct usb_request *req = &mreq->request;
  181. /* set all fields to zero as default value */
  182. memset(gpd, 0, sizeof(*gpd));
  183. gpd->buffer = cpu_to_le32((u32)req->dma);
  184. gpd->data_buf_len = cpu_to_le16(req->length);
  185. gpd->flag |= GPD_FLAGS_IOC;
  186. /* get the next GPD */
  187. enq = advance_enq_gpd(ring);
  188. dev_dbg(mep->mtu->dev, "RX-EP%d queue gpd=%p, enq=%p\n",
  189. mep->epnum, gpd, enq);
  190. enq->flag &= ~GPD_FLAGS_HWO;
  191. gpd->next_gpd = cpu_to_le32((u32)gpd_virt_to_dma(ring, enq));
  192. gpd->chksum = qmu_calc_checksum((u8 *)gpd);
  193. gpd->flag |= GPD_FLAGS_HWO;
  194. mreq->gpd = gpd;
  195. return 0;
  196. }
  197. void mtu3_insert_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq)
  198. {
  199. if (mep->is_in)
  200. mtu3_prepare_tx_gpd(mep, mreq);
  201. else
  202. mtu3_prepare_rx_gpd(mep, mreq);
  203. }
  204. int mtu3_qmu_start(struct mtu3_ep *mep)
  205. {
  206. struct mtu3 *mtu = mep->mtu;
  207. void __iomem *mbase = mtu->mac_base;
  208. struct mtu3_gpd_ring *ring = &mep->gpd_ring;
  209. u8 epnum = mep->epnum;
  210. if (mep->is_in) {
  211. /* set QMU start address */
  212. mtu3_writel(mbase, USB_QMU_TQSAR(mep->epnum), ring->dma);
  213. mtu3_setbits(mbase, MU3D_EP_TXCR0(mep->epnum), TX_DMAREQEN);
  214. mtu3_setbits(mbase, U3D_QCR0, QMU_TX_CS_EN(epnum));
  215. /* send zero length packet according to ZLP flag in GPD */
  216. mtu3_setbits(mbase, U3D_QCR1, QMU_TX_ZLP(epnum));
  217. mtu3_writel(mbase, U3D_TQERRIESR0,
  218. QMU_TX_LEN_ERR(epnum) | QMU_TX_CS_ERR(epnum));
  219. if (mtu3_readl(mbase, USB_QMU_TQCSR(epnum)) & QMU_Q_ACTIVE) {
  220. dev_warn(mtu->dev, "Tx %d Active Now!\n", epnum);
  221. return 0;
  222. }
  223. mtu3_writel(mbase, USB_QMU_TQCSR(epnum), QMU_Q_START);
  224. } else {
  225. mtu3_writel(mbase, USB_QMU_RQSAR(mep->epnum), ring->dma);
  226. mtu3_setbits(mbase, MU3D_EP_RXCR0(mep->epnum), RX_DMAREQEN);
  227. mtu3_setbits(mbase, U3D_QCR0, QMU_RX_CS_EN(epnum));
  228. /* don't expect ZLP */
  229. mtu3_clrbits(mbase, U3D_QCR3, QMU_RX_ZLP(epnum));
  230. /* move to next GPD when receive ZLP */
  231. mtu3_setbits(mbase, U3D_QCR3, QMU_RX_COZ(epnum));
  232. mtu3_writel(mbase, U3D_RQERRIESR0,
  233. QMU_RX_LEN_ERR(epnum) | QMU_RX_CS_ERR(epnum));
  234. mtu3_writel(mbase, U3D_RQERRIESR1, QMU_RX_ZLP_ERR(epnum));
  235. if (mtu3_readl(mbase, USB_QMU_RQCSR(epnum)) & QMU_Q_ACTIVE) {
  236. dev_warn(mtu->dev, "Rx %d Active Now!\n", epnum);
  237. return 0;
  238. }
  239. mtu3_writel(mbase, USB_QMU_RQCSR(epnum), QMU_Q_START);
  240. }
  241. return 0;
  242. }
  243. /* may called in atomic context */
  244. void mtu3_qmu_stop(struct mtu3_ep *mep)
  245. {
  246. struct mtu3 *mtu = mep->mtu;
  247. void __iomem *mbase = mtu->mac_base;
  248. int epnum = mep->epnum;
  249. u32 value = 0;
  250. u32 qcsr;
  251. int ret;
  252. qcsr = mep->is_in ? USB_QMU_TQCSR(epnum) : USB_QMU_RQCSR(epnum);
  253. if (!(mtu3_readl(mbase, qcsr) & QMU_Q_ACTIVE)) {
  254. dev_dbg(mtu->dev, "%s's qmu is inactive now!\n", mep->name);
  255. return;
  256. }
  257. mtu3_writel(mbase, qcsr, QMU_Q_STOP);
  258. ret = readl_poll_timeout_atomic(mbase + qcsr, value,
  259. !(value & QMU_Q_ACTIVE), 1, 1000);
  260. if (ret) {
  261. dev_err(mtu->dev, "stop %s's qmu failed\n", mep->name);
  262. return;
  263. }
  264. dev_dbg(mtu->dev, "%s's qmu stop now!\n", mep->name);
  265. }
  266. void mtu3_qmu_flush(struct mtu3_ep *mep)
  267. {
  268. dev_dbg(mep->mtu->dev, "%s flush QMU %s\n", __func__,
  269. ((mep->is_in) ? "TX" : "RX"));
  270. /*Stop QMU */
  271. mtu3_qmu_stop(mep);
  272. reset_gpd_list(mep);
  273. }
  274. /*
  275. * QMU can't transfer zero length packet directly (a hardware limit
  276. * on old SoCs), so when needs to send ZLP, we intentionally trigger
  277. * a length error interrupt, and in the ISR sends a ZLP by BMU.
  278. */
  279. static void qmu_tx_zlp_error_handler(struct mtu3 *mtu, u8 epnum)
  280. {
  281. struct mtu3_ep *mep = mtu->in_eps + epnum;
  282. struct mtu3_gpd_ring *ring = &mep->gpd_ring;
  283. void __iomem *mbase = mtu->mac_base;
  284. struct qmu_gpd *gpd_current = NULL;
  285. dma_addr_t gpd_dma = mtu3_readl(mbase, USB_QMU_TQCPR(epnum));
  286. struct usb_request *req = NULL;
  287. struct mtu3_request *mreq;
  288. u32 txcsr = 0;
  289. int ret;
  290. mreq = next_request(mep);
  291. if (mreq && mreq->request.length == 0)
  292. req = &mreq->request;
  293. else
  294. return;
  295. gpd_current = gpd_dma_to_virt(ring, gpd_dma);
  296. if (le16_to_cpu(gpd_current->buf_len) != 0) {
  297. dev_err(mtu->dev, "TX EP%d buffer length error(!=0)\n", epnum);
  298. return;
  299. }
  300. dev_dbg(mtu->dev, "%s send ZLP for req=%p\n", __func__, mreq);
  301. mtu3_clrbits(mbase, MU3D_EP_TXCR0(mep->epnum), TX_DMAREQEN);
  302. ret = readl_poll_timeout_atomic(mbase + MU3D_EP_TXCR0(mep->epnum),
  303. txcsr, !(txcsr & TX_FIFOFULL), 1, 1000);
  304. if (ret) {
  305. dev_err(mtu->dev, "%s wait for fifo empty fail\n", __func__);
  306. return;
  307. }
  308. mtu3_setbits(mbase, MU3D_EP_TXCR0(mep->epnum), TX_TXPKTRDY);
  309. /* by pass the current GDP */
  310. gpd_current->flag |= GPD_FLAGS_BPS;
  311. gpd_current->chksum = qmu_calc_checksum((u8 *)gpd_current);
  312. gpd_current->flag |= GPD_FLAGS_HWO;
  313. /*enable DMAREQEN, switch back to QMU mode */
  314. mtu3_setbits(mbase, MU3D_EP_TXCR0(mep->epnum), TX_DMAREQEN);
  315. mtu3_qmu_resume(mep);
  316. }
  317. /*
  318. * NOTE: request list maybe is already empty as following case:
  319. * queue_tx --> qmu_interrupt(clear interrupt pending, schedule tasklet)-->
  320. * queue_tx --> process_tasklet(meanwhile, the second one is transferred,
  321. * tasklet process both of them)-->qmu_interrupt for second one.
  322. * To avoid upper case, put qmu_done_tx in ISR directly to process it.
  323. */
  324. static void qmu_done_tx(struct mtu3 *mtu, u8 epnum)
  325. {
  326. struct mtu3_ep *mep = mtu->in_eps + epnum;
  327. struct mtu3_gpd_ring *ring = &mep->gpd_ring;
  328. void __iomem *mbase = mtu->mac_base;
  329. struct qmu_gpd *gpd = ring->dequeue;
  330. struct qmu_gpd *gpd_current = NULL;
  331. dma_addr_t gpd_dma = mtu3_readl(mbase, USB_QMU_TQCPR(epnum));
  332. struct usb_request *request = NULL;
  333. struct mtu3_request *mreq;
  334. /*transfer phy address got from QMU register to virtual address */
  335. gpd_current = gpd_dma_to_virt(ring, gpd_dma);
  336. dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n",
  337. __func__, epnum, gpd, gpd_current, ring->enqueue);
  338. while (gpd != gpd_current && !(gpd->flag & GPD_FLAGS_HWO)) {
  339. mreq = next_request(mep);
  340. if (mreq == NULL || mreq->gpd != gpd) {
  341. dev_err(mtu->dev, "no correct TX req is found\n");
  342. break;
  343. }
  344. request = &mreq->request;
  345. request->actual = le16_to_cpu(gpd->buf_len);
  346. mtu3_req_complete(mep, request, 0);
  347. gpd = advance_deq_gpd(ring);
  348. }
  349. dev_dbg(mtu->dev, "%s EP%d, deq=%p, enq=%p, complete\n",
  350. __func__, epnum, ring->dequeue, ring->enqueue);
  351. }
  352. static void qmu_done_rx(struct mtu3 *mtu, u8 epnum)
  353. {
  354. struct mtu3_ep *mep = mtu->out_eps + epnum;
  355. struct mtu3_gpd_ring *ring = &mep->gpd_ring;
  356. void __iomem *mbase = mtu->mac_base;
  357. struct qmu_gpd *gpd = ring->dequeue;
  358. struct qmu_gpd *gpd_current = NULL;
  359. dma_addr_t gpd_dma = mtu3_readl(mbase, USB_QMU_RQCPR(epnum));
  360. struct usb_request *req = NULL;
  361. struct mtu3_request *mreq;
  362. gpd_current = gpd_dma_to_virt(ring, gpd_dma);
  363. dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n",
  364. __func__, epnum, gpd, gpd_current, ring->enqueue);
  365. while (gpd != gpd_current && !(gpd->flag & GPD_FLAGS_HWO)) {
  366. mreq = next_request(mep);
  367. if (mreq == NULL || mreq->gpd != gpd) {
  368. dev_err(mtu->dev, "no correct RX req is found\n");
  369. break;
  370. }
  371. req = &mreq->request;
  372. req->actual = le16_to_cpu(gpd->buf_len);
  373. mtu3_req_complete(mep, req, 0);
  374. gpd = advance_deq_gpd(ring);
  375. }
  376. dev_dbg(mtu->dev, "%s EP%d, deq=%p, enq=%p, complete\n",
  377. __func__, epnum, ring->dequeue, ring->enqueue);
  378. }
  379. static void qmu_done_isr(struct mtu3 *mtu, u32 done_status)
  380. {
  381. int i;
  382. for (i = 1; i < mtu->num_eps; i++) {
  383. if (done_status & QMU_RX_DONE_INT(i))
  384. qmu_done_rx(mtu, i);
  385. if (done_status & QMU_TX_DONE_INT(i))
  386. qmu_done_tx(mtu, i);
  387. }
  388. }
  389. static void qmu_exception_isr(struct mtu3 *mtu, u32 qmu_status)
  390. {
  391. void __iomem *mbase = mtu->mac_base;
  392. u32 errval;
  393. int i;
  394. if ((qmu_status & RXQ_CSERR_INT) || (qmu_status & RXQ_LENERR_INT)) {
  395. errval = mtu3_readl(mbase, U3D_RQERRIR0);
  396. for (i = 1; i < mtu->num_eps; i++) {
  397. if (errval & QMU_RX_CS_ERR(i))
  398. dev_err(mtu->dev, "Rx %d CS error!\n", i);
  399. if (errval & QMU_RX_LEN_ERR(i))
  400. dev_err(mtu->dev, "RX %d Length error\n", i);
  401. }
  402. mtu3_writel(mbase, U3D_RQERRIR0, errval);
  403. }
  404. if (qmu_status & RXQ_ZLPERR_INT) {
  405. errval = mtu3_readl(mbase, U3D_RQERRIR1);
  406. for (i = 1; i < mtu->num_eps; i++) {
  407. if (errval & QMU_RX_ZLP_ERR(i))
  408. dev_dbg(mtu->dev, "RX EP%d Recv ZLP\n", i);
  409. }
  410. mtu3_writel(mbase, U3D_RQERRIR1, errval);
  411. }
  412. if ((qmu_status & TXQ_CSERR_INT) || (qmu_status & TXQ_LENERR_INT)) {
  413. errval = mtu3_readl(mbase, U3D_TQERRIR0);
  414. for (i = 1; i < mtu->num_eps; i++) {
  415. if (errval & QMU_TX_CS_ERR(i))
  416. dev_err(mtu->dev, "Tx %d checksum error!\n", i);
  417. if (errval & QMU_TX_LEN_ERR(i))
  418. qmu_tx_zlp_error_handler(mtu, i);
  419. }
  420. mtu3_writel(mbase, U3D_TQERRIR0, errval);
  421. }
  422. }
  423. irqreturn_t mtu3_qmu_isr(struct mtu3 *mtu)
  424. {
  425. void __iomem *mbase = mtu->mac_base;
  426. u32 qmu_status;
  427. u32 qmu_done_status;
  428. /* U3D_QISAR1 is read update */
  429. qmu_status = mtu3_readl(mbase, U3D_QISAR1);
  430. qmu_status &= mtu3_readl(mbase, U3D_QIER1);
  431. qmu_done_status = mtu3_readl(mbase, U3D_QISAR0);
  432. qmu_done_status &= mtu3_readl(mbase, U3D_QIER0);
  433. mtu3_writel(mbase, U3D_QISAR0, qmu_done_status); /* W1C */
  434. dev_dbg(mtu->dev, "=== QMUdone[tx=%x, rx=%x] QMUexp[%x] ===\n",
  435. (qmu_done_status & 0xFFFF), qmu_done_status >> 16,
  436. qmu_status);
  437. if (qmu_done_status)
  438. qmu_done_isr(mtu, qmu_done_status);
  439. if (qmu_status)
  440. qmu_exception_isr(mtu, qmu_status);
  441. return IRQ_HANDLED;
  442. }
  443. int mtu3_qmu_init(struct mtu3 *mtu)
  444. {
  445. compiletime_assert(QMU_GPD_SIZE == 16, "QMU_GPD size SHOULD be 16B");
  446. mtu->qmu_gpd_pool = dma_pool_create("QMU_GPD", mtu->dev,
  447. QMU_GPD_RING_SIZE, QMU_GPD_SIZE, 0);
  448. if (!mtu->qmu_gpd_pool)
  449. return -ENOMEM;
  450. return 0;
  451. }
  452. void mtu3_qmu_exit(struct mtu3 *mtu)
  453. {
  454. dma_pool_destroy(mtu->qmu_gpd_pool);
  455. }