mtu3_plat.c 11 KB

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  1. /*
  2. * Copyright (C) 2016 MediaTek Inc.
  3. *
  4. * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
  5. *
  6. * This software is licensed under the terms of the GNU General Public
  7. * License version 2, as published by the Free Software Foundation, and
  8. * may be copied, distributed, and modified under those terms.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. */
  16. #include <linux/clk.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/iopoll.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/of_address.h>
  22. #include <linux/of_irq.h>
  23. #include <linux/pinctrl/consumer.h>
  24. #include <linux/platform_device.h>
  25. #include "mtu3.h"
  26. #include "mtu3_dr.h"
  27. /* u2-port0 should be powered on and enabled; */
  28. int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks)
  29. {
  30. void __iomem *ibase = ssusb->ippc_base;
  31. u32 value, check_val;
  32. int ret;
  33. check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE |
  34. SSUSB_REF_RST_B_STS;
  35. ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
  36. (check_val == (value & check_val)), 100, 20000);
  37. if (ret) {
  38. dev_err(ssusb->dev, "clks of sts1 are not stable!\n");
  39. return ret;
  40. }
  41. ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value,
  42. (value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000);
  43. if (ret) {
  44. dev_err(ssusb->dev, "mac2 clock is not stable\n");
  45. return ret;
  46. }
  47. return 0;
  48. }
  49. static int ssusb_phy_init(struct ssusb_mtk *ssusb)
  50. {
  51. int i;
  52. int ret;
  53. for (i = 0; i < ssusb->num_phys; i++) {
  54. ret = phy_init(ssusb->phys[i]);
  55. if (ret)
  56. goto exit_phy;
  57. }
  58. return 0;
  59. exit_phy:
  60. for (; i > 0; i--)
  61. phy_exit(ssusb->phys[i - 1]);
  62. return ret;
  63. }
  64. static int ssusb_phy_exit(struct ssusb_mtk *ssusb)
  65. {
  66. int i;
  67. for (i = 0; i < ssusb->num_phys; i++)
  68. phy_exit(ssusb->phys[i]);
  69. return 0;
  70. }
  71. static int ssusb_phy_power_on(struct ssusb_mtk *ssusb)
  72. {
  73. int i;
  74. int ret;
  75. for (i = 0; i < ssusb->num_phys; i++) {
  76. ret = phy_power_on(ssusb->phys[i]);
  77. if (ret)
  78. goto power_off_phy;
  79. }
  80. return 0;
  81. power_off_phy:
  82. for (; i > 0; i--)
  83. phy_power_off(ssusb->phys[i - 1]);
  84. return ret;
  85. }
  86. static void ssusb_phy_power_off(struct ssusb_mtk *ssusb)
  87. {
  88. unsigned int i;
  89. for (i = 0; i < ssusb->num_phys; i++)
  90. phy_power_off(ssusb->phys[i]);
  91. }
  92. static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
  93. {
  94. int ret = 0;
  95. ret = regulator_enable(ssusb->vusb33);
  96. if (ret) {
  97. dev_err(ssusb->dev, "failed to enable vusb33\n");
  98. goto vusb33_err;
  99. }
  100. ret = clk_prepare_enable(ssusb->sys_clk);
  101. if (ret) {
  102. dev_err(ssusb->dev, "failed to enable sys_clk\n");
  103. goto clk_err;
  104. }
  105. ret = ssusb_phy_init(ssusb);
  106. if (ret) {
  107. dev_err(ssusb->dev, "failed to init phy\n");
  108. goto phy_init_err;
  109. }
  110. ret = ssusb_phy_power_on(ssusb);
  111. if (ret) {
  112. dev_err(ssusb->dev, "failed to power on phy\n");
  113. goto phy_err;
  114. }
  115. return 0;
  116. phy_err:
  117. ssusb_phy_exit(ssusb);
  118. phy_init_err:
  119. clk_disable_unprepare(ssusb->sys_clk);
  120. clk_err:
  121. regulator_disable(ssusb->vusb33);
  122. vusb33_err:
  123. return ret;
  124. }
  125. static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
  126. {
  127. clk_disable_unprepare(ssusb->sys_clk);
  128. regulator_disable(ssusb->vusb33);
  129. ssusb_phy_power_off(ssusb);
  130. ssusb_phy_exit(ssusb);
  131. }
  132. static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb)
  133. {
  134. /* reset whole ip (xhci & u3d) */
  135. mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
  136. udelay(1);
  137. mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
  138. }
  139. static int get_iddig_pinctrl(struct ssusb_mtk *ssusb)
  140. {
  141. struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
  142. otg_sx->id_pinctrl = devm_pinctrl_get(ssusb->dev);
  143. if (IS_ERR(otg_sx->id_pinctrl)) {
  144. dev_err(ssusb->dev, "Cannot find id pinctrl!\n");
  145. return PTR_ERR(otg_sx->id_pinctrl);
  146. }
  147. otg_sx->id_float =
  148. pinctrl_lookup_state(otg_sx->id_pinctrl, "id_float");
  149. if (IS_ERR(otg_sx->id_float)) {
  150. dev_err(ssusb->dev, "Cannot find pinctrl id_float!\n");
  151. return PTR_ERR(otg_sx->id_float);
  152. }
  153. otg_sx->id_ground =
  154. pinctrl_lookup_state(otg_sx->id_pinctrl, "id_ground");
  155. if (IS_ERR(otg_sx->id_ground)) {
  156. dev_err(ssusb->dev, "Cannot find pinctrl id_ground!\n");
  157. return PTR_ERR(otg_sx->id_ground);
  158. }
  159. return 0;
  160. }
  161. static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
  162. {
  163. struct device_node *node = pdev->dev.of_node;
  164. struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
  165. struct device *dev = &pdev->dev;
  166. struct regulator *vbus;
  167. struct resource *res;
  168. int i;
  169. int ret;
  170. ssusb->num_phys = of_count_phandle_with_args(node,
  171. "phys", "#phy-cells");
  172. if (ssusb->num_phys > 0) {
  173. ssusb->phys = devm_kcalloc(dev, ssusb->num_phys,
  174. sizeof(*ssusb->phys), GFP_KERNEL);
  175. if (!ssusb->phys)
  176. return -ENOMEM;
  177. } else {
  178. ssusb->num_phys = 0;
  179. }
  180. for (i = 0; i < ssusb->num_phys; i++) {
  181. ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i);
  182. if (IS_ERR(ssusb->phys[i])) {
  183. dev_err(dev, "failed to get phy-%d\n", i);
  184. return PTR_ERR(ssusb->phys[i]);
  185. }
  186. }
  187. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
  188. ssusb->ippc_base = devm_ioremap_resource(dev, res);
  189. if (IS_ERR(ssusb->ippc_base)) {
  190. dev_err(dev, "failed to map memory for ippc\n");
  191. return PTR_ERR(ssusb->ippc_base);
  192. }
  193. ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33");
  194. if (IS_ERR(ssusb->vusb33)) {
  195. dev_err(dev, "failed to get vusb33\n");
  196. return PTR_ERR(ssusb->vusb33);
  197. }
  198. ssusb->sys_clk = devm_clk_get(dev, "sys_ck");
  199. if (IS_ERR(ssusb->sys_clk)) {
  200. dev_err(dev, "failed to get sys clock\n");
  201. return PTR_ERR(ssusb->sys_clk);
  202. }
  203. ssusb->dr_mode = usb_get_dr_mode(dev);
  204. if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) {
  205. dev_err(dev, "dr_mode is error\n");
  206. return -EINVAL;
  207. }
  208. if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
  209. return 0;
  210. /* if host role is supported */
  211. ret = ssusb_wakeup_of_property_parse(ssusb, node);
  212. if (ret)
  213. return ret;
  214. if (ssusb->dr_mode != USB_DR_MODE_OTG)
  215. return 0;
  216. /* if dual-role mode is supported */
  217. vbus = devm_regulator_get(&pdev->dev, "vbus");
  218. if (IS_ERR(vbus)) {
  219. dev_err(dev, "failed to get vbus\n");
  220. return PTR_ERR(vbus);
  221. }
  222. otg_sx->vbus = vbus;
  223. otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd");
  224. otg_sx->manual_drd_enabled =
  225. of_property_read_bool(node, "enable-manual-drd");
  226. if (of_property_read_bool(node, "extcon")) {
  227. otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0);
  228. if (IS_ERR(otg_sx->edev)) {
  229. dev_err(ssusb->dev, "couldn't get extcon device\n");
  230. return -EPROBE_DEFER;
  231. }
  232. if (otg_sx->manual_drd_enabled) {
  233. ret = get_iddig_pinctrl(ssusb);
  234. if (ret)
  235. return ret;
  236. }
  237. }
  238. dev_info(dev, "dr_mode: %d, is_u3_dr: %d\n",
  239. ssusb->dr_mode, otg_sx->is_u3_drd);
  240. return 0;
  241. }
  242. static int mtu3_probe(struct platform_device *pdev)
  243. {
  244. struct device_node *node = pdev->dev.of_node;
  245. struct device *dev = &pdev->dev;
  246. struct ssusb_mtk *ssusb;
  247. int ret = -ENOMEM;
  248. /* all elements are set to ZERO as default value */
  249. ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL);
  250. if (!ssusb)
  251. return -ENOMEM;
  252. ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
  253. if (ret) {
  254. dev_err(dev, "No suitable DMA config available\n");
  255. return -ENOTSUPP;
  256. }
  257. platform_set_drvdata(pdev, ssusb);
  258. ssusb->dev = dev;
  259. ret = get_ssusb_rscs(pdev, ssusb);
  260. if (ret)
  261. return ret;
  262. /* enable power domain */
  263. pm_runtime_enable(dev);
  264. pm_runtime_get_sync(dev);
  265. device_enable_async_suspend(dev);
  266. ret = ssusb_rscs_init(ssusb);
  267. if (ret)
  268. goto comm_init_err;
  269. ssusb_ip_sw_reset(ssusb);
  270. if (IS_ENABLED(CONFIG_USB_MTU3_HOST))
  271. ssusb->dr_mode = USB_DR_MODE_HOST;
  272. else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET))
  273. ssusb->dr_mode = USB_DR_MODE_PERIPHERAL;
  274. /* default as host */
  275. ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL);
  276. switch (ssusb->dr_mode) {
  277. case USB_DR_MODE_PERIPHERAL:
  278. ret = ssusb_gadget_init(ssusb);
  279. if (ret) {
  280. dev_err(dev, "failed to initialize gadget\n");
  281. goto comm_exit;
  282. }
  283. break;
  284. case USB_DR_MODE_HOST:
  285. ret = ssusb_host_init(ssusb, node);
  286. if (ret) {
  287. dev_err(dev, "failed to initialize host\n");
  288. goto comm_exit;
  289. }
  290. break;
  291. case USB_DR_MODE_OTG:
  292. ret = ssusb_gadget_init(ssusb);
  293. if (ret) {
  294. dev_err(dev, "failed to initialize gadget\n");
  295. goto comm_exit;
  296. }
  297. ret = ssusb_host_init(ssusb, node);
  298. if (ret) {
  299. dev_err(dev, "failed to initialize host\n");
  300. goto gadget_exit;
  301. }
  302. ssusb_otg_switch_init(ssusb);
  303. break;
  304. default:
  305. dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode);
  306. ret = -EINVAL;
  307. goto comm_exit;
  308. }
  309. return 0;
  310. gadget_exit:
  311. ssusb_gadget_exit(ssusb);
  312. comm_exit:
  313. ssusb_rscs_exit(ssusb);
  314. comm_init_err:
  315. pm_runtime_put_sync(dev);
  316. pm_runtime_disable(dev);
  317. return ret;
  318. }
  319. static int mtu3_remove(struct platform_device *pdev)
  320. {
  321. struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
  322. switch (ssusb->dr_mode) {
  323. case USB_DR_MODE_PERIPHERAL:
  324. ssusb_gadget_exit(ssusb);
  325. break;
  326. case USB_DR_MODE_HOST:
  327. ssusb_host_exit(ssusb);
  328. break;
  329. case USB_DR_MODE_OTG:
  330. ssusb_otg_switch_exit(ssusb);
  331. ssusb_gadget_exit(ssusb);
  332. ssusb_host_exit(ssusb);
  333. break;
  334. default:
  335. return -EINVAL;
  336. }
  337. ssusb_rscs_exit(ssusb);
  338. pm_runtime_put_sync(&pdev->dev);
  339. pm_runtime_disable(&pdev->dev);
  340. return 0;
  341. }
  342. /*
  343. * when support dual-role mode, we reject suspend when
  344. * it works as device mode;
  345. */
  346. static int __maybe_unused mtu3_suspend(struct device *dev)
  347. {
  348. struct platform_device *pdev = to_platform_device(dev);
  349. struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
  350. dev_dbg(dev, "%s\n", __func__);
  351. /* REVISIT: disconnect it for only device mode? */
  352. if (!ssusb->is_host)
  353. return 0;
  354. ssusb_host_disable(ssusb, true);
  355. ssusb_phy_power_off(ssusb);
  356. clk_disable_unprepare(ssusb->sys_clk);
  357. ssusb_wakeup_enable(ssusb);
  358. return 0;
  359. }
  360. static int __maybe_unused mtu3_resume(struct device *dev)
  361. {
  362. struct platform_device *pdev = to_platform_device(dev);
  363. struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
  364. dev_dbg(dev, "%s\n", __func__);
  365. if (!ssusb->is_host)
  366. return 0;
  367. ssusb_wakeup_disable(ssusb);
  368. clk_prepare_enable(ssusb->sys_clk);
  369. ssusb_phy_power_on(ssusb);
  370. ssusb_host_enable(ssusb);
  371. return 0;
  372. }
  373. static const struct dev_pm_ops mtu3_pm_ops = {
  374. SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume)
  375. };
  376. #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL)
  377. #ifdef CONFIG_OF
  378. static const struct of_device_id mtu3_of_match[] = {
  379. {.compatible = "mediatek,mt8173-mtu3",},
  380. {},
  381. };
  382. MODULE_DEVICE_TABLE(of, mtu3_of_match);
  383. #endif
  384. static struct platform_driver mtu3_driver = {
  385. .probe = mtu3_probe,
  386. .remove = mtu3_remove,
  387. .driver = {
  388. .name = MTU3_DRIVER_NAME,
  389. .pm = DEV_PM_OPS,
  390. .of_match_table = of_match_ptr(mtu3_of_match),
  391. },
  392. };
  393. module_platform_driver(mtu3_driver);
  394. MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
  395. MODULE_LICENSE("GPL v2");
  396. MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver");