mtu3_host.c 7.4 KB

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  1. /*
  2. * mtu3_dr.c - dual role switch and host glue layer
  3. *
  4. * Copyright (C) 2016 MediaTek Inc.
  5. *
  6. * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
  7. *
  8. * This software is licensed under the terms of the GNU General Public
  9. * License version 2, as published by the Free Software Foundation, and
  10. * may be copied, distributed, and modified under those terms.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. */
  18. #include <linux/clk.h>
  19. #include <linux/iopoll.h>
  20. #include <linux/irq.h>
  21. #include <linux/kernel.h>
  22. #include <linux/mfd/syscon.h>
  23. #include <linux/of_device.h>
  24. #include <linux/regmap.h>
  25. #include "mtu3.h"
  26. #include "mtu3_dr.h"
  27. #define PERI_WK_CTRL1 0x404
  28. #define UWK_CTL1_IS_C(x) (((x) & 0xf) << 26)
  29. #define UWK_CTL1_IS_E BIT(25)
  30. #define UWK_CTL1_IDDIG_C(x) (((x) & 0xf) << 11) /* cycle debounce */
  31. #define UWK_CTL1_IDDIG_E BIT(10) /* enable debounce */
  32. #define UWK_CTL1_IDDIG_P BIT(9) /* polarity */
  33. #define UWK_CTL1_IS_P BIT(6) /* polarity for ip sleep */
  34. /*
  35. * ip-sleep wakeup mode:
  36. * all clocks can be turn off, but power domain should be kept on
  37. */
  38. static void ssusb_wakeup_ip_sleep_en(struct ssusb_mtk *ssusb)
  39. {
  40. u32 tmp;
  41. struct regmap *pericfg = ssusb->pericfg;
  42. regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
  43. tmp &= ~UWK_CTL1_IS_P;
  44. tmp &= ~(UWK_CTL1_IS_C(0xf));
  45. tmp |= UWK_CTL1_IS_C(0x8);
  46. regmap_write(pericfg, PERI_WK_CTRL1, tmp);
  47. regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_IS_E);
  48. regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
  49. dev_dbg(ssusb->dev, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n",
  50. __func__, tmp);
  51. }
  52. static void ssusb_wakeup_ip_sleep_dis(struct ssusb_mtk *ssusb)
  53. {
  54. u32 tmp;
  55. regmap_read(ssusb->pericfg, PERI_WK_CTRL1, &tmp);
  56. tmp &= ~UWK_CTL1_IS_E;
  57. regmap_write(ssusb->pericfg, PERI_WK_CTRL1, tmp);
  58. }
  59. int ssusb_wakeup_of_property_parse(struct ssusb_mtk *ssusb,
  60. struct device_node *dn)
  61. {
  62. struct device *dev = ssusb->dev;
  63. /*
  64. * Wakeup function is optional, so it is not an error if this property
  65. * does not exist, and in such case, no need to get relative
  66. * properties anymore.
  67. */
  68. ssusb->wakeup_en = of_property_read_bool(dn, "mediatek,enable-wakeup");
  69. if (!ssusb->wakeup_en)
  70. return 0;
  71. ssusb->wk_deb_p0 = devm_clk_get(dev, "wakeup_deb_p0");
  72. if (IS_ERR(ssusb->wk_deb_p0)) {
  73. dev_err(dev, "fail to get wakeup_deb_p0\n");
  74. return PTR_ERR(ssusb->wk_deb_p0);
  75. }
  76. if (of_property_read_bool(dn, "wakeup_deb_p1")) {
  77. ssusb->wk_deb_p1 = devm_clk_get(dev, "wakeup_deb_p1");
  78. if (IS_ERR(ssusb->wk_deb_p1)) {
  79. dev_err(dev, "fail to get wakeup_deb_p1\n");
  80. return PTR_ERR(ssusb->wk_deb_p1);
  81. }
  82. }
  83. ssusb->pericfg = syscon_regmap_lookup_by_phandle(dn,
  84. "mediatek,syscon-wakeup");
  85. if (IS_ERR(ssusb->pericfg)) {
  86. dev_err(dev, "fail to get pericfg regs\n");
  87. return PTR_ERR(ssusb->pericfg);
  88. }
  89. return 0;
  90. }
  91. static int ssusb_wakeup_clks_enable(struct ssusb_mtk *ssusb)
  92. {
  93. int ret;
  94. ret = clk_prepare_enable(ssusb->wk_deb_p0);
  95. if (ret) {
  96. dev_err(ssusb->dev, "failed to enable wk_deb_p0\n");
  97. goto usb_p0_err;
  98. }
  99. ret = clk_prepare_enable(ssusb->wk_deb_p1);
  100. if (ret) {
  101. dev_err(ssusb->dev, "failed to enable wk_deb_p1\n");
  102. goto usb_p1_err;
  103. }
  104. return 0;
  105. usb_p1_err:
  106. clk_disable_unprepare(ssusb->wk_deb_p0);
  107. usb_p0_err:
  108. return -EINVAL;
  109. }
  110. static void ssusb_wakeup_clks_disable(struct ssusb_mtk *ssusb)
  111. {
  112. clk_disable_unprepare(ssusb->wk_deb_p1);
  113. clk_disable_unprepare(ssusb->wk_deb_p0);
  114. }
  115. static void host_ports_num_get(struct ssusb_mtk *ssusb)
  116. {
  117. u32 xhci_cap;
  118. xhci_cap = mtu3_readl(ssusb->ippc_base, U3D_SSUSB_IP_XHCI_CAP);
  119. ssusb->u2_ports = SSUSB_IP_XHCI_U2_PORT_NUM(xhci_cap);
  120. ssusb->u3_ports = SSUSB_IP_XHCI_U3_PORT_NUM(xhci_cap);
  121. dev_dbg(ssusb->dev, "host - u2_ports:%d, u3_ports:%d\n",
  122. ssusb->u2_ports, ssusb->u3_ports);
  123. }
  124. /* only configure ports will be used later */
  125. int ssusb_host_enable(struct ssusb_mtk *ssusb)
  126. {
  127. void __iomem *ibase = ssusb->ippc_base;
  128. int num_u3p = ssusb->u3_ports;
  129. int num_u2p = ssusb->u2_ports;
  130. u32 check_clk;
  131. u32 value;
  132. int i;
  133. /* power on host ip */
  134. mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
  135. /* power on and enable all u3 ports */
  136. for (i = 0; i < num_u3p; i++) {
  137. value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
  138. value &= ~(SSUSB_U3_PORT_PDN | SSUSB_U3_PORT_DIS);
  139. value |= SSUSB_U3_PORT_HOST_SEL;
  140. mtu3_writel(ibase, SSUSB_U3_CTRL(i), value);
  141. }
  142. /* power on and enable all u2 ports */
  143. for (i = 0; i < num_u2p; i++) {
  144. value = mtu3_readl(ibase, SSUSB_U2_CTRL(i));
  145. value &= ~(SSUSB_U2_PORT_PDN | SSUSB_U2_PORT_DIS);
  146. value |= SSUSB_U2_PORT_HOST_SEL;
  147. mtu3_writel(ibase, SSUSB_U2_CTRL(i), value);
  148. }
  149. check_clk = SSUSB_XHCI_RST_B_STS;
  150. if (num_u3p)
  151. check_clk = SSUSB_U3_MAC_RST_B_STS;
  152. return ssusb_check_clocks(ssusb, check_clk);
  153. }
  154. int ssusb_host_disable(struct ssusb_mtk *ssusb, bool suspend)
  155. {
  156. void __iomem *ibase = ssusb->ippc_base;
  157. int num_u3p = ssusb->u3_ports;
  158. int num_u2p = ssusb->u2_ports;
  159. u32 value;
  160. int ret;
  161. int i;
  162. /* power down and disable all u3 ports */
  163. for (i = 0; i < num_u3p; i++) {
  164. value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
  165. value |= SSUSB_U3_PORT_PDN;
  166. value |= suspend ? 0 : SSUSB_U3_PORT_DIS;
  167. mtu3_writel(ibase, SSUSB_U3_CTRL(i), value);
  168. }
  169. /* power down and disable all u2 ports */
  170. for (i = 0; i < num_u2p; i++) {
  171. value = mtu3_readl(ibase, SSUSB_U2_CTRL(i));
  172. value |= SSUSB_U2_PORT_PDN;
  173. value |= suspend ? 0 : SSUSB_U2_PORT_DIS;
  174. mtu3_writel(ibase, SSUSB_U2_CTRL(i), value);
  175. }
  176. /* power down host ip */
  177. mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
  178. if (!suspend)
  179. return 0;
  180. /* wait for host ip to sleep */
  181. ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
  182. (value & SSUSB_IP_SLEEP_STS), 100, 100000);
  183. if (ret)
  184. dev_err(ssusb->dev, "ip sleep failed!!!\n");
  185. return ret;
  186. }
  187. static void ssusb_host_setup(struct ssusb_mtk *ssusb)
  188. {
  189. host_ports_num_get(ssusb);
  190. /*
  191. * power on host and power on/enable all ports
  192. * if support OTG, gadget driver will switch port0 to device mode
  193. */
  194. ssusb_host_enable(ssusb);
  195. /* if port0 supports dual-role, works as host mode by default */
  196. ssusb_set_vbus(&ssusb->otg_switch, 1);
  197. }
  198. static void ssusb_host_cleanup(struct ssusb_mtk *ssusb)
  199. {
  200. if (ssusb->is_host)
  201. ssusb_set_vbus(&ssusb->otg_switch, 0);
  202. ssusb_host_disable(ssusb, false);
  203. }
  204. /*
  205. * If host supports multiple ports, the VBUSes(5V) of ports except port0
  206. * which supports OTG are better to be enabled by default in DTS.
  207. * Because the host driver will keep link with devices attached when system
  208. * enters suspend mode, so no need to control VBUSes after initialization.
  209. */
  210. int ssusb_host_init(struct ssusb_mtk *ssusb, struct device_node *parent_dn)
  211. {
  212. struct device *parent_dev = ssusb->dev;
  213. int ret;
  214. ssusb_host_setup(ssusb);
  215. ret = of_platform_populate(parent_dn, NULL, NULL, parent_dev);
  216. if (ret) {
  217. dev_dbg(parent_dev, "failed to create child devices at %s\n",
  218. parent_dn->full_name);
  219. return ret;
  220. }
  221. dev_info(parent_dev, "xHCI platform device register success...\n");
  222. return 0;
  223. }
  224. void ssusb_host_exit(struct ssusb_mtk *ssusb)
  225. {
  226. of_platform_depopulate(ssusb->dev);
  227. ssusb_host_cleanup(ssusb);
  228. }
  229. int ssusb_wakeup_enable(struct ssusb_mtk *ssusb)
  230. {
  231. int ret = 0;
  232. if (ssusb->wakeup_en) {
  233. ret = ssusb_wakeup_clks_enable(ssusb);
  234. ssusb_wakeup_ip_sleep_en(ssusb);
  235. }
  236. return ret;
  237. }
  238. void ssusb_wakeup_disable(struct ssusb_mtk *ssusb)
  239. {
  240. if (ssusb->wakeup_en) {
  241. ssusb_wakeup_ip_sleep_dis(ssusb);
  242. ssusb_wakeup_clks_disable(ssusb);
  243. }
  244. }