atmel_usba_udc.c 54 KB

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  1. /*
  2. * Driver for the Atmel USBA high speed USB device controller
  3. *
  4. * Copyright (C) 2005-2007 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/clk/at91_pmc.h>
  12. #include <linux/module.h>
  13. #include <linux/init.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/slab.h>
  17. #include <linux/device.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/list.h>
  20. #include <linux/mfd/syscon.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/regmap.h>
  23. #include <linux/usb/ch9.h>
  24. #include <linux/usb/gadget.h>
  25. #include <linux/usb/atmel_usba_udc.h>
  26. #include <linux/delay.h>
  27. #include <linux/of.h>
  28. #include <linux/of_gpio.h>
  29. #include "atmel_usba_udc.h"
  30. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  31. #include <linux/debugfs.h>
  32. #include <linux/uaccess.h>
  33. static int queue_dbg_open(struct inode *inode, struct file *file)
  34. {
  35. struct usba_ep *ep = inode->i_private;
  36. struct usba_request *req, *req_copy;
  37. struct list_head *queue_data;
  38. queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
  39. if (!queue_data)
  40. return -ENOMEM;
  41. INIT_LIST_HEAD(queue_data);
  42. spin_lock_irq(&ep->udc->lock);
  43. list_for_each_entry(req, &ep->queue, queue) {
  44. req_copy = kmemdup(req, sizeof(*req_copy), GFP_ATOMIC);
  45. if (!req_copy)
  46. goto fail;
  47. list_add_tail(&req_copy->queue, queue_data);
  48. }
  49. spin_unlock_irq(&ep->udc->lock);
  50. file->private_data = queue_data;
  51. return 0;
  52. fail:
  53. spin_unlock_irq(&ep->udc->lock);
  54. list_for_each_entry_safe(req, req_copy, queue_data, queue) {
  55. list_del(&req->queue);
  56. kfree(req);
  57. }
  58. kfree(queue_data);
  59. return -ENOMEM;
  60. }
  61. /*
  62. * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
  63. *
  64. * b: buffer address
  65. * l: buffer length
  66. * I/i: interrupt/no interrupt
  67. * Z/z: zero/no zero
  68. * S/s: short ok/short not ok
  69. * s: status
  70. * n: nr_packets
  71. * F/f: submitted/not submitted to FIFO
  72. * D/d: using/not using DMA
  73. * L/l: last transaction/not last transaction
  74. */
  75. static ssize_t queue_dbg_read(struct file *file, char __user *buf,
  76. size_t nbytes, loff_t *ppos)
  77. {
  78. struct list_head *queue = file->private_data;
  79. struct usba_request *req, *tmp_req;
  80. size_t len, remaining, actual = 0;
  81. char tmpbuf[38];
  82. if (!access_ok(VERIFY_WRITE, buf, nbytes))
  83. return -EFAULT;
  84. inode_lock(file_inode(file));
  85. list_for_each_entry_safe(req, tmp_req, queue, queue) {
  86. len = snprintf(tmpbuf, sizeof(tmpbuf),
  87. "%8p %08x %c%c%c %5d %c%c%c\n",
  88. req->req.buf, req->req.length,
  89. req->req.no_interrupt ? 'i' : 'I',
  90. req->req.zero ? 'Z' : 'z',
  91. req->req.short_not_ok ? 's' : 'S',
  92. req->req.status,
  93. req->submitted ? 'F' : 'f',
  94. req->using_dma ? 'D' : 'd',
  95. req->last_transaction ? 'L' : 'l');
  96. len = min(len, sizeof(tmpbuf));
  97. if (len > nbytes)
  98. break;
  99. list_del(&req->queue);
  100. kfree(req);
  101. remaining = __copy_to_user(buf, tmpbuf, len);
  102. actual += len - remaining;
  103. if (remaining)
  104. break;
  105. nbytes -= len;
  106. buf += len;
  107. }
  108. inode_unlock(file_inode(file));
  109. return actual;
  110. }
  111. static int queue_dbg_release(struct inode *inode, struct file *file)
  112. {
  113. struct list_head *queue_data = file->private_data;
  114. struct usba_request *req, *tmp_req;
  115. list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
  116. list_del(&req->queue);
  117. kfree(req);
  118. }
  119. kfree(queue_data);
  120. return 0;
  121. }
  122. static int regs_dbg_open(struct inode *inode, struct file *file)
  123. {
  124. struct usba_udc *udc;
  125. unsigned int i;
  126. u32 *data;
  127. int ret = -ENOMEM;
  128. inode_lock(inode);
  129. udc = inode->i_private;
  130. data = kmalloc(inode->i_size, GFP_KERNEL);
  131. if (!data)
  132. goto out;
  133. spin_lock_irq(&udc->lock);
  134. for (i = 0; i < inode->i_size / 4; i++)
  135. data[i] = usba_io_readl(udc->regs + i * 4);
  136. spin_unlock_irq(&udc->lock);
  137. file->private_data = data;
  138. ret = 0;
  139. out:
  140. inode_unlock(inode);
  141. return ret;
  142. }
  143. static ssize_t regs_dbg_read(struct file *file, char __user *buf,
  144. size_t nbytes, loff_t *ppos)
  145. {
  146. struct inode *inode = file_inode(file);
  147. int ret;
  148. inode_lock(inode);
  149. ret = simple_read_from_buffer(buf, nbytes, ppos,
  150. file->private_data,
  151. file_inode(file)->i_size);
  152. inode_unlock(inode);
  153. return ret;
  154. }
  155. static int regs_dbg_release(struct inode *inode, struct file *file)
  156. {
  157. kfree(file->private_data);
  158. return 0;
  159. }
  160. const struct file_operations queue_dbg_fops = {
  161. .owner = THIS_MODULE,
  162. .open = queue_dbg_open,
  163. .llseek = no_llseek,
  164. .read = queue_dbg_read,
  165. .release = queue_dbg_release,
  166. };
  167. const struct file_operations regs_dbg_fops = {
  168. .owner = THIS_MODULE,
  169. .open = regs_dbg_open,
  170. .llseek = generic_file_llseek,
  171. .read = regs_dbg_read,
  172. .release = regs_dbg_release,
  173. };
  174. static void usba_ep_init_debugfs(struct usba_udc *udc,
  175. struct usba_ep *ep)
  176. {
  177. struct dentry *ep_root;
  178. ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root);
  179. if (!ep_root)
  180. goto err_root;
  181. ep->debugfs_dir = ep_root;
  182. ep->debugfs_queue = debugfs_create_file("queue", 0400, ep_root,
  183. ep, &queue_dbg_fops);
  184. if (!ep->debugfs_queue)
  185. goto err_queue;
  186. if (ep->can_dma) {
  187. ep->debugfs_dma_status
  188. = debugfs_create_u32("dma_status", 0400, ep_root,
  189. &ep->last_dma_status);
  190. if (!ep->debugfs_dma_status)
  191. goto err_dma_status;
  192. }
  193. if (ep_is_control(ep)) {
  194. ep->debugfs_state
  195. = debugfs_create_u32("state", 0400, ep_root,
  196. &ep->state);
  197. if (!ep->debugfs_state)
  198. goto err_state;
  199. }
  200. return;
  201. err_state:
  202. if (ep->can_dma)
  203. debugfs_remove(ep->debugfs_dma_status);
  204. err_dma_status:
  205. debugfs_remove(ep->debugfs_queue);
  206. err_queue:
  207. debugfs_remove(ep_root);
  208. err_root:
  209. dev_err(&ep->udc->pdev->dev,
  210. "failed to create debugfs directory for %s\n", ep->ep.name);
  211. }
  212. static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  213. {
  214. debugfs_remove(ep->debugfs_queue);
  215. debugfs_remove(ep->debugfs_dma_status);
  216. debugfs_remove(ep->debugfs_state);
  217. debugfs_remove(ep->debugfs_dir);
  218. ep->debugfs_dma_status = NULL;
  219. ep->debugfs_dir = NULL;
  220. }
  221. static void usba_init_debugfs(struct usba_udc *udc)
  222. {
  223. struct dentry *root, *regs;
  224. struct resource *regs_resource;
  225. root = debugfs_create_dir(udc->gadget.name, NULL);
  226. if (IS_ERR(root) || !root)
  227. goto err_root;
  228. udc->debugfs_root = root;
  229. regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
  230. CTRL_IOMEM_ID);
  231. if (regs_resource) {
  232. regs = debugfs_create_file_size("regs", 0400, root, udc,
  233. &regs_dbg_fops,
  234. resource_size(regs_resource));
  235. if (!regs)
  236. goto err_regs;
  237. udc->debugfs_regs = regs;
  238. }
  239. usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
  240. return;
  241. err_regs:
  242. debugfs_remove(root);
  243. err_root:
  244. udc->debugfs_root = NULL;
  245. dev_err(&udc->pdev->dev, "debugfs is not available\n");
  246. }
  247. static void usba_cleanup_debugfs(struct usba_udc *udc)
  248. {
  249. usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
  250. debugfs_remove(udc->debugfs_regs);
  251. debugfs_remove(udc->debugfs_root);
  252. udc->debugfs_regs = NULL;
  253. udc->debugfs_root = NULL;
  254. }
  255. #else
  256. static inline void usba_ep_init_debugfs(struct usba_udc *udc,
  257. struct usba_ep *ep)
  258. {
  259. }
  260. static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  261. {
  262. }
  263. static inline void usba_init_debugfs(struct usba_udc *udc)
  264. {
  265. }
  266. static inline void usba_cleanup_debugfs(struct usba_udc *udc)
  267. {
  268. }
  269. #endif
  270. static inline u32 usba_int_enb_get(struct usba_udc *udc)
  271. {
  272. return udc->int_enb_cache;
  273. }
  274. static inline void usba_int_enb_set(struct usba_udc *udc, u32 val)
  275. {
  276. usba_writel(udc, INT_ENB, val);
  277. udc->int_enb_cache = val;
  278. }
  279. static int vbus_is_present(struct usba_udc *udc)
  280. {
  281. if (gpio_is_valid(udc->vbus_pin))
  282. return gpio_get_value(udc->vbus_pin) ^ udc->vbus_pin_inverted;
  283. /* No Vbus detection: Assume always present */
  284. return 1;
  285. }
  286. static void toggle_bias(struct usba_udc *udc, int is_on)
  287. {
  288. if (udc->errata && udc->errata->toggle_bias)
  289. udc->errata->toggle_bias(udc, is_on);
  290. }
  291. static void generate_bias_pulse(struct usba_udc *udc)
  292. {
  293. if (!udc->bias_pulse_needed)
  294. return;
  295. if (udc->errata && udc->errata->pulse_bias)
  296. udc->errata->pulse_bias(udc);
  297. udc->bias_pulse_needed = false;
  298. }
  299. static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
  300. {
  301. unsigned int transaction_len;
  302. transaction_len = req->req.length - req->req.actual;
  303. req->last_transaction = 1;
  304. if (transaction_len > ep->ep.maxpacket) {
  305. transaction_len = ep->ep.maxpacket;
  306. req->last_transaction = 0;
  307. } else if (transaction_len == ep->ep.maxpacket && req->req.zero)
  308. req->last_transaction = 0;
  309. DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
  310. ep->ep.name, req, transaction_len,
  311. req->last_transaction ? ", done" : "");
  312. memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
  313. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  314. req->req.actual += transaction_len;
  315. }
  316. static void submit_request(struct usba_ep *ep, struct usba_request *req)
  317. {
  318. DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
  319. ep->ep.name, req, req->req.length);
  320. req->req.actual = 0;
  321. req->submitted = 1;
  322. if (req->using_dma) {
  323. if (req->req.length == 0) {
  324. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  325. return;
  326. }
  327. if (req->req.zero)
  328. usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET);
  329. else
  330. usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET);
  331. usba_dma_writel(ep, ADDRESS, req->req.dma);
  332. usba_dma_writel(ep, CONTROL, req->ctrl);
  333. } else {
  334. next_fifo_transaction(ep, req);
  335. if (req->last_transaction) {
  336. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  337. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  338. } else {
  339. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  340. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  341. }
  342. }
  343. }
  344. static void submit_next_request(struct usba_ep *ep)
  345. {
  346. struct usba_request *req;
  347. if (list_empty(&ep->queue)) {
  348. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY);
  349. return;
  350. }
  351. req = list_entry(ep->queue.next, struct usba_request, queue);
  352. if (!req->submitted)
  353. submit_request(ep, req);
  354. }
  355. static void send_status(struct usba_udc *udc, struct usba_ep *ep)
  356. {
  357. ep->state = STATUS_STAGE_IN;
  358. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  359. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  360. }
  361. static void receive_data(struct usba_ep *ep)
  362. {
  363. struct usba_udc *udc = ep->udc;
  364. struct usba_request *req;
  365. unsigned long status;
  366. unsigned int bytecount, nr_busy;
  367. int is_complete = 0;
  368. status = usba_ep_readl(ep, STA);
  369. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  370. DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
  371. while (nr_busy > 0) {
  372. if (list_empty(&ep->queue)) {
  373. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  374. break;
  375. }
  376. req = list_entry(ep->queue.next,
  377. struct usba_request, queue);
  378. bytecount = USBA_BFEXT(BYTE_COUNT, status);
  379. if (status & (1 << 31))
  380. is_complete = 1;
  381. if (req->req.actual + bytecount >= req->req.length) {
  382. is_complete = 1;
  383. bytecount = req->req.length - req->req.actual;
  384. }
  385. memcpy_fromio(req->req.buf + req->req.actual,
  386. ep->fifo, bytecount);
  387. req->req.actual += bytecount;
  388. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  389. if (is_complete) {
  390. DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name);
  391. req->req.status = 0;
  392. list_del_init(&req->queue);
  393. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  394. spin_unlock(&udc->lock);
  395. usb_gadget_giveback_request(&ep->ep, &req->req);
  396. spin_lock(&udc->lock);
  397. }
  398. status = usba_ep_readl(ep, STA);
  399. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  400. if (is_complete && ep_is_control(ep)) {
  401. send_status(udc, ep);
  402. break;
  403. }
  404. }
  405. }
  406. static void
  407. request_complete(struct usba_ep *ep, struct usba_request *req, int status)
  408. {
  409. struct usba_udc *udc = ep->udc;
  410. WARN_ON(!list_empty(&req->queue));
  411. if (req->req.status == -EINPROGRESS)
  412. req->req.status = status;
  413. if (req->using_dma)
  414. usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
  415. DBG(DBG_GADGET | DBG_REQ,
  416. "%s: req %p complete: status %d, actual %u\n",
  417. ep->ep.name, req, req->req.status, req->req.actual);
  418. spin_unlock(&udc->lock);
  419. usb_gadget_giveback_request(&ep->ep, &req->req);
  420. spin_lock(&udc->lock);
  421. }
  422. static void
  423. request_complete_list(struct usba_ep *ep, struct list_head *list, int status)
  424. {
  425. struct usba_request *req, *tmp_req;
  426. list_for_each_entry_safe(req, tmp_req, list, queue) {
  427. list_del_init(&req->queue);
  428. request_complete(ep, req, status);
  429. }
  430. }
  431. static int
  432. usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
  433. {
  434. struct usba_ep *ep = to_usba_ep(_ep);
  435. struct usba_udc *udc = ep->udc;
  436. unsigned long flags, ept_cfg, maxpacket;
  437. unsigned int nr_trans;
  438. DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc);
  439. maxpacket = usb_endpoint_maxp(desc);
  440. if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index)
  441. || ep->index == 0
  442. || desc->bDescriptorType != USB_DT_ENDPOINT
  443. || maxpacket == 0
  444. || maxpacket > ep->fifo_size) {
  445. DBG(DBG_ERR, "ep_enable: Invalid argument");
  446. return -EINVAL;
  447. }
  448. ep->is_isoc = 0;
  449. ep->is_in = 0;
  450. if (maxpacket <= 8)
  451. ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
  452. else
  453. /* LSB is bit 1, not 0 */
  454. ept_cfg = USBA_BF(EPT_SIZE, fls(maxpacket - 1) - 3);
  455. DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n",
  456. ep->ep.name, ept_cfg, maxpacket);
  457. if (usb_endpoint_dir_in(desc)) {
  458. ep->is_in = 1;
  459. ept_cfg |= USBA_EPT_DIR_IN;
  460. }
  461. switch (usb_endpoint_type(desc)) {
  462. case USB_ENDPOINT_XFER_CONTROL:
  463. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
  464. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE);
  465. break;
  466. case USB_ENDPOINT_XFER_ISOC:
  467. if (!ep->can_isoc) {
  468. DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
  469. ep->ep.name);
  470. return -EINVAL;
  471. }
  472. /*
  473. * Bits 11:12 specify number of _additional_
  474. * transactions per microframe.
  475. */
  476. nr_trans = usb_endpoint_maxp_mult(desc);
  477. if (nr_trans > 3)
  478. return -EINVAL;
  479. ep->is_isoc = 1;
  480. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
  481. /*
  482. * Do triple-buffering on high-bandwidth iso endpoints.
  483. */
  484. if (nr_trans > 1 && ep->nr_banks == 3)
  485. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_TRIPLE);
  486. else
  487. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  488. ept_cfg |= USBA_BF(NB_TRANS, nr_trans);
  489. break;
  490. case USB_ENDPOINT_XFER_BULK:
  491. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
  492. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  493. break;
  494. case USB_ENDPOINT_XFER_INT:
  495. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
  496. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  497. break;
  498. }
  499. spin_lock_irqsave(&ep->udc->lock, flags);
  500. ep->ep.desc = desc;
  501. ep->ep.maxpacket = maxpacket;
  502. usba_ep_writel(ep, CFG, ept_cfg);
  503. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  504. if (ep->can_dma) {
  505. u32 ctrl;
  506. usba_int_enb_set(udc, usba_int_enb_get(udc) |
  507. USBA_BF(EPT_INT, 1 << ep->index) |
  508. USBA_BF(DMA_INT, 1 << ep->index));
  509. ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA;
  510. usba_ep_writel(ep, CTL_ENB, ctrl);
  511. } else {
  512. usba_int_enb_set(udc, usba_int_enb_get(udc) |
  513. USBA_BF(EPT_INT, 1 << ep->index));
  514. }
  515. spin_unlock_irqrestore(&udc->lock, flags);
  516. DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
  517. (unsigned long)usba_ep_readl(ep, CFG));
  518. DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
  519. (unsigned long)usba_int_enb_get(udc));
  520. return 0;
  521. }
  522. static int usba_ep_disable(struct usb_ep *_ep)
  523. {
  524. struct usba_ep *ep = to_usba_ep(_ep);
  525. struct usba_udc *udc = ep->udc;
  526. LIST_HEAD(req_list);
  527. unsigned long flags;
  528. DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name);
  529. spin_lock_irqsave(&udc->lock, flags);
  530. if (!ep->ep.desc) {
  531. spin_unlock_irqrestore(&udc->lock, flags);
  532. /* REVISIT because this driver disables endpoints in
  533. * reset_all_endpoints() before calling disconnect(),
  534. * most gadget drivers would trigger this non-error ...
  535. */
  536. if (udc->gadget.speed != USB_SPEED_UNKNOWN)
  537. DBG(DBG_ERR, "ep_disable: %s not enabled\n",
  538. ep->ep.name);
  539. return -EINVAL;
  540. }
  541. ep->ep.desc = NULL;
  542. list_splice_init(&ep->queue, &req_list);
  543. if (ep->can_dma) {
  544. usba_dma_writel(ep, CONTROL, 0);
  545. usba_dma_writel(ep, ADDRESS, 0);
  546. usba_dma_readl(ep, STATUS);
  547. }
  548. usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE);
  549. usba_int_enb_set(udc, usba_int_enb_get(udc) &
  550. ~USBA_BF(EPT_INT, 1 << ep->index));
  551. request_complete_list(ep, &req_list, -ESHUTDOWN);
  552. spin_unlock_irqrestore(&udc->lock, flags);
  553. return 0;
  554. }
  555. static struct usb_request *
  556. usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
  557. {
  558. struct usba_request *req;
  559. DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
  560. req = kzalloc(sizeof(*req), gfp_flags);
  561. if (!req)
  562. return NULL;
  563. INIT_LIST_HEAD(&req->queue);
  564. return &req->req;
  565. }
  566. static void
  567. usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
  568. {
  569. struct usba_request *req = to_usba_req(_req);
  570. DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
  571. kfree(req);
  572. }
  573. static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
  574. struct usba_request *req, gfp_t gfp_flags)
  575. {
  576. unsigned long flags;
  577. int ret;
  578. DBG(DBG_DMA, "%s: req l/%u d/%pad %c%c%c\n",
  579. ep->ep.name, req->req.length, &req->req.dma,
  580. req->req.zero ? 'Z' : 'z',
  581. req->req.short_not_ok ? 'S' : 's',
  582. req->req.no_interrupt ? 'I' : 'i');
  583. if (req->req.length > 0x10000) {
  584. /* Lengths from 0 to 65536 (inclusive) are supported */
  585. DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
  586. return -EINVAL;
  587. }
  588. ret = usb_gadget_map_request(&udc->gadget, &req->req, ep->is_in);
  589. if (ret)
  590. return ret;
  591. req->using_dma = 1;
  592. req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length)
  593. | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE
  594. | USBA_DMA_END_BUF_EN;
  595. if (!ep->is_in)
  596. req->ctrl |= USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
  597. /*
  598. * Add this request to the queue and submit for DMA if
  599. * possible. Check if we're still alive first -- we may have
  600. * received a reset since last time we checked.
  601. */
  602. ret = -ESHUTDOWN;
  603. spin_lock_irqsave(&udc->lock, flags);
  604. if (ep->ep.desc) {
  605. if (list_empty(&ep->queue))
  606. submit_request(ep, req);
  607. list_add_tail(&req->queue, &ep->queue);
  608. ret = 0;
  609. }
  610. spin_unlock_irqrestore(&udc->lock, flags);
  611. return ret;
  612. }
  613. static int
  614. usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  615. {
  616. struct usba_request *req = to_usba_req(_req);
  617. struct usba_ep *ep = to_usba_ep(_ep);
  618. struct usba_udc *udc = ep->udc;
  619. unsigned long flags;
  620. int ret;
  621. DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n",
  622. ep->ep.name, req, _req->length);
  623. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN ||
  624. !ep->ep.desc)
  625. return -ESHUTDOWN;
  626. req->submitted = 0;
  627. req->using_dma = 0;
  628. req->last_transaction = 0;
  629. _req->status = -EINPROGRESS;
  630. _req->actual = 0;
  631. if (ep->can_dma)
  632. return queue_dma(udc, ep, req, gfp_flags);
  633. /* May have received a reset since last time we checked */
  634. ret = -ESHUTDOWN;
  635. spin_lock_irqsave(&udc->lock, flags);
  636. if (ep->ep.desc) {
  637. list_add_tail(&req->queue, &ep->queue);
  638. if ((!ep_is_control(ep) && ep->is_in) ||
  639. (ep_is_control(ep)
  640. && (ep->state == DATA_STAGE_IN
  641. || ep->state == STATUS_STAGE_IN)))
  642. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  643. else
  644. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  645. ret = 0;
  646. }
  647. spin_unlock_irqrestore(&udc->lock, flags);
  648. return ret;
  649. }
  650. static void
  651. usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status)
  652. {
  653. req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
  654. }
  655. static int stop_dma(struct usba_ep *ep, u32 *pstatus)
  656. {
  657. unsigned int timeout;
  658. u32 status;
  659. /*
  660. * Stop the DMA controller. When writing both CH_EN
  661. * and LINK to 0, the other bits are not affected.
  662. */
  663. usba_dma_writel(ep, CONTROL, 0);
  664. /* Wait for the FIFO to empty */
  665. for (timeout = 40; timeout; --timeout) {
  666. status = usba_dma_readl(ep, STATUS);
  667. if (!(status & USBA_DMA_CH_EN))
  668. break;
  669. udelay(1);
  670. }
  671. if (pstatus)
  672. *pstatus = status;
  673. if (timeout == 0) {
  674. dev_err(&ep->udc->pdev->dev,
  675. "%s: timed out waiting for DMA FIFO to empty\n",
  676. ep->ep.name);
  677. return -ETIMEDOUT;
  678. }
  679. return 0;
  680. }
  681. static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  682. {
  683. struct usba_ep *ep = to_usba_ep(_ep);
  684. struct usba_udc *udc = ep->udc;
  685. struct usba_request *req;
  686. unsigned long flags;
  687. u32 status;
  688. DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
  689. ep->ep.name, req);
  690. spin_lock_irqsave(&udc->lock, flags);
  691. list_for_each_entry(req, &ep->queue, queue) {
  692. if (&req->req == _req)
  693. break;
  694. }
  695. if (&req->req != _req) {
  696. spin_unlock_irqrestore(&udc->lock, flags);
  697. return -EINVAL;
  698. }
  699. if (req->using_dma) {
  700. /*
  701. * If this request is currently being transferred,
  702. * stop the DMA controller and reset the FIFO.
  703. */
  704. if (ep->queue.next == &req->queue) {
  705. status = usba_dma_readl(ep, STATUS);
  706. if (status & USBA_DMA_CH_EN)
  707. stop_dma(ep, &status);
  708. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  709. ep->last_dma_status = status;
  710. #endif
  711. usba_writel(udc, EPT_RST, 1 << ep->index);
  712. usba_update_req(ep, req, status);
  713. }
  714. }
  715. /*
  716. * Errors should stop the queue from advancing until the
  717. * completion function returns.
  718. */
  719. list_del_init(&req->queue);
  720. request_complete(ep, req, -ECONNRESET);
  721. /* Process the next request if any */
  722. submit_next_request(ep);
  723. spin_unlock_irqrestore(&udc->lock, flags);
  724. return 0;
  725. }
  726. static int usba_ep_set_halt(struct usb_ep *_ep, int value)
  727. {
  728. struct usba_ep *ep = to_usba_ep(_ep);
  729. struct usba_udc *udc = ep->udc;
  730. unsigned long flags;
  731. int ret = 0;
  732. DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name,
  733. value ? "set" : "clear");
  734. if (!ep->ep.desc) {
  735. DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
  736. ep->ep.name);
  737. return -ENODEV;
  738. }
  739. if (ep->is_isoc) {
  740. DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
  741. ep->ep.name);
  742. return -ENOTTY;
  743. }
  744. spin_lock_irqsave(&udc->lock, flags);
  745. /*
  746. * We can't halt IN endpoints while there are still data to be
  747. * transferred
  748. */
  749. if (!list_empty(&ep->queue)
  750. || ((value && ep->is_in && (usba_ep_readl(ep, STA)
  751. & USBA_BF(BUSY_BANKS, -1L))))) {
  752. ret = -EAGAIN;
  753. } else {
  754. if (value)
  755. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  756. else
  757. usba_ep_writel(ep, CLR_STA,
  758. USBA_FORCE_STALL | USBA_TOGGLE_CLR);
  759. usba_ep_readl(ep, STA);
  760. }
  761. spin_unlock_irqrestore(&udc->lock, flags);
  762. return ret;
  763. }
  764. static int usba_ep_fifo_status(struct usb_ep *_ep)
  765. {
  766. struct usba_ep *ep = to_usba_ep(_ep);
  767. return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  768. }
  769. static void usba_ep_fifo_flush(struct usb_ep *_ep)
  770. {
  771. struct usba_ep *ep = to_usba_ep(_ep);
  772. struct usba_udc *udc = ep->udc;
  773. usba_writel(udc, EPT_RST, 1 << ep->index);
  774. }
  775. static const struct usb_ep_ops usba_ep_ops = {
  776. .enable = usba_ep_enable,
  777. .disable = usba_ep_disable,
  778. .alloc_request = usba_ep_alloc_request,
  779. .free_request = usba_ep_free_request,
  780. .queue = usba_ep_queue,
  781. .dequeue = usba_ep_dequeue,
  782. .set_halt = usba_ep_set_halt,
  783. .fifo_status = usba_ep_fifo_status,
  784. .fifo_flush = usba_ep_fifo_flush,
  785. };
  786. static int usba_udc_get_frame(struct usb_gadget *gadget)
  787. {
  788. struct usba_udc *udc = to_usba_udc(gadget);
  789. return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
  790. }
  791. static int usba_udc_wakeup(struct usb_gadget *gadget)
  792. {
  793. struct usba_udc *udc = to_usba_udc(gadget);
  794. unsigned long flags;
  795. u32 ctrl;
  796. int ret = -EINVAL;
  797. spin_lock_irqsave(&udc->lock, flags);
  798. if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) {
  799. ctrl = usba_readl(udc, CTRL);
  800. usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP);
  801. ret = 0;
  802. }
  803. spin_unlock_irqrestore(&udc->lock, flags);
  804. return ret;
  805. }
  806. static int
  807. usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
  808. {
  809. struct usba_udc *udc = to_usba_udc(gadget);
  810. unsigned long flags;
  811. gadget->is_selfpowered = (is_selfpowered != 0);
  812. spin_lock_irqsave(&udc->lock, flags);
  813. if (is_selfpowered)
  814. udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
  815. else
  816. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  817. spin_unlock_irqrestore(&udc->lock, flags);
  818. return 0;
  819. }
  820. static int atmel_usba_start(struct usb_gadget *gadget,
  821. struct usb_gadget_driver *driver);
  822. static int atmel_usba_stop(struct usb_gadget *gadget);
  823. static const struct usb_gadget_ops usba_udc_ops = {
  824. .get_frame = usba_udc_get_frame,
  825. .wakeup = usba_udc_wakeup,
  826. .set_selfpowered = usba_udc_set_selfpowered,
  827. .udc_start = atmel_usba_start,
  828. .udc_stop = atmel_usba_stop,
  829. };
  830. static struct usb_endpoint_descriptor usba_ep0_desc = {
  831. .bLength = USB_DT_ENDPOINT_SIZE,
  832. .bDescriptorType = USB_DT_ENDPOINT,
  833. .bEndpointAddress = 0,
  834. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  835. .wMaxPacketSize = cpu_to_le16(64),
  836. /* FIXME: I have no idea what to put here */
  837. .bInterval = 1,
  838. };
  839. static struct usb_gadget usba_gadget_template = {
  840. .ops = &usba_udc_ops,
  841. .max_speed = USB_SPEED_HIGH,
  842. .name = "atmel_usba_udc",
  843. };
  844. /*
  845. * Called with interrupts disabled and udc->lock held.
  846. */
  847. static void reset_all_endpoints(struct usba_udc *udc)
  848. {
  849. struct usba_ep *ep;
  850. struct usba_request *req, *tmp_req;
  851. usba_writel(udc, EPT_RST, ~0UL);
  852. ep = to_usba_ep(udc->gadget.ep0);
  853. list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
  854. list_del_init(&req->queue);
  855. request_complete(ep, req, -ECONNRESET);
  856. }
  857. }
  858. static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
  859. {
  860. struct usba_ep *ep;
  861. if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
  862. return to_usba_ep(udc->gadget.ep0);
  863. list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
  864. u8 bEndpointAddress;
  865. if (!ep->ep.desc)
  866. continue;
  867. bEndpointAddress = ep->ep.desc->bEndpointAddress;
  868. if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
  869. continue;
  870. if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
  871. == (wIndex & USB_ENDPOINT_NUMBER_MASK))
  872. return ep;
  873. }
  874. return NULL;
  875. }
  876. /* Called with interrupts disabled and udc->lock held */
  877. static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep)
  878. {
  879. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  880. ep->state = WAIT_FOR_SETUP;
  881. }
  882. static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
  883. {
  884. if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL)
  885. return 1;
  886. return 0;
  887. }
  888. static inline void set_address(struct usba_udc *udc, unsigned int addr)
  889. {
  890. u32 regval;
  891. DBG(DBG_BUS, "setting address %u...\n", addr);
  892. regval = usba_readl(udc, CTRL);
  893. regval = USBA_BFINS(DEV_ADDR, addr, regval);
  894. usba_writel(udc, CTRL, regval);
  895. }
  896. static int do_test_mode(struct usba_udc *udc)
  897. {
  898. static const char test_packet_buffer[] = {
  899. /* JKJKJKJK * 9 */
  900. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  901. /* JJKKJJKK * 8 */
  902. 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
  903. /* JJKKJJKK * 8 */
  904. 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
  905. /* JJJJJJJKKKKKKK * 8 */
  906. 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  907. 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  908. /* JJJJJJJK * 8 */
  909. 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
  910. /* {JKKKKKKK * 10}, JK */
  911. 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
  912. };
  913. struct usba_ep *ep;
  914. struct device *dev = &udc->pdev->dev;
  915. int test_mode;
  916. test_mode = udc->test_mode;
  917. /* Start from a clean slate */
  918. reset_all_endpoints(udc);
  919. switch (test_mode) {
  920. case 0x0100:
  921. /* Test_J */
  922. usba_writel(udc, TST, USBA_TST_J_MODE);
  923. dev_info(dev, "Entering Test_J mode...\n");
  924. break;
  925. case 0x0200:
  926. /* Test_K */
  927. usba_writel(udc, TST, USBA_TST_K_MODE);
  928. dev_info(dev, "Entering Test_K mode...\n");
  929. break;
  930. case 0x0300:
  931. /*
  932. * Test_SE0_NAK: Force high-speed mode and set up ep0
  933. * for Bulk IN transfers
  934. */
  935. ep = &udc->usba_ep[0];
  936. usba_writel(udc, TST,
  937. USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
  938. usba_ep_writel(ep, CFG,
  939. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  940. | USBA_EPT_DIR_IN
  941. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  942. | USBA_BF(BK_NUMBER, 1));
  943. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  944. set_protocol_stall(udc, ep);
  945. dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
  946. } else {
  947. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  948. dev_info(dev, "Entering Test_SE0_NAK mode...\n");
  949. }
  950. break;
  951. case 0x0400:
  952. /* Test_Packet */
  953. ep = &udc->usba_ep[0];
  954. usba_ep_writel(ep, CFG,
  955. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  956. | USBA_EPT_DIR_IN
  957. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  958. | USBA_BF(BK_NUMBER, 1));
  959. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  960. set_protocol_stall(udc, ep);
  961. dev_err(dev, "Test_Packet: ep0 not mapped\n");
  962. } else {
  963. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  964. usba_writel(udc, TST, USBA_TST_PKT_MODE);
  965. memcpy_toio(ep->fifo, test_packet_buffer,
  966. sizeof(test_packet_buffer));
  967. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  968. dev_info(dev, "Entering Test_Packet mode...\n");
  969. }
  970. break;
  971. default:
  972. dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
  973. return -EINVAL;
  974. }
  975. return 0;
  976. }
  977. /* Avoid overly long expressions */
  978. static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
  979. {
  980. if (crq->wValue == cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
  981. return true;
  982. return false;
  983. }
  984. static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
  985. {
  986. if (crq->wValue == cpu_to_le16(USB_DEVICE_TEST_MODE))
  987. return true;
  988. return false;
  989. }
  990. static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
  991. {
  992. if (crq->wValue == cpu_to_le16(USB_ENDPOINT_HALT))
  993. return true;
  994. return false;
  995. }
  996. static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
  997. struct usb_ctrlrequest *crq)
  998. {
  999. int retval = 0;
  1000. switch (crq->bRequest) {
  1001. case USB_REQ_GET_STATUS: {
  1002. u16 status;
  1003. if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
  1004. status = cpu_to_le16(udc->devstatus);
  1005. } else if (crq->bRequestType
  1006. == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
  1007. status = cpu_to_le16(0);
  1008. } else if (crq->bRequestType
  1009. == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
  1010. struct usba_ep *target;
  1011. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1012. if (!target)
  1013. goto stall;
  1014. status = 0;
  1015. if (is_stalled(udc, target))
  1016. status |= cpu_to_le16(1);
  1017. } else
  1018. goto delegate;
  1019. /* Write directly to the FIFO. No queueing is done. */
  1020. if (crq->wLength != cpu_to_le16(sizeof(status)))
  1021. goto stall;
  1022. ep->state = DATA_STAGE_IN;
  1023. usba_io_writew(status, ep->fifo);
  1024. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  1025. break;
  1026. }
  1027. case USB_REQ_CLEAR_FEATURE: {
  1028. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1029. if (feature_is_dev_remote_wakeup(crq))
  1030. udc->devstatus
  1031. &= ~(1 << USB_DEVICE_REMOTE_WAKEUP);
  1032. else
  1033. /* Can't CLEAR_FEATURE TEST_MODE */
  1034. goto stall;
  1035. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1036. struct usba_ep *target;
  1037. if (crq->wLength != cpu_to_le16(0)
  1038. || !feature_is_ep_halt(crq))
  1039. goto stall;
  1040. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1041. if (!target)
  1042. goto stall;
  1043. usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL);
  1044. if (target->index != 0)
  1045. usba_ep_writel(target, CLR_STA,
  1046. USBA_TOGGLE_CLR);
  1047. } else {
  1048. goto delegate;
  1049. }
  1050. send_status(udc, ep);
  1051. break;
  1052. }
  1053. case USB_REQ_SET_FEATURE: {
  1054. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1055. if (feature_is_dev_test_mode(crq)) {
  1056. send_status(udc, ep);
  1057. ep->state = STATUS_STAGE_TEST;
  1058. udc->test_mode = le16_to_cpu(crq->wIndex);
  1059. return 0;
  1060. } else if (feature_is_dev_remote_wakeup(crq)) {
  1061. udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP;
  1062. } else {
  1063. goto stall;
  1064. }
  1065. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1066. struct usba_ep *target;
  1067. if (crq->wLength != cpu_to_le16(0)
  1068. || !feature_is_ep_halt(crq))
  1069. goto stall;
  1070. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1071. if (!target)
  1072. goto stall;
  1073. usba_ep_writel(target, SET_STA, USBA_FORCE_STALL);
  1074. } else
  1075. goto delegate;
  1076. send_status(udc, ep);
  1077. break;
  1078. }
  1079. case USB_REQ_SET_ADDRESS:
  1080. if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
  1081. goto delegate;
  1082. set_address(udc, le16_to_cpu(crq->wValue));
  1083. send_status(udc, ep);
  1084. ep->state = STATUS_STAGE_ADDR;
  1085. break;
  1086. default:
  1087. delegate:
  1088. spin_unlock(&udc->lock);
  1089. retval = udc->driver->setup(&udc->gadget, crq);
  1090. spin_lock(&udc->lock);
  1091. }
  1092. return retval;
  1093. stall:
  1094. pr_err("udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
  1095. "halting endpoint...\n",
  1096. ep->ep.name, crq->bRequestType, crq->bRequest,
  1097. le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
  1098. le16_to_cpu(crq->wLength));
  1099. set_protocol_stall(udc, ep);
  1100. return -1;
  1101. }
  1102. static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
  1103. {
  1104. struct usba_request *req;
  1105. u32 epstatus;
  1106. u32 epctrl;
  1107. restart:
  1108. epstatus = usba_ep_readl(ep, STA);
  1109. epctrl = usba_ep_readl(ep, CTL);
  1110. DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
  1111. ep->ep.name, ep->state, epstatus, epctrl);
  1112. req = NULL;
  1113. if (!list_empty(&ep->queue))
  1114. req = list_entry(ep->queue.next,
  1115. struct usba_request, queue);
  1116. if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1117. if (req->submitted)
  1118. next_fifo_transaction(ep, req);
  1119. else
  1120. submit_request(ep, req);
  1121. if (req->last_transaction) {
  1122. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1123. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  1124. }
  1125. goto restart;
  1126. }
  1127. if ((epstatus & epctrl) & USBA_TX_COMPLETE) {
  1128. usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE);
  1129. switch (ep->state) {
  1130. case DATA_STAGE_IN:
  1131. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  1132. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1133. ep->state = STATUS_STAGE_OUT;
  1134. break;
  1135. case STATUS_STAGE_ADDR:
  1136. /* Activate our new address */
  1137. usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
  1138. | USBA_FADDR_EN));
  1139. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1140. ep->state = WAIT_FOR_SETUP;
  1141. break;
  1142. case STATUS_STAGE_IN:
  1143. if (req) {
  1144. list_del_init(&req->queue);
  1145. request_complete(ep, req, 0);
  1146. submit_next_request(ep);
  1147. }
  1148. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1149. ep->state = WAIT_FOR_SETUP;
  1150. break;
  1151. case STATUS_STAGE_TEST:
  1152. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1153. ep->state = WAIT_FOR_SETUP;
  1154. if (do_test_mode(udc))
  1155. set_protocol_stall(udc, ep);
  1156. break;
  1157. default:
  1158. pr_err("udc: %s: TXCOMP: Invalid endpoint state %d, "
  1159. "halting endpoint...\n",
  1160. ep->ep.name, ep->state);
  1161. set_protocol_stall(udc, ep);
  1162. break;
  1163. }
  1164. goto restart;
  1165. }
  1166. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1167. switch (ep->state) {
  1168. case STATUS_STAGE_OUT:
  1169. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1170. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1171. if (req) {
  1172. list_del_init(&req->queue);
  1173. request_complete(ep, req, 0);
  1174. }
  1175. ep->state = WAIT_FOR_SETUP;
  1176. break;
  1177. case DATA_STAGE_OUT:
  1178. receive_data(ep);
  1179. break;
  1180. default:
  1181. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1182. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1183. pr_err("udc: %s: RXRDY: Invalid endpoint state %d, "
  1184. "halting endpoint...\n",
  1185. ep->ep.name, ep->state);
  1186. set_protocol_stall(udc, ep);
  1187. break;
  1188. }
  1189. goto restart;
  1190. }
  1191. if (epstatus & USBA_RX_SETUP) {
  1192. union {
  1193. struct usb_ctrlrequest crq;
  1194. unsigned long data[2];
  1195. } crq;
  1196. unsigned int pkt_len;
  1197. int ret;
  1198. if (ep->state != WAIT_FOR_SETUP) {
  1199. /*
  1200. * Didn't expect a SETUP packet at this
  1201. * point. Clean up any pending requests (which
  1202. * may be successful).
  1203. */
  1204. int status = -EPROTO;
  1205. /*
  1206. * RXRDY and TXCOMP are dropped when SETUP
  1207. * packets arrive. Just pretend we received
  1208. * the status packet.
  1209. */
  1210. if (ep->state == STATUS_STAGE_OUT
  1211. || ep->state == STATUS_STAGE_IN) {
  1212. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1213. status = 0;
  1214. }
  1215. if (req) {
  1216. list_del_init(&req->queue);
  1217. request_complete(ep, req, status);
  1218. }
  1219. }
  1220. pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  1221. DBG(DBG_HW, "Packet length: %u\n", pkt_len);
  1222. if (pkt_len != sizeof(crq)) {
  1223. pr_warn("udc: Invalid packet length %u (expected %zu)\n",
  1224. pkt_len, sizeof(crq));
  1225. set_protocol_stall(udc, ep);
  1226. return;
  1227. }
  1228. DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
  1229. memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
  1230. /* Free up one bank in the FIFO so that we can
  1231. * generate or receive a reply right away. */
  1232. usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP);
  1233. /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
  1234. ep->state, crq.crq.bRequestType,
  1235. crq.crq.bRequest); */
  1236. if (crq.crq.bRequestType & USB_DIR_IN) {
  1237. /*
  1238. * The USB 2.0 spec states that "if wLength is
  1239. * zero, there is no data transfer phase."
  1240. * However, testusb #14 seems to actually
  1241. * expect a data phase even if wLength = 0...
  1242. */
  1243. ep->state = DATA_STAGE_IN;
  1244. } else {
  1245. if (crq.crq.wLength != cpu_to_le16(0))
  1246. ep->state = DATA_STAGE_OUT;
  1247. else
  1248. ep->state = STATUS_STAGE_IN;
  1249. }
  1250. ret = -1;
  1251. if (ep->index == 0)
  1252. ret = handle_ep0_setup(udc, ep, &crq.crq);
  1253. else {
  1254. spin_unlock(&udc->lock);
  1255. ret = udc->driver->setup(&udc->gadget, &crq.crq);
  1256. spin_lock(&udc->lock);
  1257. }
  1258. DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
  1259. crq.crq.bRequestType, crq.crq.bRequest,
  1260. le16_to_cpu(crq.crq.wLength), ep->state, ret);
  1261. if (ret < 0) {
  1262. /* Let the host know that we failed */
  1263. set_protocol_stall(udc, ep);
  1264. }
  1265. }
  1266. }
  1267. static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
  1268. {
  1269. struct usba_request *req;
  1270. u32 epstatus;
  1271. u32 epctrl;
  1272. epstatus = usba_ep_readl(ep, STA);
  1273. epctrl = usba_ep_readl(ep, CTL);
  1274. DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus);
  1275. while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1276. DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name);
  1277. if (list_empty(&ep->queue)) {
  1278. dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
  1279. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1280. return;
  1281. }
  1282. req = list_entry(ep->queue.next, struct usba_request, queue);
  1283. if (req->using_dma) {
  1284. /* Send a zero-length packet */
  1285. usba_ep_writel(ep, SET_STA,
  1286. USBA_TX_PK_RDY);
  1287. usba_ep_writel(ep, CTL_DIS,
  1288. USBA_TX_PK_RDY);
  1289. list_del_init(&req->queue);
  1290. submit_next_request(ep);
  1291. request_complete(ep, req, 0);
  1292. } else {
  1293. if (req->submitted)
  1294. next_fifo_transaction(ep, req);
  1295. else
  1296. submit_request(ep, req);
  1297. if (req->last_transaction) {
  1298. list_del_init(&req->queue);
  1299. submit_next_request(ep);
  1300. request_complete(ep, req, 0);
  1301. }
  1302. }
  1303. epstatus = usba_ep_readl(ep, STA);
  1304. epctrl = usba_ep_readl(ep, CTL);
  1305. }
  1306. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1307. DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
  1308. receive_data(ep);
  1309. }
  1310. }
  1311. static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
  1312. {
  1313. struct usba_request *req;
  1314. u32 status, control, pending;
  1315. status = usba_dma_readl(ep, STATUS);
  1316. control = usba_dma_readl(ep, CONTROL);
  1317. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  1318. ep->last_dma_status = status;
  1319. #endif
  1320. pending = status & control;
  1321. DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control);
  1322. if (status & USBA_DMA_CH_EN) {
  1323. dev_err(&udc->pdev->dev,
  1324. "DMA_CH_EN is set after transfer is finished!\n");
  1325. dev_err(&udc->pdev->dev,
  1326. "status=%#08x, pending=%#08x, control=%#08x\n",
  1327. status, pending, control);
  1328. /*
  1329. * try to pretend nothing happened. We might have to
  1330. * do something here...
  1331. */
  1332. }
  1333. if (list_empty(&ep->queue))
  1334. /* Might happen if a reset comes along at the right moment */
  1335. return;
  1336. if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) {
  1337. req = list_entry(ep->queue.next, struct usba_request, queue);
  1338. usba_update_req(ep, req, status);
  1339. list_del_init(&req->queue);
  1340. submit_next_request(ep);
  1341. request_complete(ep, req, 0);
  1342. }
  1343. }
  1344. static irqreturn_t usba_udc_irq(int irq, void *devid)
  1345. {
  1346. struct usba_udc *udc = devid;
  1347. u32 status, int_enb;
  1348. u32 dma_status;
  1349. u32 ep_status;
  1350. spin_lock(&udc->lock);
  1351. int_enb = usba_int_enb_get(udc);
  1352. status = usba_readl(udc, INT_STA) & (int_enb | USBA_HIGH_SPEED);
  1353. DBG(DBG_INT, "irq, status=%#08x\n", status);
  1354. if (status & USBA_DET_SUSPEND) {
  1355. toggle_bias(udc, 0);
  1356. usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
  1357. usba_int_enb_set(udc, int_enb | USBA_WAKE_UP);
  1358. udc->bias_pulse_needed = true;
  1359. DBG(DBG_BUS, "Suspend detected\n");
  1360. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1361. && udc->driver && udc->driver->suspend) {
  1362. spin_unlock(&udc->lock);
  1363. udc->driver->suspend(&udc->gadget);
  1364. spin_lock(&udc->lock);
  1365. }
  1366. }
  1367. if (status & USBA_WAKE_UP) {
  1368. toggle_bias(udc, 1);
  1369. usba_writel(udc, INT_CLR, USBA_WAKE_UP);
  1370. usba_int_enb_set(udc, int_enb & ~USBA_WAKE_UP);
  1371. DBG(DBG_BUS, "Wake Up CPU detected\n");
  1372. }
  1373. if (status & USBA_END_OF_RESUME) {
  1374. usba_writel(udc, INT_CLR, USBA_END_OF_RESUME);
  1375. generate_bias_pulse(udc);
  1376. DBG(DBG_BUS, "Resume detected\n");
  1377. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1378. && udc->driver && udc->driver->resume) {
  1379. spin_unlock(&udc->lock);
  1380. udc->driver->resume(&udc->gadget);
  1381. spin_lock(&udc->lock);
  1382. }
  1383. }
  1384. dma_status = USBA_BFEXT(DMA_INT, status);
  1385. if (dma_status) {
  1386. int i;
  1387. for (i = 1; i <= USBA_NR_DMAS; i++)
  1388. if (dma_status & (1 << i))
  1389. usba_dma_irq(udc, &udc->usba_ep[i]);
  1390. }
  1391. ep_status = USBA_BFEXT(EPT_INT, status);
  1392. if (ep_status) {
  1393. int i;
  1394. for (i = 0; i < udc->num_ep; i++)
  1395. if (ep_status & (1 << i)) {
  1396. if (ep_is_control(&udc->usba_ep[i]))
  1397. usba_control_irq(udc, &udc->usba_ep[i]);
  1398. else
  1399. usba_ep_irq(udc, &udc->usba_ep[i]);
  1400. }
  1401. }
  1402. if (status & USBA_END_OF_RESET) {
  1403. struct usba_ep *ep0;
  1404. usba_writel(udc, INT_CLR, USBA_END_OF_RESET);
  1405. generate_bias_pulse(udc);
  1406. reset_all_endpoints(udc);
  1407. if (udc->gadget.speed != USB_SPEED_UNKNOWN && udc->driver) {
  1408. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1409. spin_unlock(&udc->lock);
  1410. usb_gadget_udc_reset(&udc->gadget, udc->driver);
  1411. spin_lock(&udc->lock);
  1412. }
  1413. if (status & USBA_HIGH_SPEED)
  1414. udc->gadget.speed = USB_SPEED_HIGH;
  1415. else
  1416. udc->gadget.speed = USB_SPEED_FULL;
  1417. DBG(DBG_BUS, "%s bus reset detected\n",
  1418. usb_speed_string(udc->gadget.speed));
  1419. ep0 = &udc->usba_ep[0];
  1420. ep0->ep.desc = &usba_ep0_desc;
  1421. ep0->state = WAIT_FOR_SETUP;
  1422. usba_ep_writel(ep0, CFG,
  1423. (USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
  1424. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
  1425. | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
  1426. usba_ep_writel(ep0, CTL_ENB,
  1427. USBA_EPT_ENABLE | USBA_RX_SETUP);
  1428. usba_int_enb_set(udc, int_enb | USBA_BF(EPT_INT, 1) |
  1429. USBA_DET_SUSPEND | USBA_END_OF_RESUME);
  1430. /*
  1431. * Unclear why we hit this irregularly, e.g. in usbtest,
  1432. * but it's clearly harmless...
  1433. */
  1434. if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED))
  1435. dev_dbg(&udc->pdev->dev,
  1436. "ODD: EP0 configuration is invalid!\n");
  1437. }
  1438. spin_unlock(&udc->lock);
  1439. return IRQ_HANDLED;
  1440. }
  1441. static int start_clock(struct usba_udc *udc)
  1442. {
  1443. int ret;
  1444. if (udc->clocked)
  1445. return 0;
  1446. ret = clk_prepare_enable(udc->pclk);
  1447. if (ret)
  1448. return ret;
  1449. ret = clk_prepare_enable(udc->hclk);
  1450. if (ret) {
  1451. clk_disable_unprepare(udc->pclk);
  1452. return ret;
  1453. }
  1454. udc->clocked = true;
  1455. return 0;
  1456. }
  1457. static void stop_clock(struct usba_udc *udc)
  1458. {
  1459. if (!udc->clocked)
  1460. return;
  1461. clk_disable_unprepare(udc->hclk);
  1462. clk_disable_unprepare(udc->pclk);
  1463. udc->clocked = false;
  1464. }
  1465. static int usba_start(struct usba_udc *udc)
  1466. {
  1467. unsigned long flags;
  1468. int ret;
  1469. ret = start_clock(udc);
  1470. if (ret)
  1471. return ret;
  1472. spin_lock_irqsave(&udc->lock, flags);
  1473. toggle_bias(udc, 1);
  1474. usba_writel(udc, CTRL, USBA_ENABLE_MASK);
  1475. usba_int_enb_set(udc, USBA_END_OF_RESET);
  1476. spin_unlock_irqrestore(&udc->lock, flags);
  1477. return 0;
  1478. }
  1479. static void usba_stop(struct usba_udc *udc)
  1480. {
  1481. unsigned long flags;
  1482. spin_lock_irqsave(&udc->lock, flags);
  1483. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1484. reset_all_endpoints(udc);
  1485. /* This will also disable the DP pullup */
  1486. toggle_bias(udc, 0);
  1487. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1488. spin_unlock_irqrestore(&udc->lock, flags);
  1489. stop_clock(udc);
  1490. }
  1491. static irqreturn_t usba_vbus_irq_thread(int irq, void *devid)
  1492. {
  1493. struct usba_udc *udc = devid;
  1494. int vbus;
  1495. /* debounce */
  1496. udelay(10);
  1497. mutex_lock(&udc->vbus_mutex);
  1498. vbus = vbus_is_present(udc);
  1499. if (vbus != udc->vbus_prev) {
  1500. if (vbus) {
  1501. usba_start(udc);
  1502. } else {
  1503. usba_stop(udc);
  1504. if (udc->driver->disconnect)
  1505. udc->driver->disconnect(&udc->gadget);
  1506. }
  1507. udc->vbus_prev = vbus;
  1508. }
  1509. mutex_unlock(&udc->vbus_mutex);
  1510. return IRQ_HANDLED;
  1511. }
  1512. static int atmel_usba_start(struct usb_gadget *gadget,
  1513. struct usb_gadget_driver *driver)
  1514. {
  1515. int ret;
  1516. struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
  1517. unsigned long flags;
  1518. spin_lock_irqsave(&udc->lock, flags);
  1519. udc->devstatus = 1 << USB_DEVICE_SELF_POWERED;
  1520. udc->driver = driver;
  1521. spin_unlock_irqrestore(&udc->lock, flags);
  1522. mutex_lock(&udc->vbus_mutex);
  1523. if (gpio_is_valid(udc->vbus_pin))
  1524. enable_irq(gpio_to_irq(udc->vbus_pin));
  1525. /* If Vbus is present, enable the controller and wait for reset */
  1526. udc->vbus_prev = vbus_is_present(udc);
  1527. if (udc->vbus_prev) {
  1528. ret = usba_start(udc);
  1529. if (ret)
  1530. goto err;
  1531. }
  1532. mutex_unlock(&udc->vbus_mutex);
  1533. return 0;
  1534. err:
  1535. if (gpio_is_valid(udc->vbus_pin))
  1536. disable_irq(gpio_to_irq(udc->vbus_pin));
  1537. mutex_unlock(&udc->vbus_mutex);
  1538. spin_lock_irqsave(&udc->lock, flags);
  1539. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  1540. udc->driver = NULL;
  1541. spin_unlock_irqrestore(&udc->lock, flags);
  1542. return ret;
  1543. }
  1544. static int atmel_usba_stop(struct usb_gadget *gadget)
  1545. {
  1546. struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
  1547. if (gpio_is_valid(udc->vbus_pin))
  1548. disable_irq(gpio_to_irq(udc->vbus_pin));
  1549. usba_stop(udc);
  1550. udc->driver = NULL;
  1551. return 0;
  1552. }
  1553. #ifdef CONFIG_OF
  1554. static void at91sam9rl_toggle_bias(struct usba_udc *udc, int is_on)
  1555. {
  1556. regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN,
  1557. is_on ? AT91_PMC_BIASEN : 0);
  1558. }
  1559. static void at91sam9g45_pulse_bias(struct usba_udc *udc)
  1560. {
  1561. regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN, 0);
  1562. regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN,
  1563. AT91_PMC_BIASEN);
  1564. }
  1565. static const struct usba_udc_errata at91sam9rl_errata = {
  1566. .toggle_bias = at91sam9rl_toggle_bias,
  1567. };
  1568. static const struct usba_udc_errata at91sam9g45_errata = {
  1569. .pulse_bias = at91sam9g45_pulse_bias,
  1570. };
  1571. static const struct of_device_id atmel_udc_dt_ids[] = {
  1572. { .compatible = "atmel,at91sam9rl-udc", .data = &at91sam9rl_errata },
  1573. { .compatible = "atmel,at91sam9g45-udc", .data = &at91sam9g45_errata },
  1574. { .compatible = "atmel,sama5d3-udc" },
  1575. { /* sentinel */ }
  1576. };
  1577. MODULE_DEVICE_TABLE(of, atmel_udc_dt_ids);
  1578. static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
  1579. struct usba_udc *udc)
  1580. {
  1581. u32 val;
  1582. const char *name;
  1583. enum of_gpio_flags flags;
  1584. struct device_node *np = pdev->dev.of_node;
  1585. const struct of_device_id *match;
  1586. struct device_node *pp;
  1587. int i, ret;
  1588. struct usba_ep *eps, *ep;
  1589. match = of_match_node(atmel_udc_dt_ids, np);
  1590. if (!match)
  1591. return ERR_PTR(-EINVAL);
  1592. udc->errata = match->data;
  1593. udc->pmc = syscon_regmap_lookup_by_compatible("atmel,at91sam9g45-pmc");
  1594. if (IS_ERR(udc->pmc))
  1595. udc->pmc = syscon_regmap_lookup_by_compatible("atmel,at91sam9x5-pmc");
  1596. if (udc->errata && IS_ERR(udc->pmc))
  1597. return ERR_CAST(udc->pmc);
  1598. udc->num_ep = 0;
  1599. udc->vbus_pin = of_get_named_gpio_flags(np, "atmel,vbus-gpio", 0,
  1600. &flags);
  1601. udc->vbus_pin_inverted = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0;
  1602. pp = NULL;
  1603. while ((pp = of_get_next_child(np, pp)))
  1604. udc->num_ep++;
  1605. eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * udc->num_ep,
  1606. GFP_KERNEL);
  1607. if (!eps)
  1608. return ERR_PTR(-ENOMEM);
  1609. udc->gadget.ep0 = &eps[0].ep;
  1610. INIT_LIST_HEAD(&eps[0].ep.ep_list);
  1611. pp = NULL;
  1612. i = 0;
  1613. while ((pp = of_get_next_child(np, pp))) {
  1614. ep = &eps[i];
  1615. ret = of_property_read_u32(pp, "reg", &val);
  1616. if (ret) {
  1617. dev_err(&pdev->dev, "of_probe: reg error(%d)\n", ret);
  1618. goto err;
  1619. }
  1620. ep->index = val;
  1621. ret = of_property_read_u32(pp, "atmel,fifo-size", &val);
  1622. if (ret) {
  1623. dev_err(&pdev->dev, "of_probe: fifo-size error(%d)\n", ret);
  1624. goto err;
  1625. }
  1626. ep->fifo_size = val;
  1627. ret = of_property_read_u32(pp, "atmel,nb-banks", &val);
  1628. if (ret) {
  1629. dev_err(&pdev->dev, "of_probe: nb-banks error(%d)\n", ret);
  1630. goto err;
  1631. }
  1632. ep->nr_banks = val;
  1633. ep->can_dma = of_property_read_bool(pp, "atmel,can-dma");
  1634. ep->can_isoc = of_property_read_bool(pp, "atmel,can-isoc");
  1635. ret = of_property_read_string(pp, "name", &name);
  1636. if (ret) {
  1637. dev_err(&pdev->dev, "of_probe: name error(%d)\n", ret);
  1638. goto err;
  1639. }
  1640. sprintf(ep->name, "ep%d", ep->index);
  1641. ep->ep.name = ep->name;
  1642. ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
  1643. ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
  1644. ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
  1645. ep->ep.ops = &usba_ep_ops;
  1646. usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size);
  1647. ep->udc = udc;
  1648. INIT_LIST_HEAD(&ep->queue);
  1649. if (ep->index == 0) {
  1650. ep->ep.caps.type_control = true;
  1651. } else {
  1652. ep->ep.caps.type_iso = ep->can_isoc;
  1653. ep->ep.caps.type_bulk = true;
  1654. ep->ep.caps.type_int = true;
  1655. }
  1656. ep->ep.caps.dir_in = true;
  1657. ep->ep.caps.dir_out = true;
  1658. if (i)
  1659. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  1660. i++;
  1661. }
  1662. if (i == 0) {
  1663. dev_err(&pdev->dev, "of_probe: no endpoint specified\n");
  1664. ret = -EINVAL;
  1665. goto err;
  1666. }
  1667. return eps;
  1668. err:
  1669. return ERR_PTR(ret);
  1670. }
  1671. #else
  1672. static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
  1673. struct usba_udc *udc)
  1674. {
  1675. return ERR_PTR(-ENOSYS);
  1676. }
  1677. #endif
  1678. static struct usba_ep * usba_udc_pdata(struct platform_device *pdev,
  1679. struct usba_udc *udc)
  1680. {
  1681. struct usba_platform_data *pdata = dev_get_platdata(&pdev->dev);
  1682. struct usba_ep *eps;
  1683. int i;
  1684. if (!pdata)
  1685. return ERR_PTR(-ENXIO);
  1686. eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * pdata->num_ep,
  1687. GFP_KERNEL);
  1688. if (!eps)
  1689. return ERR_PTR(-ENOMEM);
  1690. udc->gadget.ep0 = &eps[0].ep;
  1691. udc->vbus_pin = pdata->vbus_pin;
  1692. udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
  1693. udc->num_ep = pdata->num_ep;
  1694. INIT_LIST_HEAD(&eps[0].ep.ep_list);
  1695. for (i = 0; i < pdata->num_ep; i++) {
  1696. struct usba_ep *ep = &eps[i];
  1697. ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
  1698. ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
  1699. ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
  1700. ep->ep.ops = &usba_ep_ops;
  1701. ep->ep.name = pdata->ep[i].name;
  1702. ep->fifo_size = pdata->ep[i].fifo_size;
  1703. usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size);
  1704. ep->udc = udc;
  1705. INIT_LIST_HEAD(&ep->queue);
  1706. ep->nr_banks = pdata->ep[i].nr_banks;
  1707. ep->index = pdata->ep[i].index;
  1708. ep->can_dma = pdata->ep[i].can_dma;
  1709. ep->can_isoc = pdata->ep[i].can_isoc;
  1710. if (i == 0) {
  1711. ep->ep.caps.type_control = true;
  1712. } else {
  1713. ep->ep.caps.type_iso = ep->can_isoc;
  1714. ep->ep.caps.type_bulk = true;
  1715. ep->ep.caps.type_int = true;
  1716. }
  1717. ep->ep.caps.dir_in = true;
  1718. ep->ep.caps.dir_out = true;
  1719. if (i)
  1720. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  1721. }
  1722. return eps;
  1723. }
  1724. static int usba_udc_probe(struct platform_device *pdev)
  1725. {
  1726. struct resource *regs, *fifo;
  1727. struct clk *pclk, *hclk;
  1728. struct usba_udc *udc;
  1729. int irq, ret, i;
  1730. udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
  1731. if (!udc)
  1732. return -ENOMEM;
  1733. udc->gadget = usba_gadget_template;
  1734. INIT_LIST_HEAD(&udc->gadget.ep_list);
  1735. regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
  1736. fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
  1737. if (!regs || !fifo)
  1738. return -ENXIO;
  1739. irq = platform_get_irq(pdev, 0);
  1740. if (irq < 0)
  1741. return irq;
  1742. pclk = devm_clk_get(&pdev->dev, "pclk");
  1743. if (IS_ERR(pclk))
  1744. return PTR_ERR(pclk);
  1745. hclk = devm_clk_get(&pdev->dev, "hclk");
  1746. if (IS_ERR(hclk))
  1747. return PTR_ERR(hclk);
  1748. spin_lock_init(&udc->lock);
  1749. mutex_init(&udc->vbus_mutex);
  1750. udc->pdev = pdev;
  1751. udc->pclk = pclk;
  1752. udc->hclk = hclk;
  1753. udc->vbus_pin = -ENODEV;
  1754. ret = -ENOMEM;
  1755. udc->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
  1756. if (!udc->regs) {
  1757. dev_err(&pdev->dev, "Unable to map I/O memory, aborting.\n");
  1758. return ret;
  1759. }
  1760. dev_info(&pdev->dev, "MMIO registers at 0x%08lx mapped at %p\n",
  1761. (unsigned long)regs->start, udc->regs);
  1762. udc->fifo = devm_ioremap(&pdev->dev, fifo->start, resource_size(fifo));
  1763. if (!udc->fifo) {
  1764. dev_err(&pdev->dev, "Unable to map FIFO, aborting.\n");
  1765. return ret;
  1766. }
  1767. dev_info(&pdev->dev, "FIFO at 0x%08lx mapped at %p\n",
  1768. (unsigned long)fifo->start, udc->fifo);
  1769. platform_set_drvdata(pdev, udc);
  1770. /* Make sure we start from a clean slate */
  1771. ret = clk_prepare_enable(pclk);
  1772. if (ret) {
  1773. dev_err(&pdev->dev, "Unable to enable pclk, aborting.\n");
  1774. return ret;
  1775. }
  1776. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1777. clk_disable_unprepare(pclk);
  1778. if (pdev->dev.of_node)
  1779. udc->usba_ep = atmel_udc_of_init(pdev, udc);
  1780. else
  1781. udc->usba_ep = usba_udc_pdata(pdev, udc);
  1782. toggle_bias(udc, 0);
  1783. if (IS_ERR(udc->usba_ep))
  1784. return PTR_ERR(udc->usba_ep);
  1785. ret = devm_request_irq(&pdev->dev, irq, usba_udc_irq, 0,
  1786. "atmel_usba_udc", udc);
  1787. if (ret) {
  1788. dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
  1789. irq, ret);
  1790. return ret;
  1791. }
  1792. udc->irq = irq;
  1793. if (gpio_is_valid(udc->vbus_pin)) {
  1794. if (!devm_gpio_request(&pdev->dev, udc->vbus_pin, "atmel_usba_udc")) {
  1795. irq_set_status_flags(gpio_to_irq(udc->vbus_pin),
  1796. IRQ_NOAUTOEN);
  1797. ret = devm_request_threaded_irq(&pdev->dev,
  1798. gpio_to_irq(udc->vbus_pin), NULL,
  1799. usba_vbus_irq_thread, IRQF_ONESHOT,
  1800. "atmel_usba_udc", udc);
  1801. if (ret) {
  1802. udc->vbus_pin = -ENODEV;
  1803. dev_warn(&udc->pdev->dev,
  1804. "failed to request vbus irq; "
  1805. "assuming always on\n");
  1806. }
  1807. } else {
  1808. /* gpio_request fail so use -EINVAL for gpio_is_valid */
  1809. udc->vbus_pin = -EINVAL;
  1810. }
  1811. }
  1812. ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
  1813. if (ret)
  1814. return ret;
  1815. device_init_wakeup(&pdev->dev, 1);
  1816. usba_init_debugfs(udc);
  1817. for (i = 1; i < udc->num_ep; i++)
  1818. usba_ep_init_debugfs(udc, &udc->usba_ep[i]);
  1819. return 0;
  1820. }
  1821. static int usba_udc_remove(struct platform_device *pdev)
  1822. {
  1823. struct usba_udc *udc;
  1824. int i;
  1825. udc = platform_get_drvdata(pdev);
  1826. device_init_wakeup(&pdev->dev, 0);
  1827. usb_del_gadget_udc(&udc->gadget);
  1828. for (i = 1; i < udc->num_ep; i++)
  1829. usba_ep_cleanup_debugfs(&udc->usba_ep[i]);
  1830. usba_cleanup_debugfs(udc);
  1831. return 0;
  1832. }
  1833. #ifdef CONFIG_PM_SLEEP
  1834. static int usba_udc_suspend(struct device *dev)
  1835. {
  1836. struct usba_udc *udc = dev_get_drvdata(dev);
  1837. /* Not started */
  1838. if (!udc->driver)
  1839. return 0;
  1840. mutex_lock(&udc->vbus_mutex);
  1841. if (!device_may_wakeup(dev)) {
  1842. usba_stop(udc);
  1843. goto out;
  1844. }
  1845. /*
  1846. * Device may wake up. We stay clocked if we failed
  1847. * to request vbus irq, assuming always on.
  1848. */
  1849. if (gpio_is_valid(udc->vbus_pin)) {
  1850. usba_stop(udc);
  1851. enable_irq_wake(gpio_to_irq(udc->vbus_pin));
  1852. }
  1853. out:
  1854. mutex_unlock(&udc->vbus_mutex);
  1855. return 0;
  1856. }
  1857. static int usba_udc_resume(struct device *dev)
  1858. {
  1859. struct usba_udc *udc = dev_get_drvdata(dev);
  1860. /* Not started */
  1861. if (!udc->driver)
  1862. return 0;
  1863. if (device_may_wakeup(dev) && gpio_is_valid(udc->vbus_pin))
  1864. disable_irq_wake(gpio_to_irq(udc->vbus_pin));
  1865. /* If Vbus is present, enable the controller and wait for reset */
  1866. mutex_lock(&udc->vbus_mutex);
  1867. udc->vbus_prev = vbus_is_present(udc);
  1868. if (udc->vbus_prev)
  1869. usba_start(udc);
  1870. mutex_unlock(&udc->vbus_mutex);
  1871. return 0;
  1872. }
  1873. #endif
  1874. static SIMPLE_DEV_PM_OPS(usba_udc_pm_ops, usba_udc_suspend, usba_udc_resume);
  1875. static struct platform_driver udc_driver = {
  1876. .remove = usba_udc_remove,
  1877. .driver = {
  1878. .name = "atmel_usba_udc",
  1879. .pm = &usba_udc_pm_ops,
  1880. .of_match_table = of_match_ptr(atmel_udc_dt_ids),
  1881. },
  1882. };
  1883. module_platform_driver_probe(udc_driver, usba_udc_probe);
  1884. MODULE_DESCRIPTION("Atmel USBA UDC driver");
  1885. MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
  1886. MODULE_LICENSE("GPL");
  1887. MODULE_ALIAS("platform:atmel_usba_udc");