core.c 33 KB

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  1. /**
  2. * core.c - DesignWare USB3 DRD Controller Core file
  3. *
  4. * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  5. *
  6. * Authors: Felipe Balbi <balbi@ti.com>,
  7. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  8. *
  9. * This program is free software: you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 of
  11. * the License as published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  20. */
  21. #include <linux/version.h>
  22. #include <linux/module.h>
  23. #include <linux/kernel.h>
  24. #include <linux/slab.h>
  25. #include <linux/spinlock.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/pm_runtime.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/ioport.h>
  30. #include <linux/io.h>
  31. #include <linux/list.h>
  32. #include <linux/delay.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/of.h>
  35. #include <linux/acpi.h>
  36. #include <linux/pinctrl/consumer.h>
  37. #include <linux/usb/ch9.h>
  38. #include <linux/usb/gadget.h>
  39. #include <linux/usb/of.h>
  40. #include <linux/usb/otg.h>
  41. #include "core.h"
  42. #include "gadget.h"
  43. #include "io.h"
  44. #include "debug.h"
  45. #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
  46. /**
  47. * dwc3_get_dr_mode - Validates and sets dr_mode
  48. * @dwc: pointer to our context structure
  49. */
  50. static int dwc3_get_dr_mode(struct dwc3 *dwc)
  51. {
  52. enum usb_dr_mode mode;
  53. struct device *dev = dwc->dev;
  54. unsigned int hw_mode;
  55. if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  56. dwc->dr_mode = USB_DR_MODE_OTG;
  57. mode = dwc->dr_mode;
  58. hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  59. switch (hw_mode) {
  60. case DWC3_GHWPARAMS0_MODE_GADGET:
  61. if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  62. dev_err(dev,
  63. "Controller does not support host mode.\n");
  64. return -EINVAL;
  65. }
  66. mode = USB_DR_MODE_PERIPHERAL;
  67. break;
  68. case DWC3_GHWPARAMS0_MODE_HOST:
  69. if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  70. dev_err(dev,
  71. "Controller does not support device mode.\n");
  72. return -EINVAL;
  73. }
  74. mode = USB_DR_MODE_HOST;
  75. break;
  76. default:
  77. if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  78. mode = USB_DR_MODE_HOST;
  79. else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  80. mode = USB_DR_MODE_PERIPHERAL;
  81. }
  82. if (mode != dwc->dr_mode) {
  83. dev_warn(dev,
  84. "Configuration mismatch. dr_mode forced to %s\n",
  85. mode == USB_DR_MODE_HOST ? "host" : "gadget");
  86. dwc->dr_mode = mode;
  87. }
  88. return 0;
  89. }
  90. void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  91. {
  92. u32 reg;
  93. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  94. reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  95. reg |= DWC3_GCTL_PRTCAPDIR(mode);
  96. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  97. }
  98. u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
  99. {
  100. struct dwc3 *dwc = dep->dwc;
  101. u32 reg;
  102. dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
  103. DWC3_GDBGFIFOSPACE_NUM(dep->number) |
  104. DWC3_GDBGFIFOSPACE_TYPE(type));
  105. reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
  106. return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
  107. }
  108. /**
  109. * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  110. * @dwc: pointer to our context structure
  111. */
  112. static int dwc3_core_soft_reset(struct dwc3 *dwc)
  113. {
  114. u32 reg;
  115. int retries = 1000;
  116. int ret;
  117. usb_phy_init(dwc->usb2_phy);
  118. usb_phy_init(dwc->usb3_phy);
  119. ret = phy_init(dwc->usb2_generic_phy);
  120. if (ret < 0)
  121. return ret;
  122. ret = phy_init(dwc->usb3_generic_phy);
  123. if (ret < 0) {
  124. phy_exit(dwc->usb2_generic_phy);
  125. return ret;
  126. }
  127. /*
  128. * We're resetting only the device side because, if we're in host mode,
  129. * XHCI driver will reset the host block. If dwc3 was configured for
  130. * host-only mode, then we can return early.
  131. */
  132. if (dwc->dr_mode == USB_DR_MODE_HOST)
  133. return 0;
  134. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  135. reg |= DWC3_DCTL_CSFTRST;
  136. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  137. do {
  138. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  139. if (!(reg & DWC3_DCTL_CSFTRST))
  140. return 0;
  141. udelay(1);
  142. } while (--retries);
  143. return -ETIMEDOUT;
  144. }
  145. /*
  146. * dwc3_frame_length_adjustment - Adjusts frame length if required
  147. * @dwc3: Pointer to our controller context structure
  148. */
  149. static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
  150. {
  151. u32 reg;
  152. u32 dft;
  153. if (dwc->revision < DWC3_REVISION_250A)
  154. return;
  155. if (dwc->fladj == 0)
  156. return;
  157. reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
  158. dft = reg & DWC3_GFLADJ_30MHZ_MASK;
  159. if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
  160. "request value same as default, ignoring\n")) {
  161. reg &= ~DWC3_GFLADJ_30MHZ_MASK;
  162. reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
  163. dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
  164. }
  165. }
  166. /**
  167. * dwc3_free_one_event_buffer - Frees one event buffer
  168. * @dwc: Pointer to our controller context structure
  169. * @evt: Pointer to event buffer to be freed
  170. */
  171. static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
  172. struct dwc3_event_buffer *evt)
  173. {
  174. dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
  175. }
  176. /**
  177. * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
  178. * @dwc: Pointer to our controller context structure
  179. * @length: size of the event buffer
  180. *
  181. * Returns a pointer to the allocated event buffer structure on success
  182. * otherwise ERR_PTR(errno).
  183. */
  184. static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
  185. unsigned length)
  186. {
  187. struct dwc3_event_buffer *evt;
  188. evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
  189. if (!evt)
  190. return ERR_PTR(-ENOMEM);
  191. evt->dwc = dwc;
  192. evt->length = length;
  193. evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
  194. if (!evt->cache)
  195. return ERR_PTR(-ENOMEM);
  196. evt->buf = dma_alloc_coherent(dwc->sysdev, length,
  197. &evt->dma, GFP_KERNEL);
  198. if (!evt->buf)
  199. return ERR_PTR(-ENOMEM);
  200. return evt;
  201. }
  202. /**
  203. * dwc3_free_event_buffers - frees all allocated event buffers
  204. * @dwc: Pointer to our controller context structure
  205. */
  206. static void dwc3_free_event_buffers(struct dwc3 *dwc)
  207. {
  208. struct dwc3_event_buffer *evt;
  209. evt = dwc->ev_buf;
  210. if (evt)
  211. dwc3_free_one_event_buffer(dwc, evt);
  212. }
  213. /**
  214. * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
  215. * @dwc: pointer to our controller context structure
  216. * @length: size of event buffer
  217. *
  218. * Returns 0 on success otherwise negative errno. In the error case, dwc
  219. * may contain some buffers allocated but not all which were requested.
  220. */
  221. static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
  222. {
  223. struct dwc3_event_buffer *evt;
  224. evt = dwc3_alloc_one_event_buffer(dwc, length);
  225. if (IS_ERR(evt)) {
  226. dev_err(dwc->dev, "can't allocate event buffer\n");
  227. return PTR_ERR(evt);
  228. }
  229. dwc->ev_buf = evt;
  230. return 0;
  231. }
  232. /**
  233. * dwc3_event_buffers_setup - setup our allocated event buffers
  234. * @dwc: pointer to our controller context structure
  235. *
  236. * Returns 0 on success otherwise negative errno.
  237. */
  238. static int dwc3_event_buffers_setup(struct dwc3 *dwc)
  239. {
  240. struct dwc3_event_buffer *evt;
  241. evt = dwc->ev_buf;
  242. evt->lpos = 0;
  243. dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
  244. lower_32_bits(evt->dma));
  245. dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
  246. upper_32_bits(evt->dma));
  247. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
  248. DWC3_GEVNTSIZ_SIZE(evt->length));
  249. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
  250. return 0;
  251. }
  252. static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
  253. {
  254. struct dwc3_event_buffer *evt;
  255. evt = dwc->ev_buf;
  256. evt->lpos = 0;
  257. dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
  258. dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
  259. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
  260. | DWC3_GEVNTSIZ_SIZE(0));
  261. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
  262. }
  263. static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
  264. {
  265. if (!dwc->has_hibernation)
  266. return 0;
  267. if (!dwc->nr_scratch)
  268. return 0;
  269. dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
  270. DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
  271. if (!dwc->scratchbuf)
  272. return -ENOMEM;
  273. return 0;
  274. }
  275. static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
  276. {
  277. dma_addr_t scratch_addr;
  278. u32 param;
  279. int ret;
  280. if (!dwc->has_hibernation)
  281. return 0;
  282. if (!dwc->nr_scratch)
  283. return 0;
  284. /* should never fall here */
  285. if (!WARN_ON(dwc->scratchbuf))
  286. return 0;
  287. scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
  288. dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
  289. DMA_BIDIRECTIONAL);
  290. if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
  291. dev_err(dwc->sysdev, "failed to map scratch buffer\n");
  292. ret = -EFAULT;
  293. goto err0;
  294. }
  295. dwc->scratch_addr = scratch_addr;
  296. param = lower_32_bits(scratch_addr);
  297. ret = dwc3_send_gadget_generic_command(dwc,
  298. DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
  299. if (ret < 0)
  300. goto err1;
  301. param = upper_32_bits(scratch_addr);
  302. ret = dwc3_send_gadget_generic_command(dwc,
  303. DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
  304. if (ret < 0)
  305. goto err1;
  306. return 0;
  307. err1:
  308. dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
  309. DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
  310. err0:
  311. return ret;
  312. }
  313. static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
  314. {
  315. if (!dwc->has_hibernation)
  316. return;
  317. if (!dwc->nr_scratch)
  318. return;
  319. /* should never fall here */
  320. if (!WARN_ON(dwc->scratchbuf))
  321. return;
  322. dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
  323. DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
  324. kfree(dwc->scratchbuf);
  325. }
  326. static void dwc3_core_num_eps(struct dwc3 *dwc)
  327. {
  328. struct dwc3_hwparams *parms = &dwc->hwparams;
  329. dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
  330. dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
  331. }
  332. static void dwc3_cache_hwparams(struct dwc3 *dwc)
  333. {
  334. struct dwc3_hwparams *parms = &dwc->hwparams;
  335. parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
  336. parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
  337. parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
  338. parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
  339. parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
  340. parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
  341. parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
  342. parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
  343. parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
  344. }
  345. /**
  346. * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
  347. * @dwc: Pointer to our controller context structure
  348. *
  349. * Returns 0 on success. The USB PHY interfaces are configured but not
  350. * initialized. The PHY interfaces and the PHYs get initialized together with
  351. * the core in dwc3_core_init.
  352. */
  353. static int dwc3_phy_setup(struct dwc3 *dwc)
  354. {
  355. u32 reg;
  356. int ret;
  357. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  358. /*
  359. * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
  360. * to '0' during coreConsultant configuration. So default value
  361. * will be '0' when the core is reset. Application needs to set it
  362. * to '1' after the core initialization is completed.
  363. */
  364. if (dwc->revision > DWC3_REVISION_194A)
  365. reg |= DWC3_GUSB3PIPECTL_SUSPHY;
  366. if (dwc->u2ss_inp3_quirk)
  367. reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
  368. if (dwc->dis_rxdet_inp3_quirk)
  369. reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
  370. if (dwc->req_p1p2p3_quirk)
  371. reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
  372. if (dwc->del_p1p2p3_quirk)
  373. reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
  374. if (dwc->del_phy_power_chg_quirk)
  375. reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
  376. if (dwc->lfps_filter_quirk)
  377. reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
  378. if (dwc->rx_detect_poll_quirk)
  379. reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
  380. if (dwc->tx_de_emphasis_quirk)
  381. reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
  382. if (dwc->dis_u3_susphy_quirk)
  383. reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
  384. if (dwc->dis_del_phy_power_chg_quirk)
  385. reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
  386. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  387. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  388. /* Select the HS PHY interface */
  389. switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
  390. case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
  391. if (dwc->hsphy_interface &&
  392. !strncmp(dwc->hsphy_interface, "utmi", 4)) {
  393. reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
  394. break;
  395. } else if (dwc->hsphy_interface &&
  396. !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
  397. reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
  398. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  399. } else {
  400. /* Relying on default value. */
  401. if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
  402. break;
  403. }
  404. /* FALLTHROUGH */
  405. case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
  406. ret = dwc3_ulpi_init(dwc);
  407. if (ret)
  408. return ret;
  409. /* FALLTHROUGH */
  410. default:
  411. break;
  412. }
  413. switch (dwc->hsphy_mode) {
  414. case USBPHY_INTERFACE_MODE_UTMI:
  415. reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
  416. DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
  417. reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
  418. DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
  419. break;
  420. case USBPHY_INTERFACE_MODE_UTMIW:
  421. reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
  422. DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
  423. reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
  424. DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
  425. break;
  426. default:
  427. break;
  428. }
  429. /*
  430. * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
  431. * '0' during coreConsultant configuration. So default value will
  432. * be '0' when the core is reset. Application needs to set it to
  433. * '1' after the core initialization is completed.
  434. */
  435. if (dwc->revision > DWC3_REVISION_194A)
  436. reg |= DWC3_GUSB2PHYCFG_SUSPHY;
  437. if (dwc->dis_u2_susphy_quirk)
  438. reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
  439. if (dwc->dis_enblslpm_quirk)
  440. reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
  441. if (dwc->dis_u2_freeclk_exists_quirk)
  442. reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
  443. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  444. return 0;
  445. }
  446. static void dwc3_core_exit(struct dwc3 *dwc)
  447. {
  448. dwc3_event_buffers_cleanup(dwc);
  449. usb_phy_shutdown(dwc->usb2_phy);
  450. usb_phy_shutdown(dwc->usb3_phy);
  451. phy_exit(dwc->usb2_generic_phy);
  452. phy_exit(dwc->usb3_generic_phy);
  453. usb_phy_set_suspend(dwc->usb2_phy, 1);
  454. usb_phy_set_suspend(dwc->usb3_phy, 1);
  455. phy_power_off(dwc->usb2_generic_phy);
  456. phy_power_off(dwc->usb3_generic_phy);
  457. }
  458. static bool dwc3_core_is_valid(struct dwc3 *dwc)
  459. {
  460. u32 reg;
  461. reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
  462. /* This should read as U3 followed by revision number */
  463. if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
  464. /* Detected DWC_usb3 IP */
  465. dwc->revision = reg;
  466. } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
  467. /* Detected DWC_usb31 IP */
  468. dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
  469. dwc->revision |= DWC3_REVISION_IS_DWC31;
  470. } else {
  471. return false;
  472. }
  473. return true;
  474. }
  475. static void dwc3_core_setup_global_control(struct dwc3 *dwc)
  476. {
  477. u32 hwparams4 = dwc->hwparams.hwparams4;
  478. u32 reg;
  479. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  480. reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
  481. switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
  482. case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
  483. /**
  484. * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
  485. * issue which would cause xHCI compliance tests to fail.
  486. *
  487. * Because of that we cannot enable clock gating on such
  488. * configurations.
  489. *
  490. * Refers to:
  491. *
  492. * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
  493. * SOF/ITP Mode Used
  494. */
  495. if ((dwc->dr_mode == USB_DR_MODE_HOST ||
  496. dwc->dr_mode == USB_DR_MODE_OTG) &&
  497. (dwc->revision >= DWC3_REVISION_210A &&
  498. dwc->revision <= DWC3_REVISION_250A))
  499. reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
  500. else
  501. reg &= ~DWC3_GCTL_DSBLCLKGTNG;
  502. break;
  503. case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
  504. /* enable hibernation here */
  505. dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
  506. /*
  507. * REVISIT Enabling this bit so that host-mode hibernation
  508. * will work. Device-mode hibernation is not yet implemented.
  509. */
  510. reg |= DWC3_GCTL_GBLHIBERNATIONEN;
  511. break;
  512. default:
  513. /* nothing */
  514. break;
  515. }
  516. /* check if current dwc3 is on simulation board */
  517. if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
  518. dev_info(dwc->dev, "Running with FPGA optmizations\n");
  519. dwc->is_fpga = true;
  520. }
  521. WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
  522. "disable_scramble cannot be used on non-FPGA builds\n");
  523. if (dwc->disable_scramble_quirk && dwc->is_fpga)
  524. reg |= DWC3_GCTL_DISSCRAMBLE;
  525. else
  526. reg &= ~DWC3_GCTL_DISSCRAMBLE;
  527. if (dwc->u2exit_lfps_quirk)
  528. reg |= DWC3_GCTL_U2EXIT_LFPS;
  529. /*
  530. * WORKAROUND: DWC3 revisions <1.90a have a bug
  531. * where the device can fail to connect at SuperSpeed
  532. * and falls back to high-speed mode which causes
  533. * the device to enter a Connect/Disconnect loop
  534. */
  535. if (dwc->revision < DWC3_REVISION_190A)
  536. reg |= DWC3_GCTL_U2RSTECN;
  537. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  538. }
  539. /**
  540. * dwc3_core_init - Low-level initialization of DWC3 Core
  541. * @dwc: Pointer to our controller context structure
  542. *
  543. * Returns 0 on success otherwise negative errno.
  544. */
  545. static int dwc3_core_init(struct dwc3 *dwc)
  546. {
  547. u32 reg;
  548. int ret;
  549. if (!dwc3_core_is_valid(dwc)) {
  550. dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
  551. ret = -ENODEV;
  552. goto err0;
  553. }
  554. /*
  555. * Write Linux Version Code to our GUID register so it's easy to figure
  556. * out which kernel version a bug was found.
  557. */
  558. dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
  559. /* Handle USB2.0-only core configuration */
  560. if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
  561. DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
  562. if (dwc->maximum_speed == USB_SPEED_SUPER)
  563. dwc->maximum_speed = USB_SPEED_HIGH;
  564. }
  565. ret = dwc3_core_soft_reset(dwc);
  566. if (ret)
  567. goto err0;
  568. ret = dwc3_phy_setup(dwc);
  569. if (ret)
  570. goto err0;
  571. dwc3_core_setup_global_control(dwc);
  572. dwc3_core_num_eps(dwc);
  573. ret = dwc3_setup_scratch_buffers(dwc);
  574. if (ret)
  575. goto err1;
  576. /* Adjust Frame Length */
  577. dwc3_frame_length_adjustment(dwc);
  578. usb_phy_set_suspend(dwc->usb2_phy, 0);
  579. usb_phy_set_suspend(dwc->usb3_phy, 0);
  580. ret = phy_power_on(dwc->usb2_generic_phy);
  581. if (ret < 0)
  582. goto err2;
  583. ret = phy_power_on(dwc->usb3_generic_phy);
  584. if (ret < 0)
  585. goto err3;
  586. ret = dwc3_event_buffers_setup(dwc);
  587. if (ret) {
  588. dev_err(dwc->dev, "failed to setup event buffers\n");
  589. goto err4;
  590. }
  591. switch (dwc->dr_mode) {
  592. case USB_DR_MODE_PERIPHERAL:
  593. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
  594. break;
  595. case USB_DR_MODE_HOST:
  596. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
  597. break;
  598. case USB_DR_MODE_OTG:
  599. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
  600. break;
  601. default:
  602. dev_warn(dwc->dev, "Unsupported mode %d\n", dwc->dr_mode);
  603. break;
  604. }
  605. /*
  606. * ENDXFER polling is available on version 3.10a and later of
  607. * the DWC_usb3 controller. It is NOT available in the
  608. * DWC_usb31 controller.
  609. */
  610. if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
  611. reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
  612. reg |= DWC3_GUCTL2_RST_ACTBITLATER;
  613. dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
  614. }
  615. /*
  616. * Enable hardware control of sending remote wakeup in HS when
  617. * the device is in the L1 state.
  618. */
  619. if (dwc->revision >= DWC3_REVISION_290A) {
  620. reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
  621. reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
  622. dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
  623. }
  624. return 0;
  625. err4:
  626. phy_power_off(dwc->usb3_generic_phy);
  627. err3:
  628. phy_power_off(dwc->usb2_generic_phy);
  629. err2:
  630. usb_phy_set_suspend(dwc->usb2_phy, 1);
  631. usb_phy_set_suspend(dwc->usb3_phy, 1);
  632. err1:
  633. usb_phy_shutdown(dwc->usb2_phy);
  634. usb_phy_shutdown(dwc->usb3_phy);
  635. phy_exit(dwc->usb2_generic_phy);
  636. phy_exit(dwc->usb3_generic_phy);
  637. err0:
  638. return ret;
  639. }
  640. static int dwc3_core_get_phy(struct dwc3 *dwc)
  641. {
  642. struct device *dev = dwc->dev;
  643. struct device_node *node = dev->of_node;
  644. int ret;
  645. if (node) {
  646. dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
  647. dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
  648. } else {
  649. dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
  650. dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
  651. }
  652. if (IS_ERR(dwc->usb2_phy)) {
  653. ret = PTR_ERR(dwc->usb2_phy);
  654. if (ret == -ENXIO || ret == -ENODEV) {
  655. dwc->usb2_phy = NULL;
  656. } else if (ret == -EPROBE_DEFER) {
  657. return ret;
  658. } else {
  659. dev_err(dev, "no usb2 phy configured\n");
  660. return ret;
  661. }
  662. }
  663. if (IS_ERR(dwc->usb3_phy)) {
  664. ret = PTR_ERR(dwc->usb3_phy);
  665. if (ret == -ENXIO || ret == -ENODEV) {
  666. dwc->usb3_phy = NULL;
  667. } else if (ret == -EPROBE_DEFER) {
  668. return ret;
  669. } else {
  670. dev_err(dev, "no usb3 phy configured\n");
  671. return ret;
  672. }
  673. }
  674. dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
  675. if (IS_ERR(dwc->usb2_generic_phy)) {
  676. ret = PTR_ERR(dwc->usb2_generic_phy);
  677. if (ret == -ENOSYS || ret == -ENODEV) {
  678. dwc->usb2_generic_phy = NULL;
  679. } else if (ret == -EPROBE_DEFER) {
  680. return ret;
  681. } else {
  682. dev_err(dev, "no usb2 phy configured\n");
  683. return ret;
  684. }
  685. }
  686. dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
  687. if (IS_ERR(dwc->usb3_generic_phy)) {
  688. ret = PTR_ERR(dwc->usb3_generic_phy);
  689. if (ret == -ENOSYS || ret == -ENODEV) {
  690. dwc->usb3_generic_phy = NULL;
  691. } else if (ret == -EPROBE_DEFER) {
  692. return ret;
  693. } else {
  694. dev_err(dev, "no usb3 phy configured\n");
  695. return ret;
  696. }
  697. }
  698. return 0;
  699. }
  700. static int dwc3_core_init_mode(struct dwc3 *dwc)
  701. {
  702. struct device *dev = dwc->dev;
  703. int ret;
  704. switch (dwc->dr_mode) {
  705. case USB_DR_MODE_PERIPHERAL:
  706. ret = dwc3_gadget_init(dwc);
  707. if (ret) {
  708. if (ret != -EPROBE_DEFER)
  709. dev_err(dev, "failed to initialize gadget\n");
  710. return ret;
  711. }
  712. break;
  713. case USB_DR_MODE_HOST:
  714. ret = dwc3_host_init(dwc);
  715. if (ret) {
  716. if (ret != -EPROBE_DEFER)
  717. dev_err(dev, "failed to initialize host\n");
  718. return ret;
  719. }
  720. break;
  721. case USB_DR_MODE_OTG:
  722. ret = dwc3_host_init(dwc);
  723. if (ret) {
  724. if (ret != -EPROBE_DEFER)
  725. dev_err(dev, "failed to initialize host\n");
  726. return ret;
  727. }
  728. ret = dwc3_gadget_init(dwc);
  729. if (ret) {
  730. if (ret != -EPROBE_DEFER)
  731. dev_err(dev, "failed to initialize gadget\n");
  732. return ret;
  733. }
  734. break;
  735. default:
  736. dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
  737. return -EINVAL;
  738. }
  739. return 0;
  740. }
  741. static void dwc3_core_exit_mode(struct dwc3 *dwc)
  742. {
  743. switch (dwc->dr_mode) {
  744. case USB_DR_MODE_PERIPHERAL:
  745. dwc3_gadget_exit(dwc);
  746. break;
  747. case USB_DR_MODE_HOST:
  748. dwc3_host_exit(dwc);
  749. break;
  750. case USB_DR_MODE_OTG:
  751. dwc3_host_exit(dwc);
  752. dwc3_gadget_exit(dwc);
  753. break;
  754. default:
  755. /* do nothing */
  756. break;
  757. }
  758. }
  759. static void dwc3_get_properties(struct dwc3 *dwc)
  760. {
  761. struct device *dev = dwc->dev;
  762. u8 lpm_nyet_threshold;
  763. u8 tx_de_emphasis;
  764. u8 hird_threshold;
  765. /* default to highest possible threshold */
  766. lpm_nyet_threshold = 0xff;
  767. /* default to -3.5dB de-emphasis */
  768. tx_de_emphasis = 1;
  769. /*
  770. * default to assert utmi_sleep_n and use maximum allowed HIRD
  771. * threshold value of 0b1100
  772. */
  773. hird_threshold = 12;
  774. dwc->maximum_speed = usb_get_maximum_speed(dev);
  775. dwc->dr_mode = usb_get_dr_mode(dev);
  776. dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
  777. dwc->sysdev_is_parent = device_property_read_bool(dev,
  778. "linux,sysdev_is_parent");
  779. if (dwc->sysdev_is_parent)
  780. dwc->sysdev = dwc->dev->parent;
  781. else
  782. dwc->sysdev = dwc->dev;
  783. dwc->has_lpm_erratum = device_property_read_bool(dev,
  784. "snps,has-lpm-erratum");
  785. device_property_read_u8(dev, "snps,lpm-nyet-threshold",
  786. &lpm_nyet_threshold);
  787. dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
  788. "snps,is-utmi-l1-suspend");
  789. device_property_read_u8(dev, "snps,hird-threshold",
  790. &hird_threshold);
  791. dwc->usb3_lpm_capable = device_property_read_bool(dev,
  792. "snps,usb3_lpm_capable");
  793. dwc->disable_scramble_quirk = device_property_read_bool(dev,
  794. "snps,disable_scramble_quirk");
  795. dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
  796. "snps,u2exit_lfps_quirk");
  797. dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
  798. "snps,u2ss_inp3_quirk");
  799. dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
  800. "snps,req_p1p2p3_quirk");
  801. dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
  802. "snps,del_p1p2p3_quirk");
  803. dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
  804. "snps,del_phy_power_chg_quirk");
  805. dwc->lfps_filter_quirk = device_property_read_bool(dev,
  806. "snps,lfps_filter_quirk");
  807. dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
  808. "snps,rx_detect_poll_quirk");
  809. dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
  810. "snps,dis_u3_susphy_quirk");
  811. dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
  812. "snps,dis_u2_susphy_quirk");
  813. dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
  814. "snps,dis_enblslpm_quirk");
  815. dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
  816. "snps,dis_rxdet_inp3_quirk");
  817. dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
  818. "snps,dis-u2-freeclk-exists-quirk");
  819. dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
  820. "snps,dis-del-phy-power-chg-quirk");
  821. dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
  822. "snps,tx_de_emphasis_quirk");
  823. device_property_read_u8(dev, "snps,tx_de_emphasis",
  824. &tx_de_emphasis);
  825. device_property_read_string(dev, "snps,hsphy_interface",
  826. &dwc->hsphy_interface);
  827. device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
  828. &dwc->fladj);
  829. dwc->lpm_nyet_threshold = lpm_nyet_threshold;
  830. dwc->tx_de_emphasis = tx_de_emphasis;
  831. dwc->hird_threshold = hird_threshold
  832. | (dwc->is_utmi_l1_suspend << 4);
  833. dwc->imod_interval = 0;
  834. }
  835. /* check whether the core supports IMOD */
  836. bool dwc3_has_imod(struct dwc3 *dwc)
  837. {
  838. return ((dwc3_is_usb3(dwc) &&
  839. dwc->revision >= DWC3_REVISION_300A) ||
  840. (dwc3_is_usb31(dwc) &&
  841. dwc->revision >= DWC3_USB31_REVISION_120A));
  842. }
  843. static void dwc3_check_params(struct dwc3 *dwc)
  844. {
  845. struct device *dev = dwc->dev;
  846. /* Check for proper value of imod_interval */
  847. if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
  848. dev_warn(dwc->dev, "Interrupt moderation not supported\n");
  849. dwc->imod_interval = 0;
  850. }
  851. /*
  852. * Workaround for STAR 9000961433 which affects only version
  853. * 3.00a of the DWC_usb3 core. This prevents the controller
  854. * interrupt from being masked while handling events. IMOD
  855. * allows us to work around this issue. Enable it for the
  856. * affected version.
  857. */
  858. if (!dwc->imod_interval &&
  859. (dwc->revision == DWC3_REVISION_300A))
  860. dwc->imod_interval = 1;
  861. /* Check the maximum_speed parameter */
  862. switch (dwc->maximum_speed) {
  863. case USB_SPEED_LOW:
  864. case USB_SPEED_FULL:
  865. case USB_SPEED_HIGH:
  866. case USB_SPEED_SUPER:
  867. case USB_SPEED_SUPER_PLUS:
  868. break;
  869. default:
  870. dev_err(dev, "invalid maximum_speed parameter %d\n",
  871. dwc->maximum_speed);
  872. /* fall through */
  873. case USB_SPEED_UNKNOWN:
  874. /* default to superspeed */
  875. dwc->maximum_speed = USB_SPEED_SUPER;
  876. /*
  877. * default to superspeed plus if we are capable.
  878. */
  879. if (dwc3_is_usb31(dwc) &&
  880. (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
  881. DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
  882. dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
  883. break;
  884. }
  885. }
  886. static int dwc3_probe(struct platform_device *pdev)
  887. {
  888. struct device *dev = &pdev->dev;
  889. struct resource *res;
  890. struct dwc3 *dwc;
  891. int ret;
  892. void __iomem *regs;
  893. dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
  894. if (!dwc)
  895. return -ENOMEM;
  896. dwc->dev = dev;
  897. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  898. if (!res) {
  899. dev_err(dev, "missing memory resource\n");
  900. return -ENODEV;
  901. }
  902. dwc->xhci_resources[0].start = res->start;
  903. dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
  904. DWC3_XHCI_REGS_END;
  905. dwc->xhci_resources[0].flags = res->flags;
  906. dwc->xhci_resources[0].name = res->name;
  907. res->start += DWC3_GLOBALS_REGS_START;
  908. /*
  909. * Request memory region but exclude xHCI regs,
  910. * since it will be requested by the xhci-plat driver.
  911. */
  912. regs = devm_ioremap_resource(dev, res);
  913. if (IS_ERR(regs)) {
  914. ret = PTR_ERR(regs);
  915. goto err0;
  916. }
  917. dwc->regs = regs;
  918. dwc->regs_size = resource_size(res);
  919. dwc3_get_properties(dwc);
  920. platform_set_drvdata(pdev, dwc);
  921. dwc3_cache_hwparams(dwc);
  922. ret = dwc3_core_get_phy(dwc);
  923. if (ret)
  924. goto err0;
  925. spin_lock_init(&dwc->lock);
  926. pm_runtime_set_active(dev);
  927. pm_runtime_use_autosuspend(dev);
  928. pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
  929. pm_runtime_enable(dev);
  930. ret = pm_runtime_get_sync(dev);
  931. if (ret < 0)
  932. goto err1;
  933. pm_runtime_forbid(dev);
  934. ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
  935. if (ret) {
  936. dev_err(dwc->dev, "failed to allocate event buffers\n");
  937. ret = -ENOMEM;
  938. goto err2;
  939. }
  940. ret = dwc3_get_dr_mode(dwc);
  941. if (ret)
  942. goto err3;
  943. ret = dwc3_alloc_scratch_buffers(dwc);
  944. if (ret)
  945. goto err3;
  946. ret = dwc3_core_init(dwc);
  947. if (ret) {
  948. dev_err(dev, "failed to initialize core\n");
  949. goto err4;
  950. }
  951. dwc3_check_params(dwc);
  952. ret = dwc3_core_init_mode(dwc);
  953. if (ret)
  954. goto err5;
  955. dwc3_debugfs_init(dwc);
  956. pm_runtime_put(dev);
  957. return 0;
  958. err5:
  959. dwc3_event_buffers_cleanup(dwc);
  960. err4:
  961. dwc3_free_scratch_buffers(dwc);
  962. err3:
  963. dwc3_free_event_buffers(dwc);
  964. dwc3_ulpi_exit(dwc);
  965. err2:
  966. pm_runtime_allow(&pdev->dev);
  967. err1:
  968. pm_runtime_put_sync(&pdev->dev);
  969. pm_runtime_disable(&pdev->dev);
  970. err0:
  971. /*
  972. * restore res->start back to its original value so that, in case the
  973. * probe is deferred, we don't end up getting error in request the
  974. * memory region the next time probe is called.
  975. */
  976. res->start -= DWC3_GLOBALS_REGS_START;
  977. return ret;
  978. }
  979. static int dwc3_remove(struct platform_device *pdev)
  980. {
  981. struct dwc3 *dwc = platform_get_drvdata(pdev);
  982. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  983. pm_runtime_get_sync(&pdev->dev);
  984. /*
  985. * restore res->start back to its original value so that, in case the
  986. * probe is deferred, we don't end up getting error in request the
  987. * memory region the next time probe is called.
  988. */
  989. res->start -= DWC3_GLOBALS_REGS_START;
  990. dwc3_debugfs_exit(dwc);
  991. dwc3_core_exit_mode(dwc);
  992. dwc3_core_exit(dwc);
  993. dwc3_ulpi_exit(dwc);
  994. pm_runtime_put_sync(&pdev->dev);
  995. pm_runtime_allow(&pdev->dev);
  996. pm_runtime_disable(&pdev->dev);
  997. dwc3_free_event_buffers(dwc);
  998. dwc3_free_scratch_buffers(dwc);
  999. return 0;
  1000. }
  1001. #ifdef CONFIG_PM
  1002. static int dwc3_suspend_common(struct dwc3 *dwc)
  1003. {
  1004. unsigned long flags;
  1005. switch (dwc->dr_mode) {
  1006. case USB_DR_MODE_PERIPHERAL:
  1007. case USB_DR_MODE_OTG:
  1008. spin_lock_irqsave(&dwc->lock, flags);
  1009. dwc3_gadget_suspend(dwc);
  1010. spin_unlock_irqrestore(&dwc->lock, flags);
  1011. break;
  1012. case USB_DR_MODE_HOST:
  1013. default:
  1014. /* do nothing */
  1015. break;
  1016. }
  1017. dwc3_core_exit(dwc);
  1018. return 0;
  1019. }
  1020. static int dwc3_resume_common(struct dwc3 *dwc)
  1021. {
  1022. unsigned long flags;
  1023. int ret;
  1024. ret = dwc3_core_init(dwc);
  1025. if (ret)
  1026. return ret;
  1027. switch (dwc->dr_mode) {
  1028. case USB_DR_MODE_PERIPHERAL:
  1029. case USB_DR_MODE_OTG:
  1030. spin_lock_irqsave(&dwc->lock, flags);
  1031. dwc3_gadget_resume(dwc);
  1032. spin_unlock_irqrestore(&dwc->lock, flags);
  1033. /* FALLTHROUGH */
  1034. case USB_DR_MODE_HOST:
  1035. default:
  1036. /* do nothing */
  1037. break;
  1038. }
  1039. return 0;
  1040. }
  1041. static int dwc3_runtime_checks(struct dwc3 *dwc)
  1042. {
  1043. switch (dwc->dr_mode) {
  1044. case USB_DR_MODE_PERIPHERAL:
  1045. case USB_DR_MODE_OTG:
  1046. if (dwc->connected)
  1047. return -EBUSY;
  1048. break;
  1049. case USB_DR_MODE_HOST:
  1050. default:
  1051. /* do nothing */
  1052. break;
  1053. }
  1054. return 0;
  1055. }
  1056. static int dwc3_runtime_suspend(struct device *dev)
  1057. {
  1058. struct dwc3 *dwc = dev_get_drvdata(dev);
  1059. int ret;
  1060. if (dwc3_runtime_checks(dwc))
  1061. return -EBUSY;
  1062. ret = dwc3_suspend_common(dwc);
  1063. if (ret)
  1064. return ret;
  1065. device_init_wakeup(dev, true);
  1066. return 0;
  1067. }
  1068. static int dwc3_runtime_resume(struct device *dev)
  1069. {
  1070. struct dwc3 *dwc = dev_get_drvdata(dev);
  1071. int ret;
  1072. device_init_wakeup(dev, false);
  1073. ret = dwc3_resume_common(dwc);
  1074. if (ret)
  1075. return ret;
  1076. switch (dwc->dr_mode) {
  1077. case USB_DR_MODE_PERIPHERAL:
  1078. case USB_DR_MODE_OTG:
  1079. dwc3_gadget_process_pending_events(dwc);
  1080. break;
  1081. case USB_DR_MODE_HOST:
  1082. default:
  1083. /* do nothing */
  1084. break;
  1085. }
  1086. pm_runtime_mark_last_busy(dev);
  1087. pm_runtime_put(dev);
  1088. return 0;
  1089. }
  1090. static int dwc3_runtime_idle(struct device *dev)
  1091. {
  1092. struct dwc3 *dwc = dev_get_drvdata(dev);
  1093. switch (dwc->dr_mode) {
  1094. case USB_DR_MODE_PERIPHERAL:
  1095. case USB_DR_MODE_OTG:
  1096. if (dwc3_runtime_checks(dwc))
  1097. return -EBUSY;
  1098. break;
  1099. case USB_DR_MODE_HOST:
  1100. default:
  1101. /* do nothing */
  1102. break;
  1103. }
  1104. pm_runtime_mark_last_busy(dev);
  1105. pm_runtime_autosuspend(dev);
  1106. return 0;
  1107. }
  1108. #endif /* CONFIG_PM */
  1109. #ifdef CONFIG_PM_SLEEP
  1110. static int dwc3_suspend(struct device *dev)
  1111. {
  1112. struct dwc3 *dwc = dev_get_drvdata(dev);
  1113. int ret;
  1114. ret = dwc3_suspend_common(dwc);
  1115. if (ret)
  1116. return ret;
  1117. pinctrl_pm_select_sleep_state(dev);
  1118. return 0;
  1119. }
  1120. static int dwc3_resume(struct device *dev)
  1121. {
  1122. struct dwc3 *dwc = dev_get_drvdata(dev);
  1123. int ret;
  1124. pinctrl_pm_select_default_state(dev);
  1125. ret = dwc3_resume_common(dwc);
  1126. if (ret)
  1127. return ret;
  1128. pm_runtime_disable(dev);
  1129. pm_runtime_set_active(dev);
  1130. pm_runtime_enable(dev);
  1131. return 0;
  1132. }
  1133. #endif /* CONFIG_PM_SLEEP */
  1134. static const struct dev_pm_ops dwc3_dev_pm_ops = {
  1135. SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
  1136. SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
  1137. dwc3_runtime_idle)
  1138. };
  1139. #ifdef CONFIG_OF
  1140. static const struct of_device_id of_dwc3_match[] = {
  1141. {
  1142. .compatible = "snps,dwc3"
  1143. },
  1144. {
  1145. .compatible = "synopsys,dwc3"
  1146. },
  1147. { },
  1148. };
  1149. MODULE_DEVICE_TABLE(of, of_dwc3_match);
  1150. #endif
  1151. #ifdef CONFIG_ACPI
  1152. #define ACPI_ID_INTEL_BSW "808622B7"
  1153. static const struct acpi_device_id dwc3_acpi_match[] = {
  1154. { ACPI_ID_INTEL_BSW, 0 },
  1155. { },
  1156. };
  1157. MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
  1158. #endif
  1159. static struct platform_driver dwc3_driver = {
  1160. .probe = dwc3_probe,
  1161. .remove = dwc3_remove,
  1162. .driver = {
  1163. .name = "dwc3",
  1164. .of_match_table = of_match_ptr(of_dwc3_match),
  1165. .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
  1166. .pm = &dwc3_dev_pm_ops,
  1167. },
  1168. };
  1169. module_platform_driver(dwc3_driver);
  1170. MODULE_ALIAS("platform:dwc3");
  1171. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  1172. MODULE_LICENSE("GPL v2");
  1173. MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");