rtc-r7301.c 11 KB

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  1. /*
  2. * EPSON TOYOCOM RTC-7301SF/DG Driver
  3. *
  4. * Copyright (c) 2016 Akinobu Mita <akinobu.mita@gmail.com>
  5. *
  6. * Based on rtc-rp5c01.c
  7. *
  8. * Datasheet: http://www5.epsondevice.com/en/products/parallel/rtc7301sf.html
  9. */
  10. #include <linux/io.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/delay.h>
  14. #include <linux/regmap.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/rtc.h>
  17. #define DRV_NAME "rtc-r7301"
  18. #define RTC7301_1_SEC 0x0 /* Bank 0 and Band 1 */
  19. #define RTC7301_10_SEC 0x1 /* Bank 0 and Band 1 */
  20. #define RTC7301_AE BIT(3)
  21. #define RTC7301_1_MIN 0x2 /* Bank 0 and Band 1 */
  22. #define RTC7301_10_MIN 0x3 /* Bank 0 and Band 1 */
  23. #define RTC7301_1_HOUR 0x4 /* Bank 0 and Band 1 */
  24. #define RTC7301_10_HOUR 0x5 /* Bank 0 and Band 1 */
  25. #define RTC7301_DAY_OF_WEEK 0x6 /* Bank 0 and Band 1 */
  26. #define RTC7301_1_DAY 0x7 /* Bank 0 and Band 1 */
  27. #define RTC7301_10_DAY 0x8 /* Bank 0 and Band 1 */
  28. #define RTC7301_1_MONTH 0x9 /* Bank 0 */
  29. #define RTC7301_10_MONTH 0xa /* Bank 0 */
  30. #define RTC7301_1_YEAR 0xb /* Bank 0 */
  31. #define RTC7301_10_YEAR 0xc /* Bank 0 */
  32. #define RTC7301_100_YEAR 0xd /* Bank 0 */
  33. #define RTC7301_1000_YEAR 0xe /* Bank 0 */
  34. #define RTC7301_ALARM_CONTROL 0xe /* Bank 1 */
  35. #define RTC7301_ALARM_CONTROL_AIE BIT(0)
  36. #define RTC7301_ALARM_CONTROL_AF BIT(1)
  37. #define RTC7301_TIMER_CONTROL 0xe /* Bank 2 */
  38. #define RTC7301_TIMER_CONTROL_TIE BIT(0)
  39. #define RTC7301_TIMER_CONTROL_TF BIT(1)
  40. #define RTC7301_CONTROL 0xf /* All banks */
  41. #define RTC7301_CONTROL_BUSY BIT(0)
  42. #define RTC7301_CONTROL_STOP BIT(1)
  43. #define RTC7301_CONTROL_BANK_SEL_0 BIT(2)
  44. #define RTC7301_CONTROL_BANK_SEL_1 BIT(3)
  45. struct rtc7301_priv {
  46. struct regmap *regmap;
  47. int irq;
  48. spinlock_t lock;
  49. u8 bank;
  50. };
  51. static const struct regmap_config rtc7301_regmap_config = {
  52. .reg_bits = 32,
  53. .val_bits = 8,
  54. .reg_stride = 4,
  55. };
  56. static u8 rtc7301_read(struct rtc7301_priv *priv, unsigned int reg)
  57. {
  58. int reg_stride = regmap_get_reg_stride(priv->regmap);
  59. unsigned int val;
  60. regmap_read(priv->regmap, reg_stride * reg, &val);
  61. return val & 0xf;
  62. }
  63. static void rtc7301_write(struct rtc7301_priv *priv, u8 val, unsigned int reg)
  64. {
  65. int reg_stride = regmap_get_reg_stride(priv->regmap);
  66. regmap_write(priv->regmap, reg_stride * reg, val);
  67. }
  68. static void rtc7301_update_bits(struct rtc7301_priv *priv, unsigned int reg,
  69. u8 mask, u8 val)
  70. {
  71. int reg_stride = regmap_get_reg_stride(priv->regmap);
  72. regmap_update_bits(priv->regmap, reg_stride * reg, mask, val);
  73. }
  74. static int rtc7301_wait_while_busy(struct rtc7301_priv *priv)
  75. {
  76. int retries = 100;
  77. while (retries-- > 0) {
  78. u8 val;
  79. val = rtc7301_read(priv, RTC7301_CONTROL);
  80. if (!(val & RTC7301_CONTROL_BUSY))
  81. return 0;
  82. usleep_range(200, 300);
  83. }
  84. return -ETIMEDOUT;
  85. }
  86. static void rtc7301_stop(struct rtc7301_priv *priv)
  87. {
  88. rtc7301_update_bits(priv, RTC7301_CONTROL, RTC7301_CONTROL_STOP,
  89. RTC7301_CONTROL_STOP);
  90. }
  91. static void rtc7301_start(struct rtc7301_priv *priv)
  92. {
  93. rtc7301_update_bits(priv, RTC7301_CONTROL, RTC7301_CONTROL_STOP, 0);
  94. }
  95. static void rtc7301_select_bank(struct rtc7301_priv *priv, u8 bank)
  96. {
  97. u8 val = 0;
  98. if (bank == priv->bank)
  99. return;
  100. if (bank & BIT(0))
  101. val |= RTC7301_CONTROL_BANK_SEL_0;
  102. if (bank & BIT(1))
  103. val |= RTC7301_CONTROL_BANK_SEL_1;
  104. rtc7301_update_bits(priv, RTC7301_CONTROL,
  105. RTC7301_CONTROL_BANK_SEL_0 |
  106. RTC7301_CONTROL_BANK_SEL_1, val);
  107. priv->bank = bank;
  108. }
  109. static void rtc7301_get_time(struct rtc7301_priv *priv, struct rtc_time *tm,
  110. bool alarm)
  111. {
  112. int year;
  113. tm->tm_sec = rtc7301_read(priv, RTC7301_1_SEC);
  114. tm->tm_sec += (rtc7301_read(priv, RTC7301_10_SEC) & ~RTC7301_AE) * 10;
  115. tm->tm_min = rtc7301_read(priv, RTC7301_1_MIN);
  116. tm->tm_min += (rtc7301_read(priv, RTC7301_10_MIN) & ~RTC7301_AE) * 10;
  117. tm->tm_hour = rtc7301_read(priv, RTC7301_1_HOUR);
  118. tm->tm_hour += (rtc7301_read(priv, RTC7301_10_HOUR) & ~RTC7301_AE) * 10;
  119. tm->tm_mday = rtc7301_read(priv, RTC7301_1_DAY);
  120. tm->tm_mday += (rtc7301_read(priv, RTC7301_10_DAY) & ~RTC7301_AE) * 10;
  121. if (alarm) {
  122. tm->tm_wday = -1;
  123. tm->tm_mon = -1;
  124. tm->tm_year = -1;
  125. tm->tm_yday = -1;
  126. tm->tm_isdst = -1;
  127. return;
  128. }
  129. tm->tm_wday = (rtc7301_read(priv, RTC7301_DAY_OF_WEEK) & ~RTC7301_AE);
  130. tm->tm_mon = rtc7301_read(priv, RTC7301_10_MONTH) * 10 +
  131. rtc7301_read(priv, RTC7301_1_MONTH) - 1;
  132. year = rtc7301_read(priv, RTC7301_1000_YEAR) * 1000 +
  133. rtc7301_read(priv, RTC7301_100_YEAR) * 100 +
  134. rtc7301_read(priv, RTC7301_10_YEAR) * 10 +
  135. rtc7301_read(priv, RTC7301_1_YEAR);
  136. tm->tm_year = year - 1900;
  137. }
  138. static void rtc7301_write_time(struct rtc7301_priv *priv, struct rtc_time *tm,
  139. bool alarm)
  140. {
  141. int year;
  142. rtc7301_write(priv, tm->tm_sec % 10, RTC7301_1_SEC);
  143. rtc7301_write(priv, tm->tm_sec / 10, RTC7301_10_SEC);
  144. rtc7301_write(priv, tm->tm_min % 10, RTC7301_1_MIN);
  145. rtc7301_write(priv, tm->tm_min / 10, RTC7301_10_MIN);
  146. rtc7301_write(priv, tm->tm_hour % 10, RTC7301_1_HOUR);
  147. rtc7301_write(priv, tm->tm_hour / 10, RTC7301_10_HOUR);
  148. rtc7301_write(priv, tm->tm_mday % 10, RTC7301_1_DAY);
  149. rtc7301_write(priv, tm->tm_mday / 10, RTC7301_10_DAY);
  150. /* Don't care for alarm register */
  151. rtc7301_write(priv, alarm ? RTC7301_AE : tm->tm_wday,
  152. RTC7301_DAY_OF_WEEK);
  153. if (alarm)
  154. return;
  155. rtc7301_write(priv, (tm->tm_mon + 1) % 10, RTC7301_1_MONTH);
  156. rtc7301_write(priv, (tm->tm_mon + 1) / 10, RTC7301_10_MONTH);
  157. year = tm->tm_year + 1900;
  158. rtc7301_write(priv, year % 10, RTC7301_1_YEAR);
  159. rtc7301_write(priv, (year / 10) % 10, RTC7301_10_YEAR);
  160. rtc7301_write(priv, (year / 100) % 10, RTC7301_100_YEAR);
  161. rtc7301_write(priv, year / 1000, RTC7301_1000_YEAR);
  162. }
  163. static void rtc7301_alarm_irq(struct rtc7301_priv *priv, unsigned int enabled)
  164. {
  165. rtc7301_update_bits(priv, RTC7301_ALARM_CONTROL,
  166. RTC7301_ALARM_CONTROL_AF |
  167. RTC7301_ALARM_CONTROL_AIE,
  168. enabled ? RTC7301_ALARM_CONTROL_AIE : 0);
  169. }
  170. static int rtc7301_read_time(struct device *dev, struct rtc_time *tm)
  171. {
  172. struct rtc7301_priv *priv = dev_get_drvdata(dev);
  173. unsigned long flags;
  174. int err;
  175. spin_lock_irqsave(&priv->lock, flags);
  176. rtc7301_select_bank(priv, 0);
  177. err = rtc7301_wait_while_busy(priv);
  178. if (!err)
  179. rtc7301_get_time(priv, tm, false);
  180. spin_unlock_irqrestore(&priv->lock, flags);
  181. return err ? err : rtc_valid_tm(tm);
  182. }
  183. static int rtc7301_set_time(struct device *dev, struct rtc_time *tm)
  184. {
  185. struct rtc7301_priv *priv = dev_get_drvdata(dev);
  186. unsigned long flags;
  187. spin_lock_irqsave(&priv->lock, flags);
  188. rtc7301_stop(priv);
  189. usleep_range(200, 300);
  190. rtc7301_select_bank(priv, 0);
  191. rtc7301_write_time(priv, tm, false);
  192. rtc7301_start(priv);
  193. spin_unlock_irqrestore(&priv->lock, flags);
  194. return 0;
  195. }
  196. static int rtc7301_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  197. {
  198. struct rtc7301_priv *priv = dev_get_drvdata(dev);
  199. unsigned long flags;
  200. u8 alrm_ctrl;
  201. if (priv->irq <= 0)
  202. return -EINVAL;
  203. spin_lock_irqsave(&priv->lock, flags);
  204. rtc7301_select_bank(priv, 1);
  205. rtc7301_get_time(priv, &alarm->time, true);
  206. alrm_ctrl = rtc7301_read(priv, RTC7301_ALARM_CONTROL);
  207. alarm->enabled = !!(alrm_ctrl & RTC7301_ALARM_CONTROL_AIE);
  208. alarm->pending = !!(alrm_ctrl & RTC7301_ALARM_CONTROL_AF);
  209. spin_unlock_irqrestore(&priv->lock, flags);
  210. return 0;
  211. }
  212. static int rtc7301_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  213. {
  214. struct rtc7301_priv *priv = dev_get_drvdata(dev);
  215. unsigned long flags;
  216. if (priv->irq <= 0)
  217. return -EINVAL;
  218. spin_lock_irqsave(&priv->lock, flags);
  219. rtc7301_select_bank(priv, 1);
  220. rtc7301_write_time(priv, &alarm->time, true);
  221. rtc7301_alarm_irq(priv, alarm->enabled);
  222. spin_unlock_irqrestore(&priv->lock, flags);
  223. return 0;
  224. }
  225. static int rtc7301_alarm_irq_enable(struct device *dev, unsigned int enabled)
  226. {
  227. struct rtc7301_priv *priv = dev_get_drvdata(dev);
  228. unsigned long flags;
  229. if (priv->irq <= 0)
  230. return -EINVAL;
  231. spin_lock_irqsave(&priv->lock, flags);
  232. rtc7301_select_bank(priv, 1);
  233. rtc7301_alarm_irq(priv, enabled);
  234. spin_unlock_irqrestore(&priv->lock, flags);
  235. return 0;
  236. }
  237. static const struct rtc_class_ops rtc7301_rtc_ops = {
  238. .read_time = rtc7301_read_time,
  239. .set_time = rtc7301_set_time,
  240. .read_alarm = rtc7301_read_alarm,
  241. .set_alarm = rtc7301_set_alarm,
  242. .alarm_irq_enable = rtc7301_alarm_irq_enable,
  243. };
  244. static irqreturn_t rtc7301_irq_handler(int irq, void *dev_id)
  245. {
  246. struct rtc_device *rtc = dev_id;
  247. struct rtc7301_priv *priv = dev_get_drvdata(rtc->dev.parent);
  248. unsigned long flags;
  249. irqreturn_t ret = IRQ_NONE;
  250. u8 alrm_ctrl;
  251. spin_lock_irqsave(&priv->lock, flags);
  252. rtc7301_select_bank(priv, 1);
  253. alrm_ctrl = rtc7301_read(priv, RTC7301_ALARM_CONTROL);
  254. if (alrm_ctrl & RTC7301_ALARM_CONTROL_AF) {
  255. ret = IRQ_HANDLED;
  256. rtc7301_alarm_irq(priv, false);
  257. rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
  258. }
  259. spin_unlock_irqrestore(&priv->lock, flags);
  260. return ret;
  261. }
  262. static void rtc7301_init(struct rtc7301_priv *priv)
  263. {
  264. unsigned long flags;
  265. spin_lock_irqsave(&priv->lock, flags);
  266. rtc7301_select_bank(priv, 2);
  267. rtc7301_write(priv, 0, RTC7301_TIMER_CONTROL);
  268. spin_unlock_irqrestore(&priv->lock, flags);
  269. }
  270. static int __init rtc7301_rtc_probe(struct platform_device *dev)
  271. {
  272. struct resource *res;
  273. void __iomem *regs;
  274. struct rtc7301_priv *priv;
  275. struct rtc_device *rtc;
  276. int ret;
  277. res = platform_get_resource(dev, IORESOURCE_MEM, 0);
  278. if (!res)
  279. return -ENODEV;
  280. priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
  281. if (!priv)
  282. return -ENOMEM;
  283. regs = devm_ioremap_resource(&dev->dev, res);
  284. if (IS_ERR(regs))
  285. return PTR_ERR(regs);
  286. priv->regmap = devm_regmap_init_mmio(&dev->dev, regs,
  287. &rtc7301_regmap_config);
  288. if (IS_ERR(priv->regmap))
  289. return PTR_ERR(priv->regmap);
  290. priv->irq = platform_get_irq(dev, 0);
  291. spin_lock_init(&priv->lock);
  292. priv->bank = -1;
  293. rtc7301_init(priv);
  294. platform_set_drvdata(dev, priv);
  295. rtc = devm_rtc_device_register(&dev->dev, DRV_NAME, &rtc7301_rtc_ops,
  296. THIS_MODULE);
  297. if (IS_ERR(rtc))
  298. return PTR_ERR(rtc);
  299. if (priv->irq > 0) {
  300. ret = devm_request_irq(&dev->dev, priv->irq,
  301. rtc7301_irq_handler, IRQF_SHARED,
  302. dev_name(&dev->dev), rtc);
  303. if (ret) {
  304. priv->irq = 0;
  305. dev_err(&dev->dev, "unable to request IRQ\n");
  306. } else {
  307. device_set_wakeup_capable(&dev->dev, true);
  308. }
  309. }
  310. return 0;
  311. }
  312. #ifdef CONFIG_PM_SLEEP
  313. static int rtc7301_suspend(struct device *dev)
  314. {
  315. struct rtc7301_priv *priv = dev_get_drvdata(dev);
  316. if (device_may_wakeup(dev))
  317. enable_irq_wake(priv->irq);
  318. return 0;
  319. }
  320. static int rtc7301_resume(struct device *dev)
  321. {
  322. struct rtc7301_priv *priv = dev_get_drvdata(dev);
  323. if (device_may_wakeup(dev))
  324. disable_irq_wake(priv->irq);
  325. return 0;
  326. }
  327. #endif
  328. static SIMPLE_DEV_PM_OPS(rtc7301_pm_ops, rtc7301_suspend, rtc7301_resume);
  329. static const struct of_device_id rtc7301_dt_match[] = {
  330. { .compatible = "epson,rtc7301sf" },
  331. { .compatible = "epson,rtc7301dg" },
  332. {}
  333. };
  334. MODULE_DEVICE_TABLE(of, rtc7301_dt_match);
  335. static struct platform_driver rtc7301_rtc_driver = {
  336. .driver = {
  337. .name = DRV_NAME,
  338. .of_match_table = rtc7301_dt_match,
  339. .pm = &rtc7301_pm_ops,
  340. },
  341. };
  342. module_platform_driver_probe(rtc7301_rtc_driver, rtc7301_rtc_probe);
  343. MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");
  344. MODULE_LICENSE("GPL");
  345. MODULE_DESCRIPTION("EPSON TOYOCOM RTC-7301SF/DG Driver");
  346. MODULE_ALIAS("platform:rtc-r7301");