rtc-mcp795.c 6.7 KB

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  1. /*
  2. * SPI Driver for Microchip MCP795 RTC
  3. *
  4. * Copyright (C) Josef Gajdusek <atx@atx.name>
  5. *
  6. * based on other Linux RTC drivers
  7. *
  8. * Device datasheet:
  9. * http://ww1.microchip.com/downloads/en/DeviceDoc/22280A.pdf
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. *
  15. */
  16. #include <linux/module.h>
  17. #include <linux/kernel.h>
  18. #include <linux/device.h>
  19. #include <linux/printk.h>
  20. #include <linux/spi/spi.h>
  21. #include <linux/rtc.h>
  22. #include <linux/of.h>
  23. #include <linux/bcd.h>
  24. #include <linux/delay.h>
  25. /* MCP795 Instructions, see datasheet table 3-1 */
  26. #define MCP795_EEREAD 0x03
  27. #define MCP795_EEWRITE 0x02
  28. #define MCP795_EEWRDI 0x04
  29. #define MCP795_EEWREN 0x06
  30. #define MCP795_SRREAD 0x05
  31. #define MCP795_SRWRITE 0x01
  32. #define MCP795_READ 0x13
  33. #define MCP795_WRITE 0x12
  34. #define MCP795_UNLOCK 0x14
  35. #define MCP795_IDWRITE 0x32
  36. #define MCP795_IDREAD 0x33
  37. #define MCP795_CLRWDT 0x44
  38. #define MCP795_CLRRAM 0x54
  39. /* MCP795 RTCC registers, see datasheet table 4-1 */
  40. #define MCP795_REG_SECONDS 0x01
  41. #define MCP795_REG_DAY 0x04
  42. #define MCP795_REG_MONTH 0x06
  43. #define MCP795_REG_CONTROL 0x08
  44. #define MCP795_ST_BIT BIT(7)
  45. #define MCP795_24_BIT BIT(6)
  46. #define MCP795_LP_BIT BIT(5)
  47. #define MCP795_EXTOSC_BIT BIT(3)
  48. #define MCP795_OSCON_BIT BIT(5)
  49. static int mcp795_rtcc_read(struct device *dev, u8 addr, u8 *buf, u8 count)
  50. {
  51. struct spi_device *spi = to_spi_device(dev);
  52. int ret;
  53. u8 tx[2];
  54. tx[0] = MCP795_READ;
  55. tx[1] = addr;
  56. ret = spi_write_then_read(spi, tx, sizeof(tx), buf, count);
  57. if (ret)
  58. dev_err(dev, "Failed reading %d bytes from address %x.\n",
  59. count, addr);
  60. return ret;
  61. }
  62. static int mcp795_rtcc_write(struct device *dev, u8 addr, u8 *data, u8 count)
  63. {
  64. struct spi_device *spi = to_spi_device(dev);
  65. int ret;
  66. u8 tx[2 + count];
  67. tx[0] = MCP795_WRITE;
  68. tx[1] = addr;
  69. memcpy(&tx[2], data, count);
  70. ret = spi_write(spi, tx, 2 + count);
  71. if (ret)
  72. dev_err(dev, "Failed to write %d bytes to address %x.\n",
  73. count, addr);
  74. return ret;
  75. }
  76. static int mcp795_rtcc_set_bits(struct device *dev, u8 addr, u8 mask, u8 state)
  77. {
  78. int ret;
  79. u8 tmp;
  80. ret = mcp795_rtcc_read(dev, addr, &tmp, 1);
  81. if (ret)
  82. return ret;
  83. if ((tmp & mask) != state) {
  84. tmp = (tmp & ~mask) | state;
  85. ret = mcp795_rtcc_write(dev, addr, &tmp, 1);
  86. }
  87. return ret;
  88. }
  89. static int mcp795_stop_oscillator(struct device *dev, bool *extosc)
  90. {
  91. int retries = 5;
  92. int ret;
  93. u8 data;
  94. ret = mcp795_rtcc_set_bits(dev, MCP795_REG_SECONDS, MCP795_ST_BIT, 0);
  95. if (ret)
  96. return ret;
  97. ret = mcp795_rtcc_read(dev, MCP795_REG_CONTROL, &data, 1);
  98. if (ret)
  99. return ret;
  100. *extosc = !!(data & MCP795_EXTOSC_BIT);
  101. ret = mcp795_rtcc_set_bits(
  102. dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, 0);
  103. if (ret)
  104. return ret;
  105. /* wait for the OSCON bit to clear */
  106. do {
  107. usleep_range(700, 800);
  108. ret = mcp795_rtcc_read(dev, MCP795_REG_DAY, &data, 1);
  109. if (ret)
  110. break;
  111. if (!(data & MCP795_OSCON_BIT))
  112. break;
  113. } while (--retries);
  114. return !retries ? -EIO : ret;
  115. }
  116. static int mcp795_start_oscillator(struct device *dev, bool *extosc)
  117. {
  118. if (extosc) {
  119. u8 data = *extosc ? MCP795_EXTOSC_BIT : 0;
  120. int ret;
  121. ret = mcp795_rtcc_set_bits(
  122. dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, data);
  123. if (ret)
  124. return ret;
  125. }
  126. return mcp795_rtcc_set_bits(
  127. dev, MCP795_REG_SECONDS, MCP795_ST_BIT, MCP795_ST_BIT);
  128. }
  129. static int mcp795_set_time(struct device *dev, struct rtc_time *tim)
  130. {
  131. int ret;
  132. u8 data[7];
  133. bool extosc;
  134. /* Stop RTC and store current value of EXTOSC bit */
  135. ret = mcp795_stop_oscillator(dev, &extosc);
  136. if (ret)
  137. return ret;
  138. /* Read first, so we can leave config bits untouched */
  139. ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
  140. if (ret)
  141. return ret;
  142. data[0] = (data[0] & 0x80) | bin2bcd(tim->tm_sec);
  143. data[1] = (data[1] & 0x80) | bin2bcd(tim->tm_min);
  144. data[2] = bin2bcd(tim->tm_hour);
  145. data[4] = bin2bcd(tim->tm_mday);
  146. data[5] = (data[5] & MCP795_LP_BIT) | bin2bcd(tim->tm_mon + 1);
  147. if (tim->tm_year > 100)
  148. tim->tm_year -= 100;
  149. data[6] = bin2bcd(tim->tm_year);
  150. /* Always write the date and month using a separate Write command.
  151. * This is a workaround for a know silicon issue that some combinations
  152. * of date and month values may result in the date being reset to 1.
  153. */
  154. ret = mcp795_rtcc_write(dev, MCP795_REG_SECONDS, data, 5);
  155. if (ret)
  156. return ret;
  157. ret = mcp795_rtcc_write(dev, MCP795_REG_MONTH, &data[5], 2);
  158. if (ret)
  159. return ret;
  160. /* Start back RTC and restore previous value of EXTOSC bit.
  161. * There is no need to clear EXTOSC bit when the previous value was 0
  162. * because it was already cleared when stopping the RTC oscillator.
  163. */
  164. ret = mcp795_start_oscillator(dev, extosc ? &extosc : NULL);
  165. if (ret)
  166. return ret;
  167. dev_dbg(dev, "Set mcp795: %04d-%02d-%02d %02d:%02d:%02d\n",
  168. tim->tm_year + 1900, tim->tm_mon, tim->tm_mday,
  169. tim->tm_hour, tim->tm_min, tim->tm_sec);
  170. return 0;
  171. }
  172. static int mcp795_read_time(struct device *dev, struct rtc_time *tim)
  173. {
  174. int ret;
  175. u8 data[7];
  176. ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
  177. if (ret)
  178. return ret;
  179. tim->tm_sec = bcd2bin(data[0] & 0x7F);
  180. tim->tm_min = bcd2bin(data[1] & 0x7F);
  181. tim->tm_hour = bcd2bin(data[2] & 0x3F);
  182. tim->tm_mday = bcd2bin(data[4] & 0x3F);
  183. tim->tm_mon = bcd2bin(data[5] & 0x1F) - 1;
  184. tim->tm_year = bcd2bin(data[6]) + 100; /* Assume we are in 20xx */
  185. dev_dbg(dev, "Read from mcp795: %04d-%02d-%02d %02d:%02d:%02d\n",
  186. tim->tm_year + 1900, tim->tm_mon, tim->tm_mday,
  187. tim->tm_hour, tim->tm_min, tim->tm_sec);
  188. return rtc_valid_tm(tim);
  189. }
  190. static const struct rtc_class_ops mcp795_rtc_ops = {
  191. .read_time = mcp795_read_time,
  192. .set_time = mcp795_set_time
  193. };
  194. static int mcp795_probe(struct spi_device *spi)
  195. {
  196. struct rtc_device *rtc;
  197. int ret;
  198. spi->mode = SPI_MODE_0;
  199. spi->bits_per_word = 8;
  200. ret = spi_setup(spi);
  201. if (ret) {
  202. dev_err(&spi->dev, "Unable to setup SPI\n");
  203. return ret;
  204. }
  205. /* Start the oscillator but don't set the value of EXTOSC bit */
  206. mcp795_start_oscillator(&spi->dev, NULL);
  207. /* Clear the 12 hour mode flag*/
  208. mcp795_rtcc_set_bits(&spi->dev, 0x03, MCP795_24_BIT, 0);
  209. rtc = devm_rtc_device_register(&spi->dev, "rtc-mcp795",
  210. &mcp795_rtc_ops, THIS_MODULE);
  211. if (IS_ERR(rtc))
  212. return PTR_ERR(rtc);
  213. spi_set_drvdata(spi, rtc);
  214. return 0;
  215. }
  216. #ifdef CONFIG_OF
  217. static const struct of_device_id mcp795_of_match[] = {
  218. { .compatible = "maxim,mcp795" },
  219. { }
  220. };
  221. MODULE_DEVICE_TABLE(of, mcp795_of_match);
  222. #endif
  223. static struct spi_driver mcp795_driver = {
  224. .driver = {
  225. .name = "rtc-mcp795",
  226. .of_match_table = of_match_ptr(mcp795_of_match),
  227. },
  228. .probe = mcp795_probe,
  229. };
  230. module_spi_driver(mcp795_driver);
  231. MODULE_DESCRIPTION("MCP795 RTC SPI Driver");
  232. MODULE_AUTHOR("Josef Gajdusek <atx@atx.name>");
  233. MODULE_LICENSE("GPL");
  234. MODULE_ALIAS("spi:mcp795");