mac.c 23 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * The full GNU General Public License is included in this distribution in the
  15. * file called LICENSE.
  16. *
  17. * Contact Information:
  18. * wlanfae <wlanfae@realtek.com>
  19. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20. * Hsinchu 300, Taiwan.
  21. *
  22. * Larry Finger <Larry.Finger@lwfinger.net>
  23. *
  24. ****************************************************************************/
  25. #include "../wifi.h"
  26. #include "../pci.h"
  27. #include "../usb.h"
  28. #include "../ps.h"
  29. #include "../cam.h"
  30. #include "../stats.h"
  31. #include "reg.h"
  32. #include "def.h"
  33. #include "phy.h"
  34. #include "rf.h"
  35. #include "dm.h"
  36. #include "mac.h"
  37. #include "trx.h"
  38. #include "../rtl8192c/fw_common.h"
  39. #include <linux/module.h>
  40. /* macro to shorten lines */
  41. #define LINK_Q ui_link_quality
  42. #define RX_EVM rx_evm_percentage
  43. #define RX_SIGQ rx_mimo_sig_qual
  44. void rtl92c_read_chip_version(struct ieee80211_hw *hw)
  45. {
  46. struct rtl_priv *rtlpriv = rtl_priv(hw);
  47. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  48. struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
  49. enum version_8192c chip_version = VERSION_UNKNOWN;
  50. const char *versionid;
  51. u32 value32;
  52. value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
  53. if (value32 & TRP_VAUX_EN) {
  54. chip_version = (value32 & TYPE_ID) ? VERSION_TEST_CHIP_92C :
  55. VERSION_TEST_CHIP_88C;
  56. } else {
  57. /* Normal mass production chip. */
  58. chip_version = NORMAL_CHIP;
  59. chip_version |= ((value32 & TYPE_ID) ? CHIP_92C : 0);
  60. chip_version |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0);
  61. if (IS_VENDOR_UMC(chip_version))
  62. chip_version |= ((value32 & CHIP_VER_RTL_MASK) ?
  63. CHIP_VENDOR_UMC_B_CUT : 0);
  64. if (IS_92C_SERIAL(chip_version)) {
  65. value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
  66. chip_version |= ((CHIP_BONDING_IDENTIFIER(value32) ==
  67. CHIP_BONDING_92C_1T2R) ? CHIP_92C_1T2R : 0);
  68. }
  69. }
  70. rtlhal->version = (enum version_8192c)chip_version;
  71. pr_info("Chip version 0x%x\n", chip_version);
  72. switch (rtlhal->version) {
  73. case VERSION_NORMAL_TSMC_CHIP_92C_1T2R:
  74. versionid = "NORMAL_B_CHIP_92C";
  75. break;
  76. case VERSION_NORMAL_TSMC_CHIP_92C:
  77. versionid = "NORMAL_TSMC_CHIP_92C";
  78. break;
  79. case VERSION_NORMAL_TSMC_CHIP_88C:
  80. versionid = "NORMAL_TSMC_CHIP_88C";
  81. break;
  82. case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
  83. versionid = "NORMAL_UMC_CHIP_i92C_1T2R_A_CUT";
  84. break;
  85. case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
  86. versionid = "NORMAL_UMC_CHIP_92C_A_CUT";
  87. break;
  88. case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
  89. versionid = "NORMAL_UMC_CHIP_88C_A_CUT";
  90. break;
  91. case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
  92. versionid = "NORMAL_UMC_CHIP_92C_1T2R_B_CUT";
  93. break;
  94. case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
  95. versionid = "NORMAL_UMC_CHIP_92C_B_CUT";
  96. break;
  97. case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
  98. versionid = "NORMAL_UMC_CHIP_88C_B_CUT";
  99. break;
  100. case VERSION_TEST_CHIP_92C:
  101. versionid = "TEST_CHIP_92C";
  102. break;
  103. case VERSION_TEST_CHIP_88C:
  104. versionid = "TEST_CHIP_88C";
  105. break;
  106. default:
  107. versionid = "UNKNOWN";
  108. break;
  109. }
  110. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  111. "Chip Version ID: %s\n", versionid);
  112. if (IS_92C_SERIAL(rtlhal->version))
  113. rtlphy->rf_type =
  114. (IS_92C_1T2R(rtlhal->version)) ? RF_1T2R : RF_2T2R;
  115. else
  116. rtlphy->rf_type = RF_1T1R;
  117. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
  118. "Chip RF Type: %s\n",
  119. rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
  120. if (get_rf_type(rtlphy) == RF_1T1R)
  121. rtlpriv->dm.rfpath_rxenable[0] = true;
  122. else
  123. rtlpriv->dm.rfpath_rxenable[0] =
  124. rtlpriv->dm.rfpath_rxenable[1] = true;
  125. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
  126. rtlhal->version);
  127. }
  128. /**
  129. * writeLLT - LLT table write access
  130. * @io: io callback
  131. * @address: LLT logical address.
  132. * @data: LLT data content
  133. *
  134. * Realtek hardware access function.
  135. *
  136. */
  137. bool rtl92c_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
  138. {
  139. struct rtl_priv *rtlpriv = rtl_priv(hw);
  140. bool status = true;
  141. long count = 0;
  142. u32 value = _LLT_INIT_ADDR(address) |
  143. _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
  144. rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
  145. do {
  146. value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
  147. if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
  148. break;
  149. if (count > POLLING_LLT_THRESHOLD) {
  150. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  151. "Failed to polling write LLT done at address %d! _LLT_OP_VALUE(%x)\n",
  152. address, _LLT_OP_VALUE(value));
  153. status = false;
  154. break;
  155. }
  156. } while (++count);
  157. return status;
  158. }
  159. /**
  160. * rtl92c_init_LLT_table - Init LLT table
  161. * @io: io callback
  162. * @boundary:
  163. *
  164. * Realtek hardware access function.
  165. *
  166. */
  167. bool rtl92c_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
  168. {
  169. bool rst = true;
  170. u32 i;
  171. for (i = 0; i < (boundary - 1); i++) {
  172. rst = rtl92c_llt_write(hw, i , i + 1);
  173. if (true != rst) {
  174. pr_err("===> %s #1 fail\n", __func__);
  175. return rst;
  176. }
  177. }
  178. /* end of list */
  179. rst = rtl92c_llt_write(hw, (boundary - 1), 0xFF);
  180. if (true != rst) {
  181. pr_err("===> %s #2 fail\n", __func__);
  182. return rst;
  183. }
  184. /* Make the other pages as ring buffer
  185. * This ring buffer is used as beacon buffer if we config this MAC
  186. * as two MAC transfer.
  187. * Otherwise used as local loopback buffer.
  188. */
  189. for (i = boundary; i < LLT_LAST_ENTRY_OF_TX_PKT_BUFFER; i++) {
  190. rst = rtl92c_llt_write(hw, i, (i + 1));
  191. if (true != rst) {
  192. pr_err("===> %s #3 fail\n", __func__);
  193. return rst;
  194. }
  195. }
  196. /* Let last entry point to the start entry of ring buffer */
  197. rst = rtl92c_llt_write(hw, LLT_LAST_ENTRY_OF_TX_PKT_BUFFER, boundary);
  198. if (true != rst) {
  199. pr_err("===> %s #4 fail\n", __func__);
  200. return rst;
  201. }
  202. return rst;
  203. }
  204. void rtl92c_set_key(struct ieee80211_hw *hw, u32 key_index,
  205. u8 *p_macaddr, bool is_group, u8 enc_algo,
  206. bool is_wepkey, bool clear_all)
  207. {
  208. struct rtl_priv *rtlpriv = rtl_priv(hw);
  209. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  210. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  211. u8 *macaddr = p_macaddr;
  212. u32 entry_id = 0;
  213. bool is_pairwise = false;
  214. static u8 cam_const_addr[4][6] = {
  215. {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  216. {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
  217. {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
  218. {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
  219. };
  220. static u8 cam_const_broad[] = {
  221. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
  222. };
  223. if (clear_all) {
  224. u8 idx = 0;
  225. u8 cam_offset = 0;
  226. u8 clear_number = 5;
  227. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
  228. for (idx = 0; idx < clear_number; idx++) {
  229. rtl_cam_mark_invalid(hw, cam_offset + idx);
  230. rtl_cam_empty_entry(hw, cam_offset + idx);
  231. if (idx < 5) {
  232. memset(rtlpriv->sec.key_buf[idx], 0,
  233. MAX_KEY_LEN);
  234. rtlpriv->sec.key_len[idx] = 0;
  235. }
  236. }
  237. } else {
  238. switch (enc_algo) {
  239. case WEP40_ENCRYPTION:
  240. enc_algo = CAM_WEP40;
  241. break;
  242. case WEP104_ENCRYPTION:
  243. enc_algo = CAM_WEP104;
  244. break;
  245. case TKIP_ENCRYPTION:
  246. enc_algo = CAM_TKIP;
  247. break;
  248. case AESCCMP_ENCRYPTION:
  249. enc_algo = CAM_AES;
  250. break;
  251. default:
  252. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  253. "illegal switch case\n");
  254. enc_algo = CAM_TKIP;
  255. break;
  256. }
  257. if (is_wepkey || rtlpriv->sec.use_defaultkey) {
  258. macaddr = cam_const_addr[key_index];
  259. entry_id = key_index;
  260. } else {
  261. if (is_group) {
  262. macaddr = cam_const_broad;
  263. entry_id = key_index;
  264. } else {
  265. if (mac->opmode == NL80211_IFTYPE_AP ||
  266. mac->opmode == NL80211_IFTYPE_MESH_POINT) {
  267. entry_id = rtl_cam_get_free_entry(hw,
  268. p_macaddr);
  269. if (entry_id >= TOTAL_CAM_ENTRY) {
  270. RT_TRACE(rtlpriv, COMP_SEC,
  271. DBG_EMERG,
  272. "Can not find free hw security cam entry\n");
  273. return;
  274. }
  275. } else {
  276. entry_id = CAM_PAIRWISE_KEY_POSITION;
  277. }
  278. key_index = PAIRWISE_KEYIDX;
  279. is_pairwise = true;
  280. }
  281. }
  282. if (rtlpriv->sec.key_len[key_index] == 0) {
  283. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  284. "delete one entry\n");
  285. if (mac->opmode == NL80211_IFTYPE_AP ||
  286. mac->opmode == NL80211_IFTYPE_MESH_POINT)
  287. rtl_cam_del_entry(hw, p_macaddr);
  288. rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
  289. } else {
  290. RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
  291. "The insert KEY length is %d\n",
  292. rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
  293. RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
  294. "The insert KEY is %x %x\n",
  295. rtlpriv->sec.key_buf[0][0],
  296. rtlpriv->sec.key_buf[0][1]);
  297. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  298. "add one entry\n");
  299. if (is_pairwise) {
  300. RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
  301. "Pairwise Key content",
  302. rtlpriv->sec.pairwise_key,
  303. rtlpriv->sec.
  304. key_len[PAIRWISE_KEYIDX]);
  305. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  306. "set Pairwise key\n");
  307. rtl_cam_add_one_entry(hw, macaddr, key_index,
  308. entry_id, enc_algo,
  309. CAM_CONFIG_NO_USEDK,
  310. rtlpriv->sec.
  311. key_buf[key_index]);
  312. } else {
  313. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  314. "set group key\n");
  315. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  316. rtl_cam_add_one_entry(hw,
  317. rtlefuse->dev_addr,
  318. PAIRWISE_KEYIDX,
  319. CAM_PAIRWISE_KEY_POSITION,
  320. enc_algo,
  321. CAM_CONFIG_NO_USEDK,
  322. rtlpriv->sec.key_buf
  323. [entry_id]);
  324. }
  325. rtl_cam_add_one_entry(hw, macaddr, key_index,
  326. entry_id, enc_algo,
  327. CAM_CONFIG_NO_USEDK,
  328. rtlpriv->sec.key_buf[entry_id]);
  329. }
  330. }
  331. }
  332. }
  333. u32 rtl92c_get_txdma_status(struct ieee80211_hw *hw)
  334. {
  335. struct rtl_priv *rtlpriv = rtl_priv(hw);
  336. return rtl_read_dword(rtlpriv, REG_TXDMA_STATUS);
  337. }
  338. void rtl92c_enable_interrupt(struct ieee80211_hw *hw)
  339. {
  340. struct rtl_priv *rtlpriv = rtl_priv(hw);
  341. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  342. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  343. struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
  344. if (IS_HARDWARE_TYPE_8192CE(rtlhal)) {
  345. rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] &
  346. 0xFFFFFFFF);
  347. rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] &
  348. 0xFFFFFFFF);
  349. } else {
  350. rtl_write_dword(rtlpriv, REG_HIMR, rtlusb->irq_mask[0] &
  351. 0xFFFFFFFF);
  352. rtl_write_dword(rtlpriv, REG_HIMRE, rtlusb->irq_mask[1] &
  353. 0xFFFFFFFF);
  354. }
  355. }
  356. void rtl92c_init_interrupt(struct ieee80211_hw *hw)
  357. {
  358. rtl92c_enable_interrupt(hw);
  359. }
  360. void rtl92c_disable_interrupt(struct ieee80211_hw *hw)
  361. {
  362. struct rtl_priv *rtlpriv = rtl_priv(hw);
  363. rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
  364. rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
  365. }
  366. void rtl92c_set_qos(struct ieee80211_hw *hw, int aci)
  367. {
  368. struct rtl_priv *rtlpriv = rtl_priv(hw);
  369. rtl92c_dm_init_edca_turbo(hw);
  370. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, (u8 *)&aci);
  371. }
  372. void rtl92c_init_driver_info_size(struct ieee80211_hw *hw, u8 size)
  373. {
  374. struct rtl_priv *rtlpriv = rtl_priv(hw);
  375. rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, size);
  376. }
  377. int rtl92c_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
  378. {
  379. u8 value;
  380. struct rtl_priv *rtlpriv = rtl_priv(hw);
  381. switch (type) {
  382. case NL80211_IFTYPE_UNSPECIFIED:
  383. value = NT_NO_LINK;
  384. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  385. "Set Network type to NO LINK!\n");
  386. break;
  387. case NL80211_IFTYPE_ADHOC:
  388. value = NT_LINK_AD_HOC;
  389. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  390. "Set Network type to Ad Hoc!\n");
  391. break;
  392. case NL80211_IFTYPE_STATION:
  393. value = NT_LINK_AP;
  394. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  395. "Set Network type to STA!\n");
  396. break;
  397. case NL80211_IFTYPE_AP:
  398. value = NT_AS_AP;
  399. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  400. "Set Network type to AP!\n");
  401. break;
  402. default:
  403. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  404. "Network type %d not supported!\n", type);
  405. return -EOPNOTSUPP;
  406. }
  407. rtl_write_byte(rtlpriv, MSR, value);
  408. return 0;
  409. }
  410. void rtl92c_init_network_type(struct ieee80211_hw *hw)
  411. {
  412. rtl92c_set_network_type(hw, NL80211_IFTYPE_UNSPECIFIED);
  413. }
  414. void rtl92c_init_adaptive_ctrl(struct ieee80211_hw *hw)
  415. {
  416. u16 value16;
  417. u32 value32;
  418. struct rtl_priv *rtlpriv = rtl_priv(hw);
  419. /* Response Rate Set */
  420. value32 = rtl_read_dword(rtlpriv, REG_RRSR);
  421. value32 &= ~RATE_BITMAP_ALL;
  422. value32 |= RATE_RRSR_CCK_ONLY_1M;
  423. rtl_write_dword(rtlpriv, REG_RRSR, value32);
  424. /* SIFS (used in NAV) */
  425. value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
  426. rtl_write_word(rtlpriv, REG_SPEC_SIFS, value16);
  427. /* Retry Limit */
  428. value16 = _LRL(0x30) | _SRL(0x30);
  429. rtl_write_dword(rtlpriv, REG_RL, value16);
  430. }
  431. void rtl92c_init_rate_fallback(struct ieee80211_hw *hw)
  432. {
  433. struct rtl_priv *rtlpriv = rtl_priv(hw);
  434. /* Set Data Auto Rate Fallback Retry Count register. */
  435. rtl_write_dword(rtlpriv, REG_DARFRC, 0x00000000);
  436. rtl_write_dword(rtlpriv, REG_DARFRC+4, 0x10080404);
  437. rtl_write_dword(rtlpriv, REG_RARFRC, 0x04030201);
  438. rtl_write_dword(rtlpriv, REG_RARFRC+4, 0x08070605);
  439. }
  440. static void rtl92c_set_cck_sifs(struct ieee80211_hw *hw, u8 trx_sifs,
  441. u8 ctx_sifs)
  442. {
  443. struct rtl_priv *rtlpriv = rtl_priv(hw);
  444. rtl_write_byte(rtlpriv, REG_SIFS_CCK, trx_sifs);
  445. rtl_write_byte(rtlpriv, (REG_SIFS_CCK + 1), ctx_sifs);
  446. }
  447. static void rtl92c_set_ofdm_sifs(struct ieee80211_hw *hw, u8 trx_sifs,
  448. u8 ctx_sifs)
  449. {
  450. struct rtl_priv *rtlpriv = rtl_priv(hw);
  451. rtl_write_byte(rtlpriv, REG_SIFS_OFDM, trx_sifs);
  452. rtl_write_byte(rtlpriv, (REG_SIFS_OFDM + 1), ctx_sifs);
  453. }
  454. void rtl92c_init_edca_param(struct ieee80211_hw *hw,
  455. u16 queue, u16 txop, u8 cw_min, u8 cw_max, u8 aifs)
  456. {
  457. /* sequence: VO, VI, BE, BK ==> the same as 92C hardware design.
  458. * referenc : enum nl80211_txq_q or ieee80211_set_wmm_default function.
  459. */
  460. u32 value;
  461. struct rtl_priv *rtlpriv = rtl_priv(hw);
  462. value = (u32)aifs;
  463. value |= ((u32)cw_min & 0xF) << 8;
  464. value |= ((u32)cw_max & 0xF) << 12;
  465. value |= (u32)txop << 16;
  466. /* 92C hardware register sequence is the same as queue number. */
  467. rtl_write_dword(rtlpriv, (REG_EDCA_VO_PARAM + (queue * 4)), value);
  468. }
  469. void rtl92c_init_edca(struct ieee80211_hw *hw)
  470. {
  471. u16 value16;
  472. struct rtl_priv *rtlpriv = rtl_priv(hw);
  473. /* disable EDCCA count down, to reduce collison and retry */
  474. value16 = rtl_read_word(rtlpriv, REG_RD_CTRL);
  475. value16 |= DIS_EDCA_CNT_DWN;
  476. rtl_write_word(rtlpriv, REG_RD_CTRL, value16);
  477. /* Update SIFS timing. ??????????
  478. * pHalData->SifsTime = 0x0e0e0a0a; */
  479. rtl92c_set_cck_sifs(hw, 0xa, 0xa);
  480. rtl92c_set_ofdm_sifs(hw, 0xe, 0xe);
  481. /* Set CCK/OFDM SIFS to be 10us. */
  482. rtl_write_word(rtlpriv, REG_SIFS_CCK, 0x0a0a);
  483. rtl_write_word(rtlpriv, REG_SIFS_OFDM, 0x1010);
  484. rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0204);
  485. rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x014004);
  486. /* TXOP */
  487. rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 0x005EA42B);
  488. rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0x0000A44F);
  489. rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x005EA324);
  490. rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x002FA226);
  491. /* PIFS */
  492. rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
  493. /* AGGR BREAK TIME Register */
  494. rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
  495. rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
  496. rtl_write_byte(rtlpriv, REG_BCNDMATIM, 0x02);
  497. rtl_write_byte(rtlpriv, REG_ATIMWND, 0x02);
  498. }
  499. void rtl92c_init_ampdu_aggregation(struct ieee80211_hw *hw)
  500. {
  501. struct rtl_priv *rtlpriv = rtl_priv(hw);
  502. rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x99997631);
  503. rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
  504. /* init AMPDU aggregation number, tuning for Tx's TP, */
  505. rtl_write_word(rtlpriv, 0x4CA, 0x0708);
  506. }
  507. void rtl92c_init_beacon_max_error(struct ieee80211_hw *hw)
  508. {
  509. struct rtl_priv *rtlpriv = rtl_priv(hw);
  510. rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
  511. }
  512. void rtl92c_init_rdg_setting(struct ieee80211_hw *hw)
  513. {
  514. struct rtl_priv *rtlpriv = rtl_priv(hw);
  515. rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xFF);
  516. rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);
  517. rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);
  518. }
  519. void rtl92c_init_retry_function(struct ieee80211_hw *hw)
  520. {
  521. u8 value8;
  522. struct rtl_priv *rtlpriv = rtl_priv(hw);
  523. value8 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL);
  524. value8 |= EN_AMPDU_RTY_NEW;
  525. rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL, value8);
  526. /* Set ACK timeout */
  527. rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
  528. }
  529. void rtl92c_disable_fast_edca(struct ieee80211_hw *hw)
  530. {
  531. struct rtl_priv *rtlpriv = rtl_priv(hw);
  532. rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0);
  533. }
  534. void rtl92c_set_min_space(struct ieee80211_hw *hw, bool is2T)
  535. {
  536. struct rtl_priv *rtlpriv = rtl_priv(hw);
  537. u8 value = is2T ? MAX_MSS_DENSITY_2T : MAX_MSS_DENSITY_1T;
  538. rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, value);
  539. }
  540. /*==============================================================*/
  541. static u8 _rtl92c_query_rxpwrpercentage(s8 antpower)
  542. {
  543. if ((antpower <= -100) || (antpower >= 20))
  544. return 0;
  545. else if (antpower >= 0)
  546. return 100;
  547. else
  548. return 100 + antpower;
  549. }
  550. static u8 _rtl92c_evm_db_to_percentage(s8 value)
  551. {
  552. s8 ret_val;
  553. ret_val = value;
  554. if (ret_val >= 0)
  555. ret_val = 0;
  556. if (ret_val <= -33)
  557. ret_val = -33;
  558. ret_val = 0 - ret_val;
  559. ret_val *= 3;
  560. if (ret_val == 99)
  561. ret_val = 100;
  562. return ret_val;
  563. }
  564. static long _rtl92c_signal_scale_mapping(struct ieee80211_hw *hw,
  565. long currsig)
  566. {
  567. long retsig;
  568. if (currsig >= 61 && currsig <= 100)
  569. retsig = 90 + ((currsig - 60) / 4);
  570. else if (currsig >= 41 && currsig <= 60)
  571. retsig = 78 + ((currsig - 40) / 2);
  572. else if (currsig >= 31 && currsig <= 40)
  573. retsig = 66 + (currsig - 30);
  574. else if (currsig >= 21 && currsig <= 30)
  575. retsig = 54 + (currsig - 20);
  576. else if (currsig >= 5 && currsig <= 20)
  577. retsig = 42 + (((currsig - 5) * 2) / 3);
  578. else if (currsig == 4)
  579. retsig = 36;
  580. else if (currsig == 3)
  581. retsig = 27;
  582. else if (currsig == 2)
  583. retsig = 18;
  584. else if (currsig == 1)
  585. retsig = 9;
  586. else
  587. retsig = currsig;
  588. return retsig;
  589. }
  590. static void _rtl92c_query_rxphystatus(struct ieee80211_hw *hw,
  591. struct rtl_stats *pstats,
  592. struct rx_desc_92c *p_desc,
  593. struct rx_fwinfo_92c *p_drvinfo,
  594. bool packet_match_bssid,
  595. bool packet_toself,
  596. bool packet_beacon)
  597. {
  598. struct rtl_priv *rtlpriv = rtl_priv(hw);
  599. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  600. struct phy_sts_cck_8192s_t *cck_buf;
  601. s8 rx_pwr_all = 0, rx_pwr[4];
  602. u8 rf_rx_num = 0, evm, pwdb_all;
  603. u8 i, max_spatial_stream;
  604. u32 rssi, total_rssi = 0;
  605. bool in_powersavemode = false;
  606. bool is_cck_rate;
  607. u8 *pdesc = (u8 *)p_desc;
  608. is_cck_rate = RX_HAL_IS_CCK_RATE(p_desc->rxmcs);
  609. pstats->packet_matchbssid = packet_match_bssid;
  610. pstats->packet_toself = packet_toself;
  611. pstats->packet_beacon = packet_beacon;
  612. pstats->is_cck = is_cck_rate;
  613. pstats->RX_SIGQ[0] = -1;
  614. pstats->RX_SIGQ[1] = -1;
  615. if (is_cck_rate) {
  616. u8 report, cck_highpwr;
  617. cck_buf = (struct phy_sts_cck_8192s_t *)p_drvinfo;
  618. if (!in_powersavemode)
  619. cck_highpwr = rtlphy->cck_high_power;
  620. else
  621. cck_highpwr = false;
  622. if (!cck_highpwr) {
  623. u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
  624. report = cck_buf->cck_agc_rpt & 0xc0;
  625. report = report >> 6;
  626. switch (report) {
  627. case 0x3:
  628. rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
  629. break;
  630. case 0x2:
  631. rx_pwr_all = -26 - (cck_agc_rpt & 0x3e);
  632. break;
  633. case 0x1:
  634. rx_pwr_all = -12 - (cck_agc_rpt & 0x3e);
  635. break;
  636. case 0x0:
  637. rx_pwr_all = 16 - (cck_agc_rpt & 0x3e);
  638. break;
  639. }
  640. } else {
  641. u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
  642. report = p_drvinfo->cfosho[0] & 0x60;
  643. report = report >> 5;
  644. switch (report) {
  645. case 0x3:
  646. rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1);
  647. break;
  648. case 0x2:
  649. rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1);
  650. break;
  651. case 0x1:
  652. rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1);
  653. break;
  654. case 0x0:
  655. rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1);
  656. break;
  657. }
  658. }
  659. pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all);
  660. pstats->rx_pwdb_all = pwdb_all;
  661. pstats->recvsignalpower = rx_pwr_all;
  662. if (packet_match_bssid) {
  663. u8 sq;
  664. if (pstats->rx_pwdb_all > 40)
  665. sq = 100;
  666. else {
  667. sq = cck_buf->sq_rpt;
  668. if (sq > 64)
  669. sq = 0;
  670. else if (sq < 20)
  671. sq = 100;
  672. else
  673. sq = ((64 - sq) * 100) / 44;
  674. }
  675. pstats->signalquality = sq;
  676. pstats->RX_SIGQ[0] = sq;
  677. pstats->RX_SIGQ[1] = -1;
  678. }
  679. } else {
  680. rtlpriv->dm.rfpath_rxenable[0] =
  681. rtlpriv->dm.rfpath_rxenable[1] = true;
  682. for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
  683. if (rtlpriv->dm.rfpath_rxenable[i])
  684. rf_rx_num++;
  685. rx_pwr[i] =
  686. ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) - 110;
  687. rssi = _rtl92c_query_rxpwrpercentage(rx_pwr[i]);
  688. total_rssi += rssi;
  689. rtlpriv->stats.rx_snr_db[i] =
  690. (long)(p_drvinfo->rxsnr[i] / 2);
  691. if (packet_match_bssid)
  692. pstats->rx_mimo_signalstrength[i] = (u8) rssi;
  693. }
  694. rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110;
  695. pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all);
  696. pstats->rx_pwdb_all = pwdb_all;
  697. pstats->rxpower = rx_pwr_all;
  698. pstats->recvsignalpower = rx_pwr_all;
  699. if (GET_RX_DESC_RX_MCS(pdesc) &&
  700. GET_RX_DESC_RX_MCS(pdesc) >= DESC_RATEMCS8 &&
  701. GET_RX_DESC_RX_MCS(pdesc) <= DESC_RATEMCS15)
  702. max_spatial_stream = 2;
  703. else
  704. max_spatial_stream = 1;
  705. for (i = 0; i < max_spatial_stream; i++) {
  706. evm = _rtl92c_evm_db_to_percentage(p_drvinfo->rxevm[i]);
  707. if (packet_match_bssid) {
  708. if (i == 0)
  709. pstats->signalquality =
  710. (u8) (evm & 0xff);
  711. pstats->RX_SIGQ[i] =
  712. (u8) (evm & 0xff);
  713. }
  714. }
  715. }
  716. if (is_cck_rate)
  717. pstats->signalstrength =
  718. (u8) (_rtl92c_signal_scale_mapping(hw, pwdb_all));
  719. else if (rf_rx_num != 0)
  720. pstats->signalstrength =
  721. (u8) (_rtl92c_signal_scale_mapping
  722. (hw, total_rssi /= rf_rx_num));
  723. }
  724. void rtl92c_translate_rx_signal_stuff(struct ieee80211_hw *hw,
  725. struct sk_buff *skb,
  726. struct rtl_stats *pstats,
  727. struct rx_desc_92c *pdesc,
  728. struct rx_fwinfo_92c *p_drvinfo)
  729. {
  730. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  731. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  732. struct ieee80211_hdr *hdr;
  733. u8 *tmp_buf;
  734. u8 *praddr;
  735. __le16 fc;
  736. u16 type, cpu_fc;
  737. bool packet_matchbssid, packet_toself, packet_beacon = false;
  738. tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift;
  739. hdr = (struct ieee80211_hdr *)tmp_buf;
  740. fc = hdr->frame_control;
  741. cpu_fc = le16_to_cpu(fc);
  742. type = WLAN_FC_GET_TYPE(fc);
  743. praddr = hdr->addr1;
  744. packet_matchbssid =
  745. ((IEEE80211_FTYPE_CTL != type) &&
  746. ether_addr_equal(mac->bssid,
  747. (cpu_fc & IEEE80211_FCTL_TODS) ? hdr->addr1 :
  748. (cpu_fc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 :
  749. hdr->addr3) &&
  750. (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv));
  751. packet_toself = packet_matchbssid &&
  752. ether_addr_equal(praddr, rtlefuse->dev_addr);
  753. if (ieee80211_is_beacon(fc))
  754. packet_beacon = true;
  755. _rtl92c_query_rxphystatus(hw, pstats, pdesc, p_drvinfo,
  756. packet_matchbssid, packet_toself,
  757. packet_beacon);
  758. rtl_process_phyinfo(hw, tmp_buf, pstats);
  759. }