dm_common.c 53 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * The full GNU General Public License is included in this distribution in the
  15. * file called LICENSE.
  16. *
  17. * Contact Information:
  18. * wlanfae <wlanfae@realtek.com>
  19. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20. * Hsinchu 300, Taiwan.
  21. *
  22. * Larry Finger <Larry.Finger@lwfinger.net>
  23. *
  24. *****************************************************************************/
  25. #include <linux/export.h>
  26. #include "dm_common.h"
  27. #include "phy_common.h"
  28. #include "../pci.h"
  29. #include "../base.h"
  30. #include "../core.h"
  31. #define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
  32. #define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
  33. #define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
  34. #define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
  35. #define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
  36. #define BT_MASK 0x00ffffff
  37. #define RTLPRIV (struct rtl_priv *)
  38. #define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
  39. ((RTLPRIV(_priv))->mac80211.opmode == \
  40. NL80211_IFTYPE_ADHOC) ? \
  41. ((RTLPRIV(_priv))->dm.entry_min_undec_sm_pwdb) : \
  42. ((RTLPRIV(_priv))->dm.undec_sm_pwdb)
  43. static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
  44. 0x7f8001fe,
  45. 0x788001e2,
  46. 0x71c001c7,
  47. 0x6b8001ae,
  48. 0x65400195,
  49. 0x5fc0017f,
  50. 0x5a400169,
  51. 0x55400155,
  52. 0x50800142,
  53. 0x4c000130,
  54. 0x47c0011f,
  55. 0x43c0010f,
  56. 0x40000100,
  57. 0x3c8000f2,
  58. 0x390000e4,
  59. 0x35c000d7,
  60. 0x32c000cb,
  61. 0x300000c0,
  62. 0x2d4000b5,
  63. 0x2ac000ab,
  64. 0x288000a2,
  65. 0x26000098,
  66. 0x24000090,
  67. 0x22000088,
  68. 0x20000080,
  69. 0x1e400079,
  70. 0x1c800072,
  71. 0x1b00006c,
  72. 0x19800066,
  73. 0x18000060,
  74. 0x16c0005b,
  75. 0x15800056,
  76. 0x14400051,
  77. 0x1300004c,
  78. 0x12000048,
  79. 0x11000044,
  80. 0x10000040,
  81. };
  82. static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
  83. {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
  84. {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
  85. {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
  86. {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
  87. {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
  88. {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
  89. {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
  90. {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
  91. {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
  92. {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
  93. {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
  94. {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
  95. {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
  96. {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
  97. {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
  98. {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
  99. {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
  100. {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
  101. {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
  102. {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  103. {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  104. {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
  105. {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
  106. {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
  107. {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
  108. {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
  109. {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
  110. {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
  111. {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
  112. {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
  113. {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
  114. {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
  115. {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
  116. };
  117. static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
  118. {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
  119. {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
  120. {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
  121. {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
  122. {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
  123. {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
  124. {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
  125. {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
  126. {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
  127. {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
  128. {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
  129. {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
  130. {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
  131. {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
  132. {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
  133. {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
  134. {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
  135. {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
  136. {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
  137. {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
  138. {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
  139. {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
  140. {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
  141. {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
  142. {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
  143. {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
  144. {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
  145. {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
  146. {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
  147. {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
  148. {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
  149. {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
  150. {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
  151. };
  152. static u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
  153. void dm_restorepowerindex(struct ieee80211_hw *hw)
  154. {
  155. struct rtl_priv *rtlpriv = rtl_priv(hw);
  156. u8 index;
  157. for (index = 0; index < 6; index++)
  158. rtl_write_byte(rtlpriv, power_index_reg[index],
  159. rtlpriv->dm.powerindex_backup[index]);
  160. }
  161. EXPORT_SYMBOL_GPL(dm_restorepowerindex);
  162. void dm_writepowerindex(struct ieee80211_hw *hw, u8 value)
  163. {
  164. struct rtl_priv *rtlpriv = rtl_priv(hw);
  165. u8 index;
  166. for (index = 0; index < 6; index++)
  167. rtl_write_byte(rtlpriv, power_index_reg[index], value);
  168. }
  169. EXPORT_SYMBOL_GPL(dm_writepowerindex);
  170. void dm_savepowerindex(struct ieee80211_hw *hw)
  171. {
  172. struct rtl_priv *rtlpriv = rtl_priv(hw);
  173. u8 index;
  174. u8 tmp;
  175. for (index = 0; index < 6; index++) {
  176. tmp = rtl_read_byte(rtlpriv, power_index_reg[index]);
  177. rtlpriv->dm.powerindex_backup[index] = tmp;
  178. }
  179. }
  180. EXPORT_SYMBOL_GPL(dm_savepowerindex);
  181. static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
  182. {
  183. struct rtl_priv *rtlpriv = rtl_priv(hw);
  184. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  185. long rssi_val_min = 0;
  186. if ((dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) &&
  187. (dm_digtable->cursta_cstate == DIG_STA_CONNECT)) {
  188. if (rtlpriv->dm.entry_min_undec_sm_pwdb != 0)
  189. rssi_val_min =
  190. (rtlpriv->dm.entry_min_undec_sm_pwdb >
  191. rtlpriv->dm.undec_sm_pwdb) ?
  192. rtlpriv->dm.undec_sm_pwdb :
  193. rtlpriv->dm.entry_min_undec_sm_pwdb;
  194. else
  195. rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
  196. } else if (dm_digtable->cursta_cstate == DIG_STA_CONNECT ||
  197. dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT) {
  198. rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
  199. } else if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) {
  200. rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb;
  201. }
  202. if (rssi_val_min > 100)
  203. rssi_val_min = 100;
  204. return (u8)rssi_val_min;
  205. }
  206. static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
  207. {
  208. u32 ret_value;
  209. struct rtl_priv *rtlpriv = rtl_priv(hw);
  210. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  211. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
  212. falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
  213. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
  214. falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
  215. falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
  216. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
  217. falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
  218. ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD);
  219. falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff);
  220. falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
  221. falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
  222. falsealm_cnt->cnt_rate_illegal +
  223. falsealm_cnt->cnt_crc8_fail +
  224. falsealm_cnt->cnt_mcs_fail +
  225. falsealm_cnt->cnt_fast_fsync_fail +
  226. falsealm_cnt->cnt_sb_search_fail;
  227. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
  228. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
  229. falsealm_cnt->cnt_cck_fail = ret_value;
  230. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
  231. falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
  232. falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
  233. falsealm_cnt->cnt_rate_illegal +
  234. falsealm_cnt->cnt_crc8_fail +
  235. falsealm_cnt->cnt_mcs_fail +
  236. falsealm_cnt->cnt_cck_fail);
  237. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
  238. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
  239. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
  240. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
  241. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  242. "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
  243. falsealm_cnt->cnt_parity_fail,
  244. falsealm_cnt->cnt_rate_illegal,
  245. falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
  246. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  247. "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
  248. falsealm_cnt->cnt_ofdm_fail,
  249. falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
  250. }
  251. static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
  252. {
  253. struct rtl_priv *rtlpriv = rtl_priv(hw);
  254. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  255. u8 value_igi = dm_digtable->cur_igvalue;
  256. if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
  257. value_igi--;
  258. else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
  259. value_igi += 0;
  260. else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
  261. value_igi++;
  262. else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
  263. value_igi += 2;
  264. if (value_igi > DM_DIG_FA_UPPER)
  265. value_igi = DM_DIG_FA_UPPER;
  266. else if (value_igi < DM_DIG_FA_LOWER)
  267. value_igi = DM_DIG_FA_LOWER;
  268. if (rtlpriv->falsealm_cnt.cnt_all > 10000)
  269. value_igi = DM_DIG_FA_UPPER;
  270. dm_digtable->cur_igvalue = value_igi;
  271. rtl92c_dm_write_dig(hw);
  272. }
  273. static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
  274. {
  275. struct rtl_priv *rtlpriv = rtl_priv(hw);
  276. struct dig_t *digtable = &rtlpriv->dm_digtable;
  277. u32 isbt;
  278. /* modify DIG lower bound, deal with abnormally large false alarm */
  279. if (rtlpriv->falsealm_cnt.cnt_all > 10000) {
  280. digtable->large_fa_hit++;
  281. if (digtable->forbidden_igi < digtable->cur_igvalue) {
  282. digtable->forbidden_igi = digtable->cur_igvalue;
  283. digtable->large_fa_hit = 1;
  284. }
  285. if (digtable->large_fa_hit >= 3) {
  286. if ((digtable->forbidden_igi + 1) >
  287. digtable->rx_gain_max)
  288. digtable->rx_gain_min = digtable->rx_gain_max;
  289. else
  290. digtable->rx_gain_min = (digtable->forbidden_igi + 1);
  291. digtable->recover_cnt = 3600; /* 3600=2hr */
  292. }
  293. } else {
  294. /* Recovery mechanism for IGI lower bound */
  295. if (digtable->recover_cnt != 0) {
  296. digtable->recover_cnt--;
  297. } else {
  298. if (digtable->large_fa_hit == 0) {
  299. if ((digtable->forbidden_igi-1) < DM_DIG_MIN) {
  300. digtable->forbidden_igi = DM_DIG_MIN;
  301. digtable->rx_gain_min = DM_DIG_MIN;
  302. } else {
  303. digtable->forbidden_igi--;
  304. digtable->rx_gain_min = digtable->forbidden_igi + 1;
  305. }
  306. } else if (digtable->large_fa_hit == 3) {
  307. digtable->large_fa_hit = 0;
  308. }
  309. }
  310. }
  311. if (rtlpriv->falsealm_cnt.cnt_all < 250) {
  312. isbt = rtl_read_byte(rtlpriv, 0x4fd) & 0x01;
  313. if (!isbt) {
  314. if (rtlpriv->falsealm_cnt.cnt_all >
  315. digtable->fa_lowthresh) {
  316. if ((digtable->back_val - 2) <
  317. digtable->back_range_min)
  318. digtable->back_val = digtable->back_range_min;
  319. else
  320. digtable->back_val -= 2;
  321. } else if (rtlpriv->falsealm_cnt.cnt_all <
  322. digtable->fa_lowthresh) {
  323. if ((digtable->back_val + 2) >
  324. digtable->back_range_max)
  325. digtable->back_val = digtable->back_range_max;
  326. else
  327. digtable->back_val += 2;
  328. }
  329. } else {
  330. digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
  331. }
  332. } else {
  333. /* Adjust initial gain by false alarm */
  334. if (rtlpriv->falsealm_cnt.cnt_all > 1000)
  335. digtable->cur_igvalue = digtable->pre_igvalue + 2;
  336. else if (rtlpriv->falsealm_cnt.cnt_all > 750)
  337. digtable->cur_igvalue = digtable->pre_igvalue + 1;
  338. else if (rtlpriv->falsealm_cnt.cnt_all < 500)
  339. digtable->cur_igvalue = digtable->pre_igvalue - 1;
  340. }
  341. /* Check initial gain by upper/lower bound */
  342. if (digtable->cur_igvalue > digtable->rx_gain_max)
  343. digtable->cur_igvalue = digtable->rx_gain_max;
  344. if (digtable->cur_igvalue < digtable->rx_gain_min)
  345. digtable->cur_igvalue = digtable->rx_gain_min;
  346. rtl92c_dm_write_dig(hw);
  347. }
  348. static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
  349. {
  350. static u8 initialized; /* initialized to false */
  351. struct rtl_priv *rtlpriv = rtl_priv(hw);
  352. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  353. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  354. long rssi_strength = rtlpriv->dm.entry_min_undec_sm_pwdb;
  355. bool multi_sta = false;
  356. if (mac->opmode == NL80211_IFTYPE_ADHOC)
  357. multi_sta = true;
  358. if (!multi_sta ||
  359. dm_digtable->cursta_cstate == DIG_STA_DISCONNECT) {
  360. initialized = false;
  361. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  362. return;
  363. } else if (initialized == false) {
  364. initialized = true;
  365. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
  366. dm_digtable->cur_igvalue = 0x20;
  367. rtl92c_dm_write_dig(hw);
  368. }
  369. if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) {
  370. if ((rssi_strength < dm_digtable->rssi_lowthresh) &&
  371. (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
  372. if (dm_digtable->dig_ext_port_stage ==
  373. DIG_EXT_PORT_STAGE_2) {
  374. dm_digtable->cur_igvalue = 0x20;
  375. rtl92c_dm_write_dig(hw);
  376. }
  377. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
  378. } else if (rssi_strength > dm_digtable->rssi_highthresh) {
  379. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
  380. rtl92c_dm_ctrl_initgain_by_fa(hw);
  381. }
  382. } else if (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
  383. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
  384. dm_digtable->cur_igvalue = 0x20;
  385. rtl92c_dm_write_dig(hw);
  386. }
  387. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  388. "curmultista_cstate = %x dig_ext_port_stage %x\n",
  389. dm_digtable->curmultista_cstate,
  390. dm_digtable->dig_ext_port_stage);
  391. }
  392. static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw)
  393. {
  394. struct rtl_priv *rtlpriv = rtl_priv(hw);
  395. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  396. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  397. "presta_cstate = %x, cursta_cstate = %x\n",
  398. dm_digtable->presta_cstate, dm_digtable->cursta_cstate);
  399. if (dm_digtable->presta_cstate == dm_digtable->cursta_cstate ||
  400. dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT ||
  401. dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
  402. if (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) {
  403. dm_digtable->rssi_val_min =
  404. rtl92c_dm_initial_gain_min_pwdb(hw);
  405. if (dm_digtable->rssi_val_min > 100)
  406. dm_digtable->rssi_val_min = 100;
  407. rtl92c_dm_ctrl_initgain_by_rssi(hw);
  408. }
  409. } else {
  410. dm_digtable->rssi_val_min = 0;
  411. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  412. dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
  413. dm_digtable->cur_igvalue = 0x20;
  414. dm_digtable->pre_igvalue = 0;
  415. rtl92c_dm_write_dig(hw);
  416. }
  417. }
  418. static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
  419. {
  420. struct rtl_priv *rtlpriv = rtl_priv(hw);
  421. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  422. if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
  423. dm_digtable->rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw);
  424. if (dm_digtable->rssi_val_min > 100)
  425. dm_digtable->rssi_val_min = 100;
  426. if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
  427. if (dm_digtable->rssi_val_min <= 25)
  428. dm_digtable->cur_cck_pd_state =
  429. CCK_PD_STAGE_LOWRSSI;
  430. else
  431. dm_digtable->cur_cck_pd_state =
  432. CCK_PD_STAGE_HIGHRSSI;
  433. } else {
  434. if (dm_digtable->rssi_val_min <= 20)
  435. dm_digtable->cur_cck_pd_state =
  436. CCK_PD_STAGE_LOWRSSI;
  437. else
  438. dm_digtable->cur_cck_pd_state =
  439. CCK_PD_STAGE_HIGHRSSI;
  440. }
  441. } else {
  442. dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
  443. }
  444. if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) {
  445. if ((dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) ||
  446. (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_MAX))
  447. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83);
  448. else
  449. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
  450. dm_digtable->pre_cck_pd_state = dm_digtable->cur_cck_pd_state;
  451. }
  452. }
  453. static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
  454. {
  455. struct rtl_priv *rtlpriv = rtl_priv(hw);
  456. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  457. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  458. if (mac->act_scanning)
  459. return;
  460. if (mac->link_state >= MAC80211_LINKED)
  461. dm_digtable->cursta_cstate = DIG_STA_CONNECT;
  462. else
  463. dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
  464. dm_digtable->curmultista_cstate = DIG_MULTISTA_DISCONNECT;
  465. rtl92c_dm_initial_gain_sta(hw);
  466. rtl92c_dm_initial_gain_multi_sta(hw);
  467. rtl92c_dm_cck_packet_detection_thresh(hw);
  468. dm_digtable->presta_cstate = dm_digtable->cursta_cstate;
  469. }
  470. static void rtl92c_dm_dig(struct ieee80211_hw *hw)
  471. {
  472. struct rtl_priv *rtlpriv = rtl_priv(hw);
  473. if (rtlpriv->dm.dm_initialgain_enable == false)
  474. return;
  475. if (!(rtlpriv->dm.dm_flag & DYNAMIC_FUNC_DIG))
  476. return;
  477. rtl92c_dm_ctrl_initgain_by_twoport(hw);
  478. }
  479. static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
  480. {
  481. struct rtl_priv *rtlpriv = rtl_priv(hw);
  482. if (rtlpriv->rtlhal.interface == INTF_USB &&
  483. rtlpriv->rtlhal.board_type & 0x1) {
  484. dm_savepowerindex(hw);
  485. rtlpriv->dm.dynamic_txpower_enable = true;
  486. } else {
  487. rtlpriv->dm.dynamic_txpower_enable = false;
  488. }
  489. rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
  490. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  491. }
  492. void rtl92c_dm_write_dig(struct ieee80211_hw *hw)
  493. {
  494. struct rtl_priv *rtlpriv = rtl_priv(hw);
  495. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  496. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  497. "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n",
  498. dm_digtable->cur_igvalue, dm_digtable->pre_igvalue,
  499. dm_digtable->back_val);
  500. if (rtlpriv->rtlhal.interface == INTF_USB &&
  501. !dm_digtable->dig_enable_flag) {
  502. dm_digtable->pre_igvalue = 0x17;
  503. return;
  504. }
  505. dm_digtable->cur_igvalue -= 1;
  506. if (dm_digtable->cur_igvalue < DM_DIG_MIN)
  507. dm_digtable->cur_igvalue = DM_DIG_MIN;
  508. if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) {
  509. rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
  510. dm_digtable->cur_igvalue);
  511. rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
  512. dm_digtable->cur_igvalue);
  513. dm_digtable->pre_igvalue = dm_digtable->cur_igvalue;
  514. }
  515. RT_TRACE(rtlpriv, COMP_DIG, DBG_WARNING,
  516. "dig values 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
  517. dm_digtable->cur_igvalue, dm_digtable->pre_igvalue,
  518. dm_digtable->rssi_val_min, dm_digtable->back_val,
  519. dm_digtable->rx_gain_max, dm_digtable->rx_gain_min,
  520. dm_digtable->large_fa_hit, dm_digtable->forbidden_igi);
  521. }
  522. EXPORT_SYMBOL(rtl92c_dm_write_dig);
  523. static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw)
  524. {
  525. struct rtl_priv *rtlpriv = rtl_priv(hw);
  526. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  527. long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff;
  528. if (mac->link_state != MAC80211_LINKED)
  529. return;
  530. if (mac->opmode == NL80211_IFTYPE_ADHOC ||
  531. mac->opmode == NL80211_IFTYPE_AP) {
  532. /* TODO: Handle ADHOC and AP Mode */
  533. }
  534. if (tmpentry_max_pwdb != 0)
  535. rtlpriv->dm.entry_max_undec_sm_pwdb = tmpentry_max_pwdb;
  536. else
  537. rtlpriv->dm.entry_max_undec_sm_pwdb = 0;
  538. if (tmpentry_min_pwdb != 0xff)
  539. rtlpriv->dm.entry_min_undec_sm_pwdb = tmpentry_min_pwdb;
  540. else
  541. rtlpriv->dm.entry_min_undec_sm_pwdb = 0;
  542. /* TODO:
  543. * if (mac->opmode == NL80211_IFTYPE_STATION) {
  544. * if (rtlpriv->rtlhal.fw_ready) {
  545. * u32 param = (u32)(rtlpriv->dm.undec_sm_pwdb << 16);
  546. * rtl8192c_set_rssi_cmd(hw, param);
  547. * }
  548. * }
  549. */
  550. }
  551. void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw)
  552. {
  553. struct rtl_priv *rtlpriv = rtl_priv(hw);
  554. rtlpriv->dm.current_turbo_edca = false;
  555. rtlpriv->dm.is_any_nonbepkts = false;
  556. rtlpriv->dm.is_cur_rdlstate = false;
  557. }
  558. EXPORT_SYMBOL(rtl92c_dm_init_edca_turbo);
  559. static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw)
  560. {
  561. struct rtl_priv *rtlpriv = rtl_priv(hw);
  562. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  563. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  564. static u64 last_txok_cnt;
  565. static u64 last_rxok_cnt;
  566. static u32 last_bt_edca_ul;
  567. static u32 last_bt_edca_dl;
  568. u64 cur_txok_cnt = 0;
  569. u64 cur_rxok_cnt = 0;
  570. u32 edca_be_ul = 0x5ea42b;
  571. u32 edca_be_dl = 0x5ea42b;
  572. bool bt_change_edca = false;
  573. if ((last_bt_edca_ul != rtlpcipriv->bt_coexist.bt_edca_ul) ||
  574. (last_bt_edca_dl != rtlpcipriv->bt_coexist.bt_edca_dl)) {
  575. rtlpriv->dm.current_turbo_edca = false;
  576. last_bt_edca_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
  577. last_bt_edca_dl = rtlpcipriv->bt_coexist.bt_edca_dl;
  578. }
  579. if (rtlpcipriv->bt_coexist.bt_edca_ul != 0) {
  580. edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
  581. bt_change_edca = true;
  582. }
  583. if (rtlpcipriv->bt_coexist.bt_edca_dl != 0) {
  584. edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_dl;
  585. bt_change_edca = true;
  586. }
  587. if (mac->link_state != MAC80211_LINKED) {
  588. rtlpriv->dm.current_turbo_edca = false;
  589. return;
  590. }
  591. if ((!mac->ht_enable) && (!rtlpcipriv->bt_coexist.bt_coexistence)) {
  592. if (!(edca_be_ul & 0xffff0000))
  593. edca_be_ul |= 0x005e0000;
  594. if (!(edca_be_dl & 0xffff0000))
  595. edca_be_dl |= 0x005e0000;
  596. }
  597. if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) &&
  598. (!rtlpriv->dm.disable_framebursting))) {
  599. cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
  600. cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
  601. if (cur_rxok_cnt > 4 * cur_txok_cnt) {
  602. if (!rtlpriv->dm.is_cur_rdlstate ||
  603. !rtlpriv->dm.current_turbo_edca) {
  604. rtl_write_dword(rtlpriv,
  605. REG_EDCA_BE_PARAM,
  606. edca_be_dl);
  607. rtlpriv->dm.is_cur_rdlstate = true;
  608. }
  609. } else {
  610. if (rtlpriv->dm.is_cur_rdlstate ||
  611. !rtlpriv->dm.current_turbo_edca) {
  612. rtl_write_dword(rtlpriv,
  613. REG_EDCA_BE_PARAM,
  614. edca_be_ul);
  615. rtlpriv->dm.is_cur_rdlstate = false;
  616. }
  617. }
  618. rtlpriv->dm.current_turbo_edca = true;
  619. } else {
  620. if (rtlpriv->dm.current_turbo_edca) {
  621. u8 tmp = AC0_BE;
  622. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
  623. &tmp);
  624. rtlpriv->dm.current_turbo_edca = false;
  625. }
  626. }
  627. rtlpriv->dm.is_any_nonbepkts = false;
  628. last_txok_cnt = rtlpriv->stats.txbytesunicast;
  629. last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
  630. }
  631. static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
  632. *hw)
  633. {
  634. struct rtl_priv *rtlpriv = rtl_priv(hw);
  635. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  636. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  637. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  638. u8 thermalvalue, delta, delta_lck, delta_iqk;
  639. long ele_a, ele_d, temp_cck, val_x, value32;
  640. long val_y, ele_c = 0;
  641. u8 ofdm_index[2], ofdm_index_old[2] = {0, 0}, cck_index_old = 0;
  642. s8 cck_index = 0;
  643. int i;
  644. bool is2t = IS_92C_SERIAL(rtlhal->version);
  645. s8 txpwr_level[3] = {0, 0, 0};
  646. u8 ofdm_min_index = 6, rf;
  647. rtlpriv->dm.txpower_trackinginit = true;
  648. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  649. "rtl92c_dm_txpower_tracking_callback_thermalmeter\n");
  650. thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
  651. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  652. "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n",
  653. thermalvalue, rtlpriv->dm.thermalvalue,
  654. rtlefuse->eeprom_thermalmeter);
  655. rtl92c_phy_ap_calibrate(hw, (thermalvalue -
  656. rtlefuse->eeprom_thermalmeter));
  657. if (is2t)
  658. rf = 2;
  659. else
  660. rf = 1;
  661. if (thermalvalue) {
  662. ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  663. MASKDWORD) & MASKOFDM_D;
  664. for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
  665. if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
  666. ofdm_index_old[0] = (u8) i;
  667. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  668. "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
  669. ROFDM0_XATXIQIMBALANCE,
  670. ele_d, ofdm_index_old[0]);
  671. break;
  672. }
  673. }
  674. if (is2t) {
  675. ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
  676. MASKDWORD) & MASKOFDM_D;
  677. for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
  678. if (ele_d == (ofdmswing_table[i] &
  679. MASKOFDM_D)) {
  680. ofdm_index_old[1] = (u8) i;
  681. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  682. DBG_LOUD,
  683. "Initial pathB ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
  684. ROFDM0_XBTXIQIMBALANCE, ele_d,
  685. ofdm_index_old[1]);
  686. break;
  687. }
  688. }
  689. }
  690. temp_cck =
  691. rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
  692. for (i = 0; i < CCK_TABLE_LENGTH; i++) {
  693. if (rtlpriv->dm.cck_inch14) {
  694. if (memcmp((void *)&temp_cck,
  695. (void *)&cckswing_table_ch14[i][2],
  696. 4) == 0) {
  697. cck_index_old = (u8) i;
  698. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  699. DBG_LOUD,
  700. "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch 14 %d\n",
  701. RCCK0_TXFILTER2, temp_cck,
  702. cck_index_old,
  703. rtlpriv->dm.cck_inch14);
  704. break;
  705. }
  706. } else {
  707. if (memcmp((void *)&temp_cck,
  708. (void *)
  709. &cckswing_table_ch1ch13[i][2],
  710. 4) == 0) {
  711. cck_index_old = (u8) i;
  712. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  713. DBG_LOUD,
  714. "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch14 %d\n",
  715. RCCK0_TXFILTER2, temp_cck,
  716. cck_index_old,
  717. rtlpriv->dm.cck_inch14);
  718. break;
  719. }
  720. }
  721. }
  722. if (!rtlpriv->dm.thermalvalue) {
  723. rtlpriv->dm.thermalvalue =
  724. rtlefuse->eeprom_thermalmeter;
  725. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  726. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  727. for (i = 0; i < rf; i++)
  728. rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
  729. rtlpriv->dm.cck_index = cck_index_old;
  730. }
  731. /* Handle USB High PA boards */
  732. delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
  733. (thermalvalue - rtlpriv->dm.thermalvalue) :
  734. (rtlpriv->dm.thermalvalue - thermalvalue);
  735. delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
  736. (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
  737. (rtlpriv->dm.thermalvalue_lck - thermalvalue);
  738. delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
  739. (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
  740. (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
  741. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  742. "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n",
  743. thermalvalue, rtlpriv->dm.thermalvalue,
  744. rtlefuse->eeprom_thermalmeter, delta, delta_lck,
  745. delta_iqk);
  746. if (delta_lck > 1) {
  747. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  748. rtl92c_phy_lc_calibrate(hw);
  749. }
  750. if (delta > 0 && rtlpriv->dm.txpower_track_control) {
  751. if (thermalvalue > rtlpriv->dm.thermalvalue) {
  752. for (i = 0; i < rf; i++)
  753. rtlpriv->dm.ofdm_index[i] -= delta;
  754. rtlpriv->dm.cck_index -= delta;
  755. } else {
  756. for (i = 0; i < rf; i++)
  757. rtlpriv->dm.ofdm_index[i] += delta;
  758. rtlpriv->dm.cck_index += delta;
  759. }
  760. if (is2t) {
  761. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  762. "temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
  763. rtlpriv->dm.ofdm_index[0],
  764. rtlpriv->dm.ofdm_index[1],
  765. rtlpriv->dm.cck_index);
  766. } else {
  767. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  768. "temp OFDM_A_index=0x%x, cck_index=0x%x\n",
  769. rtlpriv->dm.ofdm_index[0],
  770. rtlpriv->dm.cck_index);
  771. }
  772. if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
  773. for (i = 0; i < rf; i++)
  774. ofdm_index[i] =
  775. rtlpriv->dm.ofdm_index[i]
  776. + 1;
  777. cck_index = rtlpriv->dm.cck_index + 1;
  778. } else {
  779. for (i = 0; i < rf; i++)
  780. ofdm_index[i] =
  781. rtlpriv->dm.ofdm_index[i];
  782. cck_index = rtlpriv->dm.cck_index;
  783. }
  784. for (i = 0; i < rf; i++) {
  785. if (txpwr_level[i] >= 0 &&
  786. txpwr_level[i] <= 26) {
  787. if (thermalvalue >
  788. rtlefuse->eeprom_thermalmeter) {
  789. if (delta < 5)
  790. ofdm_index[i] -= 1;
  791. else
  792. ofdm_index[i] -= 2;
  793. } else if (delta > 5 && thermalvalue <
  794. rtlefuse->
  795. eeprom_thermalmeter) {
  796. ofdm_index[i] += 1;
  797. }
  798. } else if (txpwr_level[i] >= 27 &&
  799. txpwr_level[i] <= 32
  800. && thermalvalue >
  801. rtlefuse->eeprom_thermalmeter) {
  802. if (delta < 5)
  803. ofdm_index[i] -= 1;
  804. else
  805. ofdm_index[i] -= 2;
  806. } else if (txpwr_level[i] >= 32 &&
  807. txpwr_level[i] <= 38 &&
  808. thermalvalue >
  809. rtlefuse->eeprom_thermalmeter
  810. && delta > 5) {
  811. ofdm_index[i] -= 1;
  812. }
  813. }
  814. if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) {
  815. if (thermalvalue >
  816. rtlefuse->eeprom_thermalmeter) {
  817. if (delta < 5)
  818. cck_index -= 1;
  819. else
  820. cck_index -= 2;
  821. } else if (delta > 5 && thermalvalue <
  822. rtlefuse->eeprom_thermalmeter) {
  823. cck_index += 1;
  824. }
  825. } else if (txpwr_level[i] >= 27 &&
  826. txpwr_level[i] <= 32 &&
  827. thermalvalue >
  828. rtlefuse->eeprom_thermalmeter) {
  829. if (delta < 5)
  830. cck_index -= 1;
  831. else
  832. cck_index -= 2;
  833. } else if (txpwr_level[i] >= 32 &&
  834. txpwr_level[i] <= 38 &&
  835. thermalvalue > rtlefuse->eeprom_thermalmeter
  836. && delta > 5) {
  837. cck_index -= 1;
  838. }
  839. for (i = 0; i < rf; i++) {
  840. if (ofdm_index[i] > OFDM_TABLE_SIZE - 1)
  841. ofdm_index[i] = OFDM_TABLE_SIZE - 1;
  842. else if (ofdm_index[i] < ofdm_min_index)
  843. ofdm_index[i] = ofdm_min_index;
  844. }
  845. if (cck_index > CCK_TABLE_SIZE - 1)
  846. cck_index = CCK_TABLE_SIZE - 1;
  847. else if (cck_index < 0)
  848. cck_index = 0;
  849. if (is2t) {
  850. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  851. "new OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
  852. ofdm_index[0], ofdm_index[1],
  853. cck_index);
  854. } else {
  855. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  856. "new OFDM_A_index=0x%x, cck_index=0x%x\n",
  857. ofdm_index[0], cck_index);
  858. }
  859. }
  860. if (rtlpriv->dm.txpower_track_control && delta != 0) {
  861. ele_d =
  862. (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
  863. val_x = rtlphy->reg_e94;
  864. val_y = rtlphy->reg_e9c;
  865. if (val_x != 0) {
  866. if ((val_x & 0x00000200) != 0)
  867. val_x = val_x | 0xFFFFFC00;
  868. ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
  869. if ((val_y & 0x00000200) != 0)
  870. val_y = val_y | 0xFFFFFC00;
  871. ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
  872. value32 = (ele_d << 22) |
  873. ((ele_c & 0x3F) << 16) | ele_a;
  874. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  875. MASKDWORD, value32);
  876. value32 = (ele_c & 0x000003C0) >> 6;
  877. rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
  878. value32);
  879. value32 = ((val_x * ele_d) >> 7) & 0x01;
  880. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  881. BIT(31), value32);
  882. value32 = ((val_y * ele_d) >> 7) & 0x01;
  883. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  884. BIT(29), value32);
  885. } else {
  886. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  887. MASKDWORD,
  888. ofdmswing_table[ofdm_index[0]]);
  889. rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
  890. 0x00);
  891. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  892. BIT(31) | BIT(29), 0x00);
  893. }
  894. if (!rtlpriv->dm.cck_inch14) {
  895. rtl_write_byte(rtlpriv, 0xa22,
  896. cckswing_table_ch1ch13[cck_index]
  897. [0]);
  898. rtl_write_byte(rtlpriv, 0xa23,
  899. cckswing_table_ch1ch13[cck_index]
  900. [1]);
  901. rtl_write_byte(rtlpriv, 0xa24,
  902. cckswing_table_ch1ch13[cck_index]
  903. [2]);
  904. rtl_write_byte(rtlpriv, 0xa25,
  905. cckswing_table_ch1ch13[cck_index]
  906. [3]);
  907. rtl_write_byte(rtlpriv, 0xa26,
  908. cckswing_table_ch1ch13[cck_index]
  909. [4]);
  910. rtl_write_byte(rtlpriv, 0xa27,
  911. cckswing_table_ch1ch13[cck_index]
  912. [5]);
  913. rtl_write_byte(rtlpriv, 0xa28,
  914. cckswing_table_ch1ch13[cck_index]
  915. [6]);
  916. rtl_write_byte(rtlpriv, 0xa29,
  917. cckswing_table_ch1ch13[cck_index]
  918. [7]);
  919. } else {
  920. rtl_write_byte(rtlpriv, 0xa22,
  921. cckswing_table_ch14[cck_index]
  922. [0]);
  923. rtl_write_byte(rtlpriv, 0xa23,
  924. cckswing_table_ch14[cck_index]
  925. [1]);
  926. rtl_write_byte(rtlpriv, 0xa24,
  927. cckswing_table_ch14[cck_index]
  928. [2]);
  929. rtl_write_byte(rtlpriv, 0xa25,
  930. cckswing_table_ch14[cck_index]
  931. [3]);
  932. rtl_write_byte(rtlpriv, 0xa26,
  933. cckswing_table_ch14[cck_index]
  934. [4]);
  935. rtl_write_byte(rtlpriv, 0xa27,
  936. cckswing_table_ch14[cck_index]
  937. [5]);
  938. rtl_write_byte(rtlpriv, 0xa28,
  939. cckswing_table_ch14[cck_index]
  940. [6]);
  941. rtl_write_byte(rtlpriv, 0xa29,
  942. cckswing_table_ch14[cck_index]
  943. [7]);
  944. }
  945. if (is2t) {
  946. ele_d = (ofdmswing_table[ofdm_index[1]] &
  947. 0xFFC00000) >> 22;
  948. val_x = rtlphy->reg_eb4;
  949. val_y = rtlphy->reg_ebc;
  950. if (val_x != 0) {
  951. if ((val_x & 0x00000200) != 0)
  952. val_x = val_x | 0xFFFFFC00;
  953. ele_a = ((val_x * ele_d) >> 8) &
  954. 0x000003FF;
  955. if ((val_y & 0x00000200) != 0)
  956. val_y = val_y | 0xFFFFFC00;
  957. ele_c = ((val_y * ele_d) >> 8) &
  958. 0x00003FF;
  959. value32 = (ele_d << 22) |
  960. ((ele_c & 0x3F) << 16) | ele_a;
  961. rtl_set_bbreg(hw,
  962. ROFDM0_XBTXIQIMBALANCE,
  963. MASKDWORD, value32);
  964. value32 = (ele_c & 0x000003C0) >> 6;
  965. rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
  966. MASKH4BITS, value32);
  967. value32 = ((val_x * ele_d) >> 7) & 0x01;
  968. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  969. BIT(27), value32);
  970. value32 = ((val_y * ele_d) >> 7) & 0x01;
  971. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  972. BIT(25), value32);
  973. } else {
  974. rtl_set_bbreg(hw,
  975. ROFDM0_XBTXIQIMBALANCE,
  976. MASKDWORD,
  977. ofdmswing_table[ofdm_index
  978. [1]]);
  979. rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
  980. MASKH4BITS, 0x00);
  981. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  982. BIT(27) | BIT(25), 0x00);
  983. }
  984. }
  985. }
  986. if (delta_iqk > 3) {
  987. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  988. rtl92c_phy_iq_calibrate(hw, false);
  989. }
  990. if (rtlpriv->dm.txpower_track_control)
  991. rtlpriv->dm.thermalvalue = thermalvalue;
  992. }
  993. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n");
  994. }
  995. static void rtl92c_dm_initialize_txpower_tracking_thermalmeter(
  996. struct ieee80211_hw *hw)
  997. {
  998. struct rtl_priv *rtlpriv = rtl_priv(hw);
  999. rtlpriv->dm.txpower_tracking = true;
  1000. rtlpriv->dm.txpower_trackinginit = false;
  1001. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  1002. "pMgntInfo->txpower_tracking = %d\n",
  1003. rtlpriv->dm.txpower_tracking);
  1004. }
  1005. static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
  1006. {
  1007. rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw);
  1008. }
  1009. static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw)
  1010. {
  1011. rtl92c_dm_txpower_tracking_callback_thermalmeter(hw);
  1012. }
  1013. static void rtl92c_dm_check_txpower_tracking_thermal_meter(
  1014. struct ieee80211_hw *hw)
  1015. {
  1016. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1017. if (!rtlpriv->dm.txpower_tracking)
  1018. return;
  1019. if (!rtlpriv->dm.tm_trigger) {
  1020. rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK,
  1021. 0x60);
  1022. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  1023. "Trigger 92S Thermal Meter!!\n");
  1024. rtlpriv->dm.tm_trigger = 1;
  1025. return;
  1026. } else {
  1027. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  1028. "Schedule TxPowerTracking direct call!!\n");
  1029. rtl92c_dm_txpower_tracking_directcall(hw);
  1030. rtlpriv->dm.tm_trigger = 0;
  1031. }
  1032. }
  1033. void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw)
  1034. {
  1035. rtl92c_dm_check_txpower_tracking_thermal_meter(hw);
  1036. }
  1037. EXPORT_SYMBOL(rtl92c_dm_check_txpower_tracking);
  1038. void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
  1039. {
  1040. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1041. struct rate_adaptive *p_ra = &(rtlpriv->ra);
  1042. p_ra->ratr_state = DM_RATR_STA_INIT;
  1043. p_ra->pre_ratr_state = DM_RATR_STA_INIT;
  1044. if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
  1045. rtlpriv->dm.useramask = true;
  1046. else
  1047. rtlpriv->dm.useramask = false;
  1048. }
  1049. EXPORT_SYMBOL(rtl92c_dm_init_rate_adaptive_mask);
  1050. static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
  1051. {
  1052. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1053. struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
  1054. dm_pstable->pre_ccastate = CCA_MAX;
  1055. dm_pstable->cur_ccasate = CCA_MAX;
  1056. dm_pstable->pre_rfstate = RF_MAX;
  1057. dm_pstable->cur_rfstate = RF_MAX;
  1058. dm_pstable->rssi_val_min = 0;
  1059. }
  1060. void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
  1061. {
  1062. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1063. struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
  1064. if (!rtlpriv->reg_init) {
  1065. rtlpriv->reg_874 = (rtl_get_bbreg(hw,
  1066. RFPGA0_XCD_RFINTERFACESW,
  1067. MASKDWORD) & 0x1CC000) >> 14;
  1068. rtlpriv->reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
  1069. MASKDWORD) & BIT(3)) >> 3;
  1070. rtlpriv->reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
  1071. MASKDWORD) & 0xFF000000) >> 24;
  1072. rtlpriv->reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) &
  1073. 0xF000) >> 12;
  1074. rtlpriv->reg_init = true;
  1075. }
  1076. if (!bforce_in_normal) {
  1077. if (dm_pstable->rssi_val_min != 0) {
  1078. if (dm_pstable->pre_rfstate == RF_NORMAL) {
  1079. if (dm_pstable->rssi_val_min >= 30)
  1080. dm_pstable->cur_rfstate = RF_SAVE;
  1081. else
  1082. dm_pstable->cur_rfstate = RF_NORMAL;
  1083. } else {
  1084. if (dm_pstable->rssi_val_min <= 25)
  1085. dm_pstable->cur_rfstate = RF_NORMAL;
  1086. else
  1087. dm_pstable->cur_rfstate = RF_SAVE;
  1088. }
  1089. } else {
  1090. dm_pstable->cur_rfstate = RF_MAX;
  1091. }
  1092. } else {
  1093. dm_pstable->cur_rfstate = RF_NORMAL;
  1094. }
  1095. if (dm_pstable->pre_rfstate != dm_pstable->cur_rfstate) {
  1096. if (dm_pstable->cur_rfstate == RF_SAVE) {
  1097. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1098. 0x1C0000, 0x2);
  1099. rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
  1100. rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
  1101. 0xFF000000, 0x63);
  1102. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1103. 0xC000, 0x2);
  1104. rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
  1105. rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
  1106. rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
  1107. } else {
  1108. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1109. 0x1CC000, rtlpriv->reg_874);
  1110. rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
  1111. rtlpriv->reg_c70);
  1112. rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
  1113. rtlpriv->reg_85c);
  1114. rtl_set_bbreg(hw, 0xa74, 0xF000, rtlpriv->reg_a74);
  1115. rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
  1116. }
  1117. dm_pstable->pre_rfstate = dm_pstable->cur_rfstate;
  1118. }
  1119. }
  1120. EXPORT_SYMBOL(rtl92c_dm_rf_saving);
  1121. static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
  1122. {
  1123. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1124. struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
  1125. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1126. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1127. /* Determine the minimum RSSI */
  1128. if (((mac->link_state == MAC80211_NOLINK)) &&
  1129. (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
  1130. dm_pstable->rssi_val_min = 0;
  1131. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, "Not connected to any\n");
  1132. }
  1133. if (mac->link_state == MAC80211_LINKED) {
  1134. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  1135. dm_pstable->rssi_val_min =
  1136. rtlpriv->dm.entry_min_undec_sm_pwdb;
  1137. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1138. "AP Client PWDB = 0x%lx\n",
  1139. dm_pstable->rssi_val_min);
  1140. } else {
  1141. dm_pstable->rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
  1142. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1143. "STA Default Port PWDB = 0x%lx\n",
  1144. dm_pstable->rssi_val_min);
  1145. }
  1146. } else {
  1147. dm_pstable->rssi_val_min =
  1148. rtlpriv->dm.entry_min_undec_sm_pwdb;
  1149. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1150. "AP Ext Port PWDB = 0x%lx\n",
  1151. dm_pstable->rssi_val_min);
  1152. }
  1153. /* Power Saving for 92C */
  1154. if (IS_92C_SERIAL(rtlhal->version))
  1155. ;/* rtl92c_dm_1r_cca(hw); */
  1156. else
  1157. rtl92c_dm_rf_saving(hw, false);
  1158. }
  1159. void rtl92c_dm_init(struct ieee80211_hw *hw)
  1160. {
  1161. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1162. rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
  1163. rtlpriv->dm.dm_flag = DYNAMIC_FUNC_DISABLE | DYNAMIC_FUNC_DIG;
  1164. rtlpriv->dm.undec_sm_pwdb = -1;
  1165. rtlpriv->dm.undec_sm_cck = -1;
  1166. rtlpriv->dm.dm_initialgain_enable = true;
  1167. rtl_dm_diginit(hw, 0x20);
  1168. rtlpriv->dm.dm_flag |= HAL_DM_HIPWR_DISABLE;
  1169. rtl92c_dm_init_dynamic_txpower(hw);
  1170. rtl92c_dm_init_edca_turbo(hw);
  1171. rtl92c_dm_init_rate_adaptive_mask(hw);
  1172. rtlpriv->dm.dm_flag |= DYNAMIC_FUNC_SS;
  1173. rtl92c_dm_initialize_txpower_tracking(hw);
  1174. rtl92c_dm_init_dynamic_bb_powersaving(hw);
  1175. rtlpriv->dm.ofdm_pkt_cnt = 0;
  1176. rtlpriv->dm.dm_rssi_sel = RSSI_DEFAULT;
  1177. }
  1178. EXPORT_SYMBOL(rtl92c_dm_init);
  1179. void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
  1180. {
  1181. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1182. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  1183. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1184. long undec_sm_pwdb;
  1185. if (!rtlpriv->dm.dynamic_txpower_enable)
  1186. return;
  1187. if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
  1188. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  1189. return;
  1190. }
  1191. if ((mac->link_state < MAC80211_LINKED) &&
  1192. (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
  1193. RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
  1194. "Not connected to any\n");
  1195. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  1196. rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
  1197. return;
  1198. }
  1199. if (mac->link_state >= MAC80211_LINKED) {
  1200. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  1201. undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
  1202. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1203. "AP Client PWDB = 0x%lx\n",
  1204. undec_sm_pwdb);
  1205. } else {
  1206. undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb;
  1207. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1208. "STA Default Port PWDB = 0x%lx\n",
  1209. undec_sm_pwdb);
  1210. }
  1211. } else {
  1212. undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
  1213. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1214. "AP Ext Port PWDB = 0x%lx\n",
  1215. undec_sm_pwdb);
  1216. }
  1217. if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
  1218. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL2;
  1219. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1220. "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
  1221. } else if ((undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
  1222. (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
  1223. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
  1224. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1225. "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
  1226. } else if (undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
  1227. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  1228. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1229. "TXHIGHPWRLEVEL_NORMAL\n");
  1230. }
  1231. if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
  1232. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1233. "PHY_SetTxPowerLevel8192S() Channel = %d\n",
  1234. rtlphy->current_channel);
  1235. rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
  1236. if (rtlpriv->dm.dynamic_txhighpower_lvl ==
  1237. TXHIGHPWRLEVEL_NORMAL)
  1238. dm_restorepowerindex(hw);
  1239. else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
  1240. TXHIGHPWRLEVEL_LEVEL1)
  1241. dm_writepowerindex(hw, 0x14);
  1242. else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
  1243. TXHIGHPWRLEVEL_LEVEL2)
  1244. dm_writepowerindex(hw, 0x10);
  1245. }
  1246. rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
  1247. }
  1248. void rtl92c_dm_watchdog(struct ieee80211_hw *hw)
  1249. {
  1250. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1251. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  1252. bool fw_current_inpsmode = false;
  1253. bool fw_ps_awake = true;
  1254. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
  1255. (u8 *) (&fw_current_inpsmode));
  1256. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
  1257. (u8 *) (&fw_ps_awake));
  1258. if (ppsc->p2p_ps_info.p2p_ps_mode)
  1259. fw_ps_awake = false;
  1260. if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
  1261. fw_ps_awake)
  1262. && (!ppsc->rfchange_inprogress)) {
  1263. rtl92c_dm_pwdb_monitor(hw);
  1264. rtl92c_dm_dig(hw);
  1265. rtl92c_dm_false_alarm_counter_statistics(hw);
  1266. rtl92c_dm_dynamic_bb_powersaving(hw);
  1267. rtl92c_dm_dynamic_txpower(hw);
  1268. rtl92c_dm_check_txpower_tracking(hw);
  1269. /* rtl92c_dm_refresh_rate_adaptive_mask(hw); */
  1270. rtl92c_dm_bt_coexist(hw);
  1271. rtl92c_dm_check_edca_turbo(hw);
  1272. }
  1273. }
  1274. EXPORT_SYMBOL(rtl92c_dm_watchdog);
  1275. u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw)
  1276. {
  1277. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1278. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1279. long undec_sm_pwdb;
  1280. u8 curr_bt_rssi_state = 0x00;
  1281. if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
  1282. undec_sm_pwdb = GET_UNDECORATED_AVERAGE_RSSI(rtlpriv);
  1283. } else {
  1284. if (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)
  1285. undec_sm_pwdb = 100;
  1286. else
  1287. undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
  1288. }
  1289. /* Check RSSI to determine HighPower/NormalPower state for
  1290. * BT coexistence. */
  1291. if (undec_sm_pwdb >= 67)
  1292. curr_bt_rssi_state &= (~BT_RSSI_STATE_NORMAL_POWER);
  1293. else if (undec_sm_pwdb < 62)
  1294. curr_bt_rssi_state |= BT_RSSI_STATE_NORMAL_POWER;
  1295. /* Check RSSI to determine AMPDU setting for BT coexistence. */
  1296. if (undec_sm_pwdb >= 40)
  1297. curr_bt_rssi_state &= (~BT_RSSI_STATE_AMDPU_OFF);
  1298. else if (undec_sm_pwdb <= 32)
  1299. curr_bt_rssi_state |= BT_RSSI_STATE_AMDPU_OFF;
  1300. /* Marked RSSI state. It will be used to determine BT coexistence
  1301. * setting later. */
  1302. if (undec_sm_pwdb < 35)
  1303. curr_bt_rssi_state |= BT_RSSI_STATE_SPECIAL_LOW;
  1304. else
  1305. curr_bt_rssi_state &= (~BT_RSSI_STATE_SPECIAL_LOW);
  1306. /* Check BT state related to BT_Idle in B/G mode. */
  1307. if (undec_sm_pwdb < 15)
  1308. curr_bt_rssi_state |= BT_RSSI_STATE_BG_EDCA_LOW;
  1309. else
  1310. curr_bt_rssi_state &= (~BT_RSSI_STATE_BG_EDCA_LOW);
  1311. if (curr_bt_rssi_state != rtlpcipriv->bt_coexist.bt_rssi_state) {
  1312. rtlpcipriv->bt_coexist.bt_rssi_state = curr_bt_rssi_state;
  1313. return true;
  1314. } else {
  1315. return false;
  1316. }
  1317. }
  1318. EXPORT_SYMBOL(rtl92c_bt_rssi_state_change);
  1319. static bool rtl92c_bt_state_change(struct ieee80211_hw *hw)
  1320. {
  1321. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1322. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1323. u32 polling, ratio_tx, ratio_pri;
  1324. u32 bt_tx, bt_pri;
  1325. u8 bt_state;
  1326. u8 cur_service_type;
  1327. if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
  1328. return false;
  1329. bt_state = rtl_read_byte(rtlpriv, 0x4fd);
  1330. bt_tx = rtl_read_dword(rtlpriv, 0x488) & BT_MASK;
  1331. bt_pri = rtl_read_dword(rtlpriv, 0x48c) & BT_MASK;
  1332. polling = rtl_read_dword(rtlpriv, 0x490);
  1333. if (bt_tx == BT_MASK && bt_pri == BT_MASK &&
  1334. polling == 0xffffffff && bt_state == 0xff)
  1335. return false;
  1336. bt_state &= BIT_OFFSET_LEN_MASK_32(0, 1);
  1337. if (bt_state != rtlpcipriv->bt_coexist.bt_cur_state) {
  1338. rtlpcipriv->bt_coexist.bt_cur_state = bt_state;
  1339. if (rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
  1340. rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
  1341. bt_state = bt_state |
  1342. ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
  1343. 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
  1344. BIT_OFFSET_LEN_MASK_32(2, 1);
  1345. rtl_write_byte(rtlpriv, 0x4fd, bt_state);
  1346. }
  1347. return true;
  1348. }
  1349. ratio_tx = bt_tx * 1000 / polling;
  1350. ratio_pri = bt_pri * 1000 / polling;
  1351. rtlpcipriv->bt_coexist.ratio_tx = ratio_tx;
  1352. rtlpcipriv->bt_coexist.ratio_pri = ratio_pri;
  1353. if (bt_state && rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
  1354. if ((ratio_tx < 30) && (ratio_pri < 30))
  1355. cur_service_type = BT_IDLE;
  1356. else if ((ratio_pri > 110) && (ratio_pri < 250))
  1357. cur_service_type = BT_SCO;
  1358. else if ((ratio_tx >= 200) && (ratio_pri >= 200))
  1359. cur_service_type = BT_BUSY;
  1360. else if ((ratio_tx >= 350) && (ratio_tx < 500))
  1361. cur_service_type = BT_OTHERBUSY;
  1362. else if (ratio_tx >= 500)
  1363. cur_service_type = BT_PAN;
  1364. else
  1365. cur_service_type = BT_OTHER_ACTION;
  1366. if (cur_service_type != rtlpcipriv->bt_coexist.bt_service) {
  1367. rtlpcipriv->bt_coexist.bt_service = cur_service_type;
  1368. bt_state = bt_state |
  1369. ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
  1370. 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
  1371. ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) ?
  1372. 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
  1373. /* Add interrupt migration when bt is not ini
  1374. * idle state (no traffic). */
  1375. if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
  1376. rtl_write_word(rtlpriv, 0x504, 0x0ccc);
  1377. rtl_write_byte(rtlpriv, 0x506, 0x54);
  1378. rtl_write_byte(rtlpriv, 0x507, 0x54);
  1379. } else {
  1380. rtl_write_byte(rtlpriv, 0x506, 0x00);
  1381. rtl_write_byte(rtlpriv, 0x507, 0x00);
  1382. }
  1383. rtl_write_byte(rtlpriv, 0x4fd, bt_state);
  1384. return true;
  1385. }
  1386. }
  1387. return false;
  1388. }
  1389. static bool rtl92c_bt_wifi_connect_change(struct ieee80211_hw *hw)
  1390. {
  1391. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1392. static bool media_connect;
  1393. if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
  1394. media_connect = false;
  1395. } else {
  1396. if (!media_connect) {
  1397. media_connect = true;
  1398. return true;
  1399. }
  1400. media_connect = true;
  1401. }
  1402. return false;
  1403. }
  1404. static void rtl92c_bt_set_normal(struct ieee80211_hw *hw)
  1405. {
  1406. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1407. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1408. if (rtlpcipriv->bt_coexist.bt_service == BT_OTHERBUSY) {
  1409. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72b;
  1410. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72b;
  1411. } else if (rtlpcipriv->bt_coexist.bt_service == BT_BUSY) {
  1412. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82f;
  1413. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82f;
  1414. } else if (rtlpcipriv->bt_coexist.bt_service == BT_SCO) {
  1415. if (rtlpcipriv->bt_coexist.ratio_tx > 160) {
  1416. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72f;
  1417. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72f;
  1418. } else {
  1419. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea32b;
  1420. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea42b;
  1421. }
  1422. } else {
  1423. rtlpcipriv->bt_coexist.bt_edca_ul = 0;
  1424. rtlpcipriv->bt_coexist.bt_edca_dl = 0;
  1425. }
  1426. if ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) &&
  1427. (rtlpriv->mac80211.mode == WIRELESS_MODE_G ||
  1428. (rtlpriv->mac80211.mode == (WIRELESS_MODE_G | WIRELESS_MODE_B))) &&
  1429. (rtlpcipriv->bt_coexist.bt_rssi_state &
  1430. BT_RSSI_STATE_BG_EDCA_LOW)) {
  1431. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82b;
  1432. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82b;
  1433. }
  1434. }
  1435. static void rtl92c_bt_ant_isolation(struct ieee80211_hw *hw, u8 tmp1byte)
  1436. {
  1437. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1438. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1439. /* Only enable HW BT coexist when BT in "Busy" state. */
  1440. if (rtlpriv->mac80211.vendor == PEER_CISCO &&
  1441. rtlpcipriv->bt_coexist.bt_service == BT_OTHER_ACTION) {
  1442. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
  1443. } else {
  1444. if ((rtlpcipriv->bt_coexist.bt_service == BT_BUSY) &&
  1445. (rtlpcipriv->bt_coexist.bt_rssi_state &
  1446. BT_RSSI_STATE_NORMAL_POWER)) {
  1447. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
  1448. } else if ((rtlpcipriv->bt_coexist.bt_service ==
  1449. BT_OTHER_ACTION) && (rtlpriv->mac80211.mode <
  1450. WIRELESS_MODE_N_24G) &&
  1451. (rtlpcipriv->bt_coexist.bt_rssi_state &
  1452. BT_RSSI_STATE_SPECIAL_LOW)) {
  1453. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
  1454. } else if (rtlpcipriv->bt_coexist.bt_service == BT_PAN) {
  1455. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte);
  1456. } else {
  1457. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte);
  1458. }
  1459. }
  1460. if (rtlpcipriv->bt_coexist.bt_service == BT_PAN)
  1461. rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x10100);
  1462. else
  1463. rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x0);
  1464. if (rtlpcipriv->bt_coexist.bt_rssi_state &
  1465. BT_RSSI_STATE_NORMAL_POWER) {
  1466. rtl92c_bt_set_normal(hw);
  1467. } else {
  1468. rtlpcipriv->bt_coexist.bt_edca_ul = 0;
  1469. rtlpcipriv->bt_coexist.bt_edca_dl = 0;
  1470. }
  1471. if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
  1472. rtlpriv->cfg->ops->set_rfreg(hw,
  1473. RF90_PATH_A,
  1474. 0x1e,
  1475. 0xf0, 0xf);
  1476. } else {
  1477. rtlpriv->cfg->ops->set_rfreg(hw,
  1478. RF90_PATH_A, 0x1e, 0xf0,
  1479. rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
  1480. }
  1481. if (!rtlpriv->dm.dynamic_txpower_enable) {
  1482. if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
  1483. if (rtlpcipriv->bt_coexist.bt_rssi_state &
  1484. BT_RSSI_STATE_TXPOWER_LOW) {
  1485. rtlpriv->dm.dynamic_txhighpower_lvl =
  1486. TXHIGHPWRLEVEL_BT2;
  1487. } else {
  1488. rtlpriv->dm.dynamic_txhighpower_lvl =
  1489. TXHIGHPWRLEVEL_BT1;
  1490. }
  1491. } else {
  1492. rtlpriv->dm.dynamic_txhighpower_lvl =
  1493. TXHIGHPWRLEVEL_NORMAL;
  1494. }
  1495. rtl92c_phy_set_txpower_level(hw,
  1496. rtlpriv->phy.current_channel);
  1497. }
  1498. }
  1499. static void rtl92c_check_bt_change(struct ieee80211_hw *hw)
  1500. {
  1501. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1502. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1503. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1504. u8 tmp1byte = 0;
  1505. if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version) &&
  1506. rtlpcipriv->bt_coexist.bt_coexistence)
  1507. tmp1byte |= BIT(5);
  1508. if (rtlpcipriv->bt_coexist.bt_cur_state) {
  1509. if (rtlpcipriv->bt_coexist.bt_ant_isolation)
  1510. rtl92c_bt_ant_isolation(hw, tmp1byte);
  1511. } else {
  1512. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte);
  1513. rtlpriv->cfg->ops->set_rfreg(hw, RF90_PATH_A, 0x1e, 0xf0,
  1514. rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
  1515. rtlpcipriv->bt_coexist.bt_edca_ul = 0;
  1516. rtlpcipriv->bt_coexist.bt_edca_dl = 0;
  1517. }
  1518. }
  1519. void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw)
  1520. {
  1521. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1522. bool wifi_connect_change;
  1523. bool bt_state_change;
  1524. bool rssi_state_change;
  1525. if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
  1526. (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
  1527. wifi_connect_change = rtl92c_bt_wifi_connect_change(hw);
  1528. bt_state_change = rtl92c_bt_state_change(hw);
  1529. rssi_state_change = rtl92c_bt_rssi_state_change(hw);
  1530. if (wifi_connect_change || bt_state_change || rssi_state_change)
  1531. rtl92c_check_bt_change(hw);
  1532. }
  1533. }
  1534. EXPORT_SYMBOL(rtl92c_dm_bt_coexist);