fw.c 38 KB

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  1. /******************************************************************************
  2. *
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * GPL LICENSE SUMMARY
  7. *
  8. * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  9. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10. * Copyright(c) 2016 Intel Deutschland GmbH
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of version 2 of the GNU General Public License as
  14. * published by the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope that it will be useful, but
  17. * WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  24. * USA
  25. *
  26. * The full GNU General Public License is included in this distribution
  27. * in the file called COPYING.
  28. *
  29. * Contact Information:
  30. * Intel Linux Wireless <linuxwifi@intel.com>
  31. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  32. *
  33. * BSD LICENSE
  34. *
  35. * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  36. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  37. * All rights reserved.
  38. *
  39. * Redistribution and use in source and binary forms, with or without
  40. * modification, are permitted provided that the following conditions
  41. * are met:
  42. *
  43. * * Redistributions of source code must retain the above copyright
  44. * notice, this list of conditions and the following disclaimer.
  45. * * Redistributions in binary form must reproduce the above copyright
  46. * notice, this list of conditions and the following disclaimer in
  47. * the documentation and/or other materials provided with the
  48. * distribution.
  49. * * Neither the name Intel Corporation nor the names of its
  50. * contributors may be used to endorse or promote products derived
  51. * from this software without specific prior written permission.
  52. *
  53. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  54. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  55. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  56. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  57. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  58. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  59. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  60. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  61. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  62. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  63. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  64. *
  65. *****************************************************************************/
  66. #include <net/mac80211.h>
  67. #include <linux/netdevice.h>
  68. #include <linux/acpi.h>
  69. #include "iwl-trans.h"
  70. #include "iwl-op-mode.h"
  71. #include "iwl-fw.h"
  72. #include "iwl-debug.h"
  73. #include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */
  74. #include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */
  75. #include "iwl-prph.h"
  76. #include "iwl-eeprom-parse.h"
  77. #include "mvm.h"
  78. #include "fw-dbg.h"
  79. #include "iwl-phy-db.h"
  80. #define MVM_UCODE_ALIVE_TIMEOUT HZ
  81. #define MVM_UCODE_CALIB_TIMEOUT (2*HZ)
  82. #define UCODE_VALID_OK cpu_to_le32(0x1)
  83. struct iwl_mvm_alive_data {
  84. bool valid;
  85. u32 scd_base_addr;
  86. };
  87. static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant)
  88. {
  89. struct iwl_tx_ant_cfg_cmd tx_ant_cmd = {
  90. .valid = cpu_to_le32(valid_tx_ant),
  91. };
  92. IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant);
  93. return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0,
  94. sizeof(tx_ant_cmd), &tx_ant_cmd);
  95. }
  96. static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm)
  97. {
  98. int i;
  99. struct iwl_rss_config_cmd cmd = {
  100. .flags = cpu_to_le32(IWL_RSS_ENABLE),
  101. .hash_mask = IWL_RSS_HASH_TYPE_IPV4_TCP |
  102. IWL_RSS_HASH_TYPE_IPV4_UDP |
  103. IWL_RSS_HASH_TYPE_IPV4_PAYLOAD |
  104. IWL_RSS_HASH_TYPE_IPV6_TCP |
  105. IWL_RSS_HASH_TYPE_IPV6_UDP |
  106. IWL_RSS_HASH_TYPE_IPV6_PAYLOAD,
  107. };
  108. if (mvm->trans->num_rx_queues == 1)
  109. return 0;
  110. /* Do not direct RSS traffic to Q 0 which is our fallback queue */
  111. for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++)
  112. cmd.indirection_table[i] =
  113. 1 + (i % (mvm->trans->num_rx_queues - 1));
  114. netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key));
  115. return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd);
  116. }
  117. static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm)
  118. {
  119. struct iwl_dqa_enable_cmd dqa_cmd = {
  120. .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE),
  121. };
  122. u32 cmd_id = iwl_cmd_id(DQA_ENABLE_CMD, DATA_PATH_GROUP, 0);
  123. int ret;
  124. ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd);
  125. if (ret)
  126. IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret);
  127. else
  128. IWL_DEBUG_FW(mvm, "Working in DQA mode\n");
  129. return ret;
  130. }
  131. void iwl_free_fw_paging(struct iwl_mvm *mvm)
  132. {
  133. int i;
  134. if (!mvm->fw_paging_db[0].fw_paging_block)
  135. return;
  136. for (i = 0; i < NUM_OF_FW_PAGING_BLOCKS; i++) {
  137. struct iwl_fw_paging *paging = &mvm->fw_paging_db[i];
  138. if (!paging->fw_paging_block) {
  139. IWL_DEBUG_FW(mvm,
  140. "Paging: block %d already freed, continue to next page\n",
  141. i);
  142. continue;
  143. }
  144. dma_unmap_page(mvm->trans->dev, paging->fw_paging_phys,
  145. paging->fw_paging_size, DMA_BIDIRECTIONAL);
  146. __free_pages(paging->fw_paging_block,
  147. get_order(paging->fw_paging_size));
  148. paging->fw_paging_block = NULL;
  149. }
  150. kfree(mvm->trans->paging_download_buf);
  151. mvm->trans->paging_download_buf = NULL;
  152. mvm->trans->paging_db = NULL;
  153. memset(mvm->fw_paging_db, 0, sizeof(mvm->fw_paging_db));
  154. }
  155. static int iwl_fill_paging_mem(struct iwl_mvm *mvm, const struct fw_img *image)
  156. {
  157. int sec_idx, idx;
  158. u32 offset = 0;
  159. /*
  160. * find where is the paging image start point:
  161. * if CPU2 exist and it's in paging format, then the image looks like:
  162. * CPU1 sections (2 or more)
  163. * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between CPU1 to CPU2
  164. * CPU2 sections (not paged)
  165. * PAGING_SEPARATOR_SECTION delimiter - separate between CPU2
  166. * non paged to CPU2 paging sec
  167. * CPU2 paging CSS
  168. * CPU2 paging image (including instruction and data)
  169. */
  170. for (sec_idx = 0; sec_idx < IWL_UCODE_SECTION_MAX; sec_idx++) {
  171. if (image->sec[sec_idx].offset == PAGING_SEPARATOR_SECTION) {
  172. sec_idx++;
  173. break;
  174. }
  175. }
  176. /*
  177. * If paging is enabled there should be at least 2 more sections left
  178. * (one for CSS and one for Paging data)
  179. */
  180. if (sec_idx >= ARRAY_SIZE(image->sec) - 1) {
  181. IWL_ERR(mvm, "Paging: Missing CSS and/or paging sections\n");
  182. iwl_free_fw_paging(mvm);
  183. return -EINVAL;
  184. }
  185. /* copy the CSS block to the dram */
  186. IWL_DEBUG_FW(mvm, "Paging: load paging CSS to FW, sec = %d\n",
  187. sec_idx);
  188. memcpy(page_address(mvm->fw_paging_db[0].fw_paging_block),
  189. image->sec[sec_idx].data,
  190. mvm->fw_paging_db[0].fw_paging_size);
  191. IWL_DEBUG_FW(mvm,
  192. "Paging: copied %d CSS bytes to first block\n",
  193. mvm->fw_paging_db[0].fw_paging_size);
  194. sec_idx++;
  195. /*
  196. * copy the paging blocks to the dram
  197. * loop index start from 1 since that CSS block already copied to dram
  198. * and CSS index is 0.
  199. * loop stop at num_of_paging_blk since that last block is not full.
  200. */
  201. for (idx = 1; idx < mvm->num_of_paging_blk; idx++) {
  202. memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block),
  203. image->sec[sec_idx].data + offset,
  204. mvm->fw_paging_db[idx].fw_paging_size);
  205. IWL_DEBUG_FW(mvm,
  206. "Paging: copied %d paging bytes to block %d\n",
  207. mvm->fw_paging_db[idx].fw_paging_size,
  208. idx);
  209. offset += mvm->fw_paging_db[idx].fw_paging_size;
  210. }
  211. /* copy the last paging block */
  212. if (mvm->num_of_pages_in_last_blk > 0) {
  213. memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block),
  214. image->sec[sec_idx].data + offset,
  215. FW_PAGING_SIZE * mvm->num_of_pages_in_last_blk);
  216. IWL_DEBUG_FW(mvm,
  217. "Paging: copied %d pages in the last block %d\n",
  218. mvm->num_of_pages_in_last_blk, idx);
  219. }
  220. return 0;
  221. }
  222. static int iwl_alloc_fw_paging_mem(struct iwl_mvm *mvm,
  223. const struct fw_img *image)
  224. {
  225. struct page *block;
  226. dma_addr_t phys = 0;
  227. int blk_idx = 0;
  228. int order, num_of_pages;
  229. int dma_enabled;
  230. if (mvm->fw_paging_db[0].fw_paging_block)
  231. return 0;
  232. dma_enabled = is_device_dma_capable(mvm->trans->dev);
  233. /* ensure BLOCK_2_EXP_SIZE is power of 2 of PAGING_BLOCK_SIZE */
  234. BUILD_BUG_ON(BIT(BLOCK_2_EXP_SIZE) != PAGING_BLOCK_SIZE);
  235. num_of_pages = image->paging_mem_size / FW_PAGING_SIZE;
  236. mvm->num_of_paging_blk = ((num_of_pages - 1) /
  237. NUM_OF_PAGE_PER_GROUP) + 1;
  238. mvm->num_of_pages_in_last_blk =
  239. num_of_pages -
  240. NUM_OF_PAGE_PER_GROUP * (mvm->num_of_paging_blk - 1);
  241. IWL_DEBUG_FW(mvm,
  242. "Paging: allocating mem for %d paging blocks, each block holds 8 pages, last block holds %d pages\n",
  243. mvm->num_of_paging_blk,
  244. mvm->num_of_pages_in_last_blk);
  245. /* allocate block of 4Kbytes for paging CSS */
  246. order = get_order(FW_PAGING_SIZE);
  247. block = alloc_pages(GFP_KERNEL, order);
  248. if (!block) {
  249. /* free all the previous pages since we failed */
  250. iwl_free_fw_paging(mvm);
  251. return -ENOMEM;
  252. }
  253. mvm->fw_paging_db[blk_idx].fw_paging_block = block;
  254. mvm->fw_paging_db[blk_idx].fw_paging_size = FW_PAGING_SIZE;
  255. if (dma_enabled) {
  256. phys = dma_map_page(mvm->trans->dev, block, 0,
  257. PAGE_SIZE << order, DMA_BIDIRECTIONAL);
  258. if (dma_mapping_error(mvm->trans->dev, phys)) {
  259. /*
  260. * free the previous pages and the current one since
  261. * we failed to map_page.
  262. */
  263. iwl_free_fw_paging(mvm);
  264. return -ENOMEM;
  265. }
  266. mvm->fw_paging_db[blk_idx].fw_paging_phys = phys;
  267. } else {
  268. mvm->fw_paging_db[blk_idx].fw_paging_phys = PAGING_ADDR_SIG |
  269. blk_idx << BLOCK_2_EXP_SIZE;
  270. }
  271. IWL_DEBUG_FW(mvm,
  272. "Paging: allocated 4K(CSS) bytes (order %d) for firmware paging.\n",
  273. order);
  274. /*
  275. * allocate blocks in dram.
  276. * since that CSS allocated in fw_paging_db[0] loop start from index 1
  277. */
  278. for (blk_idx = 1; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) {
  279. /* allocate block of PAGING_BLOCK_SIZE (32K) */
  280. order = get_order(PAGING_BLOCK_SIZE);
  281. block = alloc_pages(GFP_KERNEL, order);
  282. if (!block) {
  283. /* free all the previous pages since we failed */
  284. iwl_free_fw_paging(mvm);
  285. return -ENOMEM;
  286. }
  287. mvm->fw_paging_db[blk_idx].fw_paging_block = block;
  288. mvm->fw_paging_db[blk_idx].fw_paging_size = PAGING_BLOCK_SIZE;
  289. if (dma_enabled) {
  290. phys = dma_map_page(mvm->trans->dev, block, 0,
  291. PAGE_SIZE << order,
  292. DMA_BIDIRECTIONAL);
  293. if (dma_mapping_error(mvm->trans->dev, phys)) {
  294. /*
  295. * free the previous pages and the current one
  296. * since we failed to map_page.
  297. */
  298. iwl_free_fw_paging(mvm);
  299. return -ENOMEM;
  300. }
  301. mvm->fw_paging_db[blk_idx].fw_paging_phys = phys;
  302. } else {
  303. mvm->fw_paging_db[blk_idx].fw_paging_phys =
  304. PAGING_ADDR_SIG |
  305. blk_idx << BLOCK_2_EXP_SIZE;
  306. }
  307. IWL_DEBUG_FW(mvm,
  308. "Paging: allocated 32K bytes (order %d) for firmware paging.\n",
  309. order);
  310. }
  311. return 0;
  312. }
  313. static int iwl_save_fw_paging(struct iwl_mvm *mvm,
  314. const struct fw_img *fw)
  315. {
  316. int ret;
  317. ret = iwl_alloc_fw_paging_mem(mvm, fw);
  318. if (ret)
  319. return ret;
  320. return iwl_fill_paging_mem(mvm, fw);
  321. }
  322. /* send paging cmd to FW in case CPU2 has paging image */
  323. static int iwl_send_paging_cmd(struct iwl_mvm *mvm, const struct fw_img *fw)
  324. {
  325. struct iwl_fw_paging_cmd paging_cmd = {
  326. .flags =
  327. cpu_to_le32(PAGING_CMD_IS_SECURED |
  328. PAGING_CMD_IS_ENABLED |
  329. (mvm->num_of_pages_in_last_blk <<
  330. PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS)),
  331. .block_size = cpu_to_le32(BLOCK_2_EXP_SIZE),
  332. .block_num = cpu_to_le32(mvm->num_of_paging_blk),
  333. };
  334. int blk_idx, size = sizeof(paging_cmd);
  335. /* A bit hard coded - but this is the old API and will be deprecated */
  336. if (!iwl_mvm_has_new_tx_api(mvm))
  337. size -= NUM_OF_FW_PAGING_BLOCKS * 4;
  338. /* loop for for all paging blocks + CSS block */
  339. for (blk_idx = 0; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) {
  340. dma_addr_t addr = mvm->fw_paging_db[blk_idx].fw_paging_phys;
  341. addr = addr >> PAGE_2_EXP_SIZE;
  342. if (iwl_mvm_has_new_tx_api(mvm)) {
  343. __le64 phy_addr = cpu_to_le64(addr);
  344. paging_cmd.device_phy_addr.addr64[blk_idx] = phy_addr;
  345. } else {
  346. __le32 phy_addr = cpu_to_le32(addr);
  347. paging_cmd.device_phy_addr.addr32[blk_idx] = phy_addr;
  348. }
  349. }
  350. return iwl_mvm_send_cmd_pdu(mvm, iwl_cmd_id(FW_PAGING_BLOCK_CMD,
  351. IWL_ALWAYS_LONG_GROUP, 0),
  352. 0, size, &paging_cmd);
  353. }
  354. /*
  355. * Send paging item cmd to FW in case CPU2 has paging image
  356. */
  357. static int iwl_trans_get_paging_item(struct iwl_mvm *mvm)
  358. {
  359. int ret;
  360. struct iwl_fw_get_item_cmd fw_get_item_cmd = {
  361. .item_id = cpu_to_le32(IWL_FW_ITEM_ID_PAGING),
  362. };
  363. struct iwl_fw_get_item_resp *item_resp;
  364. struct iwl_host_cmd cmd = {
  365. .id = iwl_cmd_id(FW_GET_ITEM_CMD, IWL_ALWAYS_LONG_GROUP, 0),
  366. .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
  367. .data = { &fw_get_item_cmd, },
  368. };
  369. cmd.len[0] = sizeof(struct iwl_fw_get_item_cmd);
  370. ret = iwl_mvm_send_cmd(mvm, &cmd);
  371. if (ret) {
  372. IWL_ERR(mvm,
  373. "Paging: Failed to send FW_GET_ITEM_CMD cmd (err = %d)\n",
  374. ret);
  375. return ret;
  376. }
  377. item_resp = (void *)((struct iwl_rx_packet *)cmd.resp_pkt)->data;
  378. if (item_resp->item_id != cpu_to_le32(IWL_FW_ITEM_ID_PAGING)) {
  379. IWL_ERR(mvm,
  380. "Paging: got wrong item in FW_GET_ITEM_CMD resp (item_id = %u)\n",
  381. le32_to_cpu(item_resp->item_id));
  382. ret = -EIO;
  383. goto exit;
  384. }
  385. /* Add an extra page for headers */
  386. mvm->trans->paging_download_buf = kzalloc(PAGING_BLOCK_SIZE +
  387. FW_PAGING_SIZE,
  388. GFP_KERNEL);
  389. if (!mvm->trans->paging_download_buf) {
  390. ret = -ENOMEM;
  391. goto exit;
  392. }
  393. mvm->trans->paging_req_addr = le32_to_cpu(item_resp->item_val);
  394. mvm->trans->paging_db = mvm->fw_paging_db;
  395. IWL_DEBUG_FW(mvm,
  396. "Paging: got paging request address (paging_req_addr 0x%08x)\n",
  397. mvm->trans->paging_req_addr);
  398. exit:
  399. iwl_free_resp(&cmd);
  400. return ret;
  401. }
  402. static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait,
  403. struct iwl_rx_packet *pkt, void *data)
  404. {
  405. struct iwl_mvm *mvm =
  406. container_of(notif_wait, struct iwl_mvm, notif_wait);
  407. struct iwl_mvm_alive_data *alive_data = data;
  408. struct mvm_alive_resp_ver1 *palive1;
  409. struct mvm_alive_resp_ver2 *palive2;
  410. struct mvm_alive_resp *palive;
  411. if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive1)) {
  412. palive1 = (void *)pkt->data;
  413. mvm->support_umac_log = false;
  414. mvm->error_event_table =
  415. le32_to_cpu(palive1->error_event_table_ptr);
  416. mvm->log_event_table =
  417. le32_to_cpu(palive1->log_event_table_ptr);
  418. alive_data->scd_base_addr = le32_to_cpu(palive1->scd_base_ptr);
  419. alive_data->valid = le16_to_cpu(palive1->status) ==
  420. IWL_ALIVE_STATUS_OK;
  421. IWL_DEBUG_FW(mvm,
  422. "Alive VER1 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
  423. le16_to_cpu(palive1->status), palive1->ver_type,
  424. palive1->ver_subtype, palive1->flags);
  425. } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive2)) {
  426. palive2 = (void *)pkt->data;
  427. mvm->error_event_table =
  428. le32_to_cpu(palive2->error_event_table_ptr);
  429. mvm->log_event_table =
  430. le32_to_cpu(palive2->log_event_table_ptr);
  431. alive_data->scd_base_addr = le32_to_cpu(palive2->scd_base_ptr);
  432. mvm->umac_error_event_table =
  433. le32_to_cpu(palive2->error_info_addr);
  434. mvm->sf_space.addr = le32_to_cpu(palive2->st_fwrd_addr);
  435. mvm->sf_space.size = le32_to_cpu(palive2->st_fwrd_size);
  436. alive_data->valid = le16_to_cpu(palive2->status) ==
  437. IWL_ALIVE_STATUS_OK;
  438. if (mvm->umac_error_event_table)
  439. mvm->support_umac_log = true;
  440. IWL_DEBUG_FW(mvm,
  441. "Alive VER2 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
  442. le16_to_cpu(palive2->status), palive2->ver_type,
  443. palive2->ver_subtype, palive2->flags);
  444. IWL_DEBUG_FW(mvm,
  445. "UMAC version: Major - 0x%x, Minor - 0x%x\n",
  446. palive2->umac_major, palive2->umac_minor);
  447. } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) {
  448. palive = (void *)pkt->data;
  449. mvm->error_event_table =
  450. le32_to_cpu(palive->error_event_table_ptr);
  451. mvm->log_event_table =
  452. le32_to_cpu(palive->log_event_table_ptr);
  453. alive_data->scd_base_addr = le32_to_cpu(palive->scd_base_ptr);
  454. mvm->umac_error_event_table =
  455. le32_to_cpu(palive->error_info_addr);
  456. mvm->sf_space.addr = le32_to_cpu(palive->st_fwrd_addr);
  457. mvm->sf_space.size = le32_to_cpu(palive->st_fwrd_size);
  458. alive_data->valid = le16_to_cpu(palive->status) ==
  459. IWL_ALIVE_STATUS_OK;
  460. if (mvm->umac_error_event_table)
  461. mvm->support_umac_log = true;
  462. IWL_DEBUG_FW(mvm,
  463. "Alive VER3 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
  464. le16_to_cpu(palive->status), palive->ver_type,
  465. palive->ver_subtype, palive->flags);
  466. IWL_DEBUG_FW(mvm,
  467. "UMAC version: Major - 0x%x, Minor - 0x%x\n",
  468. le32_to_cpu(palive->umac_major),
  469. le32_to_cpu(palive->umac_minor));
  470. }
  471. return true;
  472. }
  473. static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait,
  474. struct iwl_rx_packet *pkt, void *data)
  475. {
  476. struct iwl_phy_db *phy_db = data;
  477. if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) {
  478. WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
  479. return true;
  480. }
  481. WARN_ON(iwl_phy_db_set_section(phy_db, pkt));
  482. return false;
  483. }
  484. static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
  485. enum iwl_ucode_type ucode_type)
  486. {
  487. struct iwl_notification_wait alive_wait;
  488. struct iwl_mvm_alive_data alive_data;
  489. const struct fw_img *fw;
  490. int ret, i;
  491. enum iwl_ucode_type old_type = mvm->cur_ucode;
  492. static const u16 alive_cmd[] = { MVM_ALIVE };
  493. struct iwl_sf_region st_fwrd_space;
  494. if (ucode_type == IWL_UCODE_REGULAR &&
  495. iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) &&
  496. !(fw_has_capa(&mvm->fw->ucode_capa,
  497. IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED)))
  498. fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER);
  499. else
  500. fw = iwl_get_ucode_image(mvm->fw, ucode_type);
  501. if (WARN_ON(!fw))
  502. return -EINVAL;
  503. mvm->cur_ucode = ucode_type;
  504. mvm->ucode_loaded = false;
  505. iwl_init_notification_wait(&mvm->notif_wait, &alive_wait,
  506. alive_cmd, ARRAY_SIZE(alive_cmd),
  507. iwl_alive_fn, &alive_data);
  508. ret = iwl_trans_start_fw(mvm->trans, fw, ucode_type == IWL_UCODE_INIT);
  509. if (ret) {
  510. mvm->cur_ucode = old_type;
  511. iwl_remove_notification(&mvm->notif_wait, &alive_wait);
  512. return ret;
  513. }
  514. /*
  515. * Some things may run in the background now, but we
  516. * just wait for the ALIVE notification here.
  517. */
  518. ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait,
  519. MVM_UCODE_ALIVE_TIMEOUT);
  520. if (ret) {
  521. if (mvm->trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
  522. IWL_ERR(mvm,
  523. "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
  524. iwl_read_prph(mvm->trans, SB_CPU_1_STATUS),
  525. iwl_read_prph(mvm->trans, SB_CPU_2_STATUS));
  526. mvm->cur_ucode = old_type;
  527. return ret;
  528. }
  529. if (!alive_data.valid) {
  530. IWL_ERR(mvm, "Loaded ucode is not valid!\n");
  531. mvm->cur_ucode = old_type;
  532. return -EIO;
  533. }
  534. /*
  535. * update the sdio allocation according to the pointer we get in the
  536. * alive notification.
  537. */
  538. st_fwrd_space.addr = mvm->sf_space.addr;
  539. st_fwrd_space.size = mvm->sf_space.size;
  540. ret = iwl_trans_update_sf(mvm->trans, &st_fwrd_space);
  541. if (ret) {
  542. IWL_ERR(mvm, "Failed to update SF size. ret %d\n", ret);
  543. return ret;
  544. }
  545. iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr);
  546. /*
  547. * configure and operate fw paging mechanism.
  548. * driver configures the paging flow only once, CPU2 paging image
  549. * included in the IWL_UCODE_INIT image.
  550. */
  551. if (fw->paging_mem_size) {
  552. /*
  553. * When dma is not enabled, the driver needs to copy / write
  554. * the downloaded / uploaded page to / from the smem.
  555. * This gets the location of the place were the pages are
  556. * stored.
  557. */
  558. if (!is_device_dma_capable(mvm->trans->dev)) {
  559. ret = iwl_trans_get_paging_item(mvm);
  560. if (ret) {
  561. IWL_ERR(mvm, "failed to get FW paging item\n");
  562. return ret;
  563. }
  564. }
  565. ret = iwl_save_fw_paging(mvm, fw);
  566. if (ret) {
  567. IWL_ERR(mvm, "failed to save the FW paging image\n");
  568. return ret;
  569. }
  570. ret = iwl_send_paging_cmd(mvm, fw);
  571. if (ret) {
  572. IWL_ERR(mvm, "failed to send the paging cmd\n");
  573. iwl_free_fw_paging(mvm);
  574. return ret;
  575. }
  576. }
  577. /*
  578. * Note: all the queues are enabled as part of the interface
  579. * initialization, but in firmware restart scenarios they
  580. * could be stopped, so wake them up. In firmware restart,
  581. * mac80211 will have the queues stopped as well until the
  582. * reconfiguration completes. During normal startup, they
  583. * will be empty.
  584. */
  585. memset(&mvm->queue_info, 0, sizeof(mvm->queue_info));
  586. if (iwl_mvm_is_dqa_supported(mvm))
  587. mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].hw_queue_refcount = 1;
  588. else
  589. mvm->queue_info[IWL_MVM_CMD_QUEUE].hw_queue_refcount = 1;
  590. for (i = 0; i < IEEE80211_MAX_QUEUES; i++)
  591. atomic_set(&mvm->mac80211_queue_stop_count[i], 0);
  592. mvm->ucode_loaded = true;
  593. return 0;
  594. }
  595. static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
  596. {
  597. struct iwl_phy_cfg_cmd phy_cfg_cmd;
  598. enum iwl_ucode_type ucode_type = mvm->cur_ucode;
  599. /* Set parameters */
  600. phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm));
  601. phy_cfg_cmd.calib_control.event_trigger =
  602. mvm->fw->default_calib[ucode_type].event_trigger;
  603. phy_cfg_cmd.calib_control.flow_trigger =
  604. mvm->fw->default_calib[ucode_type].flow_trigger;
  605. IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n",
  606. phy_cfg_cmd.phy_cfg);
  607. return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0,
  608. sizeof(phy_cfg_cmd), &phy_cfg_cmd);
  609. }
  610. int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm)
  611. {
  612. struct iwl_notification_wait calib_wait;
  613. static const u16 init_complete[] = {
  614. INIT_COMPLETE_NOTIF,
  615. CALIB_RES_NOTIF_PHY_DB
  616. };
  617. int ret;
  618. lockdep_assert_held(&mvm->mutex);
  619. if (WARN_ON_ONCE(mvm->calibrating))
  620. return 0;
  621. iwl_init_notification_wait(&mvm->notif_wait,
  622. &calib_wait,
  623. init_complete,
  624. ARRAY_SIZE(init_complete),
  625. iwl_wait_phy_db_entry,
  626. mvm->phy_db);
  627. /* Will also start the device */
  628. ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT);
  629. if (ret) {
  630. IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret);
  631. goto error;
  632. }
  633. ret = iwl_send_bt_init_conf(mvm);
  634. if (ret)
  635. goto error;
  636. /* Read the NVM only at driver load time, no need to do this twice */
  637. if (read_nvm) {
  638. /* Read nvm */
  639. ret = iwl_nvm_init(mvm, true);
  640. if (ret) {
  641. IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
  642. goto error;
  643. }
  644. }
  645. /* In case we read the NVM from external file, load it to the NIC */
  646. if (mvm->nvm_file_name)
  647. iwl_mvm_load_nvm_to_nic(mvm);
  648. ret = iwl_nvm_check_version(mvm->nvm_data, mvm->trans);
  649. WARN_ON(ret);
  650. /*
  651. * abort after reading the nvm in case RF Kill is on, we will complete
  652. * the init seq later when RF kill will switch to off
  653. */
  654. if (iwl_mvm_is_radio_hw_killed(mvm)) {
  655. IWL_DEBUG_RF_KILL(mvm,
  656. "jump over all phy activities due to RF kill\n");
  657. iwl_remove_notification(&mvm->notif_wait, &calib_wait);
  658. ret = 1;
  659. goto out;
  660. }
  661. mvm->calibrating = true;
  662. /* Send TX valid antennas before triggering calibrations */
  663. ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
  664. if (ret)
  665. goto error;
  666. /*
  667. * Send phy configurations command to init uCode
  668. * to start the 16.0 uCode init image internal calibrations.
  669. */
  670. ret = iwl_send_phy_cfg_cmd(mvm);
  671. if (ret) {
  672. IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
  673. ret);
  674. goto error;
  675. }
  676. /*
  677. * Some things may run in the background now, but we
  678. * just wait for the calibration complete notification.
  679. */
  680. ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait,
  681. MVM_UCODE_CALIB_TIMEOUT);
  682. if (ret && iwl_mvm_is_radio_hw_killed(mvm)) {
  683. IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n");
  684. ret = 1;
  685. }
  686. goto out;
  687. error:
  688. iwl_remove_notification(&mvm->notif_wait, &calib_wait);
  689. out:
  690. mvm->calibrating = false;
  691. if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) {
  692. /* we want to debug INIT and we have no NVM - fake */
  693. mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) +
  694. sizeof(struct ieee80211_channel) +
  695. sizeof(struct ieee80211_rate),
  696. GFP_KERNEL);
  697. if (!mvm->nvm_data)
  698. return -ENOMEM;
  699. mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels;
  700. mvm->nvm_data->bands[0].n_channels = 1;
  701. mvm->nvm_data->bands[0].n_bitrates = 1;
  702. mvm->nvm_data->bands[0].bitrates =
  703. (void *)mvm->nvm_data->channels + 1;
  704. mvm->nvm_data->bands[0].bitrates->hw_value = 10;
  705. }
  706. return ret;
  707. }
  708. static void iwl_mvm_parse_shared_mem_a000(struct iwl_mvm *mvm,
  709. struct iwl_rx_packet *pkt)
  710. {
  711. struct iwl_shared_mem_cfg *mem_cfg = (void *)pkt->data;
  712. int i;
  713. mvm->shared_mem_cfg.num_txfifo_entries =
  714. ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size);
  715. for (i = 0; i < ARRAY_SIZE(mem_cfg->txfifo_size); i++)
  716. mvm->shared_mem_cfg.txfifo_size[i] =
  717. le32_to_cpu(mem_cfg->txfifo_size[i]);
  718. for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++)
  719. mvm->shared_mem_cfg.rxfifo_size[i] =
  720. le32_to_cpu(mem_cfg->rxfifo_size[i]);
  721. BUILD_BUG_ON(sizeof(mvm->shared_mem_cfg.internal_txfifo_size) !=
  722. sizeof(mem_cfg->internal_txfifo_size));
  723. for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.internal_txfifo_size);
  724. i++)
  725. mvm->shared_mem_cfg.internal_txfifo_size[i] =
  726. le32_to_cpu(mem_cfg->internal_txfifo_size[i]);
  727. }
  728. static void iwl_mvm_parse_shared_mem(struct iwl_mvm *mvm,
  729. struct iwl_rx_packet *pkt)
  730. {
  731. struct iwl_shared_mem_cfg_v1 *mem_cfg = (void *)pkt->data;
  732. int i;
  733. mvm->shared_mem_cfg.num_txfifo_entries =
  734. ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size);
  735. for (i = 0; i < ARRAY_SIZE(mem_cfg->txfifo_size); i++)
  736. mvm->shared_mem_cfg.txfifo_size[i] =
  737. le32_to_cpu(mem_cfg->txfifo_size[i]);
  738. for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++)
  739. mvm->shared_mem_cfg.rxfifo_size[i] =
  740. le32_to_cpu(mem_cfg->rxfifo_size[i]);
  741. /* new API has more data, from rxfifo_addr field and on */
  742. if (fw_has_capa(&mvm->fw->ucode_capa,
  743. IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) {
  744. BUILD_BUG_ON(sizeof(mvm->shared_mem_cfg.internal_txfifo_size) !=
  745. sizeof(mem_cfg->internal_txfifo_size));
  746. for (i = 0;
  747. i < ARRAY_SIZE(mvm->shared_mem_cfg.internal_txfifo_size);
  748. i++)
  749. mvm->shared_mem_cfg.internal_txfifo_size[i] =
  750. le32_to_cpu(mem_cfg->internal_txfifo_size[i]);
  751. }
  752. }
  753. static void iwl_mvm_get_shared_mem_conf(struct iwl_mvm *mvm)
  754. {
  755. struct iwl_host_cmd cmd = {
  756. .flags = CMD_WANT_SKB,
  757. .data = { NULL, },
  758. .len = { 0, },
  759. };
  760. struct iwl_rx_packet *pkt;
  761. lockdep_assert_held(&mvm->mutex);
  762. if (fw_has_capa(&mvm->fw->ucode_capa,
  763. IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))
  764. cmd.id = iwl_cmd_id(SHARED_MEM_CFG_CMD, SYSTEM_GROUP, 0);
  765. else
  766. cmd.id = SHARED_MEM_CFG;
  767. if (WARN_ON(iwl_mvm_send_cmd(mvm, &cmd)))
  768. return;
  769. pkt = cmd.resp_pkt;
  770. if (iwl_mvm_has_new_tx_api(mvm))
  771. iwl_mvm_parse_shared_mem_a000(mvm, pkt);
  772. else
  773. iwl_mvm_parse_shared_mem(mvm, pkt);
  774. IWL_DEBUG_INFO(mvm, "SHARED MEM CFG: got memory offsets/sizes\n");
  775. iwl_free_resp(&cmd);
  776. }
  777. static int iwl_mvm_config_ltr(struct iwl_mvm *mvm)
  778. {
  779. struct iwl_ltr_config_cmd cmd = {
  780. .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE),
  781. };
  782. if (!mvm->trans->ltr_enabled)
  783. return 0;
  784. return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0,
  785. sizeof(cmd), &cmd);
  786. }
  787. #define ACPI_WRDS_METHOD "WRDS"
  788. #define ACPI_WRDS_WIFI (0x07)
  789. #define ACPI_WRDS_TABLE_SIZE 10
  790. struct iwl_mvm_sar_table {
  791. bool enabled;
  792. u8 values[ACPI_WRDS_TABLE_SIZE];
  793. };
  794. #ifdef CONFIG_ACPI
  795. static int iwl_mvm_sar_get_wrds(struct iwl_mvm *mvm, union acpi_object *wrds,
  796. struct iwl_mvm_sar_table *sar_table)
  797. {
  798. union acpi_object *data_pkg;
  799. u32 i;
  800. /* We need at least two packages, one for the revision and one
  801. * for the data itself. Also check that the revision is valid
  802. * (i.e. it is an integer set to 0).
  803. */
  804. if (wrds->type != ACPI_TYPE_PACKAGE ||
  805. wrds->package.count < 2 ||
  806. wrds->package.elements[0].type != ACPI_TYPE_INTEGER ||
  807. wrds->package.elements[0].integer.value != 0) {
  808. IWL_DEBUG_RADIO(mvm, "Unsupported wrds structure\n");
  809. return -EINVAL;
  810. }
  811. /* loop through all the packages to find the one for WiFi */
  812. for (i = 1; i < wrds->package.count; i++) {
  813. union acpi_object *domain;
  814. data_pkg = &wrds->package.elements[i];
  815. /* Skip anything that is not a package with the right
  816. * amount of elements (i.e. domain_type,
  817. * enabled/disabled plus the sar table size.
  818. */
  819. if (data_pkg->type != ACPI_TYPE_PACKAGE ||
  820. data_pkg->package.count != ACPI_WRDS_TABLE_SIZE + 2)
  821. continue;
  822. domain = &data_pkg->package.elements[0];
  823. if (domain->type == ACPI_TYPE_INTEGER &&
  824. domain->integer.value == ACPI_WRDS_WIFI)
  825. break;
  826. data_pkg = NULL;
  827. }
  828. if (!data_pkg)
  829. return -ENOENT;
  830. if (data_pkg->package.elements[1].type != ACPI_TYPE_INTEGER)
  831. return -EINVAL;
  832. sar_table->enabled = !!(data_pkg->package.elements[1].integer.value);
  833. for (i = 0; i < ACPI_WRDS_TABLE_SIZE; i++) {
  834. union acpi_object *entry;
  835. entry = &data_pkg->package.elements[i + 2];
  836. if ((entry->type != ACPI_TYPE_INTEGER) ||
  837. (entry->integer.value > U8_MAX))
  838. return -EINVAL;
  839. sar_table->values[i] = entry->integer.value;
  840. }
  841. return 0;
  842. }
  843. static int iwl_mvm_sar_get_table(struct iwl_mvm *mvm,
  844. struct iwl_mvm_sar_table *sar_table)
  845. {
  846. acpi_handle root_handle;
  847. acpi_handle handle;
  848. struct acpi_buffer wrds = {ACPI_ALLOCATE_BUFFER, NULL};
  849. acpi_status status;
  850. int ret;
  851. root_handle = ACPI_HANDLE(mvm->dev);
  852. if (!root_handle) {
  853. IWL_DEBUG_RADIO(mvm,
  854. "Could not retrieve root port ACPI handle\n");
  855. return -ENOENT;
  856. }
  857. /* Get the method's handle */
  858. status = acpi_get_handle(root_handle, (acpi_string)ACPI_WRDS_METHOD,
  859. &handle);
  860. if (ACPI_FAILURE(status)) {
  861. IWL_DEBUG_RADIO(mvm, "WRDS method not found\n");
  862. return -ENOENT;
  863. }
  864. /* Call WRDS with no arguments */
  865. status = acpi_evaluate_object(handle, NULL, NULL, &wrds);
  866. if (ACPI_FAILURE(status)) {
  867. IWL_DEBUG_RADIO(mvm, "WRDS invocation failed (0x%x)\n", status);
  868. return -ENOENT;
  869. }
  870. ret = iwl_mvm_sar_get_wrds(mvm, wrds.pointer, sar_table);
  871. kfree(wrds.pointer);
  872. return ret;
  873. }
  874. #else /* CONFIG_ACPI */
  875. static int iwl_mvm_sar_get_table(struct iwl_mvm *mvm,
  876. struct iwl_mvm_sar_table *sar_table)
  877. {
  878. return -ENOENT;
  879. }
  880. #endif /* CONFIG_ACPI */
  881. static int iwl_mvm_sar_init(struct iwl_mvm *mvm)
  882. {
  883. struct iwl_mvm_sar_table sar_table;
  884. struct iwl_dev_tx_power_cmd cmd = {
  885. .v3.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS),
  886. };
  887. int ret, i, j, idx;
  888. int len = sizeof(cmd);
  889. if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_TX_POWER_ACK))
  890. len = sizeof(cmd.v3);
  891. ret = iwl_mvm_sar_get_table(mvm, &sar_table);
  892. if (ret < 0) {
  893. IWL_DEBUG_RADIO(mvm,
  894. "SAR BIOS table invalid or unavailable. (%d)\n",
  895. ret);
  896. /* we don't fail if the table is not available */
  897. return 0;
  898. }
  899. if (!sar_table.enabled)
  900. return 0;
  901. IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n");
  902. BUILD_BUG_ON(IWL_NUM_CHAIN_LIMITS * IWL_NUM_SUB_BANDS !=
  903. ACPI_WRDS_TABLE_SIZE);
  904. for (i = 0; i < IWL_NUM_CHAIN_LIMITS; i++) {
  905. IWL_DEBUG_RADIO(mvm, " Chain[%d]:\n", i);
  906. for (j = 0; j < IWL_NUM_SUB_BANDS; j++) {
  907. idx = (i * IWL_NUM_SUB_BANDS) + j;
  908. cmd.v3.per_chain_restriction[i][j] =
  909. cpu_to_le16(sar_table.values[idx]);
  910. IWL_DEBUG_RADIO(mvm, " Band[%d] = %d * .125dBm\n",
  911. j, sar_table.values[idx]);
  912. }
  913. }
  914. ret = iwl_mvm_send_cmd_pdu(mvm, REDUCE_TX_POWER_CMD, 0, len, &cmd);
  915. if (ret)
  916. IWL_ERR(mvm, "failed to set per-chain TX power: %d\n", ret);
  917. return ret;
  918. }
  919. int iwl_mvm_up(struct iwl_mvm *mvm)
  920. {
  921. int ret, i;
  922. struct ieee80211_channel *chan;
  923. struct cfg80211_chan_def chandef;
  924. lockdep_assert_held(&mvm->mutex);
  925. ret = iwl_trans_start_hw(mvm->trans);
  926. if (ret)
  927. return ret;
  928. /*
  929. * If we haven't completed the run of the init ucode during
  930. * module loading, load init ucode now
  931. * (for example, if we were in RFKILL)
  932. */
  933. ret = iwl_run_init_mvm_ucode(mvm, false);
  934. if (iwlmvm_mod_params.init_dbg)
  935. return 0;
  936. if (ret) {
  937. IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret);
  938. /* this can't happen */
  939. if (WARN_ON(ret > 0))
  940. ret = -ERFKILL;
  941. goto error;
  942. }
  943. /*
  944. * Stop and start the transport without entering low power
  945. * mode. This will save the state of other components on the
  946. * device that are triggered by the INIT firwmare (MFUART).
  947. */
  948. _iwl_trans_stop_device(mvm->trans, false);
  949. ret = _iwl_trans_start_hw(mvm->trans, false);
  950. if (ret)
  951. goto error;
  952. ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
  953. if (ret) {
  954. IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
  955. goto error;
  956. }
  957. iwl_mvm_get_shared_mem_conf(mvm);
  958. ret = iwl_mvm_sf_update(mvm, NULL, false);
  959. if (ret)
  960. IWL_ERR(mvm, "Failed to initialize Smart Fifo\n");
  961. mvm->fw_dbg_conf = FW_DBG_INVALID;
  962. /* if we have a destination, assume EARLY START */
  963. if (mvm->fw->dbg_dest_tlv)
  964. mvm->fw_dbg_conf = FW_DBG_START_FROM_ALIVE;
  965. iwl_mvm_start_fw_dbg_conf(mvm, FW_DBG_START_FROM_ALIVE);
  966. ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
  967. if (ret)
  968. goto error;
  969. ret = iwl_send_bt_init_conf(mvm);
  970. if (ret)
  971. goto error;
  972. /* Send phy db control command and then phy db calibration*/
  973. ret = iwl_send_phy_db_data(mvm->phy_db);
  974. if (ret)
  975. goto error;
  976. ret = iwl_send_phy_cfg_cmd(mvm);
  977. if (ret)
  978. goto error;
  979. /* Init RSS configuration */
  980. if (iwl_mvm_has_new_rx_api(mvm)) {
  981. ret = iwl_send_rss_cfg_cmd(mvm);
  982. if (ret) {
  983. IWL_ERR(mvm, "Failed to configure RSS queues: %d\n",
  984. ret);
  985. goto error;
  986. }
  987. }
  988. /* init the fw <-> mac80211 STA mapping */
  989. for (i = 0; i < IWL_MVM_STATION_COUNT; i++)
  990. RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
  991. mvm->tdls_cs.peer.sta_id = IWL_MVM_STATION_COUNT;
  992. /* reset quota debouncing buffer - 0xff will yield invalid data */
  993. memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd));
  994. /* Enable DQA-mode if required */
  995. if (iwl_mvm_is_dqa_supported(mvm)) {
  996. ret = iwl_mvm_send_dqa_cmd(mvm);
  997. if (ret)
  998. goto error;
  999. } else {
  1000. IWL_DEBUG_FW(mvm, "Working in non-DQA mode\n");
  1001. }
  1002. /* Add auxiliary station for scanning */
  1003. ret = iwl_mvm_add_aux_sta(mvm);
  1004. if (ret)
  1005. goto error;
  1006. /* Add all the PHY contexts */
  1007. chan = &mvm->hw->wiphy->bands[NL80211_BAND_2GHZ]->channels[0];
  1008. cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT);
  1009. for (i = 0; i < NUM_PHY_CTX; i++) {
  1010. /*
  1011. * The channel used here isn't relevant as it's
  1012. * going to be overwritten in the other flows.
  1013. * For now use the first channel we have.
  1014. */
  1015. ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i],
  1016. &chandef, 1, 1);
  1017. if (ret)
  1018. goto error;
  1019. }
  1020. #ifdef CONFIG_THERMAL
  1021. if (iwl_mvm_is_tt_in_fw(mvm)) {
  1022. /* in order to give the responsibility of ct-kill and
  1023. * TX backoff to FW we need to send empty temperature reporting
  1024. * cmd during init time
  1025. */
  1026. iwl_mvm_send_temp_report_ths_cmd(mvm);
  1027. } else {
  1028. /* Initialize tx backoffs to the minimal possible */
  1029. iwl_mvm_tt_tx_backoff(mvm, 0);
  1030. }
  1031. /* TODO: read the budget from BIOS / Platform NVM */
  1032. if (iwl_mvm_is_ctdp_supported(mvm) && mvm->cooling_dev.cur_state > 0) {
  1033. ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START,
  1034. mvm->cooling_dev.cur_state);
  1035. if (ret)
  1036. goto error;
  1037. }
  1038. #else
  1039. /* Initialize tx backoffs to the minimal possible */
  1040. iwl_mvm_tt_tx_backoff(mvm, 0);
  1041. #endif
  1042. WARN_ON(iwl_mvm_config_ltr(mvm));
  1043. ret = iwl_mvm_power_update_device(mvm);
  1044. if (ret)
  1045. goto error;
  1046. /*
  1047. * RTNL is not taken during Ct-kill, but we don't need to scan/Tx
  1048. * anyway, so don't init MCC.
  1049. */
  1050. if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) {
  1051. ret = iwl_mvm_init_mcc(mvm);
  1052. if (ret)
  1053. goto error;
  1054. }
  1055. if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) {
  1056. mvm->scan_type = IWL_SCAN_TYPE_NOT_SET;
  1057. ret = iwl_mvm_config_scan(mvm);
  1058. if (ret)
  1059. goto error;
  1060. }
  1061. if (iwl_mvm_is_csum_supported(mvm) &&
  1062. mvm->cfg->features & NETIF_F_RXCSUM)
  1063. iwl_trans_write_prph(mvm->trans, RX_EN_CSUM, 0x3);
  1064. /* allow FW/transport low power modes if not during restart */
  1065. if (!test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status))
  1066. iwl_mvm_unref(mvm, IWL_MVM_REF_UCODE_DOWN);
  1067. ret = iwl_mvm_sar_init(mvm);
  1068. if (ret)
  1069. goto error;
  1070. IWL_DEBUG_INFO(mvm, "RT uCode started.\n");
  1071. return 0;
  1072. error:
  1073. iwl_mvm_stop_device(mvm);
  1074. return ret;
  1075. }
  1076. int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm)
  1077. {
  1078. int ret, i;
  1079. lockdep_assert_held(&mvm->mutex);
  1080. ret = iwl_trans_start_hw(mvm->trans);
  1081. if (ret)
  1082. return ret;
  1083. ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN);
  1084. if (ret) {
  1085. IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret);
  1086. goto error;
  1087. }
  1088. ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
  1089. if (ret)
  1090. goto error;
  1091. /* Send phy db control command and then phy db calibration*/
  1092. ret = iwl_send_phy_db_data(mvm->phy_db);
  1093. if (ret)
  1094. goto error;
  1095. ret = iwl_send_phy_cfg_cmd(mvm);
  1096. if (ret)
  1097. goto error;
  1098. /* init the fw <-> mac80211 STA mapping */
  1099. for (i = 0; i < IWL_MVM_STATION_COUNT; i++)
  1100. RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
  1101. /* Add auxiliary station for scanning */
  1102. ret = iwl_mvm_add_aux_sta(mvm);
  1103. if (ret)
  1104. goto error;
  1105. return 0;
  1106. error:
  1107. iwl_mvm_stop_device(mvm);
  1108. return ret;
  1109. }
  1110. void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm,
  1111. struct iwl_rx_cmd_buffer *rxb)
  1112. {
  1113. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1114. struct iwl_card_state_notif *card_state_notif = (void *)pkt->data;
  1115. u32 flags = le32_to_cpu(card_state_notif->flags);
  1116. IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n",
  1117. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  1118. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  1119. (flags & CT_KILL_CARD_DISABLED) ?
  1120. "Reached" : "Not reached");
  1121. }
  1122. void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm,
  1123. struct iwl_rx_cmd_buffer *rxb)
  1124. {
  1125. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1126. struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data;
  1127. IWL_DEBUG_INFO(mvm,
  1128. "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n",
  1129. le32_to_cpu(mfuart_notif->installed_ver),
  1130. le32_to_cpu(mfuart_notif->external_ver),
  1131. le32_to_cpu(mfuart_notif->status),
  1132. le32_to_cpu(mfuart_notif->duration));
  1133. }