core.c 61 KB

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  1. /*
  2. * Copyright (c) 2005-2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/firmware.h>
  19. #include <linux/of.h>
  20. #include <asm/byteorder.h>
  21. #include "core.h"
  22. #include "mac.h"
  23. #include "htc.h"
  24. #include "hif.h"
  25. #include "wmi.h"
  26. #include "bmi.h"
  27. #include "debug.h"
  28. #include "htt.h"
  29. #include "testmode.h"
  30. #include "wmi-ops.h"
  31. unsigned int ath10k_debug_mask;
  32. static unsigned int ath10k_cryptmode_param;
  33. static bool uart_print;
  34. static bool skip_otp;
  35. static bool rawmode;
  36. module_param_named(debug_mask, ath10k_debug_mask, uint, 0644);
  37. module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644);
  38. module_param(uart_print, bool, 0644);
  39. module_param(skip_otp, bool, 0644);
  40. module_param(rawmode, bool, 0644);
  41. MODULE_PARM_DESC(debug_mask, "Debugging mask");
  42. MODULE_PARM_DESC(uart_print, "Uart target debugging");
  43. MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode");
  44. MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
  45. MODULE_PARM_DESC(rawmode, "Use raw 802.11 frame datapath");
  46. static const struct ath10k_hw_params ath10k_hw_params_list[] = {
  47. {
  48. .id = QCA988X_HW_2_0_VERSION,
  49. .dev_id = QCA988X_2_0_DEVICE_ID,
  50. .name = "qca988x hw2.0",
  51. .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
  52. .uart_pin = 7,
  53. .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
  54. .otp_exe_param = 0,
  55. .channel_counters_freq_hz = 88000,
  56. .max_probe_resp_desc_thres = 0,
  57. .cal_data_len = 2116,
  58. .fw = {
  59. .dir = QCA988X_HW_2_0_FW_DIR,
  60. .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
  61. .board_size = QCA988X_BOARD_DATA_SZ,
  62. .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
  63. },
  64. .hw_ops = &qca988x_ops,
  65. .decap_align_bytes = 4,
  66. },
  67. {
  68. .id = QCA9887_HW_1_0_VERSION,
  69. .dev_id = QCA9887_1_0_DEVICE_ID,
  70. .name = "qca9887 hw1.0",
  71. .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR,
  72. .uart_pin = 7,
  73. .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
  74. .otp_exe_param = 0,
  75. .channel_counters_freq_hz = 88000,
  76. .max_probe_resp_desc_thres = 0,
  77. .cal_data_len = 2116,
  78. .fw = {
  79. .dir = QCA9887_HW_1_0_FW_DIR,
  80. .board = QCA9887_HW_1_0_BOARD_DATA_FILE,
  81. .board_size = QCA9887_BOARD_DATA_SZ,
  82. .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ,
  83. },
  84. .hw_ops = &qca988x_ops,
  85. .decap_align_bytes = 4,
  86. },
  87. {
  88. .id = QCA6174_HW_2_1_VERSION,
  89. .dev_id = QCA6164_2_1_DEVICE_ID,
  90. .name = "qca6164 hw2.1",
  91. .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
  92. .uart_pin = 6,
  93. .otp_exe_param = 0,
  94. .channel_counters_freq_hz = 88000,
  95. .max_probe_resp_desc_thres = 0,
  96. .cal_data_len = 8124,
  97. .fw = {
  98. .dir = QCA6174_HW_2_1_FW_DIR,
  99. .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
  100. .board_size = QCA6174_BOARD_DATA_SZ,
  101. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  102. },
  103. .hw_ops = &qca988x_ops,
  104. .decap_align_bytes = 4,
  105. },
  106. {
  107. .id = QCA6174_HW_2_1_VERSION,
  108. .dev_id = QCA6174_2_1_DEVICE_ID,
  109. .name = "qca6174 hw2.1",
  110. .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
  111. .uart_pin = 6,
  112. .otp_exe_param = 0,
  113. .channel_counters_freq_hz = 88000,
  114. .max_probe_resp_desc_thres = 0,
  115. .cal_data_len = 8124,
  116. .fw = {
  117. .dir = QCA6174_HW_2_1_FW_DIR,
  118. .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
  119. .board_size = QCA6174_BOARD_DATA_SZ,
  120. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  121. },
  122. .hw_ops = &qca988x_ops,
  123. .decap_align_bytes = 4,
  124. },
  125. {
  126. .id = QCA6174_HW_3_0_VERSION,
  127. .dev_id = QCA6174_2_1_DEVICE_ID,
  128. .name = "qca6174 hw3.0",
  129. .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
  130. .uart_pin = 6,
  131. .otp_exe_param = 0,
  132. .channel_counters_freq_hz = 88000,
  133. .max_probe_resp_desc_thres = 0,
  134. .cal_data_len = 8124,
  135. .fw = {
  136. .dir = QCA6174_HW_3_0_FW_DIR,
  137. .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
  138. .board_size = QCA6174_BOARD_DATA_SZ,
  139. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  140. },
  141. .hw_ops = &qca988x_ops,
  142. .decap_align_bytes = 4,
  143. },
  144. {
  145. .id = QCA6174_HW_3_2_VERSION,
  146. .dev_id = QCA6174_2_1_DEVICE_ID,
  147. .name = "qca6174 hw3.2",
  148. .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
  149. .uart_pin = 6,
  150. .otp_exe_param = 0,
  151. .channel_counters_freq_hz = 88000,
  152. .max_probe_resp_desc_thres = 0,
  153. .cal_data_len = 8124,
  154. .fw = {
  155. /* uses same binaries as hw3.0 */
  156. .dir = QCA6174_HW_3_0_FW_DIR,
  157. .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
  158. .board_size = QCA6174_BOARD_DATA_SZ,
  159. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  160. },
  161. .hw_ops = &qca988x_ops,
  162. .decap_align_bytes = 4,
  163. },
  164. {
  165. .id = QCA99X0_HW_2_0_DEV_VERSION,
  166. .dev_id = QCA99X0_2_0_DEVICE_ID,
  167. .name = "qca99x0 hw2.0",
  168. .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
  169. .uart_pin = 7,
  170. .otp_exe_param = 0x00000700,
  171. .continuous_frag_desc = true,
  172. .cck_rate_map_rev2 = true,
  173. .channel_counters_freq_hz = 150000,
  174. .max_probe_resp_desc_thres = 24,
  175. .tx_chain_mask = 0xf,
  176. .rx_chain_mask = 0xf,
  177. .max_spatial_stream = 4,
  178. .cal_data_len = 12064,
  179. .fw = {
  180. .dir = QCA99X0_HW_2_0_FW_DIR,
  181. .board = QCA99X0_HW_2_0_BOARD_DATA_FILE,
  182. .board_size = QCA99X0_BOARD_DATA_SZ,
  183. .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
  184. },
  185. .sw_decrypt_mcast_mgmt = true,
  186. .hw_ops = &qca99x0_ops,
  187. .decap_align_bytes = 1,
  188. },
  189. {
  190. .id = QCA9984_HW_1_0_DEV_VERSION,
  191. .dev_id = QCA9984_1_0_DEVICE_ID,
  192. .name = "qca9984/qca9994 hw1.0",
  193. .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR,
  194. .uart_pin = 7,
  195. .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
  196. .otp_exe_param = 0x00000700,
  197. .continuous_frag_desc = true,
  198. .cck_rate_map_rev2 = true,
  199. .channel_counters_freq_hz = 150000,
  200. .max_probe_resp_desc_thres = 24,
  201. .tx_chain_mask = 0xf,
  202. .rx_chain_mask = 0xf,
  203. .max_spatial_stream = 4,
  204. .cal_data_len = 12064,
  205. .fw = {
  206. .dir = QCA9984_HW_1_0_FW_DIR,
  207. .board = QCA9984_HW_1_0_BOARD_DATA_FILE,
  208. .board_size = QCA99X0_BOARD_DATA_SZ,
  209. .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
  210. },
  211. .sw_decrypt_mcast_mgmt = true,
  212. .hw_ops = &qca99x0_ops,
  213. .decap_align_bytes = 1,
  214. },
  215. {
  216. .id = QCA9888_HW_2_0_DEV_VERSION,
  217. .dev_id = QCA9888_2_0_DEVICE_ID,
  218. .name = "qca9888 hw2.0",
  219. .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR,
  220. .uart_pin = 7,
  221. .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
  222. .otp_exe_param = 0x00000700,
  223. .continuous_frag_desc = true,
  224. .channel_counters_freq_hz = 150000,
  225. .max_probe_resp_desc_thres = 24,
  226. .tx_chain_mask = 3,
  227. .rx_chain_mask = 3,
  228. .max_spatial_stream = 2,
  229. .cal_data_len = 12064,
  230. .fw = {
  231. .dir = QCA9888_HW_2_0_FW_DIR,
  232. .board = QCA9888_HW_2_0_BOARD_DATA_FILE,
  233. .board_size = QCA99X0_BOARD_DATA_SZ,
  234. .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
  235. },
  236. .sw_decrypt_mcast_mgmt = true,
  237. .hw_ops = &qca99x0_ops,
  238. .decap_align_bytes = 1,
  239. },
  240. {
  241. .id = QCA9377_HW_1_0_DEV_VERSION,
  242. .dev_id = QCA9377_1_0_DEVICE_ID,
  243. .name = "qca9377 hw1.0",
  244. .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
  245. .uart_pin = 6,
  246. .otp_exe_param = 0,
  247. .channel_counters_freq_hz = 88000,
  248. .max_probe_resp_desc_thres = 0,
  249. .cal_data_len = 8124,
  250. .fw = {
  251. .dir = QCA9377_HW_1_0_FW_DIR,
  252. .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
  253. .board_size = QCA9377_BOARD_DATA_SZ,
  254. .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
  255. },
  256. .hw_ops = &qca988x_ops,
  257. .decap_align_bytes = 4,
  258. },
  259. {
  260. .id = QCA9377_HW_1_1_DEV_VERSION,
  261. .dev_id = QCA9377_1_0_DEVICE_ID,
  262. .name = "qca9377 hw1.1",
  263. .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
  264. .uart_pin = 6,
  265. .otp_exe_param = 0,
  266. .channel_counters_freq_hz = 88000,
  267. .max_probe_resp_desc_thres = 0,
  268. .cal_data_len = 8124,
  269. .fw = {
  270. .dir = QCA9377_HW_1_0_FW_DIR,
  271. .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
  272. .board_size = QCA9377_BOARD_DATA_SZ,
  273. .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
  274. },
  275. .hw_ops = &qca988x_ops,
  276. .decap_align_bytes = 4,
  277. },
  278. {
  279. .id = QCA4019_HW_1_0_DEV_VERSION,
  280. .dev_id = 0,
  281. .name = "qca4019 hw1.0",
  282. .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR,
  283. .uart_pin = 7,
  284. .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
  285. .otp_exe_param = 0x0010000,
  286. .continuous_frag_desc = true,
  287. .cck_rate_map_rev2 = true,
  288. .channel_counters_freq_hz = 125000,
  289. .max_probe_resp_desc_thres = 24,
  290. .tx_chain_mask = 0x3,
  291. .rx_chain_mask = 0x3,
  292. .max_spatial_stream = 2,
  293. .cal_data_len = 12064,
  294. .fw = {
  295. .dir = QCA4019_HW_1_0_FW_DIR,
  296. .board = QCA4019_HW_1_0_BOARD_DATA_FILE,
  297. .board_size = QCA4019_BOARD_DATA_SZ,
  298. .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ,
  299. },
  300. .sw_decrypt_mcast_mgmt = true,
  301. .hw_ops = &qca99x0_ops,
  302. .decap_align_bytes = 1,
  303. },
  304. };
  305. static const char *const ath10k_core_fw_feature_str[] = {
  306. [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx",
  307. [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x",
  308. [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx",
  309. [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p",
  310. [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2",
  311. [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps",
  312. [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan",
  313. [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp",
  314. [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad",
  315. [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init",
  316. [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode",
  317. [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca",
  318. [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp",
  319. [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl",
  320. [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param",
  321. [ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war",
  322. [ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST] = "allows-mesh-bcast",
  323. };
  324. static unsigned int ath10k_core_get_fw_feature_str(char *buf,
  325. size_t buf_len,
  326. enum ath10k_fw_features feat)
  327. {
  328. /* make sure that ath10k_core_fw_feature_str[] gets updated */
  329. BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) !=
  330. ATH10K_FW_FEATURE_COUNT);
  331. if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) ||
  332. WARN_ON(!ath10k_core_fw_feature_str[feat])) {
  333. return scnprintf(buf, buf_len, "bit%d", feat);
  334. }
  335. return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]);
  336. }
  337. void ath10k_core_get_fw_features_str(struct ath10k *ar,
  338. char *buf,
  339. size_t buf_len)
  340. {
  341. unsigned int len = 0;
  342. int i;
  343. for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
  344. if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) {
  345. if (len > 0)
  346. len += scnprintf(buf + len, buf_len - len, ",");
  347. len += ath10k_core_get_fw_feature_str(buf + len,
  348. buf_len - len,
  349. i);
  350. }
  351. }
  352. }
  353. static void ath10k_send_suspend_complete(struct ath10k *ar)
  354. {
  355. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n");
  356. complete(&ar->target_suspend);
  357. }
  358. static int ath10k_init_configure_target(struct ath10k *ar)
  359. {
  360. u32 param_host;
  361. int ret;
  362. /* tell target which HTC version it is used*/
  363. ret = ath10k_bmi_write32(ar, hi_app_host_interest,
  364. HTC_PROTOCOL_VERSION);
  365. if (ret) {
  366. ath10k_err(ar, "settings HTC version failed\n");
  367. return ret;
  368. }
  369. /* set the firmware mode to STA/IBSS/AP */
  370. ret = ath10k_bmi_read32(ar, hi_option_flag, &param_host);
  371. if (ret) {
  372. ath10k_err(ar, "setting firmware mode (1/2) failed\n");
  373. return ret;
  374. }
  375. /* TODO following parameters need to be re-visited. */
  376. /* num_device */
  377. param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT);
  378. /* Firmware mode */
  379. /* FIXME: Why FW_MODE_AP ??.*/
  380. param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT);
  381. /* mac_addr_method */
  382. param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
  383. /* firmware_bridge */
  384. param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
  385. /* fwsubmode */
  386. param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT);
  387. ret = ath10k_bmi_write32(ar, hi_option_flag, param_host);
  388. if (ret) {
  389. ath10k_err(ar, "setting firmware mode (2/2) failed\n");
  390. return ret;
  391. }
  392. /* We do all byte-swapping on the host */
  393. ret = ath10k_bmi_write32(ar, hi_be, 0);
  394. if (ret) {
  395. ath10k_err(ar, "setting host CPU BE mode failed\n");
  396. return ret;
  397. }
  398. /* FW descriptor/Data swap flags */
  399. ret = ath10k_bmi_write32(ar, hi_fw_swap, 0);
  400. if (ret) {
  401. ath10k_err(ar, "setting FW data/desc swap flags failed\n");
  402. return ret;
  403. }
  404. /* Some devices have a special sanity check that verifies the PCI
  405. * Device ID is written to this host interest var. It is known to be
  406. * required to boot QCA6164.
  407. */
  408. ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext,
  409. ar->dev_id);
  410. if (ret) {
  411. ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret);
  412. return ret;
  413. }
  414. return 0;
  415. }
  416. static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar,
  417. const char *dir,
  418. const char *file)
  419. {
  420. char filename[100];
  421. const struct firmware *fw;
  422. int ret;
  423. if (file == NULL)
  424. return ERR_PTR(-ENOENT);
  425. if (dir == NULL)
  426. dir = ".";
  427. snprintf(filename, sizeof(filename), "%s/%s", dir, file);
  428. ret = request_firmware(&fw, filename, ar->dev);
  429. if (ret)
  430. return ERR_PTR(ret);
  431. return fw;
  432. }
  433. static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data,
  434. size_t data_len)
  435. {
  436. u32 board_data_size = ar->hw_params.fw.board_size;
  437. u32 board_ext_data_size = ar->hw_params.fw.board_ext_size;
  438. u32 board_ext_data_addr;
  439. int ret;
  440. ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr);
  441. if (ret) {
  442. ath10k_err(ar, "could not read board ext data addr (%d)\n",
  443. ret);
  444. return ret;
  445. }
  446. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  447. "boot push board extended data addr 0x%x\n",
  448. board_ext_data_addr);
  449. if (board_ext_data_addr == 0)
  450. return 0;
  451. if (data_len != (board_data_size + board_ext_data_size)) {
  452. ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n",
  453. data_len, board_data_size, board_ext_data_size);
  454. return -EINVAL;
  455. }
  456. ret = ath10k_bmi_write_memory(ar, board_ext_data_addr,
  457. data + board_data_size,
  458. board_ext_data_size);
  459. if (ret) {
  460. ath10k_err(ar, "could not write board ext data (%d)\n", ret);
  461. return ret;
  462. }
  463. ret = ath10k_bmi_write32(ar, hi_board_ext_data_config,
  464. (board_ext_data_size << 16) | 1);
  465. if (ret) {
  466. ath10k_err(ar, "could not write board ext data bit (%d)\n",
  467. ret);
  468. return ret;
  469. }
  470. return 0;
  471. }
  472. static int ath10k_download_board_data(struct ath10k *ar, const void *data,
  473. size_t data_len)
  474. {
  475. u32 board_data_size = ar->hw_params.fw.board_size;
  476. u32 address;
  477. int ret;
  478. ret = ath10k_push_board_ext_data(ar, data, data_len);
  479. if (ret) {
  480. ath10k_err(ar, "could not push board ext data (%d)\n", ret);
  481. goto exit;
  482. }
  483. ret = ath10k_bmi_read32(ar, hi_board_data, &address);
  484. if (ret) {
  485. ath10k_err(ar, "could not read board data addr (%d)\n", ret);
  486. goto exit;
  487. }
  488. ret = ath10k_bmi_write_memory(ar, address, data,
  489. min_t(u32, board_data_size,
  490. data_len));
  491. if (ret) {
  492. ath10k_err(ar, "could not write board data (%d)\n", ret);
  493. goto exit;
  494. }
  495. ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1);
  496. if (ret) {
  497. ath10k_err(ar, "could not write board data bit (%d)\n", ret);
  498. goto exit;
  499. }
  500. exit:
  501. return ret;
  502. }
  503. static int ath10k_download_cal_file(struct ath10k *ar,
  504. const struct firmware *file)
  505. {
  506. int ret;
  507. if (!file)
  508. return -ENOENT;
  509. if (IS_ERR(file))
  510. return PTR_ERR(file);
  511. ret = ath10k_download_board_data(ar, file->data, file->size);
  512. if (ret) {
  513. ath10k_err(ar, "failed to download cal_file data: %d\n", ret);
  514. return ret;
  515. }
  516. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n");
  517. return 0;
  518. }
  519. static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name)
  520. {
  521. struct device_node *node;
  522. int data_len;
  523. void *data;
  524. int ret;
  525. node = ar->dev->of_node;
  526. if (!node)
  527. /* Device Tree is optional, don't print any warnings if
  528. * there's no node for ath10k.
  529. */
  530. return -ENOENT;
  531. if (!of_get_property(node, dt_name, &data_len)) {
  532. /* The calibration data node is optional */
  533. return -ENOENT;
  534. }
  535. if (data_len != ar->hw_params.cal_data_len) {
  536. ath10k_warn(ar, "invalid calibration data length in DT: %d\n",
  537. data_len);
  538. ret = -EMSGSIZE;
  539. goto out;
  540. }
  541. data = kmalloc(data_len, GFP_KERNEL);
  542. if (!data) {
  543. ret = -ENOMEM;
  544. goto out;
  545. }
  546. ret = of_property_read_u8_array(node, dt_name, data, data_len);
  547. if (ret) {
  548. ath10k_warn(ar, "failed to read calibration data from DT: %d\n",
  549. ret);
  550. goto out_free;
  551. }
  552. ret = ath10k_download_board_data(ar, data, data_len);
  553. if (ret) {
  554. ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n",
  555. ret);
  556. goto out_free;
  557. }
  558. ret = 0;
  559. out_free:
  560. kfree(data);
  561. out:
  562. return ret;
  563. }
  564. static int ath10k_download_cal_eeprom(struct ath10k *ar)
  565. {
  566. size_t data_len;
  567. void *data = NULL;
  568. int ret;
  569. ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len);
  570. if (ret) {
  571. if (ret != -EOPNOTSUPP)
  572. ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n",
  573. ret);
  574. goto out_free;
  575. }
  576. ret = ath10k_download_board_data(ar, data, data_len);
  577. if (ret) {
  578. ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n",
  579. ret);
  580. goto out_free;
  581. }
  582. ret = 0;
  583. out_free:
  584. kfree(data);
  585. return ret;
  586. }
  587. static int ath10k_core_get_board_id_from_otp(struct ath10k *ar)
  588. {
  589. u32 result, address;
  590. u8 board_id, chip_id;
  591. int ret;
  592. address = ar->hw_params.patch_load_addr;
  593. if (!ar->normal_mode_fw.fw_file.otp_data ||
  594. !ar->normal_mode_fw.fw_file.otp_len) {
  595. ath10k_warn(ar,
  596. "failed to retrieve board id because of invalid otp\n");
  597. return -ENODATA;
  598. }
  599. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  600. "boot upload otp to 0x%x len %zd for board id\n",
  601. address, ar->normal_mode_fw.fw_file.otp_len);
  602. ret = ath10k_bmi_fast_download(ar, address,
  603. ar->normal_mode_fw.fw_file.otp_data,
  604. ar->normal_mode_fw.fw_file.otp_len);
  605. if (ret) {
  606. ath10k_err(ar, "could not write otp for board id check: %d\n",
  607. ret);
  608. return ret;
  609. }
  610. ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EEPROM_BOARD_ID,
  611. &result);
  612. if (ret) {
  613. ath10k_err(ar, "could not execute otp for board id check: %d\n",
  614. ret);
  615. return ret;
  616. }
  617. board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP);
  618. chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP);
  619. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  620. "boot get otp board id result 0x%08x board_id %d chip_id %d\n",
  621. result, board_id, chip_id);
  622. if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0)
  623. return -EOPNOTSUPP;
  624. ar->id.bmi_ids_valid = true;
  625. ar->id.bmi_board_id = board_id;
  626. ar->id.bmi_chip_id = chip_id;
  627. return 0;
  628. }
  629. static int ath10k_download_and_run_otp(struct ath10k *ar)
  630. {
  631. u32 result, address = ar->hw_params.patch_load_addr;
  632. u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param;
  633. int ret;
  634. ret = ath10k_download_board_data(ar,
  635. ar->running_fw->board_data,
  636. ar->running_fw->board_len);
  637. if (ret) {
  638. ath10k_err(ar, "failed to download board data: %d\n", ret);
  639. return ret;
  640. }
  641. /* OTP is optional */
  642. if (!ar->running_fw->fw_file.otp_data ||
  643. !ar->running_fw->fw_file.otp_len) {
  644. ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %pK otp_len %zd)!\n",
  645. ar->running_fw->fw_file.otp_data,
  646. ar->running_fw->fw_file.otp_len);
  647. return 0;
  648. }
  649. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n",
  650. address, ar->running_fw->fw_file.otp_len);
  651. ret = ath10k_bmi_fast_download(ar, address,
  652. ar->running_fw->fw_file.otp_data,
  653. ar->running_fw->fw_file.otp_len);
  654. if (ret) {
  655. ath10k_err(ar, "could not write otp (%d)\n", ret);
  656. return ret;
  657. }
  658. ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result);
  659. if (ret) {
  660. ath10k_err(ar, "could not execute otp (%d)\n", ret);
  661. return ret;
  662. }
  663. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result);
  664. if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT,
  665. ar->running_fw->fw_file.fw_features)) &&
  666. result != 0) {
  667. ath10k_err(ar, "otp calibration failed: %d", result);
  668. return -EINVAL;
  669. }
  670. return 0;
  671. }
  672. static int ath10k_download_fw(struct ath10k *ar)
  673. {
  674. u32 address, data_len;
  675. const void *data;
  676. int ret;
  677. address = ar->hw_params.patch_load_addr;
  678. data = ar->running_fw->fw_file.firmware_data;
  679. data_len = ar->running_fw->fw_file.firmware_len;
  680. ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file);
  681. if (ret) {
  682. ath10k_err(ar, "failed to configure fw code swap: %d\n",
  683. ret);
  684. return ret;
  685. }
  686. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  687. "boot uploading firmware image %pK len %d\n",
  688. data, data_len);
  689. ret = ath10k_bmi_fast_download(ar, address, data, data_len);
  690. if (ret) {
  691. ath10k_err(ar, "failed to download firmware: %d\n",
  692. ret);
  693. return ret;
  694. }
  695. return ret;
  696. }
  697. static void ath10k_core_free_board_files(struct ath10k *ar)
  698. {
  699. if (!IS_ERR(ar->normal_mode_fw.board))
  700. release_firmware(ar->normal_mode_fw.board);
  701. ar->normal_mode_fw.board = NULL;
  702. ar->normal_mode_fw.board_data = NULL;
  703. ar->normal_mode_fw.board_len = 0;
  704. }
  705. static void ath10k_core_free_firmware_files(struct ath10k *ar)
  706. {
  707. if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware))
  708. release_firmware(ar->normal_mode_fw.fw_file.firmware);
  709. if (!IS_ERR(ar->cal_file))
  710. release_firmware(ar->cal_file);
  711. if (!IS_ERR(ar->pre_cal_file))
  712. release_firmware(ar->pre_cal_file);
  713. ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file);
  714. ar->normal_mode_fw.fw_file.otp_data = NULL;
  715. ar->normal_mode_fw.fw_file.otp_len = 0;
  716. ar->normal_mode_fw.fw_file.firmware = NULL;
  717. ar->normal_mode_fw.fw_file.firmware_data = NULL;
  718. ar->normal_mode_fw.fw_file.firmware_len = 0;
  719. ar->cal_file = NULL;
  720. ar->pre_cal_file = NULL;
  721. }
  722. static int ath10k_fetch_cal_file(struct ath10k *ar)
  723. {
  724. char filename[100];
  725. /* pre-cal-<bus>-<id>.bin */
  726. scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin",
  727. ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
  728. ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
  729. if (!IS_ERR(ar->pre_cal_file))
  730. goto success;
  731. /* cal-<bus>-<id>.bin */
  732. scnprintf(filename, sizeof(filename), "cal-%s-%s.bin",
  733. ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
  734. ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
  735. if (IS_ERR(ar->cal_file))
  736. /* calibration file is optional, don't print any warnings */
  737. return PTR_ERR(ar->cal_file);
  738. success:
  739. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n",
  740. ATH10K_FW_DIR, filename);
  741. return 0;
  742. }
  743. static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar)
  744. {
  745. if (!ar->hw_params.fw.board) {
  746. ath10k_err(ar, "failed to find board file fw entry\n");
  747. return -EINVAL;
  748. }
  749. ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
  750. ar->hw_params.fw.dir,
  751. ar->hw_params.fw.board);
  752. if (IS_ERR(ar->normal_mode_fw.board))
  753. return PTR_ERR(ar->normal_mode_fw.board);
  754. ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data;
  755. ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size;
  756. return 0;
  757. }
  758. static int ath10k_core_parse_bd_ie_board(struct ath10k *ar,
  759. const void *buf, size_t buf_len,
  760. const char *boardname)
  761. {
  762. const struct ath10k_fw_ie *hdr;
  763. bool name_match_found;
  764. int ret, board_ie_id;
  765. size_t board_ie_len;
  766. const void *board_ie_data;
  767. name_match_found = false;
  768. /* go through ATH10K_BD_IE_BOARD_ elements */
  769. while (buf_len > sizeof(struct ath10k_fw_ie)) {
  770. hdr = buf;
  771. board_ie_id = le32_to_cpu(hdr->id);
  772. board_ie_len = le32_to_cpu(hdr->len);
  773. board_ie_data = hdr->data;
  774. buf_len -= sizeof(*hdr);
  775. buf += sizeof(*hdr);
  776. if (buf_len < ALIGN(board_ie_len, 4)) {
  777. ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n",
  778. buf_len, ALIGN(board_ie_len, 4));
  779. ret = -EINVAL;
  780. goto out;
  781. }
  782. switch (board_ie_id) {
  783. case ATH10K_BD_IE_BOARD_NAME:
  784. ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "",
  785. board_ie_data, board_ie_len);
  786. if (board_ie_len != strlen(boardname))
  787. break;
  788. ret = memcmp(board_ie_data, boardname, strlen(boardname));
  789. if (ret)
  790. break;
  791. name_match_found = true;
  792. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  793. "boot found match for name '%s'",
  794. boardname);
  795. break;
  796. case ATH10K_BD_IE_BOARD_DATA:
  797. if (!name_match_found)
  798. /* no match found */
  799. break;
  800. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  801. "boot found board data for '%s'",
  802. boardname);
  803. ar->normal_mode_fw.board_data = board_ie_data;
  804. ar->normal_mode_fw.board_len = board_ie_len;
  805. ret = 0;
  806. goto out;
  807. default:
  808. ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n",
  809. board_ie_id);
  810. break;
  811. }
  812. /* jump over the padding */
  813. board_ie_len = ALIGN(board_ie_len, 4);
  814. buf_len -= board_ie_len;
  815. buf += board_ie_len;
  816. }
  817. /* no match found */
  818. ret = -ENOENT;
  819. out:
  820. return ret;
  821. }
  822. static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar,
  823. const char *boardname,
  824. const char *filename)
  825. {
  826. size_t len, magic_len, ie_len;
  827. struct ath10k_fw_ie *hdr;
  828. const u8 *data;
  829. int ret, ie_id;
  830. ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
  831. ar->hw_params.fw.dir,
  832. filename);
  833. if (IS_ERR(ar->normal_mode_fw.board))
  834. return PTR_ERR(ar->normal_mode_fw.board);
  835. data = ar->normal_mode_fw.board->data;
  836. len = ar->normal_mode_fw.board->size;
  837. /* magic has extra null byte padded */
  838. magic_len = strlen(ATH10K_BOARD_MAGIC) + 1;
  839. if (len < magic_len) {
  840. ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n",
  841. ar->hw_params.fw.dir, filename, len);
  842. ret = -EINVAL;
  843. goto err;
  844. }
  845. if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) {
  846. ath10k_err(ar, "found invalid board magic\n");
  847. ret = -EINVAL;
  848. goto err;
  849. }
  850. /* magic is padded to 4 bytes */
  851. magic_len = ALIGN(magic_len, 4);
  852. if (len < magic_len) {
  853. ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n",
  854. ar->hw_params.fw.dir, filename, len);
  855. ret = -EINVAL;
  856. goto err;
  857. }
  858. data += magic_len;
  859. len -= magic_len;
  860. while (len > sizeof(struct ath10k_fw_ie)) {
  861. hdr = (struct ath10k_fw_ie *)data;
  862. ie_id = le32_to_cpu(hdr->id);
  863. ie_len = le32_to_cpu(hdr->len);
  864. len -= sizeof(*hdr);
  865. data = hdr->data;
  866. if (len < ALIGN(ie_len, 4)) {
  867. ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n",
  868. ie_id, ie_len, len);
  869. ret = -EINVAL;
  870. goto err;
  871. }
  872. switch (ie_id) {
  873. case ATH10K_BD_IE_BOARD:
  874. ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
  875. boardname);
  876. if (ret == -ENOENT)
  877. /* no match found, continue */
  878. break;
  879. else if (ret)
  880. /* there was an error, bail out */
  881. goto err;
  882. /* board data found */
  883. goto out;
  884. }
  885. /* jump over the padding */
  886. ie_len = ALIGN(ie_len, 4);
  887. len -= ie_len;
  888. data += ie_len;
  889. }
  890. out:
  891. if (!ar->normal_mode_fw.board_data || !ar->normal_mode_fw.board_len) {
  892. ath10k_err(ar,
  893. "failed to fetch board data for %s from %s/%s\n",
  894. boardname, ar->hw_params.fw.dir, filename);
  895. ret = -ENODATA;
  896. goto err;
  897. }
  898. return 0;
  899. err:
  900. ath10k_core_free_board_files(ar);
  901. return ret;
  902. }
  903. static int ath10k_core_create_board_name(struct ath10k *ar, char *name,
  904. size_t name_len)
  905. {
  906. if (ar->id.bmi_ids_valid) {
  907. scnprintf(name, name_len,
  908. "bus=%s,bmi-chip-id=%d,bmi-board-id=%d",
  909. ath10k_bus_str(ar->hif.bus),
  910. ar->id.bmi_chip_id,
  911. ar->id.bmi_board_id);
  912. goto out;
  913. }
  914. scnprintf(name, name_len,
  915. "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x",
  916. ath10k_bus_str(ar->hif.bus),
  917. ar->id.vendor, ar->id.device,
  918. ar->id.subsystem_vendor, ar->id.subsystem_device);
  919. out:
  920. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name);
  921. return 0;
  922. }
  923. static int ath10k_core_fetch_board_file(struct ath10k *ar)
  924. {
  925. char boardname[100];
  926. int ret;
  927. ret = ath10k_core_create_board_name(ar, boardname, sizeof(boardname));
  928. if (ret) {
  929. ath10k_err(ar, "failed to create board name: %d", ret);
  930. return ret;
  931. }
  932. ar->bd_api = 2;
  933. ret = ath10k_core_fetch_board_data_api_n(ar, boardname,
  934. ATH10K_BOARD_API2_FILE);
  935. if (!ret)
  936. goto success;
  937. ar->bd_api = 1;
  938. ret = ath10k_core_fetch_board_data_api_1(ar);
  939. if (ret) {
  940. ath10k_err(ar, "failed to fetch board data\n");
  941. return ret;
  942. }
  943. success:
  944. ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api);
  945. return 0;
  946. }
  947. int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
  948. struct ath10k_fw_file *fw_file)
  949. {
  950. size_t magic_len, len, ie_len;
  951. int ie_id, i, index, bit, ret;
  952. struct ath10k_fw_ie *hdr;
  953. const u8 *data;
  954. __le32 *timestamp, *version;
  955. /* first fetch the firmware file (firmware-*.bin) */
  956. fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir,
  957. name);
  958. if (IS_ERR(fw_file->firmware)) {
  959. ath10k_err(ar, "could not fetch firmware file '%s/%s': %ld\n",
  960. ar->hw_params.fw.dir, name,
  961. PTR_ERR(fw_file->firmware));
  962. return PTR_ERR(fw_file->firmware);
  963. }
  964. data = fw_file->firmware->data;
  965. len = fw_file->firmware->size;
  966. /* magic also includes the null byte, check that as well */
  967. magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1;
  968. if (len < magic_len) {
  969. ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n",
  970. ar->hw_params.fw.dir, name, len);
  971. ret = -EINVAL;
  972. goto err;
  973. }
  974. if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) {
  975. ath10k_err(ar, "invalid firmware magic\n");
  976. ret = -EINVAL;
  977. goto err;
  978. }
  979. /* jump over the padding */
  980. magic_len = ALIGN(magic_len, 4);
  981. len -= magic_len;
  982. data += magic_len;
  983. /* loop elements */
  984. while (len > sizeof(struct ath10k_fw_ie)) {
  985. hdr = (struct ath10k_fw_ie *)data;
  986. ie_id = le32_to_cpu(hdr->id);
  987. ie_len = le32_to_cpu(hdr->len);
  988. len -= sizeof(*hdr);
  989. data += sizeof(*hdr);
  990. if (len < ie_len) {
  991. ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n",
  992. ie_id, len, ie_len);
  993. ret = -EINVAL;
  994. goto err;
  995. }
  996. switch (ie_id) {
  997. case ATH10K_FW_IE_FW_VERSION:
  998. if (ie_len > sizeof(fw_file->fw_version) - 1)
  999. break;
  1000. memcpy(fw_file->fw_version, data, ie_len);
  1001. fw_file->fw_version[ie_len] = '\0';
  1002. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1003. "found fw version %s\n",
  1004. fw_file->fw_version);
  1005. break;
  1006. case ATH10K_FW_IE_TIMESTAMP:
  1007. if (ie_len != sizeof(u32))
  1008. break;
  1009. timestamp = (__le32 *)data;
  1010. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n",
  1011. le32_to_cpup(timestamp));
  1012. break;
  1013. case ATH10K_FW_IE_FEATURES:
  1014. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1015. "found firmware features ie (%zd B)\n",
  1016. ie_len);
  1017. for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
  1018. index = i / 8;
  1019. bit = i % 8;
  1020. if (index == ie_len)
  1021. break;
  1022. if (data[index] & (1 << bit)) {
  1023. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1024. "Enabling feature bit: %i\n",
  1025. i);
  1026. __set_bit(i, fw_file->fw_features);
  1027. }
  1028. }
  1029. ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "",
  1030. fw_file->fw_features,
  1031. sizeof(fw_file->fw_features));
  1032. break;
  1033. case ATH10K_FW_IE_FW_IMAGE:
  1034. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1035. "found fw image ie (%zd B)\n",
  1036. ie_len);
  1037. fw_file->firmware_data = data;
  1038. fw_file->firmware_len = ie_len;
  1039. break;
  1040. case ATH10K_FW_IE_OTP_IMAGE:
  1041. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1042. "found otp image ie (%zd B)\n",
  1043. ie_len);
  1044. fw_file->otp_data = data;
  1045. fw_file->otp_len = ie_len;
  1046. break;
  1047. case ATH10K_FW_IE_WMI_OP_VERSION:
  1048. if (ie_len != sizeof(u32))
  1049. break;
  1050. version = (__le32 *)data;
  1051. fw_file->wmi_op_version = le32_to_cpup(version);
  1052. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n",
  1053. fw_file->wmi_op_version);
  1054. break;
  1055. case ATH10K_FW_IE_HTT_OP_VERSION:
  1056. if (ie_len != sizeof(u32))
  1057. break;
  1058. version = (__le32 *)data;
  1059. fw_file->htt_op_version = le32_to_cpup(version);
  1060. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n",
  1061. fw_file->htt_op_version);
  1062. break;
  1063. case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE:
  1064. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1065. "found fw code swap image ie (%zd B)\n",
  1066. ie_len);
  1067. fw_file->codeswap_data = data;
  1068. fw_file->codeswap_len = ie_len;
  1069. break;
  1070. default:
  1071. ath10k_warn(ar, "Unknown FW IE: %u\n",
  1072. le32_to_cpu(hdr->id));
  1073. break;
  1074. }
  1075. /* jump over the padding */
  1076. ie_len = ALIGN(ie_len, 4);
  1077. len -= ie_len;
  1078. data += ie_len;
  1079. }
  1080. if (!fw_file->firmware_data ||
  1081. !fw_file->firmware_len) {
  1082. ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n",
  1083. ar->hw_params.fw.dir, name);
  1084. ret = -ENOMEDIUM;
  1085. goto err;
  1086. }
  1087. return 0;
  1088. err:
  1089. ath10k_core_free_firmware_files(ar);
  1090. return ret;
  1091. }
  1092. static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
  1093. {
  1094. int ret;
  1095. /* calibration file is optional, don't check for any errors */
  1096. ath10k_fetch_cal_file(ar);
  1097. ar->fw_api = 5;
  1098. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1099. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API5_FILE,
  1100. &ar->normal_mode_fw.fw_file);
  1101. if (ret == 0)
  1102. goto success;
  1103. ar->fw_api = 4;
  1104. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1105. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API4_FILE,
  1106. &ar->normal_mode_fw.fw_file);
  1107. if (ret == 0)
  1108. goto success;
  1109. ar->fw_api = 3;
  1110. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1111. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API3_FILE,
  1112. &ar->normal_mode_fw.fw_file);
  1113. if (ret == 0)
  1114. goto success;
  1115. ar->fw_api = 2;
  1116. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1117. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API2_FILE,
  1118. &ar->normal_mode_fw.fw_file);
  1119. if (ret)
  1120. return ret;
  1121. success:
  1122. ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api);
  1123. return 0;
  1124. }
  1125. static int ath10k_core_pre_cal_download(struct ath10k *ar)
  1126. {
  1127. int ret;
  1128. ret = ath10k_download_cal_file(ar, ar->pre_cal_file);
  1129. if (ret == 0) {
  1130. ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE;
  1131. goto success;
  1132. }
  1133. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1134. "boot did not find a pre calibration file, try DT next: %d\n",
  1135. ret);
  1136. ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data");
  1137. if (ret) {
  1138. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1139. "unable to load pre cal data from DT: %d\n", ret);
  1140. return ret;
  1141. }
  1142. ar->cal_mode = ATH10K_PRE_CAL_MODE_DT;
  1143. success:
  1144. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
  1145. ath10k_cal_mode_str(ar->cal_mode));
  1146. return 0;
  1147. }
  1148. static int ath10k_core_pre_cal_config(struct ath10k *ar)
  1149. {
  1150. int ret;
  1151. ret = ath10k_core_pre_cal_download(ar);
  1152. if (ret) {
  1153. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1154. "failed to load pre cal data: %d\n", ret);
  1155. return ret;
  1156. }
  1157. ret = ath10k_core_get_board_id_from_otp(ar);
  1158. if (ret) {
  1159. ath10k_err(ar, "failed to get board id: %d\n", ret);
  1160. return ret;
  1161. }
  1162. ret = ath10k_download_and_run_otp(ar);
  1163. if (ret) {
  1164. ath10k_err(ar, "failed to run otp: %d\n", ret);
  1165. return ret;
  1166. }
  1167. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1168. "pre cal configuration done successfully\n");
  1169. return 0;
  1170. }
  1171. static int ath10k_download_cal_data(struct ath10k *ar)
  1172. {
  1173. int ret;
  1174. ret = ath10k_core_pre_cal_config(ar);
  1175. if (ret == 0)
  1176. return 0;
  1177. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1178. "pre cal download procedure failed, try cal file: %d\n",
  1179. ret);
  1180. ret = ath10k_download_cal_file(ar, ar->cal_file);
  1181. if (ret == 0) {
  1182. ar->cal_mode = ATH10K_CAL_MODE_FILE;
  1183. goto done;
  1184. }
  1185. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1186. "boot did not find a calibration file, try DT next: %d\n",
  1187. ret);
  1188. ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data");
  1189. if (ret == 0) {
  1190. ar->cal_mode = ATH10K_CAL_MODE_DT;
  1191. goto done;
  1192. }
  1193. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1194. "boot did not find DT entry, try target EEPROM next: %d\n",
  1195. ret);
  1196. ret = ath10k_download_cal_eeprom(ar);
  1197. if (ret == 0) {
  1198. ar->cal_mode = ATH10K_CAL_MODE_EEPROM;
  1199. goto done;
  1200. }
  1201. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1202. "boot did not find target EEPROM entry, try OTP next: %d\n",
  1203. ret);
  1204. ret = ath10k_download_and_run_otp(ar);
  1205. if (ret) {
  1206. ath10k_err(ar, "failed to run otp: %d\n", ret);
  1207. return ret;
  1208. }
  1209. ar->cal_mode = ATH10K_CAL_MODE_OTP;
  1210. done:
  1211. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
  1212. ath10k_cal_mode_str(ar->cal_mode));
  1213. return 0;
  1214. }
  1215. static int ath10k_init_uart(struct ath10k *ar)
  1216. {
  1217. int ret;
  1218. /*
  1219. * Explicitly setting UART prints to zero as target turns it on
  1220. * based on scratch registers.
  1221. */
  1222. ret = ath10k_bmi_write32(ar, hi_serial_enable, 0);
  1223. if (ret) {
  1224. ath10k_warn(ar, "could not disable UART prints (%d)\n", ret);
  1225. return ret;
  1226. }
  1227. if (!uart_print)
  1228. return 0;
  1229. ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin);
  1230. if (ret) {
  1231. ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
  1232. return ret;
  1233. }
  1234. ret = ath10k_bmi_write32(ar, hi_serial_enable, 1);
  1235. if (ret) {
  1236. ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
  1237. return ret;
  1238. }
  1239. /* Set the UART baud rate to 19200. */
  1240. ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200);
  1241. if (ret) {
  1242. ath10k_warn(ar, "could not set the baud rate (%d)\n", ret);
  1243. return ret;
  1244. }
  1245. ath10k_info(ar, "UART prints enabled\n");
  1246. return 0;
  1247. }
  1248. static int ath10k_init_hw_params(struct ath10k *ar)
  1249. {
  1250. const struct ath10k_hw_params *uninitialized_var(hw_params);
  1251. int i;
  1252. for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) {
  1253. hw_params = &ath10k_hw_params_list[i];
  1254. if (hw_params->id == ar->target_version &&
  1255. hw_params->dev_id == ar->dev_id)
  1256. break;
  1257. }
  1258. if (i == ARRAY_SIZE(ath10k_hw_params_list)) {
  1259. ath10k_err(ar, "Unsupported hardware version: 0x%x\n",
  1260. ar->target_version);
  1261. return -EINVAL;
  1262. }
  1263. ar->hw_params = *hw_params;
  1264. ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n",
  1265. ar->hw_params.name, ar->target_version);
  1266. return 0;
  1267. }
  1268. static void ath10k_core_restart(struct work_struct *work)
  1269. {
  1270. struct ath10k *ar = container_of(work, struct ath10k, restart_work);
  1271. set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
  1272. /* Place a barrier to make sure the compiler doesn't reorder
  1273. * CRASH_FLUSH and calling other functions.
  1274. */
  1275. barrier();
  1276. ieee80211_stop_queues(ar->hw);
  1277. ath10k_drain_tx(ar);
  1278. complete(&ar->scan.started);
  1279. complete(&ar->scan.completed);
  1280. complete(&ar->scan.on_channel);
  1281. complete(&ar->offchan_tx_completed);
  1282. complete(&ar->install_key_done);
  1283. complete(&ar->vdev_setup_done);
  1284. complete(&ar->thermal.wmi_sync);
  1285. complete(&ar->bss_survey_done);
  1286. wake_up(&ar->htt.empty_tx_wq);
  1287. wake_up(&ar->wmi.tx_credits_wq);
  1288. wake_up(&ar->peer_mapping_wq);
  1289. mutex_lock(&ar->conf_mutex);
  1290. switch (ar->state) {
  1291. case ATH10K_STATE_ON:
  1292. ar->state = ATH10K_STATE_RESTARTING;
  1293. ath10k_halt(ar);
  1294. ath10k_scan_finish(ar);
  1295. ieee80211_restart_hw(ar->hw);
  1296. break;
  1297. case ATH10K_STATE_OFF:
  1298. /* this can happen if driver is being unloaded
  1299. * or if the crash happens during FW probing */
  1300. ath10k_warn(ar, "cannot restart a device that hasn't been started\n");
  1301. break;
  1302. case ATH10K_STATE_RESTARTING:
  1303. /* hw restart might be requested from multiple places */
  1304. break;
  1305. case ATH10K_STATE_RESTARTED:
  1306. ar->state = ATH10K_STATE_WEDGED;
  1307. /* fall through */
  1308. case ATH10K_STATE_WEDGED:
  1309. ath10k_warn(ar, "device is wedged, will not restart\n");
  1310. break;
  1311. case ATH10K_STATE_UTF:
  1312. ath10k_warn(ar, "firmware restart in UTF mode not supported\n");
  1313. break;
  1314. }
  1315. mutex_unlock(&ar->conf_mutex);
  1316. }
  1317. static void ath10k_core_set_coverage_class_work(struct work_struct *work)
  1318. {
  1319. struct ath10k *ar = container_of(work, struct ath10k,
  1320. set_coverage_class_work);
  1321. if (ar->hw_params.hw_ops->set_coverage_class)
  1322. ar->hw_params.hw_ops->set_coverage_class(ar, -1);
  1323. }
  1324. static int ath10k_core_init_firmware_features(struct ath10k *ar)
  1325. {
  1326. struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file;
  1327. if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) &&
  1328. !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
  1329. ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well");
  1330. return -EINVAL;
  1331. }
  1332. if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) {
  1333. ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n",
  1334. ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version);
  1335. return -EINVAL;
  1336. }
  1337. ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI;
  1338. switch (ath10k_cryptmode_param) {
  1339. case ATH10K_CRYPT_MODE_HW:
  1340. clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1341. clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
  1342. break;
  1343. case ATH10K_CRYPT_MODE_SW:
  1344. if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
  1345. fw_file->fw_features)) {
  1346. ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware");
  1347. return -EINVAL;
  1348. }
  1349. set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1350. set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
  1351. break;
  1352. default:
  1353. ath10k_info(ar, "invalid cryptmode: %d\n",
  1354. ath10k_cryptmode_param);
  1355. return -EINVAL;
  1356. }
  1357. ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT;
  1358. ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT;
  1359. if (rawmode) {
  1360. if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
  1361. fw_file->fw_features)) {
  1362. ath10k_err(ar, "rawmode = 1 requires support from firmware");
  1363. return -EINVAL;
  1364. }
  1365. set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1366. }
  1367. if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
  1368. ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW;
  1369. /* Workaround:
  1370. *
  1371. * Firmware A-MSDU aggregation breaks with RAW Tx encap mode
  1372. * and causes enormous performance issues (malformed frames,
  1373. * etc).
  1374. *
  1375. * Disabling A-MSDU makes RAW mode stable with heavy traffic
  1376. * albeit a bit slower compared to regular operation.
  1377. */
  1378. ar->htt.max_num_amsdu = 1;
  1379. }
  1380. /* Backwards compatibility for firmwares without
  1381. * ATH10K_FW_IE_WMI_OP_VERSION.
  1382. */
  1383. if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) {
  1384. if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
  1385. if (test_bit(ATH10K_FW_FEATURE_WMI_10_2,
  1386. fw_file->fw_features))
  1387. fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2;
  1388. else
  1389. fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1;
  1390. } else {
  1391. fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN;
  1392. }
  1393. }
  1394. switch (fw_file->wmi_op_version) {
  1395. case ATH10K_FW_WMI_OP_VERSION_MAIN:
  1396. ar->max_num_peers = TARGET_NUM_PEERS;
  1397. ar->max_num_stations = TARGET_NUM_STATIONS;
  1398. ar->max_num_vdevs = TARGET_NUM_VDEVS;
  1399. ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC;
  1400. ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
  1401. WMI_STAT_PEER;
  1402. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1403. break;
  1404. case ATH10K_FW_WMI_OP_VERSION_10_1:
  1405. case ATH10K_FW_WMI_OP_VERSION_10_2:
  1406. case ATH10K_FW_WMI_OP_VERSION_10_2_4:
  1407. if (ath10k_peer_stats_enabled(ar)) {
  1408. ar->max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS;
  1409. ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS;
  1410. } else {
  1411. ar->max_num_peers = TARGET_10X_NUM_PEERS;
  1412. ar->max_num_stations = TARGET_10X_NUM_STATIONS;
  1413. }
  1414. ar->max_num_vdevs = TARGET_10X_NUM_VDEVS;
  1415. ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
  1416. ar->fw_stats_req_mask = WMI_STAT_PEER;
  1417. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1418. break;
  1419. case ATH10K_FW_WMI_OP_VERSION_TLV:
  1420. ar->max_num_peers = TARGET_TLV_NUM_PEERS;
  1421. ar->max_num_stations = TARGET_TLV_NUM_STATIONS;
  1422. ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS;
  1423. ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS;
  1424. ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC;
  1425. ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS;
  1426. ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
  1427. WMI_STAT_PEER;
  1428. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1429. break;
  1430. case ATH10K_FW_WMI_OP_VERSION_10_4:
  1431. ar->max_num_peers = TARGET_10_4_NUM_PEERS;
  1432. ar->max_num_stations = TARGET_10_4_NUM_STATIONS;
  1433. ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS;
  1434. ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS;
  1435. ar->num_tids = TARGET_10_4_TGT_NUM_TIDS;
  1436. ar->fw_stats_req_mask = WMI_10_4_STAT_PEER |
  1437. WMI_10_4_STAT_PEER_EXTD;
  1438. ar->max_spatial_stream = ar->hw_params.max_spatial_stream;
  1439. if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
  1440. fw_file->fw_features))
  1441. ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC;
  1442. else
  1443. ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC;
  1444. break;
  1445. case ATH10K_FW_WMI_OP_VERSION_UNSET:
  1446. case ATH10K_FW_WMI_OP_VERSION_MAX:
  1447. WARN_ON(1);
  1448. return -EINVAL;
  1449. }
  1450. /* Backwards compatibility for firmwares without
  1451. * ATH10K_FW_IE_HTT_OP_VERSION.
  1452. */
  1453. if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) {
  1454. switch (fw_file->wmi_op_version) {
  1455. case ATH10K_FW_WMI_OP_VERSION_MAIN:
  1456. fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN;
  1457. break;
  1458. case ATH10K_FW_WMI_OP_VERSION_10_1:
  1459. case ATH10K_FW_WMI_OP_VERSION_10_2:
  1460. case ATH10K_FW_WMI_OP_VERSION_10_2_4:
  1461. fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1;
  1462. break;
  1463. case ATH10K_FW_WMI_OP_VERSION_TLV:
  1464. fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV;
  1465. break;
  1466. case ATH10K_FW_WMI_OP_VERSION_10_4:
  1467. case ATH10K_FW_WMI_OP_VERSION_UNSET:
  1468. case ATH10K_FW_WMI_OP_VERSION_MAX:
  1469. ath10k_err(ar, "htt op version not found from fw meta data");
  1470. return -EINVAL;
  1471. }
  1472. }
  1473. return 0;
  1474. }
  1475. static int ath10k_core_reset_rx_filter(struct ath10k *ar)
  1476. {
  1477. int ret;
  1478. int vdev_id;
  1479. int vdev_type;
  1480. int vdev_subtype;
  1481. const u8 *vdev_addr;
  1482. vdev_id = 0;
  1483. vdev_type = WMI_VDEV_TYPE_STA;
  1484. vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE);
  1485. vdev_addr = ar->mac_addr;
  1486. ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype,
  1487. vdev_addr);
  1488. if (ret) {
  1489. ath10k_err(ar, "failed to create dummy vdev: %d\n", ret);
  1490. return ret;
  1491. }
  1492. ret = ath10k_wmi_vdev_delete(ar, vdev_id);
  1493. if (ret) {
  1494. ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret);
  1495. return ret;
  1496. }
  1497. /* WMI and HTT may use separate HIF pipes and are not guaranteed to be
  1498. * serialized properly implicitly.
  1499. *
  1500. * Moreover (most) WMI commands have no explicit acknowledges. It is
  1501. * possible to infer it implicitly by poking firmware with echo
  1502. * command - getting a reply means all preceding comments have been
  1503. * (mostly) processed.
  1504. *
  1505. * In case of vdev create/delete this is sufficient.
  1506. *
  1507. * Without this it's possible to end up with a race when HTT Rx ring is
  1508. * started before vdev create/delete hack is complete allowing a short
  1509. * window of opportunity to receive (and Tx ACK) a bunch of frames.
  1510. */
  1511. ret = ath10k_wmi_barrier(ar);
  1512. if (ret) {
  1513. ath10k_err(ar, "failed to ping firmware: %d\n", ret);
  1514. return ret;
  1515. }
  1516. return 0;
  1517. }
  1518. int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
  1519. const struct ath10k_fw_components *fw)
  1520. {
  1521. int status;
  1522. u32 val;
  1523. lockdep_assert_held(&ar->conf_mutex);
  1524. clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
  1525. ar->running_fw = fw;
  1526. ath10k_bmi_start(ar);
  1527. if (ath10k_init_configure_target(ar)) {
  1528. status = -EINVAL;
  1529. goto err;
  1530. }
  1531. status = ath10k_download_cal_data(ar);
  1532. if (status)
  1533. goto err;
  1534. /* Some of of qca988x solutions are having global reset issue
  1535. * during target initialization. Bypassing PLL setting before
  1536. * downloading firmware and letting the SoC run on REF_CLK is
  1537. * fixing the problem. Corresponding firmware change is also needed
  1538. * to set the clock source once the target is initialized.
  1539. */
  1540. if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT,
  1541. ar->running_fw->fw_file.fw_features)) {
  1542. status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1);
  1543. if (status) {
  1544. ath10k_err(ar, "could not write to skip_clock_init: %d\n",
  1545. status);
  1546. goto err;
  1547. }
  1548. }
  1549. status = ath10k_download_fw(ar);
  1550. if (status)
  1551. goto err;
  1552. status = ath10k_init_uart(ar);
  1553. if (status)
  1554. goto err;
  1555. ar->htc.htc_ops.target_send_suspend_complete =
  1556. ath10k_send_suspend_complete;
  1557. status = ath10k_htc_init(ar);
  1558. if (status) {
  1559. ath10k_err(ar, "could not init HTC (%d)\n", status);
  1560. goto err;
  1561. }
  1562. status = ath10k_bmi_done(ar);
  1563. if (status)
  1564. goto err;
  1565. status = ath10k_wmi_attach(ar);
  1566. if (status) {
  1567. ath10k_err(ar, "WMI attach failed: %d\n", status);
  1568. goto err;
  1569. }
  1570. status = ath10k_htt_init(ar);
  1571. if (status) {
  1572. ath10k_err(ar, "failed to init htt: %d\n", status);
  1573. goto err_wmi_detach;
  1574. }
  1575. status = ath10k_htt_tx_start(&ar->htt);
  1576. if (status) {
  1577. ath10k_err(ar, "failed to alloc htt tx: %d\n", status);
  1578. goto err_wmi_detach;
  1579. }
  1580. status = ath10k_htt_rx_alloc(&ar->htt);
  1581. if (status) {
  1582. ath10k_err(ar, "failed to alloc htt rx: %d\n", status);
  1583. goto err_htt_tx_detach;
  1584. }
  1585. status = ath10k_hif_start(ar);
  1586. if (status) {
  1587. ath10k_err(ar, "could not start HIF: %d\n", status);
  1588. goto err_htt_rx_detach;
  1589. }
  1590. status = ath10k_htc_wait_target(&ar->htc);
  1591. if (status) {
  1592. ath10k_err(ar, "failed to connect to HTC: %d\n", status);
  1593. goto err_hif_stop;
  1594. }
  1595. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1596. status = ath10k_htt_connect(&ar->htt);
  1597. if (status) {
  1598. ath10k_err(ar, "failed to connect htt (%d)\n", status);
  1599. goto err_hif_stop;
  1600. }
  1601. }
  1602. status = ath10k_wmi_connect(ar);
  1603. if (status) {
  1604. ath10k_err(ar, "could not connect wmi: %d\n", status);
  1605. goto err_hif_stop;
  1606. }
  1607. status = ath10k_htc_start(&ar->htc);
  1608. if (status) {
  1609. ath10k_err(ar, "failed to start htc: %d\n", status);
  1610. goto err_hif_stop;
  1611. }
  1612. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1613. status = ath10k_wmi_wait_for_service_ready(ar);
  1614. if (status) {
  1615. ath10k_warn(ar, "wmi service ready event not received");
  1616. goto err_hif_stop;
  1617. }
  1618. }
  1619. ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n",
  1620. ar->hw->wiphy->fw_version);
  1621. if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map)) {
  1622. val = 0;
  1623. if (ath10k_peer_stats_enabled(ar))
  1624. val = WMI_10_4_PEER_STATS;
  1625. if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map))
  1626. val |= WMI_10_4_BSS_CHANNEL_INFO_64;
  1627. /* 10.4 firmware supports BT-Coex without reloading firmware
  1628. * via pdev param. To support Bluetooth coexistence pdev param,
  1629. * WMI_COEX_GPIO_SUPPORT of extended resource config should be
  1630. * enabled always.
  1631. */
  1632. if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) &&
  1633. test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM,
  1634. ar->running_fw->fw_file.fw_features))
  1635. val |= WMI_10_4_COEX_GPIO_SUPPORT;
  1636. status = ath10k_mac_ext_resource_config(ar, val);
  1637. if (status) {
  1638. ath10k_err(ar,
  1639. "failed to send ext resource cfg command : %d\n",
  1640. status);
  1641. goto err_hif_stop;
  1642. }
  1643. }
  1644. status = ath10k_wmi_cmd_init(ar);
  1645. if (status) {
  1646. ath10k_err(ar, "could not send WMI init command (%d)\n",
  1647. status);
  1648. goto err_hif_stop;
  1649. }
  1650. status = ath10k_wmi_wait_for_unified_ready(ar);
  1651. if (status) {
  1652. ath10k_err(ar, "wmi unified ready event not received\n");
  1653. goto err_hif_stop;
  1654. }
  1655. /* Some firmware revisions do not properly set up hardware rx filter
  1656. * registers.
  1657. *
  1658. * A known example from QCA9880 and 10.2.4 is that MAC_PCU_ADDR1_MASK
  1659. * is filled with 0s instead of 1s allowing HW to respond with ACKs to
  1660. * any frames that matches MAC_PCU_RX_FILTER which is also
  1661. * misconfigured to accept anything.
  1662. *
  1663. * The ADDR1 is programmed using internal firmware structure field and
  1664. * can't be (easily/sanely) reached from the driver explicitly. It is
  1665. * possible to implicitly make it correct by creating a dummy vdev and
  1666. * then deleting it.
  1667. */
  1668. status = ath10k_core_reset_rx_filter(ar);
  1669. if (status) {
  1670. ath10k_err(ar, "failed to reset rx filter: %d\n", status);
  1671. goto err_hif_stop;
  1672. }
  1673. /* If firmware indicates Full Rx Reorder support it must be used in a
  1674. * slightly different manner. Let HTT code know.
  1675. */
  1676. ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER,
  1677. ar->wmi.svc_map));
  1678. status = ath10k_htt_rx_ring_refill(ar);
  1679. if (status) {
  1680. ath10k_err(ar, "failed to refill htt rx ring: %d\n", status);
  1681. goto err_hif_stop;
  1682. }
  1683. if (ar->max_num_vdevs >= 64)
  1684. ar->free_vdev_map = 0xFFFFFFFFFFFFFFFFLL;
  1685. else
  1686. ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1;
  1687. INIT_LIST_HEAD(&ar->arvifs);
  1688. /* we don't care about HTT in UTF mode */
  1689. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1690. status = ath10k_htt_setup(&ar->htt);
  1691. if (status) {
  1692. ath10k_err(ar, "failed to setup htt: %d\n", status);
  1693. goto err_hif_stop;
  1694. }
  1695. }
  1696. status = ath10k_debug_start(ar);
  1697. if (status)
  1698. goto err_hif_stop;
  1699. return 0;
  1700. err_hif_stop:
  1701. ath10k_hif_stop(ar);
  1702. err_htt_rx_detach:
  1703. ath10k_htt_rx_free(&ar->htt);
  1704. err_htt_tx_detach:
  1705. ath10k_htt_tx_free(&ar->htt);
  1706. err_wmi_detach:
  1707. ath10k_wmi_detach(ar);
  1708. err:
  1709. return status;
  1710. }
  1711. EXPORT_SYMBOL(ath10k_core_start);
  1712. int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt)
  1713. {
  1714. int ret;
  1715. unsigned long time_left;
  1716. reinit_completion(&ar->target_suspend);
  1717. ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt);
  1718. if (ret) {
  1719. ath10k_warn(ar, "could not suspend target (%d)\n", ret);
  1720. return ret;
  1721. }
  1722. time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ);
  1723. if (!time_left) {
  1724. ath10k_warn(ar, "suspend timed out - target pause event never came\n");
  1725. return -ETIMEDOUT;
  1726. }
  1727. return 0;
  1728. }
  1729. void ath10k_core_stop(struct ath10k *ar)
  1730. {
  1731. lockdep_assert_held(&ar->conf_mutex);
  1732. ath10k_debug_stop(ar);
  1733. /* try to suspend target */
  1734. if (ar->state != ATH10K_STATE_RESTARTING &&
  1735. ar->state != ATH10K_STATE_UTF)
  1736. ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR);
  1737. ath10k_hif_stop(ar);
  1738. ath10k_htt_tx_stop(&ar->htt);
  1739. ath10k_htt_rx_free(&ar->htt);
  1740. ath10k_wmi_detach(ar);
  1741. }
  1742. EXPORT_SYMBOL(ath10k_core_stop);
  1743. /* mac80211 manages fw/hw initialization through start/stop hooks. However in
  1744. * order to know what hw capabilities should be advertised to mac80211 it is
  1745. * necessary to load the firmware (and tear it down immediately since start
  1746. * hook will try to init it again) before registering */
  1747. static int ath10k_core_probe_fw(struct ath10k *ar)
  1748. {
  1749. struct bmi_target_info target_info;
  1750. int ret = 0;
  1751. ret = ath10k_hif_power_up(ar);
  1752. if (ret) {
  1753. ath10k_err(ar, "could not start pci hif (%d)\n", ret);
  1754. return ret;
  1755. }
  1756. memset(&target_info, 0, sizeof(target_info));
  1757. ret = ath10k_bmi_get_target_info(ar, &target_info);
  1758. if (ret) {
  1759. ath10k_err(ar, "could not get target info (%d)\n", ret);
  1760. goto err_power_down;
  1761. }
  1762. ar->target_version = target_info.version;
  1763. ar->hw->wiphy->hw_version = target_info.version;
  1764. ret = ath10k_init_hw_params(ar);
  1765. if (ret) {
  1766. ath10k_err(ar, "could not get hw params (%d)\n", ret);
  1767. goto err_power_down;
  1768. }
  1769. ret = ath10k_core_fetch_firmware_files(ar);
  1770. if (ret) {
  1771. ath10k_err(ar, "could not fetch firmware files (%d)\n", ret);
  1772. goto err_power_down;
  1773. }
  1774. BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) !=
  1775. sizeof(ar->normal_mode_fw.fw_file.fw_version));
  1776. memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version,
  1777. sizeof(ar->hw->wiphy->fw_version));
  1778. ath10k_debug_print_hwfw_info(ar);
  1779. ret = ath10k_core_pre_cal_download(ar);
  1780. if (ret) {
  1781. /* pre calibration data download is not necessary
  1782. * for all the chipsets. Ignore failures and continue.
  1783. */
  1784. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1785. "could not load pre cal data: %d\n", ret);
  1786. }
  1787. ret = ath10k_core_get_board_id_from_otp(ar);
  1788. if (ret && ret != -EOPNOTSUPP) {
  1789. ath10k_err(ar, "failed to get board id from otp: %d\n",
  1790. ret);
  1791. goto err_free_firmware_files;
  1792. }
  1793. ret = ath10k_core_fetch_board_file(ar);
  1794. if (ret) {
  1795. ath10k_err(ar, "failed to fetch board file: %d\n", ret);
  1796. goto err_free_firmware_files;
  1797. }
  1798. ath10k_debug_print_board_info(ar);
  1799. ret = ath10k_core_init_firmware_features(ar);
  1800. if (ret) {
  1801. ath10k_err(ar, "fatal problem with firmware features: %d\n",
  1802. ret);
  1803. goto err_free_firmware_files;
  1804. }
  1805. ret = ath10k_swap_code_seg_init(ar, &ar->normal_mode_fw.fw_file);
  1806. if (ret) {
  1807. ath10k_err(ar, "failed to initialize code swap segment: %d\n",
  1808. ret);
  1809. goto err_free_firmware_files;
  1810. }
  1811. mutex_lock(&ar->conf_mutex);
  1812. ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL,
  1813. &ar->normal_mode_fw);
  1814. if (ret) {
  1815. ath10k_err(ar, "could not init core (%d)\n", ret);
  1816. goto err_unlock;
  1817. }
  1818. ath10k_debug_print_boot_info(ar);
  1819. ath10k_core_stop(ar);
  1820. mutex_unlock(&ar->conf_mutex);
  1821. ath10k_hif_power_down(ar);
  1822. return 0;
  1823. err_unlock:
  1824. mutex_unlock(&ar->conf_mutex);
  1825. err_free_firmware_files:
  1826. ath10k_core_free_firmware_files(ar);
  1827. err_power_down:
  1828. ath10k_hif_power_down(ar);
  1829. return ret;
  1830. }
  1831. static void ath10k_core_register_work(struct work_struct *work)
  1832. {
  1833. struct ath10k *ar = container_of(work, struct ath10k, register_work);
  1834. int status;
  1835. /* peer stats are enabled by default */
  1836. set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags);
  1837. status = ath10k_core_probe_fw(ar);
  1838. if (status) {
  1839. ath10k_err(ar, "could not probe fw (%d)\n", status);
  1840. goto err;
  1841. }
  1842. status = ath10k_mac_register(ar);
  1843. if (status) {
  1844. ath10k_err(ar, "could not register to mac80211 (%d)\n", status);
  1845. goto err_release_fw;
  1846. }
  1847. status = ath10k_debug_register(ar);
  1848. if (status) {
  1849. ath10k_err(ar, "unable to initialize debugfs\n");
  1850. goto err_unregister_mac;
  1851. }
  1852. status = ath10k_spectral_create(ar);
  1853. if (status) {
  1854. ath10k_err(ar, "failed to initialize spectral\n");
  1855. goto err_debug_destroy;
  1856. }
  1857. status = ath10k_thermal_register(ar);
  1858. if (status) {
  1859. ath10k_err(ar, "could not register thermal device: %d\n",
  1860. status);
  1861. goto err_spectral_destroy;
  1862. }
  1863. set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags);
  1864. return;
  1865. err_spectral_destroy:
  1866. ath10k_spectral_destroy(ar);
  1867. err_debug_destroy:
  1868. ath10k_debug_destroy(ar);
  1869. err_unregister_mac:
  1870. ath10k_mac_unregister(ar);
  1871. err_release_fw:
  1872. ath10k_core_free_firmware_files(ar);
  1873. err:
  1874. /* TODO: It's probably a good idea to release device from the driver
  1875. * but calling device_release_driver() here will cause a deadlock.
  1876. */
  1877. return;
  1878. }
  1879. int ath10k_core_register(struct ath10k *ar, u32 chip_id)
  1880. {
  1881. ar->chip_id = chip_id;
  1882. queue_work(ar->workqueue, &ar->register_work);
  1883. return 0;
  1884. }
  1885. EXPORT_SYMBOL(ath10k_core_register);
  1886. void ath10k_core_unregister(struct ath10k *ar)
  1887. {
  1888. cancel_work_sync(&ar->register_work);
  1889. if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))
  1890. return;
  1891. ath10k_thermal_unregister(ar);
  1892. /* Stop spectral before unregistering from mac80211 to remove the
  1893. * relayfs debugfs file cleanly. Otherwise the parent debugfs tree
  1894. * would be already be free'd recursively, leading to a double free.
  1895. */
  1896. ath10k_spectral_destroy(ar);
  1897. /* We must unregister from mac80211 before we stop HTC and HIF.
  1898. * Otherwise we will fail to submit commands to FW and mac80211 will be
  1899. * unhappy about callback failures. */
  1900. ath10k_mac_unregister(ar);
  1901. ath10k_testmode_destroy(ar);
  1902. ath10k_core_free_firmware_files(ar);
  1903. ath10k_core_free_board_files(ar);
  1904. ath10k_debug_unregister(ar);
  1905. }
  1906. EXPORT_SYMBOL(ath10k_core_unregister);
  1907. struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
  1908. enum ath10k_bus bus,
  1909. enum ath10k_hw_rev hw_rev,
  1910. const struct ath10k_hif_ops *hif_ops)
  1911. {
  1912. struct ath10k *ar;
  1913. int ret;
  1914. ar = ath10k_mac_create(priv_size);
  1915. if (!ar)
  1916. return NULL;
  1917. ar->ath_common.priv = ar;
  1918. ar->ath_common.hw = ar->hw;
  1919. ar->dev = dev;
  1920. ar->hw_rev = hw_rev;
  1921. ar->hif.ops = hif_ops;
  1922. ar->hif.bus = bus;
  1923. switch (hw_rev) {
  1924. case ATH10K_HW_QCA988X:
  1925. case ATH10K_HW_QCA9887:
  1926. ar->regs = &qca988x_regs;
  1927. ar->hw_values = &qca988x_values;
  1928. break;
  1929. case ATH10K_HW_QCA6174:
  1930. case ATH10K_HW_QCA9377:
  1931. ar->regs = &qca6174_regs;
  1932. ar->hw_values = &qca6174_values;
  1933. break;
  1934. case ATH10K_HW_QCA99X0:
  1935. case ATH10K_HW_QCA9984:
  1936. ar->regs = &qca99x0_regs;
  1937. ar->hw_values = &qca99x0_values;
  1938. break;
  1939. case ATH10K_HW_QCA9888:
  1940. ar->regs = &qca99x0_regs;
  1941. ar->hw_values = &qca9888_values;
  1942. break;
  1943. case ATH10K_HW_QCA4019:
  1944. ar->regs = &qca4019_regs;
  1945. ar->hw_values = &qca4019_values;
  1946. break;
  1947. default:
  1948. ath10k_err(ar, "unsupported core hardware revision %d\n",
  1949. hw_rev);
  1950. ret = -ENOTSUPP;
  1951. goto err_free_mac;
  1952. }
  1953. init_completion(&ar->scan.started);
  1954. init_completion(&ar->scan.completed);
  1955. init_completion(&ar->scan.on_channel);
  1956. init_completion(&ar->target_suspend);
  1957. init_completion(&ar->wow.wakeup_completed);
  1958. init_completion(&ar->install_key_done);
  1959. init_completion(&ar->vdev_setup_done);
  1960. init_completion(&ar->thermal.wmi_sync);
  1961. init_completion(&ar->bss_survey_done);
  1962. INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work);
  1963. ar->workqueue = create_singlethread_workqueue("ath10k_wq");
  1964. if (!ar->workqueue)
  1965. goto err_free_mac;
  1966. ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq");
  1967. if (!ar->workqueue_aux)
  1968. goto err_free_wq;
  1969. mutex_init(&ar->conf_mutex);
  1970. spin_lock_init(&ar->data_lock);
  1971. spin_lock_init(&ar->txqs_lock);
  1972. INIT_LIST_HEAD(&ar->txqs);
  1973. INIT_LIST_HEAD(&ar->peers);
  1974. init_waitqueue_head(&ar->peer_mapping_wq);
  1975. init_waitqueue_head(&ar->htt.empty_tx_wq);
  1976. init_waitqueue_head(&ar->wmi.tx_credits_wq);
  1977. init_completion(&ar->offchan_tx_completed);
  1978. INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work);
  1979. skb_queue_head_init(&ar->offchan_tx_queue);
  1980. INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work);
  1981. skb_queue_head_init(&ar->wmi_mgmt_tx_queue);
  1982. INIT_WORK(&ar->register_work, ath10k_core_register_work);
  1983. INIT_WORK(&ar->restart_work, ath10k_core_restart);
  1984. INIT_WORK(&ar->set_coverage_class_work,
  1985. ath10k_core_set_coverage_class_work);
  1986. init_dummy_netdev(&ar->napi_dev);
  1987. ret = ath10k_debug_create(ar);
  1988. if (ret)
  1989. goto err_free_aux_wq;
  1990. return ar;
  1991. err_free_aux_wq:
  1992. destroy_workqueue(ar->workqueue_aux);
  1993. err_free_wq:
  1994. destroy_workqueue(ar->workqueue);
  1995. err_free_mac:
  1996. ath10k_mac_destroy(ar);
  1997. return NULL;
  1998. }
  1999. EXPORT_SYMBOL(ath10k_core_create);
  2000. void ath10k_core_destroy(struct ath10k *ar)
  2001. {
  2002. flush_workqueue(ar->workqueue);
  2003. destroy_workqueue(ar->workqueue);
  2004. flush_workqueue(ar->workqueue_aux);
  2005. destroy_workqueue(ar->workqueue_aux);
  2006. ath10k_debug_destroy(ar);
  2007. ath10k_htt_tx_destroy(&ar->htt);
  2008. ath10k_wmi_free_host_mem(ar);
  2009. ath10k_mac_destroy(ar);
  2010. }
  2011. EXPORT_SYMBOL(ath10k_core_destroy);
  2012. MODULE_AUTHOR("Qualcomm Atheros");
  2013. MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards.");
  2014. MODULE_LICENSE("Dual BSD/GPL");