smsc75xx.c 56 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2010 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. *****************************************************************************/
  19. #include <linux/module.h>
  20. #include <linux/kmod.h>
  21. #include <linux/netdevice.h>
  22. #include <linux/etherdevice.h>
  23. #include <linux/ethtool.h>
  24. #include <linux/mii.h>
  25. #include <linux/usb.h>
  26. #include <linux/bitrev.h>
  27. #include <linux/crc16.h>
  28. #include <linux/crc32.h>
  29. #include <linux/usb/usbnet.h>
  30. #include <linux/slab.h>
  31. #include <linux/of_net.h>
  32. #include "smsc75xx.h"
  33. #define SMSC_CHIPNAME "smsc75xx"
  34. #define SMSC_DRIVER_VERSION "1.0.0"
  35. #define HS_USB_PKT_SIZE (512)
  36. #define FS_USB_PKT_SIZE (64)
  37. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  38. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  39. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  40. #define MAX_SINGLE_PACKET_SIZE (9000)
  41. #define LAN75XX_EEPROM_MAGIC (0x7500)
  42. #define EEPROM_MAC_OFFSET (0x01)
  43. #define DEFAULT_TX_CSUM_ENABLE (true)
  44. #define DEFAULT_RX_CSUM_ENABLE (true)
  45. #define SMSC75XX_INTERNAL_PHY_ID (1)
  46. #define SMSC75XX_TX_OVERHEAD (8)
  47. #define MAX_RX_FIFO_SIZE (20 * 1024)
  48. #define MAX_TX_FIFO_SIZE (12 * 1024)
  49. #define USB_VENDOR_ID_SMSC (0x0424)
  50. #define USB_PRODUCT_ID_LAN7500 (0x7500)
  51. #define USB_PRODUCT_ID_LAN7505 (0x7505)
  52. #define RXW_PADDING 2
  53. #define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
  54. WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
  55. #define SUSPEND_SUSPEND0 (0x01)
  56. #define SUSPEND_SUSPEND1 (0x02)
  57. #define SUSPEND_SUSPEND2 (0x04)
  58. #define SUSPEND_SUSPEND3 (0x08)
  59. #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
  60. SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
  61. struct smsc75xx_priv {
  62. struct usbnet *dev;
  63. u32 rfe_ctl;
  64. u32 wolopts;
  65. u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
  66. struct mutex dataport_mutex;
  67. spinlock_t rfe_ctl_lock;
  68. struct work_struct set_multicast;
  69. u8 suspend_flags;
  70. };
  71. struct usb_context {
  72. struct usb_ctrlrequest req;
  73. struct usbnet *dev;
  74. };
  75. static bool turbo_mode = true;
  76. module_param(turbo_mode, bool, 0644);
  77. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  78. static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
  79. u32 *data, int in_pm)
  80. {
  81. u32 buf;
  82. int ret;
  83. int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
  84. BUG_ON(!dev);
  85. if (!in_pm)
  86. fn = usbnet_read_cmd;
  87. else
  88. fn = usbnet_read_cmd_nopm;
  89. ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
  90. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  91. 0, index, &buf, 4);
  92. if (unlikely(ret < 0)) {
  93. netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
  94. index, ret);
  95. return ret;
  96. }
  97. le32_to_cpus(&buf);
  98. *data = buf;
  99. return ret;
  100. }
  101. static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
  102. u32 data, int in_pm)
  103. {
  104. u32 buf;
  105. int ret;
  106. int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
  107. BUG_ON(!dev);
  108. if (!in_pm)
  109. fn = usbnet_write_cmd;
  110. else
  111. fn = usbnet_write_cmd_nopm;
  112. buf = data;
  113. cpu_to_le32s(&buf);
  114. ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
  115. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  116. 0, index, &buf, 4);
  117. if (unlikely(ret < 0))
  118. netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
  119. index, ret);
  120. return ret;
  121. }
  122. static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
  123. u32 *data)
  124. {
  125. return __smsc75xx_read_reg(dev, index, data, 1);
  126. }
  127. static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
  128. u32 data)
  129. {
  130. return __smsc75xx_write_reg(dev, index, data, 1);
  131. }
  132. static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
  133. u32 *data)
  134. {
  135. return __smsc75xx_read_reg(dev, index, data, 0);
  136. }
  137. static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
  138. u32 data)
  139. {
  140. return __smsc75xx_write_reg(dev, index, data, 0);
  141. }
  142. /* Loop until the read is completed with timeout
  143. * called with phy_mutex held */
  144. static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
  145. int in_pm)
  146. {
  147. unsigned long start_time = jiffies;
  148. u32 val;
  149. int ret;
  150. do {
  151. ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
  152. if (ret < 0) {
  153. netdev_warn(dev->net, "Error reading MII_ACCESS\n");
  154. return ret;
  155. }
  156. if (!(val & MII_ACCESS_BUSY))
  157. return 0;
  158. } while (!time_after(jiffies, start_time + HZ));
  159. return -EIO;
  160. }
  161. static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
  162. int in_pm)
  163. {
  164. struct usbnet *dev = netdev_priv(netdev);
  165. u32 val, addr;
  166. int ret;
  167. mutex_lock(&dev->phy_mutex);
  168. /* confirm MII not busy */
  169. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  170. if (ret < 0) {
  171. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_read\n");
  172. goto done;
  173. }
  174. /* set the address, index & direction (read from PHY) */
  175. phy_id &= dev->mii.phy_id_mask;
  176. idx &= dev->mii.reg_num_mask;
  177. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  178. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  179. | MII_ACCESS_READ | MII_ACCESS_BUSY;
  180. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  181. if (ret < 0) {
  182. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  183. goto done;
  184. }
  185. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  186. if (ret < 0) {
  187. netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
  188. goto done;
  189. }
  190. ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
  191. if (ret < 0) {
  192. netdev_warn(dev->net, "Error reading MII_DATA\n");
  193. goto done;
  194. }
  195. ret = (u16)(val & 0xFFFF);
  196. done:
  197. mutex_unlock(&dev->phy_mutex);
  198. return ret;
  199. }
  200. static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
  201. int idx, int regval, int in_pm)
  202. {
  203. struct usbnet *dev = netdev_priv(netdev);
  204. u32 val, addr;
  205. int ret;
  206. mutex_lock(&dev->phy_mutex);
  207. /* confirm MII not busy */
  208. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  209. if (ret < 0) {
  210. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_write\n");
  211. goto done;
  212. }
  213. val = regval;
  214. ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
  215. if (ret < 0) {
  216. netdev_warn(dev->net, "Error writing MII_DATA\n");
  217. goto done;
  218. }
  219. /* set the address, index & direction (write to PHY) */
  220. phy_id &= dev->mii.phy_id_mask;
  221. idx &= dev->mii.reg_num_mask;
  222. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  223. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  224. | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
  225. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  226. if (ret < 0) {
  227. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  228. goto done;
  229. }
  230. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  231. if (ret < 0) {
  232. netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
  233. goto done;
  234. }
  235. done:
  236. mutex_unlock(&dev->phy_mutex);
  237. }
  238. static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
  239. int idx)
  240. {
  241. return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
  242. }
  243. static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
  244. int idx, int regval)
  245. {
  246. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
  247. }
  248. static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  249. {
  250. return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
  251. }
  252. static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  253. int regval)
  254. {
  255. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
  256. }
  257. static int smsc75xx_wait_eeprom(struct usbnet *dev)
  258. {
  259. unsigned long start_time = jiffies;
  260. u32 val;
  261. int ret;
  262. do {
  263. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  264. if (ret < 0) {
  265. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  266. return ret;
  267. }
  268. if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
  269. break;
  270. udelay(40);
  271. } while (!time_after(jiffies, start_time + HZ));
  272. if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
  273. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  274. return -EIO;
  275. }
  276. return 0;
  277. }
  278. static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
  279. {
  280. unsigned long start_time = jiffies;
  281. u32 val;
  282. int ret;
  283. do {
  284. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  285. if (ret < 0) {
  286. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  287. return ret;
  288. }
  289. if (!(val & E2P_CMD_BUSY))
  290. return 0;
  291. udelay(40);
  292. } while (!time_after(jiffies, start_time + HZ));
  293. netdev_warn(dev->net, "EEPROM is busy\n");
  294. return -EIO;
  295. }
  296. static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  297. u8 *data)
  298. {
  299. u32 val;
  300. int i, ret;
  301. BUG_ON(!dev);
  302. BUG_ON(!data);
  303. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  304. if (ret)
  305. return ret;
  306. for (i = 0; i < length; i++) {
  307. val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
  308. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  309. if (ret < 0) {
  310. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  311. return ret;
  312. }
  313. ret = smsc75xx_wait_eeprom(dev);
  314. if (ret < 0)
  315. return ret;
  316. ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
  317. if (ret < 0) {
  318. netdev_warn(dev->net, "Error reading E2P_DATA\n");
  319. return ret;
  320. }
  321. data[i] = val & 0xFF;
  322. offset++;
  323. }
  324. return 0;
  325. }
  326. static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  327. u8 *data)
  328. {
  329. u32 val;
  330. int i, ret;
  331. BUG_ON(!dev);
  332. BUG_ON(!data);
  333. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  334. if (ret)
  335. return ret;
  336. /* Issue write/erase enable command */
  337. val = E2P_CMD_BUSY | E2P_CMD_EWEN;
  338. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  339. if (ret < 0) {
  340. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  341. return ret;
  342. }
  343. ret = smsc75xx_wait_eeprom(dev);
  344. if (ret < 0)
  345. return ret;
  346. for (i = 0; i < length; i++) {
  347. /* Fill data register */
  348. val = data[i];
  349. ret = smsc75xx_write_reg(dev, E2P_DATA, val);
  350. if (ret < 0) {
  351. netdev_warn(dev->net, "Error writing E2P_DATA\n");
  352. return ret;
  353. }
  354. /* Send "write" command */
  355. val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
  356. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  357. if (ret < 0) {
  358. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  359. return ret;
  360. }
  361. ret = smsc75xx_wait_eeprom(dev);
  362. if (ret < 0)
  363. return ret;
  364. offset++;
  365. }
  366. return 0;
  367. }
  368. static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
  369. {
  370. int i, ret;
  371. for (i = 0; i < 100; i++) {
  372. u32 dp_sel;
  373. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  374. if (ret < 0) {
  375. netdev_warn(dev->net, "Error reading DP_SEL\n");
  376. return ret;
  377. }
  378. if (dp_sel & DP_SEL_DPRDY)
  379. return 0;
  380. udelay(40);
  381. }
  382. netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
  383. return -EIO;
  384. }
  385. static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
  386. u32 length, u32 *buf)
  387. {
  388. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  389. u32 dp_sel;
  390. int i, ret;
  391. mutex_lock(&pdata->dataport_mutex);
  392. ret = smsc75xx_dataport_wait_not_busy(dev);
  393. if (ret < 0) {
  394. netdev_warn(dev->net, "smsc75xx_dataport_write busy on entry\n");
  395. goto done;
  396. }
  397. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  398. if (ret < 0) {
  399. netdev_warn(dev->net, "Error reading DP_SEL\n");
  400. goto done;
  401. }
  402. dp_sel &= ~DP_SEL_RSEL;
  403. dp_sel |= ram_select;
  404. ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
  405. if (ret < 0) {
  406. netdev_warn(dev->net, "Error writing DP_SEL\n");
  407. goto done;
  408. }
  409. for (i = 0; i < length; i++) {
  410. ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
  411. if (ret < 0) {
  412. netdev_warn(dev->net, "Error writing DP_ADDR\n");
  413. goto done;
  414. }
  415. ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
  416. if (ret < 0) {
  417. netdev_warn(dev->net, "Error writing DP_DATA\n");
  418. goto done;
  419. }
  420. ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
  421. if (ret < 0) {
  422. netdev_warn(dev->net, "Error writing DP_CMD\n");
  423. goto done;
  424. }
  425. ret = smsc75xx_dataport_wait_not_busy(dev);
  426. if (ret < 0) {
  427. netdev_warn(dev->net, "smsc75xx_dataport_write timeout\n");
  428. goto done;
  429. }
  430. }
  431. done:
  432. mutex_unlock(&pdata->dataport_mutex);
  433. return ret;
  434. }
  435. /* returns hash bit number for given MAC address */
  436. static u32 smsc75xx_hash(char addr[ETH_ALEN])
  437. {
  438. return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
  439. }
  440. static void smsc75xx_deferred_multicast_write(struct work_struct *param)
  441. {
  442. struct smsc75xx_priv *pdata =
  443. container_of(param, struct smsc75xx_priv, set_multicast);
  444. struct usbnet *dev = pdata->dev;
  445. int ret;
  446. netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
  447. pdata->rfe_ctl);
  448. smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
  449. DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
  450. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  451. if (ret < 0)
  452. netdev_warn(dev->net, "Error writing RFE_CRL\n");
  453. }
  454. static void smsc75xx_set_multicast(struct net_device *netdev)
  455. {
  456. struct usbnet *dev = netdev_priv(netdev);
  457. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  458. unsigned long flags;
  459. int i;
  460. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  461. pdata->rfe_ctl &=
  462. ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
  463. pdata->rfe_ctl |= RFE_CTL_AB;
  464. for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
  465. pdata->multicast_hash_table[i] = 0;
  466. if (dev->net->flags & IFF_PROMISC) {
  467. netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
  468. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
  469. } else if (dev->net->flags & IFF_ALLMULTI) {
  470. netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
  471. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
  472. } else if (!netdev_mc_empty(dev->net)) {
  473. struct netdev_hw_addr *ha;
  474. netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
  475. pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
  476. netdev_for_each_mc_addr(ha, netdev) {
  477. u32 bitnum = smsc75xx_hash(ha->addr);
  478. pdata->multicast_hash_table[bitnum / 32] |=
  479. (1 << (bitnum % 32));
  480. }
  481. } else {
  482. netif_dbg(dev, drv, dev->net, "receive own packets only\n");
  483. pdata->rfe_ctl |= RFE_CTL_DPF;
  484. }
  485. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  486. /* defer register writes to a sleepable context */
  487. schedule_work(&pdata->set_multicast);
  488. }
  489. static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
  490. u16 lcladv, u16 rmtadv)
  491. {
  492. u32 flow = 0, fct_flow = 0;
  493. int ret;
  494. if (duplex == DUPLEX_FULL) {
  495. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  496. if (cap & FLOW_CTRL_TX) {
  497. flow = (FLOW_TX_FCEN | 0xFFFF);
  498. /* set fct_flow thresholds to 20% and 80% */
  499. fct_flow = (8 << 8) | 32;
  500. }
  501. if (cap & FLOW_CTRL_RX)
  502. flow |= FLOW_RX_FCEN;
  503. netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
  504. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  505. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  506. } else {
  507. netif_dbg(dev, link, dev->net, "half duplex\n");
  508. }
  509. ret = smsc75xx_write_reg(dev, FLOW, flow);
  510. if (ret < 0) {
  511. netdev_warn(dev->net, "Error writing FLOW\n");
  512. return ret;
  513. }
  514. ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
  515. if (ret < 0) {
  516. netdev_warn(dev->net, "Error writing FCT_FLOW\n");
  517. return ret;
  518. }
  519. return 0;
  520. }
  521. static int smsc75xx_link_reset(struct usbnet *dev)
  522. {
  523. struct mii_if_info *mii = &dev->mii;
  524. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  525. u16 lcladv, rmtadv;
  526. int ret;
  527. /* write to clear phy interrupt status */
  528. smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
  529. PHY_INT_SRC_CLEAR_ALL);
  530. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  531. if (ret < 0) {
  532. netdev_warn(dev->net, "Error writing INT_STS\n");
  533. return ret;
  534. }
  535. mii_check_media(mii, 1, 1);
  536. mii_ethtool_gset(&dev->mii, &ecmd);
  537. lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  538. rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  539. netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
  540. ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
  541. return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  542. }
  543. static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
  544. {
  545. u32 intdata;
  546. if (urb->actual_length != 4) {
  547. netdev_warn(dev->net, "unexpected urb length %d\n",
  548. urb->actual_length);
  549. return;
  550. }
  551. memcpy(&intdata, urb->transfer_buffer, 4);
  552. le32_to_cpus(&intdata);
  553. netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
  554. if (intdata & INT_ENP_PHY_INT)
  555. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  556. else
  557. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  558. intdata);
  559. }
  560. static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
  561. {
  562. return MAX_EEPROM_SIZE;
  563. }
  564. static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
  565. struct ethtool_eeprom *ee, u8 *data)
  566. {
  567. struct usbnet *dev = netdev_priv(netdev);
  568. ee->magic = LAN75XX_EEPROM_MAGIC;
  569. return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
  570. }
  571. static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
  572. struct ethtool_eeprom *ee, u8 *data)
  573. {
  574. struct usbnet *dev = netdev_priv(netdev);
  575. if (ee->magic != LAN75XX_EEPROM_MAGIC) {
  576. netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
  577. ee->magic);
  578. return -EINVAL;
  579. }
  580. return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
  581. }
  582. static void smsc75xx_ethtool_get_wol(struct net_device *net,
  583. struct ethtool_wolinfo *wolinfo)
  584. {
  585. struct usbnet *dev = netdev_priv(net);
  586. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  587. wolinfo->supported = SUPPORTED_WAKE;
  588. wolinfo->wolopts = pdata->wolopts;
  589. }
  590. static int smsc75xx_ethtool_set_wol(struct net_device *net,
  591. struct ethtool_wolinfo *wolinfo)
  592. {
  593. struct usbnet *dev = netdev_priv(net);
  594. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  595. int ret;
  596. pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
  597. ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
  598. if (ret < 0)
  599. netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
  600. return ret;
  601. }
  602. static const struct ethtool_ops smsc75xx_ethtool_ops = {
  603. .get_link = usbnet_get_link,
  604. .nway_reset = usbnet_nway_reset,
  605. .get_drvinfo = usbnet_get_drvinfo,
  606. .get_msglevel = usbnet_get_msglevel,
  607. .set_msglevel = usbnet_set_msglevel,
  608. .get_settings = usbnet_get_settings,
  609. .set_settings = usbnet_set_settings,
  610. .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
  611. .get_eeprom = smsc75xx_ethtool_get_eeprom,
  612. .set_eeprom = smsc75xx_ethtool_set_eeprom,
  613. .get_wol = smsc75xx_ethtool_get_wol,
  614. .set_wol = smsc75xx_ethtool_set_wol,
  615. };
  616. static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  617. {
  618. struct usbnet *dev = netdev_priv(netdev);
  619. if (!netif_running(netdev))
  620. return -EINVAL;
  621. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  622. }
  623. static void smsc75xx_init_mac_address(struct usbnet *dev)
  624. {
  625. const u8 *mac_addr;
  626. /* maybe the boot loader passed the MAC address in devicetree */
  627. mac_addr = of_get_mac_address(dev->udev->dev.of_node);
  628. if (mac_addr) {
  629. memcpy(dev->net->dev_addr, mac_addr, ETH_ALEN);
  630. return;
  631. }
  632. /* try reading mac address from EEPROM */
  633. if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  634. dev->net->dev_addr) == 0) {
  635. if (is_valid_ether_addr(dev->net->dev_addr)) {
  636. /* eeprom values are valid so use them */
  637. netif_dbg(dev, ifup, dev->net,
  638. "MAC address read from EEPROM\n");
  639. return;
  640. }
  641. }
  642. /* no useful static MAC address found. generate a random one */
  643. eth_hw_addr_random(dev->net);
  644. netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
  645. }
  646. static int smsc75xx_set_mac_address(struct usbnet *dev)
  647. {
  648. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  649. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  650. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  651. int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
  652. if (ret < 0) {
  653. netdev_warn(dev->net, "Failed to write RX_ADDRH: %d\n", ret);
  654. return ret;
  655. }
  656. ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
  657. if (ret < 0) {
  658. netdev_warn(dev->net, "Failed to write RX_ADDRL: %d\n", ret);
  659. return ret;
  660. }
  661. addr_hi |= ADDR_FILTX_FB_VALID;
  662. ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
  663. if (ret < 0) {
  664. netdev_warn(dev->net, "Failed to write ADDR_FILTX: %d\n", ret);
  665. return ret;
  666. }
  667. ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
  668. if (ret < 0)
  669. netdev_warn(dev->net, "Failed to write ADDR_FILTX+4: %d\n", ret);
  670. return ret;
  671. }
  672. static int smsc75xx_phy_initialize(struct usbnet *dev)
  673. {
  674. int bmcr, ret, timeout = 0;
  675. /* Initialize MII structure */
  676. dev->mii.dev = dev->net;
  677. dev->mii.mdio_read = smsc75xx_mdio_read;
  678. dev->mii.mdio_write = smsc75xx_mdio_write;
  679. dev->mii.phy_id_mask = 0x1f;
  680. dev->mii.reg_num_mask = 0x1f;
  681. dev->mii.supports_gmii = 1;
  682. dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
  683. /* reset phy and wait for reset to complete */
  684. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  685. do {
  686. msleep(10);
  687. bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
  688. if (bmcr < 0) {
  689. netdev_warn(dev->net, "Error reading MII_BMCR\n");
  690. return bmcr;
  691. }
  692. timeout++;
  693. } while ((bmcr & BMCR_RESET) && (timeout < 100));
  694. if (timeout >= 100) {
  695. netdev_warn(dev->net, "timeout on PHY Reset\n");
  696. return -EIO;
  697. }
  698. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  699. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  700. ADVERTISE_PAUSE_ASYM);
  701. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
  702. ADVERTISE_1000FULL);
  703. /* read and write to clear phy interrupt status */
  704. ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  705. if (ret < 0) {
  706. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  707. return ret;
  708. }
  709. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
  710. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  711. PHY_INT_MASK_DEFAULT);
  712. mii_nway_restart(&dev->mii);
  713. netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
  714. return 0;
  715. }
  716. static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
  717. {
  718. int ret = 0;
  719. u32 buf;
  720. bool rxenabled;
  721. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  722. if (ret < 0) {
  723. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  724. return ret;
  725. }
  726. rxenabled = ((buf & MAC_RX_RXEN) != 0);
  727. if (rxenabled) {
  728. buf &= ~MAC_RX_RXEN;
  729. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  730. if (ret < 0) {
  731. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  732. return ret;
  733. }
  734. }
  735. /* add 4 to size for FCS */
  736. buf &= ~MAC_RX_MAX_SIZE;
  737. buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
  738. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  739. if (ret < 0) {
  740. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  741. return ret;
  742. }
  743. if (rxenabled) {
  744. buf |= MAC_RX_RXEN;
  745. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  746. if (ret < 0) {
  747. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  748. return ret;
  749. }
  750. }
  751. return 0;
  752. }
  753. static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
  754. {
  755. struct usbnet *dev = netdev_priv(netdev);
  756. int ret;
  757. ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
  758. if (ret < 0) {
  759. netdev_warn(dev->net, "Failed to set mac rx frame length\n");
  760. return ret;
  761. }
  762. return usbnet_change_mtu(netdev, new_mtu);
  763. }
  764. /* Enable or disable Rx checksum offload engine */
  765. static int smsc75xx_set_features(struct net_device *netdev,
  766. netdev_features_t features)
  767. {
  768. struct usbnet *dev = netdev_priv(netdev);
  769. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  770. unsigned long flags;
  771. int ret;
  772. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  773. if (features & NETIF_F_RXCSUM)
  774. pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
  775. else
  776. pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
  777. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  778. /* it's racing here! */
  779. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  780. if (ret < 0)
  781. netdev_warn(dev->net, "Error writing RFE_CTL\n");
  782. return ret;
  783. }
  784. static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
  785. {
  786. int timeout = 0;
  787. do {
  788. u32 buf;
  789. int ret;
  790. ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
  791. if (ret < 0) {
  792. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  793. return ret;
  794. }
  795. if (buf & PMT_CTL_DEV_RDY)
  796. return 0;
  797. msleep(10);
  798. timeout++;
  799. } while (timeout < 100);
  800. netdev_warn(dev->net, "timeout waiting for device ready\n");
  801. return -EIO;
  802. }
  803. static int smsc75xx_reset(struct usbnet *dev)
  804. {
  805. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  806. u32 buf;
  807. int ret = 0, timeout;
  808. netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
  809. ret = smsc75xx_wait_ready(dev, 0);
  810. if (ret < 0) {
  811. netdev_warn(dev->net, "device not ready in smsc75xx_reset\n");
  812. return ret;
  813. }
  814. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  815. if (ret < 0) {
  816. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  817. return ret;
  818. }
  819. buf |= HW_CFG_LRST;
  820. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  821. if (ret < 0) {
  822. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  823. return ret;
  824. }
  825. timeout = 0;
  826. do {
  827. msleep(10);
  828. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  829. if (ret < 0) {
  830. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  831. return ret;
  832. }
  833. timeout++;
  834. } while ((buf & HW_CFG_LRST) && (timeout < 100));
  835. if (timeout >= 100) {
  836. netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
  837. return -EIO;
  838. }
  839. netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
  840. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  841. if (ret < 0) {
  842. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  843. return ret;
  844. }
  845. buf |= PMT_CTL_PHY_RST;
  846. ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
  847. if (ret < 0) {
  848. netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
  849. return ret;
  850. }
  851. timeout = 0;
  852. do {
  853. msleep(10);
  854. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  855. if (ret < 0) {
  856. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  857. return ret;
  858. }
  859. timeout++;
  860. } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
  861. if (timeout >= 100) {
  862. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  863. return -EIO;
  864. }
  865. netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
  866. ret = smsc75xx_set_mac_address(dev);
  867. if (ret < 0) {
  868. netdev_warn(dev->net, "Failed to set mac address\n");
  869. return ret;
  870. }
  871. netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
  872. dev->net->dev_addr);
  873. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  874. if (ret < 0) {
  875. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  876. return ret;
  877. }
  878. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
  879. buf);
  880. buf |= HW_CFG_BIR;
  881. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  882. if (ret < 0) {
  883. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  884. return ret;
  885. }
  886. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  887. if (ret < 0) {
  888. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  889. return ret;
  890. }
  891. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
  892. buf);
  893. if (!turbo_mode) {
  894. buf = 0;
  895. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  896. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  897. buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  898. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  899. } else {
  900. buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  901. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  902. }
  903. netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
  904. (ulong)dev->rx_urb_size);
  905. ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
  906. if (ret < 0) {
  907. netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
  908. return ret;
  909. }
  910. ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
  911. if (ret < 0) {
  912. netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
  913. return ret;
  914. }
  915. netif_dbg(dev, ifup, dev->net,
  916. "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
  917. ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
  918. if (ret < 0) {
  919. netdev_warn(dev->net, "Failed to write BULK_IN_DLY: %d\n", ret);
  920. return ret;
  921. }
  922. ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
  923. if (ret < 0) {
  924. netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
  925. return ret;
  926. }
  927. netif_dbg(dev, ifup, dev->net,
  928. "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
  929. if (turbo_mode) {
  930. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  931. if (ret < 0) {
  932. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  933. return ret;
  934. }
  935. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  936. buf |= (HW_CFG_MEF | HW_CFG_BCE);
  937. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  938. if (ret < 0) {
  939. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  940. return ret;
  941. }
  942. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  943. if (ret < 0) {
  944. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  945. return ret;
  946. }
  947. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  948. }
  949. /* set FIFO sizes */
  950. buf = (MAX_RX_FIFO_SIZE - 512) / 512;
  951. ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
  952. if (ret < 0) {
  953. netdev_warn(dev->net, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
  954. return ret;
  955. }
  956. netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
  957. buf = (MAX_TX_FIFO_SIZE - 512) / 512;
  958. ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
  959. if (ret < 0) {
  960. netdev_warn(dev->net, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
  961. return ret;
  962. }
  963. netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
  964. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  965. if (ret < 0) {
  966. netdev_warn(dev->net, "Failed to write INT_STS: %d\n", ret);
  967. return ret;
  968. }
  969. ret = smsc75xx_read_reg(dev, ID_REV, &buf);
  970. if (ret < 0) {
  971. netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
  972. return ret;
  973. }
  974. netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
  975. ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
  976. if (ret < 0) {
  977. netdev_warn(dev->net, "Failed to read E2P_CMD: %d\n", ret);
  978. return ret;
  979. }
  980. /* only set default GPIO/LED settings if no EEPROM is detected */
  981. if (!(buf & E2P_CMD_LOADED)) {
  982. ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
  983. if (ret < 0) {
  984. netdev_warn(dev->net, "Failed to read LED_GPIO_CFG: %d\n", ret);
  985. return ret;
  986. }
  987. buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
  988. buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
  989. ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
  990. if (ret < 0) {
  991. netdev_warn(dev->net, "Failed to write LED_GPIO_CFG: %d\n", ret);
  992. return ret;
  993. }
  994. }
  995. ret = smsc75xx_write_reg(dev, FLOW, 0);
  996. if (ret < 0) {
  997. netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
  998. return ret;
  999. }
  1000. ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
  1001. if (ret < 0) {
  1002. netdev_warn(dev->net, "Failed to write FCT_FLOW: %d\n", ret);
  1003. return ret;
  1004. }
  1005. /* Don't need rfe_ctl_lock during initialisation */
  1006. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  1007. if (ret < 0) {
  1008. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1009. return ret;
  1010. }
  1011. pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
  1012. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  1013. if (ret < 0) {
  1014. netdev_warn(dev->net, "Failed to write RFE_CTL: %d\n", ret);
  1015. return ret;
  1016. }
  1017. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  1018. if (ret < 0) {
  1019. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1020. return ret;
  1021. }
  1022. netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x\n",
  1023. pdata->rfe_ctl);
  1024. /* Enable or disable checksum offload engines */
  1025. smsc75xx_set_features(dev->net, dev->net->features);
  1026. smsc75xx_set_multicast(dev->net);
  1027. ret = smsc75xx_phy_initialize(dev);
  1028. if (ret < 0) {
  1029. netdev_warn(dev->net, "Failed to initialize PHY: %d\n", ret);
  1030. return ret;
  1031. }
  1032. ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
  1033. if (ret < 0) {
  1034. netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
  1035. return ret;
  1036. }
  1037. /* enable PHY interrupts */
  1038. buf |= INT_ENP_PHY_INT;
  1039. ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
  1040. if (ret < 0) {
  1041. netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
  1042. return ret;
  1043. }
  1044. /* allow mac to detect speed and duplex from phy */
  1045. ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
  1046. if (ret < 0) {
  1047. netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
  1048. return ret;
  1049. }
  1050. buf |= (MAC_CR_ADD | MAC_CR_ASD);
  1051. ret = smsc75xx_write_reg(dev, MAC_CR, buf);
  1052. if (ret < 0) {
  1053. netdev_warn(dev->net, "Failed to write MAC_CR: %d\n", ret);
  1054. return ret;
  1055. }
  1056. ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
  1057. if (ret < 0) {
  1058. netdev_warn(dev->net, "Failed to read MAC_TX: %d\n", ret);
  1059. return ret;
  1060. }
  1061. buf |= MAC_TX_TXEN;
  1062. ret = smsc75xx_write_reg(dev, MAC_TX, buf);
  1063. if (ret < 0) {
  1064. netdev_warn(dev->net, "Failed to write MAC_TX: %d\n", ret);
  1065. return ret;
  1066. }
  1067. netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x\n", buf);
  1068. ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
  1069. if (ret < 0) {
  1070. netdev_warn(dev->net, "Failed to read FCT_TX_CTL: %d\n", ret);
  1071. return ret;
  1072. }
  1073. buf |= FCT_TX_CTL_EN;
  1074. ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
  1075. if (ret < 0) {
  1076. netdev_warn(dev->net, "Failed to write FCT_TX_CTL: %d\n", ret);
  1077. return ret;
  1078. }
  1079. netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
  1080. ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
  1081. if (ret < 0) {
  1082. netdev_warn(dev->net, "Failed to set max rx frame length\n");
  1083. return ret;
  1084. }
  1085. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  1086. if (ret < 0) {
  1087. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1088. return ret;
  1089. }
  1090. buf |= MAC_RX_RXEN;
  1091. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  1092. if (ret < 0) {
  1093. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1094. return ret;
  1095. }
  1096. netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x\n", buf);
  1097. ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
  1098. if (ret < 0) {
  1099. netdev_warn(dev->net, "Failed to read FCT_RX_CTL: %d\n", ret);
  1100. return ret;
  1101. }
  1102. buf |= FCT_RX_CTL_EN;
  1103. ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
  1104. if (ret < 0) {
  1105. netdev_warn(dev->net, "Failed to write FCT_RX_CTL: %d\n", ret);
  1106. return ret;
  1107. }
  1108. netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x\n", buf);
  1109. netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0\n");
  1110. return 0;
  1111. }
  1112. static const struct net_device_ops smsc75xx_netdev_ops = {
  1113. .ndo_open = usbnet_open,
  1114. .ndo_stop = usbnet_stop,
  1115. .ndo_start_xmit = usbnet_start_xmit,
  1116. .ndo_tx_timeout = usbnet_tx_timeout,
  1117. .ndo_change_mtu = smsc75xx_change_mtu,
  1118. .ndo_set_mac_address = eth_mac_addr,
  1119. .ndo_validate_addr = eth_validate_addr,
  1120. .ndo_do_ioctl = smsc75xx_ioctl,
  1121. .ndo_set_rx_mode = smsc75xx_set_multicast,
  1122. .ndo_set_features = smsc75xx_set_features,
  1123. };
  1124. static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
  1125. {
  1126. struct smsc75xx_priv *pdata = NULL;
  1127. int ret;
  1128. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  1129. ret = usbnet_get_endpoints(dev, intf);
  1130. if (ret < 0) {
  1131. netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
  1132. return ret;
  1133. }
  1134. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv),
  1135. GFP_KERNEL);
  1136. pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1137. if (!pdata)
  1138. return -ENOMEM;
  1139. pdata->dev = dev;
  1140. spin_lock_init(&pdata->rfe_ctl_lock);
  1141. mutex_init(&pdata->dataport_mutex);
  1142. INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
  1143. if (DEFAULT_TX_CSUM_ENABLE)
  1144. dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
  1145. if (DEFAULT_RX_CSUM_ENABLE)
  1146. dev->net->features |= NETIF_F_RXCSUM;
  1147. dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1148. NETIF_F_RXCSUM;
  1149. ret = smsc75xx_wait_ready(dev, 0);
  1150. if (ret < 0) {
  1151. netdev_warn(dev->net, "device not ready in smsc75xx_bind\n");
  1152. return ret;
  1153. }
  1154. smsc75xx_init_mac_address(dev);
  1155. /* Init all registers */
  1156. ret = smsc75xx_reset(dev);
  1157. if (ret < 0) {
  1158. netdev_warn(dev->net, "smsc75xx_reset error %d\n", ret);
  1159. return ret;
  1160. }
  1161. dev->net->netdev_ops = &smsc75xx_netdev_ops;
  1162. dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
  1163. dev->net->flags |= IFF_MULTICAST;
  1164. dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
  1165. dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
  1166. dev->net->max_mtu = MAX_SINGLE_PACKET_SIZE;
  1167. return 0;
  1168. }
  1169. static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  1170. {
  1171. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1172. if (pdata) {
  1173. netif_dbg(dev, ifdown, dev->net, "free pdata\n");
  1174. kfree(pdata);
  1175. pdata = NULL;
  1176. dev->data[0] = 0;
  1177. }
  1178. }
  1179. static u16 smsc_crc(const u8 *buffer, size_t len)
  1180. {
  1181. return bitrev16(crc16(0xFFFF, buffer, len));
  1182. }
  1183. static int smsc75xx_write_wuff(struct usbnet *dev, int filter, u32 wuf_cfg,
  1184. u32 wuf_mask1)
  1185. {
  1186. int cfg_base = WUF_CFGX + filter * 4;
  1187. int mask_base = WUF_MASKX + filter * 16;
  1188. int ret;
  1189. ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
  1190. if (ret < 0) {
  1191. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1192. return ret;
  1193. }
  1194. ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
  1195. if (ret < 0) {
  1196. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1197. return ret;
  1198. }
  1199. ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
  1200. if (ret < 0) {
  1201. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1202. return ret;
  1203. }
  1204. ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
  1205. if (ret < 0) {
  1206. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1207. return ret;
  1208. }
  1209. ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
  1210. if (ret < 0) {
  1211. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1212. return ret;
  1213. }
  1214. return 0;
  1215. }
  1216. static int smsc75xx_enter_suspend0(struct usbnet *dev)
  1217. {
  1218. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1219. u32 val;
  1220. int ret;
  1221. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1222. if (ret < 0) {
  1223. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1224. return ret;
  1225. }
  1226. val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST));
  1227. val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS;
  1228. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1229. if (ret < 0) {
  1230. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1231. return ret;
  1232. }
  1233. pdata->suspend_flags |= SUSPEND_SUSPEND0;
  1234. return 0;
  1235. }
  1236. static int smsc75xx_enter_suspend1(struct usbnet *dev)
  1237. {
  1238. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1239. u32 val;
  1240. int ret;
  1241. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1242. if (ret < 0) {
  1243. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1244. return ret;
  1245. }
  1246. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1247. val |= PMT_CTL_SUS_MODE_1;
  1248. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1249. if (ret < 0) {
  1250. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1251. return ret;
  1252. }
  1253. /* clear wol status, enable energy detection */
  1254. val &= ~PMT_CTL_WUPS;
  1255. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1256. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1257. if (ret < 0) {
  1258. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1259. return ret;
  1260. }
  1261. pdata->suspend_flags |= SUSPEND_SUSPEND1;
  1262. return 0;
  1263. }
  1264. static int smsc75xx_enter_suspend2(struct usbnet *dev)
  1265. {
  1266. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1267. u32 val;
  1268. int ret;
  1269. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1270. if (ret < 0) {
  1271. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1272. return ret;
  1273. }
  1274. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1275. val |= PMT_CTL_SUS_MODE_2;
  1276. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1277. if (ret < 0) {
  1278. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1279. return ret;
  1280. }
  1281. pdata->suspend_flags |= SUSPEND_SUSPEND2;
  1282. return 0;
  1283. }
  1284. static int smsc75xx_enter_suspend3(struct usbnet *dev)
  1285. {
  1286. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1287. u32 val;
  1288. int ret;
  1289. ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
  1290. if (ret < 0) {
  1291. netdev_warn(dev->net, "Error reading FCT_RX_CTL\n");
  1292. return ret;
  1293. }
  1294. if (val & FCT_RX_CTL_RXUSED) {
  1295. netdev_dbg(dev->net, "rx fifo not empty in autosuspend\n");
  1296. return -EBUSY;
  1297. }
  1298. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1299. if (ret < 0) {
  1300. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1301. return ret;
  1302. }
  1303. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1304. val |= PMT_CTL_SUS_MODE_3 | PMT_CTL_RES_CLR_WKP_EN;
  1305. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1306. if (ret < 0) {
  1307. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1308. return ret;
  1309. }
  1310. /* clear wol status */
  1311. val &= ~PMT_CTL_WUPS;
  1312. val |= PMT_CTL_WUPS_WOL;
  1313. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1314. if (ret < 0) {
  1315. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1316. return ret;
  1317. }
  1318. pdata->suspend_flags |= SUSPEND_SUSPEND3;
  1319. return 0;
  1320. }
  1321. static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
  1322. {
  1323. struct mii_if_info *mii = &dev->mii;
  1324. int ret;
  1325. netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
  1326. /* read to clear */
  1327. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
  1328. if (ret < 0) {
  1329. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  1330. return ret;
  1331. }
  1332. /* enable interrupt source */
  1333. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
  1334. if (ret < 0) {
  1335. netdev_warn(dev->net, "Error reading PHY_INT_MASK\n");
  1336. return ret;
  1337. }
  1338. ret |= mask;
  1339. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
  1340. return 0;
  1341. }
  1342. static int smsc75xx_link_ok_nopm(struct usbnet *dev)
  1343. {
  1344. struct mii_if_info *mii = &dev->mii;
  1345. int ret;
  1346. /* first, a dummy read, needed to latch some MII phys */
  1347. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1348. if (ret < 0) {
  1349. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1350. return ret;
  1351. }
  1352. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1353. if (ret < 0) {
  1354. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1355. return ret;
  1356. }
  1357. return !!(ret & BMSR_LSTATUS);
  1358. }
  1359. static int smsc75xx_autosuspend(struct usbnet *dev, u32 link_up)
  1360. {
  1361. int ret;
  1362. if (!netif_running(dev->net)) {
  1363. /* interface is ifconfig down so fully power down hw */
  1364. netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
  1365. return smsc75xx_enter_suspend2(dev);
  1366. }
  1367. if (!link_up) {
  1368. /* link is down so enter EDPD mode */
  1369. netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
  1370. /* enable PHY wakeup events for if cable is attached */
  1371. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1372. PHY_INT_MASK_ANEG_COMP);
  1373. if (ret < 0) {
  1374. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1375. return ret;
  1376. }
  1377. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1378. return smsc75xx_enter_suspend1(dev);
  1379. }
  1380. /* enable PHY wakeup events so we remote wakeup if cable is pulled */
  1381. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1382. PHY_INT_MASK_LINK_DOWN);
  1383. if (ret < 0) {
  1384. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1385. return ret;
  1386. }
  1387. netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
  1388. return smsc75xx_enter_suspend3(dev);
  1389. }
  1390. static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message)
  1391. {
  1392. struct usbnet *dev = usb_get_intfdata(intf);
  1393. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1394. u32 val, link_up;
  1395. int ret;
  1396. ret = usbnet_suspend(intf, message);
  1397. if (ret < 0) {
  1398. netdev_warn(dev->net, "usbnet_suspend error\n");
  1399. return ret;
  1400. }
  1401. if (pdata->suspend_flags) {
  1402. netdev_warn(dev->net, "error during last resume\n");
  1403. pdata->suspend_flags = 0;
  1404. }
  1405. /* determine if link is up using only _nopm functions */
  1406. link_up = smsc75xx_link_ok_nopm(dev);
  1407. if (message.event == PM_EVENT_AUTO_SUSPEND) {
  1408. ret = smsc75xx_autosuspend(dev, link_up);
  1409. goto done;
  1410. }
  1411. /* if we get this far we're not autosuspending */
  1412. /* if no wol options set, or if link is down and we're not waking on
  1413. * PHY activity, enter lowest power SUSPEND2 mode
  1414. */
  1415. if (!(pdata->wolopts & SUPPORTED_WAKE) ||
  1416. !(link_up || (pdata->wolopts & WAKE_PHY))) {
  1417. netdev_info(dev->net, "entering SUSPEND2 mode\n");
  1418. /* disable energy detect (link up) & wake up events */
  1419. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1420. if (ret < 0) {
  1421. netdev_warn(dev->net, "Error reading WUCSR\n");
  1422. goto done;
  1423. }
  1424. val &= ~(WUCSR_MPEN | WUCSR_WUEN);
  1425. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1426. if (ret < 0) {
  1427. netdev_warn(dev->net, "Error writing WUCSR\n");
  1428. goto done;
  1429. }
  1430. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1431. if (ret < 0) {
  1432. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1433. goto done;
  1434. }
  1435. val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN);
  1436. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1437. if (ret < 0) {
  1438. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1439. goto done;
  1440. }
  1441. ret = smsc75xx_enter_suspend2(dev);
  1442. goto done;
  1443. }
  1444. if (pdata->wolopts & WAKE_PHY) {
  1445. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1446. (PHY_INT_MASK_ANEG_COMP | PHY_INT_MASK_LINK_DOWN));
  1447. if (ret < 0) {
  1448. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1449. goto done;
  1450. }
  1451. /* if link is down then configure EDPD and enter SUSPEND1,
  1452. * otherwise enter SUSPEND0 below
  1453. */
  1454. if (!link_up) {
  1455. struct mii_if_info *mii = &dev->mii;
  1456. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1457. /* enable energy detect power-down mode */
  1458. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
  1459. PHY_MODE_CTRL_STS);
  1460. if (ret < 0) {
  1461. netdev_warn(dev->net, "Error reading PHY_MODE_CTRL_STS\n");
  1462. goto done;
  1463. }
  1464. ret |= MODE_CTRL_STS_EDPWRDOWN;
  1465. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id,
  1466. PHY_MODE_CTRL_STS, ret);
  1467. /* enter SUSPEND1 mode */
  1468. ret = smsc75xx_enter_suspend1(dev);
  1469. goto done;
  1470. }
  1471. }
  1472. if (pdata->wolopts & (WAKE_MCAST | WAKE_ARP)) {
  1473. int i, filter = 0;
  1474. /* disable all filters */
  1475. for (i = 0; i < WUF_NUM; i++) {
  1476. ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
  1477. if (ret < 0) {
  1478. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1479. goto done;
  1480. }
  1481. }
  1482. if (pdata->wolopts & WAKE_MCAST) {
  1483. const u8 mcast[] = {0x01, 0x00, 0x5E};
  1484. netdev_info(dev->net, "enabling multicast detection\n");
  1485. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST
  1486. | smsc_crc(mcast, 3);
  1487. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
  1488. if (ret < 0) {
  1489. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1490. goto done;
  1491. }
  1492. }
  1493. if (pdata->wolopts & WAKE_ARP) {
  1494. const u8 arp[] = {0x08, 0x06};
  1495. netdev_info(dev->net, "enabling ARP detection\n");
  1496. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16)
  1497. | smsc_crc(arp, 2);
  1498. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
  1499. if (ret < 0) {
  1500. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1501. goto done;
  1502. }
  1503. }
  1504. /* clear any pending pattern match packet status */
  1505. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1506. if (ret < 0) {
  1507. netdev_warn(dev->net, "Error reading WUCSR\n");
  1508. goto done;
  1509. }
  1510. val |= WUCSR_WUFR;
  1511. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1512. if (ret < 0) {
  1513. netdev_warn(dev->net, "Error writing WUCSR\n");
  1514. goto done;
  1515. }
  1516. netdev_info(dev->net, "enabling packet match detection\n");
  1517. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1518. if (ret < 0) {
  1519. netdev_warn(dev->net, "Error reading WUCSR\n");
  1520. goto done;
  1521. }
  1522. val |= WUCSR_WUEN;
  1523. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1524. if (ret < 0) {
  1525. netdev_warn(dev->net, "Error writing WUCSR\n");
  1526. goto done;
  1527. }
  1528. } else {
  1529. netdev_info(dev->net, "disabling packet match detection\n");
  1530. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1531. if (ret < 0) {
  1532. netdev_warn(dev->net, "Error reading WUCSR\n");
  1533. goto done;
  1534. }
  1535. val &= ~WUCSR_WUEN;
  1536. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1537. if (ret < 0) {
  1538. netdev_warn(dev->net, "Error writing WUCSR\n");
  1539. goto done;
  1540. }
  1541. }
  1542. /* disable magic, bcast & unicast wakeup sources */
  1543. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1544. if (ret < 0) {
  1545. netdev_warn(dev->net, "Error reading WUCSR\n");
  1546. goto done;
  1547. }
  1548. val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN);
  1549. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1550. if (ret < 0) {
  1551. netdev_warn(dev->net, "Error writing WUCSR\n");
  1552. goto done;
  1553. }
  1554. if (pdata->wolopts & WAKE_PHY) {
  1555. netdev_info(dev->net, "enabling PHY wakeup\n");
  1556. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1557. if (ret < 0) {
  1558. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1559. goto done;
  1560. }
  1561. /* clear wol status, enable energy detection */
  1562. val &= ~PMT_CTL_WUPS;
  1563. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1564. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1565. if (ret < 0) {
  1566. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1567. goto done;
  1568. }
  1569. }
  1570. if (pdata->wolopts & WAKE_MAGIC) {
  1571. netdev_info(dev->net, "enabling magic packet wakeup\n");
  1572. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1573. if (ret < 0) {
  1574. netdev_warn(dev->net, "Error reading WUCSR\n");
  1575. goto done;
  1576. }
  1577. /* clear any pending magic packet status */
  1578. val |= WUCSR_MPR | WUCSR_MPEN;
  1579. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1580. if (ret < 0) {
  1581. netdev_warn(dev->net, "Error writing WUCSR\n");
  1582. goto done;
  1583. }
  1584. }
  1585. if (pdata->wolopts & WAKE_BCAST) {
  1586. netdev_info(dev->net, "enabling broadcast detection\n");
  1587. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1588. if (ret < 0) {
  1589. netdev_warn(dev->net, "Error reading WUCSR\n");
  1590. goto done;
  1591. }
  1592. val |= WUCSR_BCAST_FR | WUCSR_BCST_EN;
  1593. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1594. if (ret < 0) {
  1595. netdev_warn(dev->net, "Error writing WUCSR\n");
  1596. goto done;
  1597. }
  1598. }
  1599. if (pdata->wolopts & WAKE_UCAST) {
  1600. netdev_info(dev->net, "enabling unicast detection\n");
  1601. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1602. if (ret < 0) {
  1603. netdev_warn(dev->net, "Error reading WUCSR\n");
  1604. goto done;
  1605. }
  1606. val |= WUCSR_WUFR | WUCSR_PFDA_EN;
  1607. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1608. if (ret < 0) {
  1609. netdev_warn(dev->net, "Error writing WUCSR\n");
  1610. goto done;
  1611. }
  1612. }
  1613. /* enable receiver to enable frame reception */
  1614. ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
  1615. if (ret < 0) {
  1616. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1617. goto done;
  1618. }
  1619. val |= MAC_RX_RXEN;
  1620. ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
  1621. if (ret < 0) {
  1622. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1623. goto done;
  1624. }
  1625. /* some wol options are enabled, so enter SUSPEND0 */
  1626. netdev_info(dev->net, "entering SUSPEND0 mode\n");
  1627. ret = smsc75xx_enter_suspend0(dev);
  1628. done:
  1629. /*
  1630. * TODO: resume() might need to handle the suspend failure
  1631. * in system sleep
  1632. */
  1633. if (ret && PMSG_IS_AUTO(message))
  1634. usbnet_resume(intf);
  1635. return ret;
  1636. }
  1637. static int smsc75xx_resume(struct usb_interface *intf)
  1638. {
  1639. struct usbnet *dev = usb_get_intfdata(intf);
  1640. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1641. u8 suspend_flags = pdata->suspend_flags;
  1642. int ret;
  1643. u32 val;
  1644. netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
  1645. /* do this first to ensure it's cleared even in error case */
  1646. pdata->suspend_flags = 0;
  1647. if (suspend_flags & SUSPEND_ALLMODES) {
  1648. /* Disable wakeup sources */
  1649. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1650. if (ret < 0) {
  1651. netdev_warn(dev->net, "Error reading WUCSR\n");
  1652. return ret;
  1653. }
  1654. val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN
  1655. | WUCSR_BCST_EN);
  1656. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1657. if (ret < 0) {
  1658. netdev_warn(dev->net, "Error writing WUCSR\n");
  1659. return ret;
  1660. }
  1661. /* clear wake-up status */
  1662. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1663. if (ret < 0) {
  1664. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1665. return ret;
  1666. }
  1667. val &= ~PMT_CTL_WOL_EN;
  1668. val |= PMT_CTL_WUPS;
  1669. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1670. if (ret < 0) {
  1671. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1672. return ret;
  1673. }
  1674. }
  1675. if (suspend_flags & SUSPEND_SUSPEND2) {
  1676. netdev_info(dev->net, "resuming from SUSPEND2\n");
  1677. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1678. if (ret < 0) {
  1679. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1680. return ret;
  1681. }
  1682. val |= PMT_CTL_PHY_PWRUP;
  1683. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1684. if (ret < 0) {
  1685. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1686. return ret;
  1687. }
  1688. }
  1689. ret = smsc75xx_wait_ready(dev, 1);
  1690. if (ret < 0) {
  1691. netdev_warn(dev->net, "device not ready in smsc75xx_resume\n");
  1692. return ret;
  1693. }
  1694. return usbnet_resume(intf);
  1695. }
  1696. static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
  1697. u32 rx_cmd_a, u32 rx_cmd_b)
  1698. {
  1699. if (!(dev->net->features & NETIF_F_RXCSUM) ||
  1700. unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
  1701. skb->ip_summed = CHECKSUM_NONE;
  1702. } else {
  1703. skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
  1704. skb->ip_summed = CHECKSUM_COMPLETE;
  1705. }
  1706. }
  1707. static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  1708. {
  1709. /* This check is no longer done by usbnet */
  1710. if (skb->len < dev->net->hard_header_len)
  1711. return 0;
  1712. while (skb->len > 0) {
  1713. u32 rx_cmd_a, rx_cmd_b, align_count, size;
  1714. struct sk_buff *ax_skb;
  1715. unsigned char *packet;
  1716. memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
  1717. le32_to_cpus(&rx_cmd_a);
  1718. skb_pull(skb, 4);
  1719. memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
  1720. le32_to_cpus(&rx_cmd_b);
  1721. skb_pull(skb, 4 + RXW_PADDING);
  1722. packet = skb->data;
  1723. /* get the packet length */
  1724. size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
  1725. align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
  1726. if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
  1727. netif_dbg(dev, rx_err, dev->net,
  1728. "Error rx_cmd_a=0x%08x\n", rx_cmd_a);
  1729. dev->net->stats.rx_errors++;
  1730. dev->net->stats.rx_dropped++;
  1731. if (rx_cmd_a & RX_CMD_A_FCS)
  1732. dev->net->stats.rx_crc_errors++;
  1733. else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
  1734. dev->net->stats.rx_frame_errors++;
  1735. } else {
  1736. /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */
  1737. if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) {
  1738. netif_dbg(dev, rx_err, dev->net,
  1739. "size err rx_cmd_a=0x%08x\n",
  1740. rx_cmd_a);
  1741. return 0;
  1742. }
  1743. /* last frame in this batch */
  1744. if (skb->len == size) {
  1745. smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
  1746. rx_cmd_b);
  1747. skb_trim(skb, skb->len - 4); /* remove fcs */
  1748. skb->truesize = size + sizeof(struct sk_buff);
  1749. return 1;
  1750. }
  1751. ax_skb = skb_clone(skb, GFP_ATOMIC);
  1752. if (unlikely(!ax_skb)) {
  1753. netdev_warn(dev->net, "Error allocating skb\n");
  1754. return 0;
  1755. }
  1756. ax_skb->len = size;
  1757. ax_skb->data = packet;
  1758. skb_set_tail_pointer(ax_skb, size);
  1759. smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
  1760. rx_cmd_b);
  1761. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  1762. ax_skb->truesize = size + sizeof(struct sk_buff);
  1763. usbnet_skb_return(dev, ax_skb);
  1764. }
  1765. skb_pull(skb, size);
  1766. /* padding bytes before the next frame starts */
  1767. if (skb->len)
  1768. skb_pull(skb, align_count);
  1769. }
  1770. return 1;
  1771. }
  1772. static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
  1773. struct sk_buff *skb, gfp_t flags)
  1774. {
  1775. u32 tx_cmd_a, tx_cmd_b;
  1776. if (skb_headroom(skb) < SMSC75XX_TX_OVERHEAD) {
  1777. struct sk_buff *skb2 =
  1778. skb_copy_expand(skb, SMSC75XX_TX_OVERHEAD, 0, flags);
  1779. dev_kfree_skb_any(skb);
  1780. skb = skb2;
  1781. if (!skb)
  1782. return NULL;
  1783. }
  1784. tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
  1785. if (skb->ip_summed == CHECKSUM_PARTIAL)
  1786. tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
  1787. if (skb_is_gso(skb)) {
  1788. u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
  1789. tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
  1790. tx_cmd_a |= TX_CMD_A_LSO;
  1791. } else {
  1792. tx_cmd_b = 0;
  1793. }
  1794. skb_push(skb, 4);
  1795. cpu_to_le32s(&tx_cmd_b);
  1796. memcpy(skb->data, &tx_cmd_b, 4);
  1797. skb_push(skb, 4);
  1798. cpu_to_le32s(&tx_cmd_a);
  1799. memcpy(skb->data, &tx_cmd_a, 4);
  1800. return skb;
  1801. }
  1802. static int smsc75xx_manage_power(struct usbnet *dev, int on)
  1803. {
  1804. dev->intf->needs_remote_wakeup = on;
  1805. return 0;
  1806. }
  1807. static const struct driver_info smsc75xx_info = {
  1808. .description = "smsc75xx USB 2.0 Gigabit Ethernet",
  1809. .bind = smsc75xx_bind,
  1810. .unbind = smsc75xx_unbind,
  1811. .link_reset = smsc75xx_link_reset,
  1812. .reset = smsc75xx_reset,
  1813. .rx_fixup = smsc75xx_rx_fixup,
  1814. .tx_fixup = smsc75xx_tx_fixup,
  1815. .status = smsc75xx_status,
  1816. .manage_power = smsc75xx_manage_power,
  1817. .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
  1818. };
  1819. static const struct usb_device_id products[] = {
  1820. {
  1821. /* SMSC7500 USB Gigabit Ethernet Device */
  1822. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
  1823. .driver_info = (unsigned long) &smsc75xx_info,
  1824. },
  1825. {
  1826. /* SMSC7500 USB Gigabit Ethernet Device */
  1827. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
  1828. .driver_info = (unsigned long) &smsc75xx_info,
  1829. },
  1830. { }, /* END */
  1831. };
  1832. MODULE_DEVICE_TABLE(usb, products);
  1833. static struct usb_driver smsc75xx_driver = {
  1834. .name = SMSC_CHIPNAME,
  1835. .id_table = products,
  1836. .probe = usbnet_probe,
  1837. .suspend = smsc75xx_suspend,
  1838. .resume = smsc75xx_resume,
  1839. .reset_resume = smsc75xx_resume,
  1840. .disconnect = usbnet_disconnect,
  1841. .disable_hub_initiated_lpm = 1,
  1842. .supports_autosuspend = 1,
  1843. };
  1844. module_usb_driver(smsc75xx_driver);
  1845. MODULE_AUTHOR("Nancy Lin");
  1846. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
  1847. MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
  1848. MODULE_LICENSE("GPL");