netcp_ethss.c 104 KB

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  1. /*
  2. * Keystone GBE and XGBE subsystem code
  3. *
  4. * Copyright (C) 2014 Texas Instruments Incorporated
  5. * Authors: Sandeep Nair <sandeep_n@ti.com>
  6. * Sandeep Paulraj <s-paulraj@ti.com>
  7. * Cyril Chemparathy <cyril@ti.com>
  8. * Santosh Shilimkar <santosh.shilimkar@ti.com>
  9. * Wingman Kwok <w-kwok2@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation version 2.
  14. *
  15. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  16. * kind, whether express or implied; without even the implied warranty
  17. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. */
  20. #include <linux/io.h>
  21. #include <linux/module.h>
  22. #include <linux/of_mdio.h>
  23. #include <linux/of_address.h>
  24. #include <linux/if_vlan.h>
  25. #include <linux/ptp_classify.h>
  26. #include <linux/net_tstamp.h>
  27. #include <linux/ethtool.h>
  28. #include "cpsw_ale.h"
  29. #include "netcp.h"
  30. #include "cpts.h"
  31. #define NETCP_DRIVER_NAME "TI KeyStone Ethernet Driver"
  32. #define NETCP_DRIVER_VERSION "v1.0"
  33. #define GBE_IDENT(reg) ((reg >> 16) & 0xffff)
  34. #define GBE_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
  35. #define GBE_MINOR_VERSION(reg) (reg & 0xff)
  36. #define GBE_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
  37. /* 1G Ethernet SS defines */
  38. #define GBE_MODULE_NAME "netcp-gbe"
  39. #define GBE_SS_VERSION_14 0x4ed21104
  40. #define GBE_SS_REG_INDEX 0
  41. #define GBE_SGMII34_REG_INDEX 1
  42. #define GBE_SM_REG_INDEX 2
  43. /* offset relative to base of GBE_SS_REG_INDEX */
  44. #define GBE13_SGMII_MODULE_OFFSET 0x100
  45. /* offset relative to base of GBE_SM_REG_INDEX */
  46. #define GBE13_HOST_PORT_OFFSET 0x34
  47. #define GBE13_SLAVE_PORT_OFFSET 0x60
  48. #define GBE13_EMAC_OFFSET 0x100
  49. #define GBE13_SLAVE_PORT2_OFFSET 0x200
  50. #define GBE13_HW_STATS_OFFSET 0x300
  51. #define GBE13_CPTS_OFFSET 0x500
  52. #define GBE13_ALE_OFFSET 0x600
  53. #define GBE13_HOST_PORT_NUM 0
  54. #define GBE13_NUM_ALE_ENTRIES 1024
  55. /* 1G Ethernet NU SS defines */
  56. #define GBENU_MODULE_NAME "netcp-gbenu"
  57. #define GBE_SS_ID_NU 0x4ee6
  58. #define GBE_SS_ID_2U 0x4ee8
  59. #define IS_SS_ID_MU(d) \
  60. ((GBE_IDENT((d)->ss_version) == GBE_SS_ID_NU) || \
  61. (GBE_IDENT((d)->ss_version) == GBE_SS_ID_2U))
  62. #define IS_SS_ID_NU(d) \
  63. (GBE_IDENT((d)->ss_version) == GBE_SS_ID_NU)
  64. #define GBENU_SS_REG_INDEX 0
  65. #define GBENU_SM_REG_INDEX 1
  66. #define GBENU_SGMII_MODULE_OFFSET 0x100
  67. #define GBENU_HOST_PORT_OFFSET 0x1000
  68. #define GBENU_SLAVE_PORT_OFFSET 0x2000
  69. #define GBENU_EMAC_OFFSET 0x2330
  70. #define GBENU_HW_STATS_OFFSET 0x1a000
  71. #define GBENU_CPTS_OFFSET 0x1d000
  72. #define GBENU_ALE_OFFSET 0x1e000
  73. #define GBENU_HOST_PORT_NUM 0
  74. #define GBENU_NUM_ALE_ENTRIES 1024
  75. #define GBENU_SGMII_MODULE_SIZE 0x100
  76. /* 10G Ethernet SS defines */
  77. #define XGBE_MODULE_NAME "netcp-xgbe"
  78. #define XGBE_SS_VERSION_10 0x4ee42100
  79. #define XGBE_SS_REG_INDEX 0
  80. #define XGBE_SM_REG_INDEX 1
  81. #define XGBE_SERDES_REG_INDEX 2
  82. /* offset relative to base of XGBE_SS_REG_INDEX */
  83. #define XGBE10_SGMII_MODULE_OFFSET 0x100
  84. #define IS_SS_ID_XGBE(d) ((d)->ss_version == XGBE_SS_VERSION_10)
  85. /* offset relative to base of XGBE_SM_REG_INDEX */
  86. #define XGBE10_HOST_PORT_OFFSET 0x34
  87. #define XGBE10_SLAVE_PORT_OFFSET 0x64
  88. #define XGBE10_EMAC_OFFSET 0x400
  89. #define XGBE10_CPTS_OFFSET 0x600
  90. #define XGBE10_ALE_OFFSET 0x700
  91. #define XGBE10_HW_STATS_OFFSET 0x800
  92. #define XGBE10_HOST_PORT_NUM 0
  93. #define XGBE10_NUM_ALE_ENTRIES 1024
  94. #define GBE_TIMER_INTERVAL (HZ / 2)
  95. /* Soft reset register values */
  96. #define SOFT_RESET_MASK BIT(0)
  97. #define SOFT_RESET BIT(0)
  98. #define DEVICE_EMACSL_RESET_POLL_COUNT 100
  99. #define GMACSL_RET_WARN_RESET_INCOMPLETE -2
  100. #define MACSL_RX_ENABLE_CSF BIT(23)
  101. #define MACSL_ENABLE_EXT_CTL BIT(18)
  102. #define MACSL_XGMII_ENABLE BIT(13)
  103. #define MACSL_XGIG_MODE BIT(8)
  104. #define MACSL_GIG_MODE BIT(7)
  105. #define MACSL_GMII_ENABLE BIT(5)
  106. #define MACSL_FULLDUPLEX BIT(0)
  107. #define GBE_CTL_P0_ENABLE BIT(2)
  108. #define GBE13_REG_VAL_STAT_ENABLE_ALL 0xff
  109. #define XGBE_REG_VAL_STAT_ENABLE_ALL 0xf
  110. #define GBE_STATS_CD_SEL BIT(28)
  111. #define GBE_PORT_MASK(x) (BIT(x) - 1)
  112. #define GBE_MASK_NO_PORTS 0
  113. #define GBE_DEF_1G_MAC_CONTROL \
  114. (MACSL_GIG_MODE | MACSL_GMII_ENABLE | \
  115. MACSL_ENABLE_EXT_CTL | MACSL_RX_ENABLE_CSF)
  116. #define GBE_DEF_10G_MAC_CONTROL \
  117. (MACSL_XGIG_MODE | MACSL_XGMII_ENABLE | \
  118. MACSL_ENABLE_EXT_CTL | MACSL_RX_ENABLE_CSF)
  119. #define GBE_STATSA_MODULE 0
  120. #define GBE_STATSB_MODULE 1
  121. #define GBE_STATSC_MODULE 2
  122. #define GBE_STATSD_MODULE 3
  123. #define GBENU_STATS0_MODULE 0
  124. #define GBENU_STATS1_MODULE 1
  125. #define GBENU_STATS2_MODULE 2
  126. #define GBENU_STATS3_MODULE 3
  127. #define GBENU_STATS4_MODULE 4
  128. #define GBENU_STATS5_MODULE 5
  129. #define GBENU_STATS6_MODULE 6
  130. #define GBENU_STATS7_MODULE 7
  131. #define GBENU_STATS8_MODULE 8
  132. #define XGBE_STATS0_MODULE 0
  133. #define XGBE_STATS1_MODULE 1
  134. #define XGBE_STATS2_MODULE 2
  135. /* s: 0-based slave_port */
  136. #define SGMII_BASE(d, s) \
  137. (((s) < 2) ? (d)->sgmii_port_regs : (d)->sgmii_port34_regs)
  138. #define GBE_TX_QUEUE 648
  139. #define GBE_TXHOOK_ORDER 0
  140. #define GBE_RXHOOK_ORDER 0
  141. #define GBE_DEFAULT_ALE_AGEOUT 30
  142. #define SLAVE_LINK_IS_XGMII(s) ((s)->link_interface >= XGMII_LINK_MAC_PHY)
  143. #define NETCP_LINK_STATE_INVALID -1
  144. #define GBE_SET_REG_OFS(p, rb, rn) p->rb##_ofs.rn = \
  145. offsetof(struct gbe##_##rb, rn)
  146. #define GBENU_SET_REG_OFS(p, rb, rn) p->rb##_ofs.rn = \
  147. offsetof(struct gbenu##_##rb, rn)
  148. #define XGBE_SET_REG_OFS(p, rb, rn) p->rb##_ofs.rn = \
  149. offsetof(struct xgbe##_##rb, rn)
  150. #define GBE_REG_ADDR(p, rb, rn) (p->rb + p->rb##_ofs.rn)
  151. #define HOST_TX_PRI_MAP_DEFAULT 0x00000000
  152. #if IS_ENABLED(CONFIG_TI_CPTS)
  153. /* Px_TS_CTL register fields */
  154. #define TS_RX_ANX_F_EN BIT(0)
  155. #define TS_RX_VLAN_LT1_EN BIT(1)
  156. #define TS_RX_VLAN_LT2_EN BIT(2)
  157. #define TS_RX_ANX_D_EN BIT(3)
  158. #define TS_TX_ANX_F_EN BIT(4)
  159. #define TS_TX_VLAN_LT1_EN BIT(5)
  160. #define TS_TX_VLAN_LT2_EN BIT(6)
  161. #define TS_TX_ANX_D_EN BIT(7)
  162. #define TS_LT2_EN BIT(8)
  163. #define TS_RX_ANX_E_EN BIT(9)
  164. #define TS_TX_ANX_E_EN BIT(10)
  165. #define TS_MSG_TYPE_EN_SHIFT 16
  166. #define TS_MSG_TYPE_EN_MASK 0xffff
  167. /* Px_TS_SEQ_LTYPE register fields */
  168. #define TS_SEQ_ID_OFS_SHIFT 16
  169. #define TS_SEQ_ID_OFS_MASK 0x3f
  170. /* Px_TS_CTL_LTYPE2 register fields */
  171. #define TS_107 BIT(16)
  172. #define TS_129 BIT(17)
  173. #define TS_130 BIT(18)
  174. #define TS_131 BIT(19)
  175. #define TS_132 BIT(20)
  176. #define TS_319 BIT(21)
  177. #define TS_320 BIT(22)
  178. #define TS_TTL_NONZERO BIT(23)
  179. #define TS_UNI_EN BIT(24)
  180. #define TS_UNI_EN_SHIFT 24
  181. #define TS_TX_ANX_ALL_EN \
  182. (TS_TX_ANX_D_EN | TS_TX_ANX_E_EN | TS_TX_ANX_F_EN)
  183. #define TS_RX_ANX_ALL_EN \
  184. (TS_RX_ANX_D_EN | TS_RX_ANX_E_EN | TS_RX_ANX_F_EN)
  185. #define TS_CTL_DST_PORT TS_319
  186. #define TS_CTL_DST_PORT_SHIFT 21
  187. #define TS_CTL_MADDR_ALL \
  188. (TS_107 | TS_129 | TS_130 | TS_131 | TS_132)
  189. #define TS_CTL_MADDR_SHIFT 16
  190. /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
  191. #define EVENT_MSG_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3))
  192. #endif /* CONFIG_TI_CPTS */
  193. struct xgbe_ss_regs {
  194. u32 id_ver;
  195. u32 synce_count;
  196. u32 synce_mux;
  197. u32 control;
  198. };
  199. struct xgbe_switch_regs {
  200. u32 id_ver;
  201. u32 control;
  202. u32 emcontrol;
  203. u32 stat_port_en;
  204. u32 ptype;
  205. u32 soft_idle;
  206. u32 thru_rate;
  207. u32 gap_thresh;
  208. u32 tx_start_wds;
  209. u32 flow_control;
  210. u32 cppi_thresh;
  211. };
  212. struct xgbe_port_regs {
  213. u32 blk_cnt;
  214. u32 port_vlan;
  215. u32 tx_pri_map;
  216. u32 sa_lo;
  217. u32 sa_hi;
  218. u32 ts_ctl;
  219. u32 ts_seq_ltype;
  220. u32 ts_vlan;
  221. u32 ts_ctl_ltype2;
  222. u32 ts_ctl2;
  223. u32 control;
  224. };
  225. struct xgbe_host_port_regs {
  226. u32 blk_cnt;
  227. u32 port_vlan;
  228. u32 tx_pri_map;
  229. u32 src_id;
  230. u32 rx_pri_map;
  231. u32 rx_maxlen;
  232. };
  233. struct xgbe_emac_regs {
  234. u32 id_ver;
  235. u32 mac_control;
  236. u32 mac_status;
  237. u32 soft_reset;
  238. u32 rx_maxlen;
  239. u32 __reserved_0;
  240. u32 rx_pause;
  241. u32 tx_pause;
  242. u32 em_control;
  243. u32 __reserved_1;
  244. u32 tx_gap;
  245. u32 rsvd[4];
  246. };
  247. struct xgbe_host_hw_stats {
  248. u32 rx_good_frames;
  249. u32 rx_broadcast_frames;
  250. u32 rx_multicast_frames;
  251. u32 __rsvd_0[3];
  252. u32 rx_oversized_frames;
  253. u32 __rsvd_1;
  254. u32 rx_undersized_frames;
  255. u32 __rsvd_2;
  256. u32 overrun_type4;
  257. u32 overrun_type5;
  258. u32 rx_bytes;
  259. u32 tx_good_frames;
  260. u32 tx_broadcast_frames;
  261. u32 tx_multicast_frames;
  262. u32 __rsvd_3[9];
  263. u32 tx_bytes;
  264. u32 tx_64byte_frames;
  265. u32 tx_65_to_127byte_frames;
  266. u32 tx_128_to_255byte_frames;
  267. u32 tx_256_to_511byte_frames;
  268. u32 tx_512_to_1023byte_frames;
  269. u32 tx_1024byte_frames;
  270. u32 net_bytes;
  271. u32 rx_sof_overruns;
  272. u32 rx_mof_overruns;
  273. u32 rx_dma_overruns;
  274. };
  275. struct xgbe_hw_stats {
  276. u32 rx_good_frames;
  277. u32 rx_broadcast_frames;
  278. u32 rx_multicast_frames;
  279. u32 rx_pause_frames;
  280. u32 rx_crc_errors;
  281. u32 rx_align_code_errors;
  282. u32 rx_oversized_frames;
  283. u32 rx_jabber_frames;
  284. u32 rx_undersized_frames;
  285. u32 rx_fragments;
  286. u32 overrun_type4;
  287. u32 overrun_type5;
  288. u32 rx_bytes;
  289. u32 tx_good_frames;
  290. u32 tx_broadcast_frames;
  291. u32 tx_multicast_frames;
  292. u32 tx_pause_frames;
  293. u32 tx_deferred_frames;
  294. u32 tx_collision_frames;
  295. u32 tx_single_coll_frames;
  296. u32 tx_mult_coll_frames;
  297. u32 tx_excessive_collisions;
  298. u32 tx_late_collisions;
  299. u32 tx_underrun;
  300. u32 tx_carrier_sense_errors;
  301. u32 tx_bytes;
  302. u32 tx_64byte_frames;
  303. u32 tx_65_to_127byte_frames;
  304. u32 tx_128_to_255byte_frames;
  305. u32 tx_256_to_511byte_frames;
  306. u32 tx_512_to_1023byte_frames;
  307. u32 tx_1024byte_frames;
  308. u32 net_bytes;
  309. u32 rx_sof_overruns;
  310. u32 rx_mof_overruns;
  311. u32 rx_dma_overruns;
  312. };
  313. struct gbenu_ss_regs {
  314. u32 id_ver;
  315. u32 synce_count; /* NU */
  316. u32 synce_mux; /* NU */
  317. u32 control; /* 2U */
  318. u32 __rsvd_0[2]; /* 2U */
  319. u32 rgmii_status; /* 2U */
  320. u32 ss_status; /* 2U */
  321. };
  322. struct gbenu_switch_regs {
  323. u32 id_ver;
  324. u32 control;
  325. u32 __rsvd_0[2];
  326. u32 emcontrol;
  327. u32 stat_port_en;
  328. u32 ptype; /* NU */
  329. u32 soft_idle;
  330. u32 thru_rate; /* NU */
  331. u32 gap_thresh; /* NU */
  332. u32 tx_start_wds; /* NU */
  333. u32 eee_prescale; /* 2U */
  334. u32 tx_g_oflow_thresh_set; /* NU */
  335. u32 tx_g_oflow_thresh_clr; /* NU */
  336. u32 tx_g_buf_thresh_set_l; /* NU */
  337. u32 tx_g_buf_thresh_set_h; /* NU */
  338. u32 tx_g_buf_thresh_clr_l; /* NU */
  339. u32 tx_g_buf_thresh_clr_h; /* NU */
  340. };
  341. struct gbenu_port_regs {
  342. u32 __rsvd_0;
  343. u32 control;
  344. u32 max_blks; /* 2U */
  345. u32 mem_align1;
  346. u32 blk_cnt;
  347. u32 port_vlan;
  348. u32 tx_pri_map; /* NU */
  349. u32 pri_ctl; /* 2U */
  350. u32 rx_pri_map;
  351. u32 rx_maxlen;
  352. u32 tx_blks_pri; /* NU */
  353. u32 __rsvd_1;
  354. u32 idle2lpi; /* 2U */
  355. u32 lpi2idle; /* 2U */
  356. u32 eee_status; /* 2U */
  357. u32 __rsvd_2;
  358. u32 __rsvd_3[176]; /* NU: more to add */
  359. u32 __rsvd_4[2];
  360. u32 sa_lo;
  361. u32 sa_hi;
  362. u32 ts_ctl;
  363. u32 ts_seq_ltype;
  364. u32 ts_vlan;
  365. u32 ts_ctl_ltype2;
  366. u32 ts_ctl2;
  367. };
  368. struct gbenu_host_port_regs {
  369. u32 __rsvd_0;
  370. u32 control;
  371. u32 flow_id_offset; /* 2U */
  372. u32 __rsvd_1;
  373. u32 blk_cnt;
  374. u32 port_vlan;
  375. u32 tx_pri_map; /* NU */
  376. u32 pri_ctl;
  377. u32 rx_pri_map;
  378. u32 rx_maxlen;
  379. u32 tx_blks_pri; /* NU */
  380. u32 __rsvd_2;
  381. u32 idle2lpi; /* 2U */
  382. u32 lpi2wake; /* 2U */
  383. u32 eee_status; /* 2U */
  384. u32 __rsvd_3;
  385. u32 __rsvd_4[184]; /* NU */
  386. u32 host_blks_pri; /* NU */
  387. };
  388. struct gbenu_emac_regs {
  389. u32 mac_control;
  390. u32 mac_status;
  391. u32 soft_reset;
  392. u32 boff_test;
  393. u32 rx_pause;
  394. u32 __rsvd_0[11]; /* NU */
  395. u32 tx_pause;
  396. u32 __rsvd_1[11]; /* NU */
  397. u32 em_control;
  398. u32 tx_gap;
  399. };
  400. /* Some hw stat regs are applicable to slave port only.
  401. * This is handled by gbenu_et_stats struct. Also some
  402. * are for SS version NU and some are for 2U.
  403. */
  404. struct gbenu_hw_stats {
  405. u32 rx_good_frames;
  406. u32 rx_broadcast_frames;
  407. u32 rx_multicast_frames;
  408. u32 rx_pause_frames; /* slave */
  409. u32 rx_crc_errors;
  410. u32 rx_align_code_errors; /* slave */
  411. u32 rx_oversized_frames;
  412. u32 rx_jabber_frames; /* slave */
  413. u32 rx_undersized_frames;
  414. u32 rx_fragments; /* slave */
  415. u32 ale_drop;
  416. u32 ale_overrun_drop;
  417. u32 rx_bytes;
  418. u32 tx_good_frames;
  419. u32 tx_broadcast_frames;
  420. u32 tx_multicast_frames;
  421. u32 tx_pause_frames; /* slave */
  422. u32 tx_deferred_frames; /* slave */
  423. u32 tx_collision_frames; /* slave */
  424. u32 tx_single_coll_frames; /* slave */
  425. u32 tx_mult_coll_frames; /* slave */
  426. u32 tx_excessive_collisions; /* slave */
  427. u32 tx_late_collisions; /* slave */
  428. u32 rx_ipg_error; /* slave 10G only */
  429. u32 tx_carrier_sense_errors; /* slave */
  430. u32 tx_bytes;
  431. u32 tx_64B_frames;
  432. u32 tx_65_to_127B_frames;
  433. u32 tx_128_to_255B_frames;
  434. u32 tx_256_to_511B_frames;
  435. u32 tx_512_to_1023B_frames;
  436. u32 tx_1024B_frames;
  437. u32 net_bytes;
  438. u32 rx_bottom_fifo_drop;
  439. u32 rx_port_mask_drop;
  440. u32 rx_top_fifo_drop;
  441. u32 ale_rate_limit_drop;
  442. u32 ale_vid_ingress_drop;
  443. u32 ale_da_eq_sa_drop;
  444. u32 __rsvd_0[3];
  445. u32 ale_unknown_ucast;
  446. u32 ale_unknown_ucast_bytes;
  447. u32 ale_unknown_mcast;
  448. u32 ale_unknown_mcast_bytes;
  449. u32 ale_unknown_bcast;
  450. u32 ale_unknown_bcast_bytes;
  451. u32 ale_pol_match;
  452. u32 ale_pol_match_red; /* NU */
  453. u32 ale_pol_match_yellow; /* NU */
  454. u32 __rsvd_1[44];
  455. u32 tx_mem_protect_err;
  456. /* following NU only */
  457. u32 tx_pri0;
  458. u32 tx_pri1;
  459. u32 tx_pri2;
  460. u32 tx_pri3;
  461. u32 tx_pri4;
  462. u32 tx_pri5;
  463. u32 tx_pri6;
  464. u32 tx_pri7;
  465. u32 tx_pri0_bcnt;
  466. u32 tx_pri1_bcnt;
  467. u32 tx_pri2_bcnt;
  468. u32 tx_pri3_bcnt;
  469. u32 tx_pri4_bcnt;
  470. u32 tx_pri5_bcnt;
  471. u32 tx_pri6_bcnt;
  472. u32 tx_pri7_bcnt;
  473. u32 tx_pri0_drop;
  474. u32 tx_pri1_drop;
  475. u32 tx_pri2_drop;
  476. u32 tx_pri3_drop;
  477. u32 tx_pri4_drop;
  478. u32 tx_pri5_drop;
  479. u32 tx_pri6_drop;
  480. u32 tx_pri7_drop;
  481. u32 tx_pri0_drop_bcnt;
  482. u32 tx_pri1_drop_bcnt;
  483. u32 tx_pri2_drop_bcnt;
  484. u32 tx_pri3_drop_bcnt;
  485. u32 tx_pri4_drop_bcnt;
  486. u32 tx_pri5_drop_bcnt;
  487. u32 tx_pri6_drop_bcnt;
  488. u32 tx_pri7_drop_bcnt;
  489. };
  490. #define GBENU_HW_STATS_REG_MAP_SZ 0x200
  491. struct gbe_ss_regs {
  492. u32 id_ver;
  493. u32 synce_count;
  494. u32 synce_mux;
  495. };
  496. struct gbe_ss_regs_ofs {
  497. u16 id_ver;
  498. u16 control;
  499. };
  500. struct gbe_switch_regs {
  501. u32 id_ver;
  502. u32 control;
  503. u32 soft_reset;
  504. u32 stat_port_en;
  505. u32 ptype;
  506. u32 soft_idle;
  507. u32 thru_rate;
  508. u32 gap_thresh;
  509. u32 tx_start_wds;
  510. u32 flow_control;
  511. };
  512. struct gbe_switch_regs_ofs {
  513. u16 id_ver;
  514. u16 control;
  515. u16 soft_reset;
  516. u16 emcontrol;
  517. u16 stat_port_en;
  518. u16 ptype;
  519. u16 flow_control;
  520. };
  521. struct gbe_port_regs {
  522. u32 max_blks;
  523. u32 blk_cnt;
  524. u32 port_vlan;
  525. u32 tx_pri_map;
  526. u32 sa_lo;
  527. u32 sa_hi;
  528. u32 ts_ctl;
  529. u32 ts_seq_ltype;
  530. u32 ts_vlan;
  531. u32 ts_ctl_ltype2;
  532. u32 ts_ctl2;
  533. };
  534. struct gbe_port_regs_ofs {
  535. u16 port_vlan;
  536. u16 tx_pri_map;
  537. u16 sa_lo;
  538. u16 sa_hi;
  539. u16 ts_ctl;
  540. u16 ts_seq_ltype;
  541. u16 ts_vlan;
  542. u16 ts_ctl_ltype2;
  543. u16 ts_ctl2;
  544. u16 rx_maxlen; /* 2U, NU */
  545. };
  546. struct gbe_host_port_regs {
  547. u32 src_id;
  548. u32 port_vlan;
  549. u32 rx_pri_map;
  550. u32 rx_maxlen;
  551. };
  552. struct gbe_host_port_regs_ofs {
  553. u16 port_vlan;
  554. u16 tx_pri_map;
  555. u16 rx_maxlen;
  556. };
  557. struct gbe_emac_regs {
  558. u32 id_ver;
  559. u32 mac_control;
  560. u32 mac_status;
  561. u32 soft_reset;
  562. u32 rx_maxlen;
  563. u32 __reserved_0;
  564. u32 rx_pause;
  565. u32 tx_pause;
  566. u32 __reserved_1;
  567. u32 rx_pri_map;
  568. u32 rsvd[6];
  569. };
  570. struct gbe_emac_regs_ofs {
  571. u16 mac_control;
  572. u16 soft_reset;
  573. u16 rx_maxlen;
  574. };
  575. struct gbe_hw_stats {
  576. u32 rx_good_frames;
  577. u32 rx_broadcast_frames;
  578. u32 rx_multicast_frames;
  579. u32 rx_pause_frames;
  580. u32 rx_crc_errors;
  581. u32 rx_align_code_errors;
  582. u32 rx_oversized_frames;
  583. u32 rx_jabber_frames;
  584. u32 rx_undersized_frames;
  585. u32 rx_fragments;
  586. u32 __pad_0[2];
  587. u32 rx_bytes;
  588. u32 tx_good_frames;
  589. u32 tx_broadcast_frames;
  590. u32 tx_multicast_frames;
  591. u32 tx_pause_frames;
  592. u32 tx_deferred_frames;
  593. u32 tx_collision_frames;
  594. u32 tx_single_coll_frames;
  595. u32 tx_mult_coll_frames;
  596. u32 tx_excessive_collisions;
  597. u32 tx_late_collisions;
  598. u32 tx_underrun;
  599. u32 tx_carrier_sense_errors;
  600. u32 tx_bytes;
  601. u32 tx_64byte_frames;
  602. u32 tx_65_to_127byte_frames;
  603. u32 tx_128_to_255byte_frames;
  604. u32 tx_256_to_511byte_frames;
  605. u32 tx_512_to_1023byte_frames;
  606. u32 tx_1024byte_frames;
  607. u32 net_bytes;
  608. u32 rx_sof_overruns;
  609. u32 rx_mof_overruns;
  610. u32 rx_dma_overruns;
  611. };
  612. #define GBE_MAX_HW_STAT_MODS 9
  613. #define GBE_HW_STATS_REG_MAP_SZ 0x100
  614. struct ts_ctl {
  615. int uni;
  616. u8 dst_port_map;
  617. u8 maddr_map;
  618. u8 ts_mcast_type;
  619. };
  620. struct gbe_slave {
  621. void __iomem *port_regs;
  622. void __iomem *emac_regs;
  623. struct gbe_port_regs_ofs port_regs_ofs;
  624. struct gbe_emac_regs_ofs emac_regs_ofs;
  625. int slave_num; /* 0 based logical number */
  626. int port_num; /* actual port number */
  627. atomic_t link_state;
  628. bool open;
  629. struct phy_device *phy;
  630. u32 link_interface;
  631. u32 mac_control;
  632. u8 phy_port_t;
  633. struct device_node *phy_node;
  634. struct ts_ctl ts_ctl;
  635. struct list_head slave_list;
  636. };
  637. struct gbe_priv {
  638. struct device *dev;
  639. struct netcp_device *netcp_device;
  640. struct timer_list timer;
  641. u32 num_slaves;
  642. u32 ale_entries;
  643. u32 ale_ports;
  644. bool enable_ale;
  645. u8 max_num_slaves;
  646. u8 max_num_ports; /* max_num_slaves + 1 */
  647. u8 num_stats_mods;
  648. struct netcp_tx_pipe tx_pipe;
  649. int host_port;
  650. u32 rx_packet_max;
  651. u32 ss_version;
  652. u32 stats_en_mask;
  653. void __iomem *ss_regs;
  654. void __iomem *switch_regs;
  655. void __iomem *host_port_regs;
  656. void __iomem *ale_reg;
  657. void __iomem *cpts_reg;
  658. void __iomem *sgmii_port_regs;
  659. void __iomem *sgmii_port34_regs;
  660. void __iomem *xgbe_serdes_regs;
  661. void __iomem *hw_stats_regs[GBE_MAX_HW_STAT_MODS];
  662. struct gbe_ss_regs_ofs ss_regs_ofs;
  663. struct gbe_switch_regs_ofs switch_regs_ofs;
  664. struct gbe_host_port_regs_ofs host_port_regs_ofs;
  665. struct cpsw_ale *ale;
  666. unsigned int tx_queue_id;
  667. const char *dma_chan_name;
  668. struct list_head gbe_intf_head;
  669. struct list_head secondary_slaves;
  670. struct net_device *dummy_ndev;
  671. u64 *hw_stats;
  672. u32 *hw_stats_prev;
  673. const struct netcp_ethtool_stat *et_stats;
  674. int num_et_stats;
  675. /* Lock for updating the hwstats */
  676. spinlock_t hw_stats_lock;
  677. int cpts_registered;
  678. struct cpts *cpts;
  679. };
  680. struct gbe_intf {
  681. struct net_device *ndev;
  682. struct device *dev;
  683. struct gbe_priv *gbe_dev;
  684. struct netcp_tx_pipe tx_pipe;
  685. struct gbe_slave *slave;
  686. struct list_head gbe_intf_list;
  687. unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
  688. };
  689. static struct netcp_module gbe_module;
  690. static struct netcp_module xgbe_module;
  691. /* Statistic management */
  692. struct netcp_ethtool_stat {
  693. char desc[ETH_GSTRING_LEN];
  694. int type;
  695. u32 size;
  696. int offset;
  697. };
  698. #define GBE_STATSA_INFO(field) \
  699. { \
  700. "GBE_A:"#field, GBE_STATSA_MODULE, \
  701. FIELD_SIZEOF(struct gbe_hw_stats, field), \
  702. offsetof(struct gbe_hw_stats, field) \
  703. }
  704. #define GBE_STATSB_INFO(field) \
  705. { \
  706. "GBE_B:"#field, GBE_STATSB_MODULE, \
  707. FIELD_SIZEOF(struct gbe_hw_stats, field), \
  708. offsetof(struct gbe_hw_stats, field) \
  709. }
  710. #define GBE_STATSC_INFO(field) \
  711. { \
  712. "GBE_C:"#field, GBE_STATSC_MODULE, \
  713. FIELD_SIZEOF(struct gbe_hw_stats, field), \
  714. offsetof(struct gbe_hw_stats, field) \
  715. }
  716. #define GBE_STATSD_INFO(field) \
  717. { \
  718. "GBE_D:"#field, GBE_STATSD_MODULE, \
  719. FIELD_SIZEOF(struct gbe_hw_stats, field), \
  720. offsetof(struct gbe_hw_stats, field) \
  721. }
  722. static const struct netcp_ethtool_stat gbe13_et_stats[] = {
  723. /* GBE module A */
  724. GBE_STATSA_INFO(rx_good_frames),
  725. GBE_STATSA_INFO(rx_broadcast_frames),
  726. GBE_STATSA_INFO(rx_multicast_frames),
  727. GBE_STATSA_INFO(rx_pause_frames),
  728. GBE_STATSA_INFO(rx_crc_errors),
  729. GBE_STATSA_INFO(rx_align_code_errors),
  730. GBE_STATSA_INFO(rx_oversized_frames),
  731. GBE_STATSA_INFO(rx_jabber_frames),
  732. GBE_STATSA_INFO(rx_undersized_frames),
  733. GBE_STATSA_INFO(rx_fragments),
  734. GBE_STATSA_INFO(rx_bytes),
  735. GBE_STATSA_INFO(tx_good_frames),
  736. GBE_STATSA_INFO(tx_broadcast_frames),
  737. GBE_STATSA_INFO(tx_multicast_frames),
  738. GBE_STATSA_INFO(tx_pause_frames),
  739. GBE_STATSA_INFO(tx_deferred_frames),
  740. GBE_STATSA_INFO(tx_collision_frames),
  741. GBE_STATSA_INFO(tx_single_coll_frames),
  742. GBE_STATSA_INFO(tx_mult_coll_frames),
  743. GBE_STATSA_INFO(tx_excessive_collisions),
  744. GBE_STATSA_INFO(tx_late_collisions),
  745. GBE_STATSA_INFO(tx_underrun),
  746. GBE_STATSA_INFO(tx_carrier_sense_errors),
  747. GBE_STATSA_INFO(tx_bytes),
  748. GBE_STATSA_INFO(tx_64byte_frames),
  749. GBE_STATSA_INFO(tx_65_to_127byte_frames),
  750. GBE_STATSA_INFO(tx_128_to_255byte_frames),
  751. GBE_STATSA_INFO(tx_256_to_511byte_frames),
  752. GBE_STATSA_INFO(tx_512_to_1023byte_frames),
  753. GBE_STATSA_INFO(tx_1024byte_frames),
  754. GBE_STATSA_INFO(net_bytes),
  755. GBE_STATSA_INFO(rx_sof_overruns),
  756. GBE_STATSA_INFO(rx_mof_overruns),
  757. GBE_STATSA_INFO(rx_dma_overruns),
  758. /* GBE module B */
  759. GBE_STATSB_INFO(rx_good_frames),
  760. GBE_STATSB_INFO(rx_broadcast_frames),
  761. GBE_STATSB_INFO(rx_multicast_frames),
  762. GBE_STATSB_INFO(rx_pause_frames),
  763. GBE_STATSB_INFO(rx_crc_errors),
  764. GBE_STATSB_INFO(rx_align_code_errors),
  765. GBE_STATSB_INFO(rx_oversized_frames),
  766. GBE_STATSB_INFO(rx_jabber_frames),
  767. GBE_STATSB_INFO(rx_undersized_frames),
  768. GBE_STATSB_INFO(rx_fragments),
  769. GBE_STATSB_INFO(rx_bytes),
  770. GBE_STATSB_INFO(tx_good_frames),
  771. GBE_STATSB_INFO(tx_broadcast_frames),
  772. GBE_STATSB_INFO(tx_multicast_frames),
  773. GBE_STATSB_INFO(tx_pause_frames),
  774. GBE_STATSB_INFO(tx_deferred_frames),
  775. GBE_STATSB_INFO(tx_collision_frames),
  776. GBE_STATSB_INFO(tx_single_coll_frames),
  777. GBE_STATSB_INFO(tx_mult_coll_frames),
  778. GBE_STATSB_INFO(tx_excessive_collisions),
  779. GBE_STATSB_INFO(tx_late_collisions),
  780. GBE_STATSB_INFO(tx_underrun),
  781. GBE_STATSB_INFO(tx_carrier_sense_errors),
  782. GBE_STATSB_INFO(tx_bytes),
  783. GBE_STATSB_INFO(tx_64byte_frames),
  784. GBE_STATSB_INFO(tx_65_to_127byte_frames),
  785. GBE_STATSB_INFO(tx_128_to_255byte_frames),
  786. GBE_STATSB_INFO(tx_256_to_511byte_frames),
  787. GBE_STATSB_INFO(tx_512_to_1023byte_frames),
  788. GBE_STATSB_INFO(tx_1024byte_frames),
  789. GBE_STATSB_INFO(net_bytes),
  790. GBE_STATSB_INFO(rx_sof_overruns),
  791. GBE_STATSB_INFO(rx_mof_overruns),
  792. GBE_STATSB_INFO(rx_dma_overruns),
  793. /* GBE module C */
  794. GBE_STATSC_INFO(rx_good_frames),
  795. GBE_STATSC_INFO(rx_broadcast_frames),
  796. GBE_STATSC_INFO(rx_multicast_frames),
  797. GBE_STATSC_INFO(rx_pause_frames),
  798. GBE_STATSC_INFO(rx_crc_errors),
  799. GBE_STATSC_INFO(rx_align_code_errors),
  800. GBE_STATSC_INFO(rx_oversized_frames),
  801. GBE_STATSC_INFO(rx_jabber_frames),
  802. GBE_STATSC_INFO(rx_undersized_frames),
  803. GBE_STATSC_INFO(rx_fragments),
  804. GBE_STATSC_INFO(rx_bytes),
  805. GBE_STATSC_INFO(tx_good_frames),
  806. GBE_STATSC_INFO(tx_broadcast_frames),
  807. GBE_STATSC_INFO(tx_multicast_frames),
  808. GBE_STATSC_INFO(tx_pause_frames),
  809. GBE_STATSC_INFO(tx_deferred_frames),
  810. GBE_STATSC_INFO(tx_collision_frames),
  811. GBE_STATSC_INFO(tx_single_coll_frames),
  812. GBE_STATSC_INFO(tx_mult_coll_frames),
  813. GBE_STATSC_INFO(tx_excessive_collisions),
  814. GBE_STATSC_INFO(tx_late_collisions),
  815. GBE_STATSC_INFO(tx_underrun),
  816. GBE_STATSC_INFO(tx_carrier_sense_errors),
  817. GBE_STATSC_INFO(tx_bytes),
  818. GBE_STATSC_INFO(tx_64byte_frames),
  819. GBE_STATSC_INFO(tx_65_to_127byte_frames),
  820. GBE_STATSC_INFO(tx_128_to_255byte_frames),
  821. GBE_STATSC_INFO(tx_256_to_511byte_frames),
  822. GBE_STATSC_INFO(tx_512_to_1023byte_frames),
  823. GBE_STATSC_INFO(tx_1024byte_frames),
  824. GBE_STATSC_INFO(net_bytes),
  825. GBE_STATSC_INFO(rx_sof_overruns),
  826. GBE_STATSC_INFO(rx_mof_overruns),
  827. GBE_STATSC_INFO(rx_dma_overruns),
  828. /* GBE module D */
  829. GBE_STATSD_INFO(rx_good_frames),
  830. GBE_STATSD_INFO(rx_broadcast_frames),
  831. GBE_STATSD_INFO(rx_multicast_frames),
  832. GBE_STATSD_INFO(rx_pause_frames),
  833. GBE_STATSD_INFO(rx_crc_errors),
  834. GBE_STATSD_INFO(rx_align_code_errors),
  835. GBE_STATSD_INFO(rx_oversized_frames),
  836. GBE_STATSD_INFO(rx_jabber_frames),
  837. GBE_STATSD_INFO(rx_undersized_frames),
  838. GBE_STATSD_INFO(rx_fragments),
  839. GBE_STATSD_INFO(rx_bytes),
  840. GBE_STATSD_INFO(tx_good_frames),
  841. GBE_STATSD_INFO(tx_broadcast_frames),
  842. GBE_STATSD_INFO(tx_multicast_frames),
  843. GBE_STATSD_INFO(tx_pause_frames),
  844. GBE_STATSD_INFO(tx_deferred_frames),
  845. GBE_STATSD_INFO(tx_collision_frames),
  846. GBE_STATSD_INFO(tx_single_coll_frames),
  847. GBE_STATSD_INFO(tx_mult_coll_frames),
  848. GBE_STATSD_INFO(tx_excessive_collisions),
  849. GBE_STATSD_INFO(tx_late_collisions),
  850. GBE_STATSD_INFO(tx_underrun),
  851. GBE_STATSD_INFO(tx_carrier_sense_errors),
  852. GBE_STATSD_INFO(tx_bytes),
  853. GBE_STATSD_INFO(tx_64byte_frames),
  854. GBE_STATSD_INFO(tx_65_to_127byte_frames),
  855. GBE_STATSD_INFO(tx_128_to_255byte_frames),
  856. GBE_STATSD_INFO(tx_256_to_511byte_frames),
  857. GBE_STATSD_INFO(tx_512_to_1023byte_frames),
  858. GBE_STATSD_INFO(tx_1024byte_frames),
  859. GBE_STATSD_INFO(net_bytes),
  860. GBE_STATSD_INFO(rx_sof_overruns),
  861. GBE_STATSD_INFO(rx_mof_overruns),
  862. GBE_STATSD_INFO(rx_dma_overruns),
  863. };
  864. /* This is the size of entries in GBENU_STATS_HOST */
  865. #define GBENU_ET_STATS_HOST_SIZE 52
  866. #define GBENU_STATS_HOST(field) \
  867. { \
  868. "GBE_HOST:"#field, GBENU_STATS0_MODULE, \
  869. FIELD_SIZEOF(struct gbenu_hw_stats, field), \
  870. offsetof(struct gbenu_hw_stats, field) \
  871. }
  872. /* This is the size of entries in GBENU_STATS_PORT */
  873. #define GBENU_ET_STATS_PORT_SIZE 65
  874. #define GBENU_STATS_P1(field) \
  875. { \
  876. "GBE_P1:"#field, GBENU_STATS1_MODULE, \
  877. FIELD_SIZEOF(struct gbenu_hw_stats, field), \
  878. offsetof(struct gbenu_hw_stats, field) \
  879. }
  880. #define GBENU_STATS_P2(field) \
  881. { \
  882. "GBE_P2:"#field, GBENU_STATS2_MODULE, \
  883. FIELD_SIZEOF(struct gbenu_hw_stats, field), \
  884. offsetof(struct gbenu_hw_stats, field) \
  885. }
  886. #define GBENU_STATS_P3(field) \
  887. { \
  888. "GBE_P3:"#field, GBENU_STATS3_MODULE, \
  889. FIELD_SIZEOF(struct gbenu_hw_stats, field), \
  890. offsetof(struct gbenu_hw_stats, field) \
  891. }
  892. #define GBENU_STATS_P4(field) \
  893. { \
  894. "GBE_P4:"#field, GBENU_STATS4_MODULE, \
  895. FIELD_SIZEOF(struct gbenu_hw_stats, field), \
  896. offsetof(struct gbenu_hw_stats, field) \
  897. }
  898. #define GBENU_STATS_P5(field) \
  899. { \
  900. "GBE_P5:"#field, GBENU_STATS5_MODULE, \
  901. FIELD_SIZEOF(struct gbenu_hw_stats, field), \
  902. offsetof(struct gbenu_hw_stats, field) \
  903. }
  904. #define GBENU_STATS_P6(field) \
  905. { \
  906. "GBE_P6:"#field, GBENU_STATS6_MODULE, \
  907. FIELD_SIZEOF(struct gbenu_hw_stats, field), \
  908. offsetof(struct gbenu_hw_stats, field) \
  909. }
  910. #define GBENU_STATS_P7(field) \
  911. { \
  912. "GBE_P7:"#field, GBENU_STATS7_MODULE, \
  913. FIELD_SIZEOF(struct gbenu_hw_stats, field), \
  914. offsetof(struct gbenu_hw_stats, field) \
  915. }
  916. #define GBENU_STATS_P8(field) \
  917. { \
  918. "GBE_P8:"#field, GBENU_STATS8_MODULE, \
  919. FIELD_SIZEOF(struct gbenu_hw_stats, field), \
  920. offsetof(struct gbenu_hw_stats, field) \
  921. }
  922. static const struct netcp_ethtool_stat gbenu_et_stats[] = {
  923. /* GBENU Host Module */
  924. GBENU_STATS_HOST(rx_good_frames),
  925. GBENU_STATS_HOST(rx_broadcast_frames),
  926. GBENU_STATS_HOST(rx_multicast_frames),
  927. GBENU_STATS_HOST(rx_crc_errors),
  928. GBENU_STATS_HOST(rx_oversized_frames),
  929. GBENU_STATS_HOST(rx_undersized_frames),
  930. GBENU_STATS_HOST(ale_drop),
  931. GBENU_STATS_HOST(ale_overrun_drop),
  932. GBENU_STATS_HOST(rx_bytes),
  933. GBENU_STATS_HOST(tx_good_frames),
  934. GBENU_STATS_HOST(tx_broadcast_frames),
  935. GBENU_STATS_HOST(tx_multicast_frames),
  936. GBENU_STATS_HOST(tx_bytes),
  937. GBENU_STATS_HOST(tx_64B_frames),
  938. GBENU_STATS_HOST(tx_65_to_127B_frames),
  939. GBENU_STATS_HOST(tx_128_to_255B_frames),
  940. GBENU_STATS_HOST(tx_256_to_511B_frames),
  941. GBENU_STATS_HOST(tx_512_to_1023B_frames),
  942. GBENU_STATS_HOST(tx_1024B_frames),
  943. GBENU_STATS_HOST(net_bytes),
  944. GBENU_STATS_HOST(rx_bottom_fifo_drop),
  945. GBENU_STATS_HOST(rx_port_mask_drop),
  946. GBENU_STATS_HOST(rx_top_fifo_drop),
  947. GBENU_STATS_HOST(ale_rate_limit_drop),
  948. GBENU_STATS_HOST(ale_vid_ingress_drop),
  949. GBENU_STATS_HOST(ale_da_eq_sa_drop),
  950. GBENU_STATS_HOST(ale_unknown_ucast),
  951. GBENU_STATS_HOST(ale_unknown_ucast_bytes),
  952. GBENU_STATS_HOST(ale_unknown_mcast),
  953. GBENU_STATS_HOST(ale_unknown_mcast_bytes),
  954. GBENU_STATS_HOST(ale_unknown_bcast),
  955. GBENU_STATS_HOST(ale_unknown_bcast_bytes),
  956. GBENU_STATS_HOST(ale_pol_match),
  957. GBENU_STATS_HOST(ale_pol_match_red),
  958. GBENU_STATS_HOST(ale_pol_match_yellow),
  959. GBENU_STATS_HOST(tx_mem_protect_err),
  960. GBENU_STATS_HOST(tx_pri0_drop),
  961. GBENU_STATS_HOST(tx_pri1_drop),
  962. GBENU_STATS_HOST(tx_pri2_drop),
  963. GBENU_STATS_HOST(tx_pri3_drop),
  964. GBENU_STATS_HOST(tx_pri4_drop),
  965. GBENU_STATS_HOST(tx_pri5_drop),
  966. GBENU_STATS_HOST(tx_pri6_drop),
  967. GBENU_STATS_HOST(tx_pri7_drop),
  968. GBENU_STATS_HOST(tx_pri0_drop_bcnt),
  969. GBENU_STATS_HOST(tx_pri1_drop_bcnt),
  970. GBENU_STATS_HOST(tx_pri2_drop_bcnt),
  971. GBENU_STATS_HOST(tx_pri3_drop_bcnt),
  972. GBENU_STATS_HOST(tx_pri4_drop_bcnt),
  973. GBENU_STATS_HOST(tx_pri5_drop_bcnt),
  974. GBENU_STATS_HOST(tx_pri6_drop_bcnt),
  975. GBENU_STATS_HOST(tx_pri7_drop_bcnt),
  976. /* GBENU Module 1 */
  977. GBENU_STATS_P1(rx_good_frames),
  978. GBENU_STATS_P1(rx_broadcast_frames),
  979. GBENU_STATS_P1(rx_multicast_frames),
  980. GBENU_STATS_P1(rx_pause_frames),
  981. GBENU_STATS_P1(rx_crc_errors),
  982. GBENU_STATS_P1(rx_align_code_errors),
  983. GBENU_STATS_P1(rx_oversized_frames),
  984. GBENU_STATS_P1(rx_jabber_frames),
  985. GBENU_STATS_P1(rx_undersized_frames),
  986. GBENU_STATS_P1(rx_fragments),
  987. GBENU_STATS_P1(ale_drop),
  988. GBENU_STATS_P1(ale_overrun_drop),
  989. GBENU_STATS_P1(rx_bytes),
  990. GBENU_STATS_P1(tx_good_frames),
  991. GBENU_STATS_P1(tx_broadcast_frames),
  992. GBENU_STATS_P1(tx_multicast_frames),
  993. GBENU_STATS_P1(tx_pause_frames),
  994. GBENU_STATS_P1(tx_deferred_frames),
  995. GBENU_STATS_P1(tx_collision_frames),
  996. GBENU_STATS_P1(tx_single_coll_frames),
  997. GBENU_STATS_P1(tx_mult_coll_frames),
  998. GBENU_STATS_P1(tx_excessive_collisions),
  999. GBENU_STATS_P1(tx_late_collisions),
  1000. GBENU_STATS_P1(rx_ipg_error),
  1001. GBENU_STATS_P1(tx_carrier_sense_errors),
  1002. GBENU_STATS_P1(tx_bytes),
  1003. GBENU_STATS_P1(tx_64B_frames),
  1004. GBENU_STATS_P1(tx_65_to_127B_frames),
  1005. GBENU_STATS_P1(tx_128_to_255B_frames),
  1006. GBENU_STATS_P1(tx_256_to_511B_frames),
  1007. GBENU_STATS_P1(tx_512_to_1023B_frames),
  1008. GBENU_STATS_P1(tx_1024B_frames),
  1009. GBENU_STATS_P1(net_bytes),
  1010. GBENU_STATS_P1(rx_bottom_fifo_drop),
  1011. GBENU_STATS_P1(rx_port_mask_drop),
  1012. GBENU_STATS_P1(rx_top_fifo_drop),
  1013. GBENU_STATS_P1(ale_rate_limit_drop),
  1014. GBENU_STATS_P1(ale_vid_ingress_drop),
  1015. GBENU_STATS_P1(ale_da_eq_sa_drop),
  1016. GBENU_STATS_P1(ale_unknown_ucast),
  1017. GBENU_STATS_P1(ale_unknown_ucast_bytes),
  1018. GBENU_STATS_P1(ale_unknown_mcast),
  1019. GBENU_STATS_P1(ale_unknown_mcast_bytes),
  1020. GBENU_STATS_P1(ale_unknown_bcast),
  1021. GBENU_STATS_P1(ale_unknown_bcast_bytes),
  1022. GBENU_STATS_P1(ale_pol_match),
  1023. GBENU_STATS_P1(ale_pol_match_red),
  1024. GBENU_STATS_P1(ale_pol_match_yellow),
  1025. GBENU_STATS_P1(tx_mem_protect_err),
  1026. GBENU_STATS_P1(tx_pri0_drop),
  1027. GBENU_STATS_P1(tx_pri1_drop),
  1028. GBENU_STATS_P1(tx_pri2_drop),
  1029. GBENU_STATS_P1(tx_pri3_drop),
  1030. GBENU_STATS_P1(tx_pri4_drop),
  1031. GBENU_STATS_P1(tx_pri5_drop),
  1032. GBENU_STATS_P1(tx_pri6_drop),
  1033. GBENU_STATS_P1(tx_pri7_drop),
  1034. GBENU_STATS_P1(tx_pri0_drop_bcnt),
  1035. GBENU_STATS_P1(tx_pri1_drop_bcnt),
  1036. GBENU_STATS_P1(tx_pri2_drop_bcnt),
  1037. GBENU_STATS_P1(tx_pri3_drop_bcnt),
  1038. GBENU_STATS_P1(tx_pri4_drop_bcnt),
  1039. GBENU_STATS_P1(tx_pri5_drop_bcnt),
  1040. GBENU_STATS_P1(tx_pri6_drop_bcnt),
  1041. GBENU_STATS_P1(tx_pri7_drop_bcnt),
  1042. /* GBENU Module 2 */
  1043. GBENU_STATS_P2(rx_good_frames),
  1044. GBENU_STATS_P2(rx_broadcast_frames),
  1045. GBENU_STATS_P2(rx_multicast_frames),
  1046. GBENU_STATS_P2(rx_pause_frames),
  1047. GBENU_STATS_P2(rx_crc_errors),
  1048. GBENU_STATS_P2(rx_align_code_errors),
  1049. GBENU_STATS_P2(rx_oversized_frames),
  1050. GBENU_STATS_P2(rx_jabber_frames),
  1051. GBENU_STATS_P2(rx_undersized_frames),
  1052. GBENU_STATS_P2(rx_fragments),
  1053. GBENU_STATS_P2(ale_drop),
  1054. GBENU_STATS_P2(ale_overrun_drop),
  1055. GBENU_STATS_P2(rx_bytes),
  1056. GBENU_STATS_P2(tx_good_frames),
  1057. GBENU_STATS_P2(tx_broadcast_frames),
  1058. GBENU_STATS_P2(tx_multicast_frames),
  1059. GBENU_STATS_P2(tx_pause_frames),
  1060. GBENU_STATS_P2(tx_deferred_frames),
  1061. GBENU_STATS_P2(tx_collision_frames),
  1062. GBENU_STATS_P2(tx_single_coll_frames),
  1063. GBENU_STATS_P2(tx_mult_coll_frames),
  1064. GBENU_STATS_P2(tx_excessive_collisions),
  1065. GBENU_STATS_P2(tx_late_collisions),
  1066. GBENU_STATS_P2(rx_ipg_error),
  1067. GBENU_STATS_P2(tx_carrier_sense_errors),
  1068. GBENU_STATS_P2(tx_bytes),
  1069. GBENU_STATS_P2(tx_64B_frames),
  1070. GBENU_STATS_P2(tx_65_to_127B_frames),
  1071. GBENU_STATS_P2(tx_128_to_255B_frames),
  1072. GBENU_STATS_P2(tx_256_to_511B_frames),
  1073. GBENU_STATS_P2(tx_512_to_1023B_frames),
  1074. GBENU_STATS_P2(tx_1024B_frames),
  1075. GBENU_STATS_P2(net_bytes),
  1076. GBENU_STATS_P2(rx_bottom_fifo_drop),
  1077. GBENU_STATS_P2(rx_port_mask_drop),
  1078. GBENU_STATS_P2(rx_top_fifo_drop),
  1079. GBENU_STATS_P2(ale_rate_limit_drop),
  1080. GBENU_STATS_P2(ale_vid_ingress_drop),
  1081. GBENU_STATS_P2(ale_da_eq_sa_drop),
  1082. GBENU_STATS_P2(ale_unknown_ucast),
  1083. GBENU_STATS_P2(ale_unknown_ucast_bytes),
  1084. GBENU_STATS_P2(ale_unknown_mcast),
  1085. GBENU_STATS_P2(ale_unknown_mcast_bytes),
  1086. GBENU_STATS_P2(ale_unknown_bcast),
  1087. GBENU_STATS_P2(ale_unknown_bcast_bytes),
  1088. GBENU_STATS_P2(ale_pol_match),
  1089. GBENU_STATS_P2(ale_pol_match_red),
  1090. GBENU_STATS_P2(ale_pol_match_yellow),
  1091. GBENU_STATS_P2(tx_mem_protect_err),
  1092. GBENU_STATS_P2(tx_pri0_drop),
  1093. GBENU_STATS_P2(tx_pri1_drop),
  1094. GBENU_STATS_P2(tx_pri2_drop),
  1095. GBENU_STATS_P2(tx_pri3_drop),
  1096. GBENU_STATS_P2(tx_pri4_drop),
  1097. GBENU_STATS_P2(tx_pri5_drop),
  1098. GBENU_STATS_P2(tx_pri6_drop),
  1099. GBENU_STATS_P2(tx_pri7_drop),
  1100. GBENU_STATS_P2(tx_pri0_drop_bcnt),
  1101. GBENU_STATS_P2(tx_pri1_drop_bcnt),
  1102. GBENU_STATS_P2(tx_pri2_drop_bcnt),
  1103. GBENU_STATS_P2(tx_pri3_drop_bcnt),
  1104. GBENU_STATS_P2(tx_pri4_drop_bcnt),
  1105. GBENU_STATS_P2(tx_pri5_drop_bcnt),
  1106. GBENU_STATS_P2(tx_pri6_drop_bcnt),
  1107. GBENU_STATS_P2(tx_pri7_drop_bcnt),
  1108. /* GBENU Module 3 */
  1109. GBENU_STATS_P3(rx_good_frames),
  1110. GBENU_STATS_P3(rx_broadcast_frames),
  1111. GBENU_STATS_P3(rx_multicast_frames),
  1112. GBENU_STATS_P3(rx_pause_frames),
  1113. GBENU_STATS_P3(rx_crc_errors),
  1114. GBENU_STATS_P3(rx_align_code_errors),
  1115. GBENU_STATS_P3(rx_oversized_frames),
  1116. GBENU_STATS_P3(rx_jabber_frames),
  1117. GBENU_STATS_P3(rx_undersized_frames),
  1118. GBENU_STATS_P3(rx_fragments),
  1119. GBENU_STATS_P3(ale_drop),
  1120. GBENU_STATS_P3(ale_overrun_drop),
  1121. GBENU_STATS_P3(rx_bytes),
  1122. GBENU_STATS_P3(tx_good_frames),
  1123. GBENU_STATS_P3(tx_broadcast_frames),
  1124. GBENU_STATS_P3(tx_multicast_frames),
  1125. GBENU_STATS_P3(tx_pause_frames),
  1126. GBENU_STATS_P3(tx_deferred_frames),
  1127. GBENU_STATS_P3(tx_collision_frames),
  1128. GBENU_STATS_P3(tx_single_coll_frames),
  1129. GBENU_STATS_P3(tx_mult_coll_frames),
  1130. GBENU_STATS_P3(tx_excessive_collisions),
  1131. GBENU_STATS_P3(tx_late_collisions),
  1132. GBENU_STATS_P3(rx_ipg_error),
  1133. GBENU_STATS_P3(tx_carrier_sense_errors),
  1134. GBENU_STATS_P3(tx_bytes),
  1135. GBENU_STATS_P3(tx_64B_frames),
  1136. GBENU_STATS_P3(tx_65_to_127B_frames),
  1137. GBENU_STATS_P3(tx_128_to_255B_frames),
  1138. GBENU_STATS_P3(tx_256_to_511B_frames),
  1139. GBENU_STATS_P3(tx_512_to_1023B_frames),
  1140. GBENU_STATS_P3(tx_1024B_frames),
  1141. GBENU_STATS_P3(net_bytes),
  1142. GBENU_STATS_P3(rx_bottom_fifo_drop),
  1143. GBENU_STATS_P3(rx_port_mask_drop),
  1144. GBENU_STATS_P3(rx_top_fifo_drop),
  1145. GBENU_STATS_P3(ale_rate_limit_drop),
  1146. GBENU_STATS_P3(ale_vid_ingress_drop),
  1147. GBENU_STATS_P3(ale_da_eq_sa_drop),
  1148. GBENU_STATS_P3(ale_unknown_ucast),
  1149. GBENU_STATS_P3(ale_unknown_ucast_bytes),
  1150. GBENU_STATS_P3(ale_unknown_mcast),
  1151. GBENU_STATS_P3(ale_unknown_mcast_bytes),
  1152. GBENU_STATS_P3(ale_unknown_bcast),
  1153. GBENU_STATS_P3(ale_unknown_bcast_bytes),
  1154. GBENU_STATS_P3(ale_pol_match),
  1155. GBENU_STATS_P3(ale_pol_match_red),
  1156. GBENU_STATS_P3(ale_pol_match_yellow),
  1157. GBENU_STATS_P3(tx_mem_protect_err),
  1158. GBENU_STATS_P3(tx_pri0_drop),
  1159. GBENU_STATS_P3(tx_pri1_drop),
  1160. GBENU_STATS_P3(tx_pri2_drop),
  1161. GBENU_STATS_P3(tx_pri3_drop),
  1162. GBENU_STATS_P3(tx_pri4_drop),
  1163. GBENU_STATS_P3(tx_pri5_drop),
  1164. GBENU_STATS_P3(tx_pri6_drop),
  1165. GBENU_STATS_P3(tx_pri7_drop),
  1166. GBENU_STATS_P3(tx_pri0_drop_bcnt),
  1167. GBENU_STATS_P3(tx_pri1_drop_bcnt),
  1168. GBENU_STATS_P3(tx_pri2_drop_bcnt),
  1169. GBENU_STATS_P3(tx_pri3_drop_bcnt),
  1170. GBENU_STATS_P3(tx_pri4_drop_bcnt),
  1171. GBENU_STATS_P3(tx_pri5_drop_bcnt),
  1172. GBENU_STATS_P3(tx_pri6_drop_bcnt),
  1173. GBENU_STATS_P3(tx_pri7_drop_bcnt),
  1174. /* GBENU Module 4 */
  1175. GBENU_STATS_P4(rx_good_frames),
  1176. GBENU_STATS_P4(rx_broadcast_frames),
  1177. GBENU_STATS_P4(rx_multicast_frames),
  1178. GBENU_STATS_P4(rx_pause_frames),
  1179. GBENU_STATS_P4(rx_crc_errors),
  1180. GBENU_STATS_P4(rx_align_code_errors),
  1181. GBENU_STATS_P4(rx_oversized_frames),
  1182. GBENU_STATS_P4(rx_jabber_frames),
  1183. GBENU_STATS_P4(rx_undersized_frames),
  1184. GBENU_STATS_P4(rx_fragments),
  1185. GBENU_STATS_P4(ale_drop),
  1186. GBENU_STATS_P4(ale_overrun_drop),
  1187. GBENU_STATS_P4(rx_bytes),
  1188. GBENU_STATS_P4(tx_good_frames),
  1189. GBENU_STATS_P4(tx_broadcast_frames),
  1190. GBENU_STATS_P4(tx_multicast_frames),
  1191. GBENU_STATS_P4(tx_pause_frames),
  1192. GBENU_STATS_P4(tx_deferred_frames),
  1193. GBENU_STATS_P4(tx_collision_frames),
  1194. GBENU_STATS_P4(tx_single_coll_frames),
  1195. GBENU_STATS_P4(tx_mult_coll_frames),
  1196. GBENU_STATS_P4(tx_excessive_collisions),
  1197. GBENU_STATS_P4(tx_late_collisions),
  1198. GBENU_STATS_P4(rx_ipg_error),
  1199. GBENU_STATS_P4(tx_carrier_sense_errors),
  1200. GBENU_STATS_P4(tx_bytes),
  1201. GBENU_STATS_P4(tx_64B_frames),
  1202. GBENU_STATS_P4(tx_65_to_127B_frames),
  1203. GBENU_STATS_P4(tx_128_to_255B_frames),
  1204. GBENU_STATS_P4(tx_256_to_511B_frames),
  1205. GBENU_STATS_P4(tx_512_to_1023B_frames),
  1206. GBENU_STATS_P4(tx_1024B_frames),
  1207. GBENU_STATS_P4(net_bytes),
  1208. GBENU_STATS_P4(rx_bottom_fifo_drop),
  1209. GBENU_STATS_P4(rx_port_mask_drop),
  1210. GBENU_STATS_P4(rx_top_fifo_drop),
  1211. GBENU_STATS_P4(ale_rate_limit_drop),
  1212. GBENU_STATS_P4(ale_vid_ingress_drop),
  1213. GBENU_STATS_P4(ale_da_eq_sa_drop),
  1214. GBENU_STATS_P4(ale_unknown_ucast),
  1215. GBENU_STATS_P4(ale_unknown_ucast_bytes),
  1216. GBENU_STATS_P4(ale_unknown_mcast),
  1217. GBENU_STATS_P4(ale_unknown_mcast_bytes),
  1218. GBENU_STATS_P4(ale_unknown_bcast),
  1219. GBENU_STATS_P4(ale_unknown_bcast_bytes),
  1220. GBENU_STATS_P4(ale_pol_match),
  1221. GBENU_STATS_P4(ale_pol_match_red),
  1222. GBENU_STATS_P4(ale_pol_match_yellow),
  1223. GBENU_STATS_P4(tx_mem_protect_err),
  1224. GBENU_STATS_P4(tx_pri0_drop),
  1225. GBENU_STATS_P4(tx_pri1_drop),
  1226. GBENU_STATS_P4(tx_pri2_drop),
  1227. GBENU_STATS_P4(tx_pri3_drop),
  1228. GBENU_STATS_P4(tx_pri4_drop),
  1229. GBENU_STATS_P4(tx_pri5_drop),
  1230. GBENU_STATS_P4(tx_pri6_drop),
  1231. GBENU_STATS_P4(tx_pri7_drop),
  1232. GBENU_STATS_P4(tx_pri0_drop_bcnt),
  1233. GBENU_STATS_P4(tx_pri1_drop_bcnt),
  1234. GBENU_STATS_P4(tx_pri2_drop_bcnt),
  1235. GBENU_STATS_P4(tx_pri3_drop_bcnt),
  1236. GBENU_STATS_P4(tx_pri4_drop_bcnt),
  1237. GBENU_STATS_P4(tx_pri5_drop_bcnt),
  1238. GBENU_STATS_P4(tx_pri6_drop_bcnt),
  1239. GBENU_STATS_P4(tx_pri7_drop_bcnt),
  1240. /* GBENU Module 5 */
  1241. GBENU_STATS_P5(rx_good_frames),
  1242. GBENU_STATS_P5(rx_broadcast_frames),
  1243. GBENU_STATS_P5(rx_multicast_frames),
  1244. GBENU_STATS_P5(rx_pause_frames),
  1245. GBENU_STATS_P5(rx_crc_errors),
  1246. GBENU_STATS_P5(rx_align_code_errors),
  1247. GBENU_STATS_P5(rx_oversized_frames),
  1248. GBENU_STATS_P5(rx_jabber_frames),
  1249. GBENU_STATS_P5(rx_undersized_frames),
  1250. GBENU_STATS_P5(rx_fragments),
  1251. GBENU_STATS_P5(ale_drop),
  1252. GBENU_STATS_P5(ale_overrun_drop),
  1253. GBENU_STATS_P5(rx_bytes),
  1254. GBENU_STATS_P5(tx_good_frames),
  1255. GBENU_STATS_P5(tx_broadcast_frames),
  1256. GBENU_STATS_P5(tx_multicast_frames),
  1257. GBENU_STATS_P5(tx_pause_frames),
  1258. GBENU_STATS_P5(tx_deferred_frames),
  1259. GBENU_STATS_P5(tx_collision_frames),
  1260. GBENU_STATS_P5(tx_single_coll_frames),
  1261. GBENU_STATS_P5(tx_mult_coll_frames),
  1262. GBENU_STATS_P5(tx_excessive_collisions),
  1263. GBENU_STATS_P5(tx_late_collisions),
  1264. GBENU_STATS_P5(rx_ipg_error),
  1265. GBENU_STATS_P5(tx_carrier_sense_errors),
  1266. GBENU_STATS_P5(tx_bytes),
  1267. GBENU_STATS_P5(tx_64B_frames),
  1268. GBENU_STATS_P5(tx_65_to_127B_frames),
  1269. GBENU_STATS_P5(tx_128_to_255B_frames),
  1270. GBENU_STATS_P5(tx_256_to_511B_frames),
  1271. GBENU_STATS_P5(tx_512_to_1023B_frames),
  1272. GBENU_STATS_P5(tx_1024B_frames),
  1273. GBENU_STATS_P5(net_bytes),
  1274. GBENU_STATS_P5(rx_bottom_fifo_drop),
  1275. GBENU_STATS_P5(rx_port_mask_drop),
  1276. GBENU_STATS_P5(rx_top_fifo_drop),
  1277. GBENU_STATS_P5(ale_rate_limit_drop),
  1278. GBENU_STATS_P5(ale_vid_ingress_drop),
  1279. GBENU_STATS_P5(ale_da_eq_sa_drop),
  1280. GBENU_STATS_P5(ale_unknown_ucast),
  1281. GBENU_STATS_P5(ale_unknown_ucast_bytes),
  1282. GBENU_STATS_P5(ale_unknown_mcast),
  1283. GBENU_STATS_P5(ale_unknown_mcast_bytes),
  1284. GBENU_STATS_P5(ale_unknown_bcast),
  1285. GBENU_STATS_P5(ale_unknown_bcast_bytes),
  1286. GBENU_STATS_P5(ale_pol_match),
  1287. GBENU_STATS_P5(ale_pol_match_red),
  1288. GBENU_STATS_P5(ale_pol_match_yellow),
  1289. GBENU_STATS_P5(tx_mem_protect_err),
  1290. GBENU_STATS_P5(tx_pri0_drop),
  1291. GBENU_STATS_P5(tx_pri1_drop),
  1292. GBENU_STATS_P5(tx_pri2_drop),
  1293. GBENU_STATS_P5(tx_pri3_drop),
  1294. GBENU_STATS_P5(tx_pri4_drop),
  1295. GBENU_STATS_P5(tx_pri5_drop),
  1296. GBENU_STATS_P5(tx_pri6_drop),
  1297. GBENU_STATS_P5(tx_pri7_drop),
  1298. GBENU_STATS_P5(tx_pri0_drop_bcnt),
  1299. GBENU_STATS_P5(tx_pri1_drop_bcnt),
  1300. GBENU_STATS_P5(tx_pri2_drop_bcnt),
  1301. GBENU_STATS_P5(tx_pri3_drop_bcnt),
  1302. GBENU_STATS_P5(tx_pri4_drop_bcnt),
  1303. GBENU_STATS_P5(tx_pri5_drop_bcnt),
  1304. GBENU_STATS_P5(tx_pri6_drop_bcnt),
  1305. GBENU_STATS_P5(tx_pri7_drop_bcnt),
  1306. /* GBENU Module 6 */
  1307. GBENU_STATS_P6(rx_good_frames),
  1308. GBENU_STATS_P6(rx_broadcast_frames),
  1309. GBENU_STATS_P6(rx_multicast_frames),
  1310. GBENU_STATS_P6(rx_pause_frames),
  1311. GBENU_STATS_P6(rx_crc_errors),
  1312. GBENU_STATS_P6(rx_align_code_errors),
  1313. GBENU_STATS_P6(rx_oversized_frames),
  1314. GBENU_STATS_P6(rx_jabber_frames),
  1315. GBENU_STATS_P6(rx_undersized_frames),
  1316. GBENU_STATS_P6(rx_fragments),
  1317. GBENU_STATS_P6(ale_drop),
  1318. GBENU_STATS_P6(ale_overrun_drop),
  1319. GBENU_STATS_P6(rx_bytes),
  1320. GBENU_STATS_P6(tx_good_frames),
  1321. GBENU_STATS_P6(tx_broadcast_frames),
  1322. GBENU_STATS_P6(tx_multicast_frames),
  1323. GBENU_STATS_P6(tx_pause_frames),
  1324. GBENU_STATS_P6(tx_deferred_frames),
  1325. GBENU_STATS_P6(tx_collision_frames),
  1326. GBENU_STATS_P6(tx_single_coll_frames),
  1327. GBENU_STATS_P6(tx_mult_coll_frames),
  1328. GBENU_STATS_P6(tx_excessive_collisions),
  1329. GBENU_STATS_P6(tx_late_collisions),
  1330. GBENU_STATS_P6(rx_ipg_error),
  1331. GBENU_STATS_P6(tx_carrier_sense_errors),
  1332. GBENU_STATS_P6(tx_bytes),
  1333. GBENU_STATS_P6(tx_64B_frames),
  1334. GBENU_STATS_P6(tx_65_to_127B_frames),
  1335. GBENU_STATS_P6(tx_128_to_255B_frames),
  1336. GBENU_STATS_P6(tx_256_to_511B_frames),
  1337. GBENU_STATS_P6(tx_512_to_1023B_frames),
  1338. GBENU_STATS_P6(tx_1024B_frames),
  1339. GBENU_STATS_P6(net_bytes),
  1340. GBENU_STATS_P6(rx_bottom_fifo_drop),
  1341. GBENU_STATS_P6(rx_port_mask_drop),
  1342. GBENU_STATS_P6(rx_top_fifo_drop),
  1343. GBENU_STATS_P6(ale_rate_limit_drop),
  1344. GBENU_STATS_P6(ale_vid_ingress_drop),
  1345. GBENU_STATS_P6(ale_da_eq_sa_drop),
  1346. GBENU_STATS_P6(ale_unknown_ucast),
  1347. GBENU_STATS_P6(ale_unknown_ucast_bytes),
  1348. GBENU_STATS_P6(ale_unknown_mcast),
  1349. GBENU_STATS_P6(ale_unknown_mcast_bytes),
  1350. GBENU_STATS_P6(ale_unknown_bcast),
  1351. GBENU_STATS_P6(ale_unknown_bcast_bytes),
  1352. GBENU_STATS_P6(ale_pol_match),
  1353. GBENU_STATS_P6(ale_pol_match_red),
  1354. GBENU_STATS_P6(ale_pol_match_yellow),
  1355. GBENU_STATS_P6(tx_mem_protect_err),
  1356. GBENU_STATS_P6(tx_pri0_drop),
  1357. GBENU_STATS_P6(tx_pri1_drop),
  1358. GBENU_STATS_P6(tx_pri2_drop),
  1359. GBENU_STATS_P6(tx_pri3_drop),
  1360. GBENU_STATS_P6(tx_pri4_drop),
  1361. GBENU_STATS_P6(tx_pri5_drop),
  1362. GBENU_STATS_P6(tx_pri6_drop),
  1363. GBENU_STATS_P6(tx_pri7_drop),
  1364. GBENU_STATS_P6(tx_pri0_drop_bcnt),
  1365. GBENU_STATS_P6(tx_pri1_drop_bcnt),
  1366. GBENU_STATS_P6(tx_pri2_drop_bcnt),
  1367. GBENU_STATS_P6(tx_pri3_drop_bcnt),
  1368. GBENU_STATS_P6(tx_pri4_drop_bcnt),
  1369. GBENU_STATS_P6(tx_pri5_drop_bcnt),
  1370. GBENU_STATS_P6(tx_pri6_drop_bcnt),
  1371. GBENU_STATS_P6(tx_pri7_drop_bcnt),
  1372. /* GBENU Module 7 */
  1373. GBENU_STATS_P7(rx_good_frames),
  1374. GBENU_STATS_P7(rx_broadcast_frames),
  1375. GBENU_STATS_P7(rx_multicast_frames),
  1376. GBENU_STATS_P7(rx_pause_frames),
  1377. GBENU_STATS_P7(rx_crc_errors),
  1378. GBENU_STATS_P7(rx_align_code_errors),
  1379. GBENU_STATS_P7(rx_oversized_frames),
  1380. GBENU_STATS_P7(rx_jabber_frames),
  1381. GBENU_STATS_P7(rx_undersized_frames),
  1382. GBENU_STATS_P7(rx_fragments),
  1383. GBENU_STATS_P7(ale_drop),
  1384. GBENU_STATS_P7(ale_overrun_drop),
  1385. GBENU_STATS_P7(rx_bytes),
  1386. GBENU_STATS_P7(tx_good_frames),
  1387. GBENU_STATS_P7(tx_broadcast_frames),
  1388. GBENU_STATS_P7(tx_multicast_frames),
  1389. GBENU_STATS_P7(tx_pause_frames),
  1390. GBENU_STATS_P7(tx_deferred_frames),
  1391. GBENU_STATS_P7(tx_collision_frames),
  1392. GBENU_STATS_P7(tx_single_coll_frames),
  1393. GBENU_STATS_P7(tx_mult_coll_frames),
  1394. GBENU_STATS_P7(tx_excessive_collisions),
  1395. GBENU_STATS_P7(tx_late_collisions),
  1396. GBENU_STATS_P7(rx_ipg_error),
  1397. GBENU_STATS_P7(tx_carrier_sense_errors),
  1398. GBENU_STATS_P7(tx_bytes),
  1399. GBENU_STATS_P7(tx_64B_frames),
  1400. GBENU_STATS_P7(tx_65_to_127B_frames),
  1401. GBENU_STATS_P7(tx_128_to_255B_frames),
  1402. GBENU_STATS_P7(tx_256_to_511B_frames),
  1403. GBENU_STATS_P7(tx_512_to_1023B_frames),
  1404. GBENU_STATS_P7(tx_1024B_frames),
  1405. GBENU_STATS_P7(net_bytes),
  1406. GBENU_STATS_P7(rx_bottom_fifo_drop),
  1407. GBENU_STATS_P7(rx_port_mask_drop),
  1408. GBENU_STATS_P7(rx_top_fifo_drop),
  1409. GBENU_STATS_P7(ale_rate_limit_drop),
  1410. GBENU_STATS_P7(ale_vid_ingress_drop),
  1411. GBENU_STATS_P7(ale_da_eq_sa_drop),
  1412. GBENU_STATS_P7(ale_unknown_ucast),
  1413. GBENU_STATS_P7(ale_unknown_ucast_bytes),
  1414. GBENU_STATS_P7(ale_unknown_mcast),
  1415. GBENU_STATS_P7(ale_unknown_mcast_bytes),
  1416. GBENU_STATS_P7(ale_unknown_bcast),
  1417. GBENU_STATS_P7(ale_unknown_bcast_bytes),
  1418. GBENU_STATS_P7(ale_pol_match),
  1419. GBENU_STATS_P7(ale_pol_match_red),
  1420. GBENU_STATS_P7(ale_pol_match_yellow),
  1421. GBENU_STATS_P7(tx_mem_protect_err),
  1422. GBENU_STATS_P7(tx_pri0_drop),
  1423. GBENU_STATS_P7(tx_pri1_drop),
  1424. GBENU_STATS_P7(tx_pri2_drop),
  1425. GBENU_STATS_P7(tx_pri3_drop),
  1426. GBENU_STATS_P7(tx_pri4_drop),
  1427. GBENU_STATS_P7(tx_pri5_drop),
  1428. GBENU_STATS_P7(tx_pri6_drop),
  1429. GBENU_STATS_P7(tx_pri7_drop),
  1430. GBENU_STATS_P7(tx_pri0_drop_bcnt),
  1431. GBENU_STATS_P7(tx_pri1_drop_bcnt),
  1432. GBENU_STATS_P7(tx_pri2_drop_bcnt),
  1433. GBENU_STATS_P7(tx_pri3_drop_bcnt),
  1434. GBENU_STATS_P7(tx_pri4_drop_bcnt),
  1435. GBENU_STATS_P7(tx_pri5_drop_bcnt),
  1436. GBENU_STATS_P7(tx_pri6_drop_bcnt),
  1437. GBENU_STATS_P7(tx_pri7_drop_bcnt),
  1438. /* GBENU Module 8 */
  1439. GBENU_STATS_P8(rx_good_frames),
  1440. GBENU_STATS_P8(rx_broadcast_frames),
  1441. GBENU_STATS_P8(rx_multicast_frames),
  1442. GBENU_STATS_P8(rx_pause_frames),
  1443. GBENU_STATS_P8(rx_crc_errors),
  1444. GBENU_STATS_P8(rx_align_code_errors),
  1445. GBENU_STATS_P8(rx_oversized_frames),
  1446. GBENU_STATS_P8(rx_jabber_frames),
  1447. GBENU_STATS_P8(rx_undersized_frames),
  1448. GBENU_STATS_P8(rx_fragments),
  1449. GBENU_STATS_P8(ale_drop),
  1450. GBENU_STATS_P8(ale_overrun_drop),
  1451. GBENU_STATS_P8(rx_bytes),
  1452. GBENU_STATS_P8(tx_good_frames),
  1453. GBENU_STATS_P8(tx_broadcast_frames),
  1454. GBENU_STATS_P8(tx_multicast_frames),
  1455. GBENU_STATS_P8(tx_pause_frames),
  1456. GBENU_STATS_P8(tx_deferred_frames),
  1457. GBENU_STATS_P8(tx_collision_frames),
  1458. GBENU_STATS_P8(tx_single_coll_frames),
  1459. GBENU_STATS_P8(tx_mult_coll_frames),
  1460. GBENU_STATS_P8(tx_excessive_collisions),
  1461. GBENU_STATS_P8(tx_late_collisions),
  1462. GBENU_STATS_P8(rx_ipg_error),
  1463. GBENU_STATS_P8(tx_carrier_sense_errors),
  1464. GBENU_STATS_P8(tx_bytes),
  1465. GBENU_STATS_P8(tx_64B_frames),
  1466. GBENU_STATS_P8(tx_65_to_127B_frames),
  1467. GBENU_STATS_P8(tx_128_to_255B_frames),
  1468. GBENU_STATS_P8(tx_256_to_511B_frames),
  1469. GBENU_STATS_P8(tx_512_to_1023B_frames),
  1470. GBENU_STATS_P8(tx_1024B_frames),
  1471. GBENU_STATS_P8(net_bytes),
  1472. GBENU_STATS_P8(rx_bottom_fifo_drop),
  1473. GBENU_STATS_P8(rx_port_mask_drop),
  1474. GBENU_STATS_P8(rx_top_fifo_drop),
  1475. GBENU_STATS_P8(ale_rate_limit_drop),
  1476. GBENU_STATS_P8(ale_vid_ingress_drop),
  1477. GBENU_STATS_P8(ale_da_eq_sa_drop),
  1478. GBENU_STATS_P8(ale_unknown_ucast),
  1479. GBENU_STATS_P8(ale_unknown_ucast_bytes),
  1480. GBENU_STATS_P8(ale_unknown_mcast),
  1481. GBENU_STATS_P8(ale_unknown_mcast_bytes),
  1482. GBENU_STATS_P8(ale_unknown_bcast),
  1483. GBENU_STATS_P8(ale_unknown_bcast_bytes),
  1484. GBENU_STATS_P8(ale_pol_match),
  1485. GBENU_STATS_P8(ale_pol_match_red),
  1486. GBENU_STATS_P8(ale_pol_match_yellow),
  1487. GBENU_STATS_P8(tx_mem_protect_err),
  1488. GBENU_STATS_P8(tx_pri0_drop),
  1489. GBENU_STATS_P8(tx_pri1_drop),
  1490. GBENU_STATS_P8(tx_pri2_drop),
  1491. GBENU_STATS_P8(tx_pri3_drop),
  1492. GBENU_STATS_P8(tx_pri4_drop),
  1493. GBENU_STATS_P8(tx_pri5_drop),
  1494. GBENU_STATS_P8(tx_pri6_drop),
  1495. GBENU_STATS_P8(tx_pri7_drop),
  1496. GBENU_STATS_P8(tx_pri0_drop_bcnt),
  1497. GBENU_STATS_P8(tx_pri1_drop_bcnt),
  1498. GBENU_STATS_P8(tx_pri2_drop_bcnt),
  1499. GBENU_STATS_P8(tx_pri3_drop_bcnt),
  1500. GBENU_STATS_P8(tx_pri4_drop_bcnt),
  1501. GBENU_STATS_P8(tx_pri5_drop_bcnt),
  1502. GBENU_STATS_P8(tx_pri6_drop_bcnt),
  1503. GBENU_STATS_P8(tx_pri7_drop_bcnt),
  1504. };
  1505. #define XGBE_STATS0_INFO(field) \
  1506. { \
  1507. "GBE_0:"#field, XGBE_STATS0_MODULE, \
  1508. FIELD_SIZEOF(struct xgbe_hw_stats, field), \
  1509. offsetof(struct xgbe_hw_stats, field) \
  1510. }
  1511. #define XGBE_STATS1_INFO(field) \
  1512. { \
  1513. "GBE_1:"#field, XGBE_STATS1_MODULE, \
  1514. FIELD_SIZEOF(struct xgbe_hw_stats, field), \
  1515. offsetof(struct xgbe_hw_stats, field) \
  1516. }
  1517. #define XGBE_STATS2_INFO(field) \
  1518. { \
  1519. "GBE_2:"#field, XGBE_STATS2_MODULE, \
  1520. FIELD_SIZEOF(struct xgbe_hw_stats, field), \
  1521. offsetof(struct xgbe_hw_stats, field) \
  1522. }
  1523. static const struct netcp_ethtool_stat xgbe10_et_stats[] = {
  1524. /* GBE module 0 */
  1525. XGBE_STATS0_INFO(rx_good_frames),
  1526. XGBE_STATS0_INFO(rx_broadcast_frames),
  1527. XGBE_STATS0_INFO(rx_multicast_frames),
  1528. XGBE_STATS0_INFO(rx_oversized_frames),
  1529. XGBE_STATS0_INFO(rx_undersized_frames),
  1530. XGBE_STATS0_INFO(overrun_type4),
  1531. XGBE_STATS0_INFO(overrun_type5),
  1532. XGBE_STATS0_INFO(rx_bytes),
  1533. XGBE_STATS0_INFO(tx_good_frames),
  1534. XGBE_STATS0_INFO(tx_broadcast_frames),
  1535. XGBE_STATS0_INFO(tx_multicast_frames),
  1536. XGBE_STATS0_INFO(tx_bytes),
  1537. XGBE_STATS0_INFO(tx_64byte_frames),
  1538. XGBE_STATS0_INFO(tx_65_to_127byte_frames),
  1539. XGBE_STATS0_INFO(tx_128_to_255byte_frames),
  1540. XGBE_STATS0_INFO(tx_256_to_511byte_frames),
  1541. XGBE_STATS0_INFO(tx_512_to_1023byte_frames),
  1542. XGBE_STATS0_INFO(tx_1024byte_frames),
  1543. XGBE_STATS0_INFO(net_bytes),
  1544. XGBE_STATS0_INFO(rx_sof_overruns),
  1545. XGBE_STATS0_INFO(rx_mof_overruns),
  1546. XGBE_STATS0_INFO(rx_dma_overruns),
  1547. /* XGBE module 1 */
  1548. XGBE_STATS1_INFO(rx_good_frames),
  1549. XGBE_STATS1_INFO(rx_broadcast_frames),
  1550. XGBE_STATS1_INFO(rx_multicast_frames),
  1551. XGBE_STATS1_INFO(rx_pause_frames),
  1552. XGBE_STATS1_INFO(rx_crc_errors),
  1553. XGBE_STATS1_INFO(rx_align_code_errors),
  1554. XGBE_STATS1_INFO(rx_oversized_frames),
  1555. XGBE_STATS1_INFO(rx_jabber_frames),
  1556. XGBE_STATS1_INFO(rx_undersized_frames),
  1557. XGBE_STATS1_INFO(rx_fragments),
  1558. XGBE_STATS1_INFO(overrun_type4),
  1559. XGBE_STATS1_INFO(overrun_type5),
  1560. XGBE_STATS1_INFO(rx_bytes),
  1561. XGBE_STATS1_INFO(tx_good_frames),
  1562. XGBE_STATS1_INFO(tx_broadcast_frames),
  1563. XGBE_STATS1_INFO(tx_multicast_frames),
  1564. XGBE_STATS1_INFO(tx_pause_frames),
  1565. XGBE_STATS1_INFO(tx_deferred_frames),
  1566. XGBE_STATS1_INFO(tx_collision_frames),
  1567. XGBE_STATS1_INFO(tx_single_coll_frames),
  1568. XGBE_STATS1_INFO(tx_mult_coll_frames),
  1569. XGBE_STATS1_INFO(tx_excessive_collisions),
  1570. XGBE_STATS1_INFO(tx_late_collisions),
  1571. XGBE_STATS1_INFO(tx_underrun),
  1572. XGBE_STATS1_INFO(tx_carrier_sense_errors),
  1573. XGBE_STATS1_INFO(tx_bytes),
  1574. XGBE_STATS1_INFO(tx_64byte_frames),
  1575. XGBE_STATS1_INFO(tx_65_to_127byte_frames),
  1576. XGBE_STATS1_INFO(tx_128_to_255byte_frames),
  1577. XGBE_STATS1_INFO(tx_256_to_511byte_frames),
  1578. XGBE_STATS1_INFO(tx_512_to_1023byte_frames),
  1579. XGBE_STATS1_INFO(tx_1024byte_frames),
  1580. XGBE_STATS1_INFO(net_bytes),
  1581. XGBE_STATS1_INFO(rx_sof_overruns),
  1582. XGBE_STATS1_INFO(rx_mof_overruns),
  1583. XGBE_STATS1_INFO(rx_dma_overruns),
  1584. /* XGBE module 2 */
  1585. XGBE_STATS2_INFO(rx_good_frames),
  1586. XGBE_STATS2_INFO(rx_broadcast_frames),
  1587. XGBE_STATS2_INFO(rx_multicast_frames),
  1588. XGBE_STATS2_INFO(rx_pause_frames),
  1589. XGBE_STATS2_INFO(rx_crc_errors),
  1590. XGBE_STATS2_INFO(rx_align_code_errors),
  1591. XGBE_STATS2_INFO(rx_oversized_frames),
  1592. XGBE_STATS2_INFO(rx_jabber_frames),
  1593. XGBE_STATS2_INFO(rx_undersized_frames),
  1594. XGBE_STATS2_INFO(rx_fragments),
  1595. XGBE_STATS2_INFO(overrun_type4),
  1596. XGBE_STATS2_INFO(overrun_type5),
  1597. XGBE_STATS2_INFO(rx_bytes),
  1598. XGBE_STATS2_INFO(tx_good_frames),
  1599. XGBE_STATS2_INFO(tx_broadcast_frames),
  1600. XGBE_STATS2_INFO(tx_multicast_frames),
  1601. XGBE_STATS2_INFO(tx_pause_frames),
  1602. XGBE_STATS2_INFO(tx_deferred_frames),
  1603. XGBE_STATS2_INFO(tx_collision_frames),
  1604. XGBE_STATS2_INFO(tx_single_coll_frames),
  1605. XGBE_STATS2_INFO(tx_mult_coll_frames),
  1606. XGBE_STATS2_INFO(tx_excessive_collisions),
  1607. XGBE_STATS2_INFO(tx_late_collisions),
  1608. XGBE_STATS2_INFO(tx_underrun),
  1609. XGBE_STATS2_INFO(tx_carrier_sense_errors),
  1610. XGBE_STATS2_INFO(tx_bytes),
  1611. XGBE_STATS2_INFO(tx_64byte_frames),
  1612. XGBE_STATS2_INFO(tx_65_to_127byte_frames),
  1613. XGBE_STATS2_INFO(tx_128_to_255byte_frames),
  1614. XGBE_STATS2_INFO(tx_256_to_511byte_frames),
  1615. XGBE_STATS2_INFO(tx_512_to_1023byte_frames),
  1616. XGBE_STATS2_INFO(tx_1024byte_frames),
  1617. XGBE_STATS2_INFO(net_bytes),
  1618. XGBE_STATS2_INFO(rx_sof_overruns),
  1619. XGBE_STATS2_INFO(rx_mof_overruns),
  1620. XGBE_STATS2_INFO(rx_dma_overruns),
  1621. };
  1622. #define for_each_intf(i, priv) \
  1623. list_for_each_entry((i), &(priv)->gbe_intf_head, gbe_intf_list)
  1624. #define for_each_sec_slave(slave, priv) \
  1625. list_for_each_entry((slave), &(priv)->secondary_slaves, slave_list)
  1626. #define first_sec_slave(priv) \
  1627. list_first_entry(&priv->secondary_slaves, \
  1628. struct gbe_slave, slave_list)
  1629. static void keystone_get_drvinfo(struct net_device *ndev,
  1630. struct ethtool_drvinfo *info)
  1631. {
  1632. strncpy(info->driver, NETCP_DRIVER_NAME, sizeof(info->driver));
  1633. strncpy(info->version, NETCP_DRIVER_VERSION, sizeof(info->version));
  1634. }
  1635. static u32 keystone_get_msglevel(struct net_device *ndev)
  1636. {
  1637. struct netcp_intf *netcp = netdev_priv(ndev);
  1638. return netcp->msg_enable;
  1639. }
  1640. static void keystone_set_msglevel(struct net_device *ndev, u32 value)
  1641. {
  1642. struct netcp_intf *netcp = netdev_priv(ndev);
  1643. netcp->msg_enable = value;
  1644. }
  1645. static struct gbe_intf *keystone_get_intf_data(struct netcp_intf *netcp)
  1646. {
  1647. struct gbe_intf *gbe_intf;
  1648. gbe_intf = netcp_module_get_intf_data(&gbe_module, netcp);
  1649. if (!gbe_intf)
  1650. gbe_intf = netcp_module_get_intf_data(&xgbe_module, netcp);
  1651. return gbe_intf;
  1652. }
  1653. static void keystone_get_stat_strings(struct net_device *ndev,
  1654. uint32_t stringset, uint8_t *data)
  1655. {
  1656. struct netcp_intf *netcp = netdev_priv(ndev);
  1657. struct gbe_intf *gbe_intf;
  1658. struct gbe_priv *gbe_dev;
  1659. int i;
  1660. gbe_intf = keystone_get_intf_data(netcp);
  1661. if (!gbe_intf)
  1662. return;
  1663. gbe_dev = gbe_intf->gbe_dev;
  1664. switch (stringset) {
  1665. case ETH_SS_STATS:
  1666. for (i = 0; i < gbe_dev->num_et_stats; i++) {
  1667. memcpy(data, gbe_dev->et_stats[i].desc,
  1668. ETH_GSTRING_LEN);
  1669. data += ETH_GSTRING_LEN;
  1670. }
  1671. break;
  1672. case ETH_SS_TEST:
  1673. break;
  1674. }
  1675. }
  1676. static int keystone_get_sset_count(struct net_device *ndev, int stringset)
  1677. {
  1678. struct netcp_intf *netcp = netdev_priv(ndev);
  1679. struct gbe_intf *gbe_intf;
  1680. struct gbe_priv *gbe_dev;
  1681. gbe_intf = keystone_get_intf_data(netcp);
  1682. if (!gbe_intf)
  1683. return -EINVAL;
  1684. gbe_dev = gbe_intf->gbe_dev;
  1685. switch (stringset) {
  1686. case ETH_SS_TEST:
  1687. return 0;
  1688. case ETH_SS_STATS:
  1689. return gbe_dev->num_et_stats;
  1690. default:
  1691. return -EINVAL;
  1692. }
  1693. }
  1694. static void gbe_reset_mod_stats(struct gbe_priv *gbe_dev, int stats_mod)
  1695. {
  1696. void __iomem *base = gbe_dev->hw_stats_regs[stats_mod];
  1697. u32 __iomem *p_stats_entry;
  1698. int i;
  1699. for (i = 0; i < gbe_dev->num_et_stats; i++) {
  1700. if (gbe_dev->et_stats[i].type == stats_mod) {
  1701. p_stats_entry = base + gbe_dev->et_stats[i].offset;
  1702. gbe_dev->hw_stats[i] = 0;
  1703. gbe_dev->hw_stats_prev[i] = readl(p_stats_entry);
  1704. }
  1705. }
  1706. }
  1707. static inline void gbe_update_hw_stats_entry(struct gbe_priv *gbe_dev,
  1708. int et_stats_entry)
  1709. {
  1710. void __iomem *base = NULL;
  1711. u32 __iomem *p_stats_entry;
  1712. u32 curr, delta;
  1713. /* The hw_stats_regs pointers are already
  1714. * properly set to point to the right base:
  1715. */
  1716. base = gbe_dev->hw_stats_regs[gbe_dev->et_stats[et_stats_entry].type];
  1717. p_stats_entry = base + gbe_dev->et_stats[et_stats_entry].offset;
  1718. curr = readl(p_stats_entry);
  1719. delta = curr - gbe_dev->hw_stats_prev[et_stats_entry];
  1720. gbe_dev->hw_stats_prev[et_stats_entry] = curr;
  1721. gbe_dev->hw_stats[et_stats_entry] += delta;
  1722. }
  1723. static void gbe_update_stats(struct gbe_priv *gbe_dev, uint64_t *data)
  1724. {
  1725. int i;
  1726. for (i = 0; i < gbe_dev->num_et_stats; i++) {
  1727. gbe_update_hw_stats_entry(gbe_dev, i);
  1728. if (data)
  1729. data[i] = gbe_dev->hw_stats[i];
  1730. }
  1731. }
  1732. static inline void gbe_stats_mod_visible_ver14(struct gbe_priv *gbe_dev,
  1733. int stats_mod)
  1734. {
  1735. u32 val;
  1736. val = readl(GBE_REG_ADDR(gbe_dev, switch_regs, stat_port_en));
  1737. switch (stats_mod) {
  1738. case GBE_STATSA_MODULE:
  1739. case GBE_STATSB_MODULE:
  1740. val &= ~GBE_STATS_CD_SEL;
  1741. break;
  1742. case GBE_STATSC_MODULE:
  1743. case GBE_STATSD_MODULE:
  1744. val |= GBE_STATS_CD_SEL;
  1745. break;
  1746. default:
  1747. return;
  1748. }
  1749. /* make the stat module visible */
  1750. writel(val, GBE_REG_ADDR(gbe_dev, switch_regs, stat_port_en));
  1751. }
  1752. static void gbe_reset_mod_stats_ver14(struct gbe_priv *gbe_dev, int stats_mod)
  1753. {
  1754. gbe_stats_mod_visible_ver14(gbe_dev, stats_mod);
  1755. gbe_reset_mod_stats(gbe_dev, stats_mod);
  1756. }
  1757. static void gbe_update_stats_ver14(struct gbe_priv *gbe_dev, uint64_t *data)
  1758. {
  1759. u32 half_num_et_stats = (gbe_dev->num_et_stats / 2);
  1760. int et_entry, j, pair;
  1761. for (pair = 0; pair < 2; pair++) {
  1762. gbe_stats_mod_visible_ver14(gbe_dev, (pair ?
  1763. GBE_STATSC_MODULE :
  1764. GBE_STATSA_MODULE));
  1765. for (j = 0; j < half_num_et_stats; j++) {
  1766. et_entry = pair * half_num_et_stats + j;
  1767. gbe_update_hw_stats_entry(gbe_dev, et_entry);
  1768. if (data)
  1769. data[et_entry] = gbe_dev->hw_stats[et_entry];
  1770. }
  1771. }
  1772. }
  1773. static void keystone_get_ethtool_stats(struct net_device *ndev,
  1774. struct ethtool_stats *stats,
  1775. uint64_t *data)
  1776. {
  1777. struct netcp_intf *netcp = netdev_priv(ndev);
  1778. struct gbe_intf *gbe_intf;
  1779. struct gbe_priv *gbe_dev;
  1780. gbe_intf = keystone_get_intf_data(netcp);
  1781. if (!gbe_intf)
  1782. return;
  1783. gbe_dev = gbe_intf->gbe_dev;
  1784. spin_lock_bh(&gbe_dev->hw_stats_lock);
  1785. if (gbe_dev->ss_version == GBE_SS_VERSION_14)
  1786. gbe_update_stats_ver14(gbe_dev, data);
  1787. else
  1788. gbe_update_stats(gbe_dev, data);
  1789. spin_unlock_bh(&gbe_dev->hw_stats_lock);
  1790. }
  1791. static int keystone_get_link_ksettings(struct net_device *ndev,
  1792. struct ethtool_link_ksettings *cmd)
  1793. {
  1794. struct netcp_intf *netcp = netdev_priv(ndev);
  1795. struct phy_device *phy = ndev->phydev;
  1796. struct gbe_intf *gbe_intf;
  1797. int ret;
  1798. if (!phy)
  1799. return -EINVAL;
  1800. gbe_intf = keystone_get_intf_data(netcp);
  1801. if (!gbe_intf)
  1802. return -EINVAL;
  1803. if (!gbe_intf->slave)
  1804. return -EINVAL;
  1805. ret = phy_ethtool_ksettings_get(phy, cmd);
  1806. if (!ret)
  1807. cmd->base.port = gbe_intf->slave->phy_port_t;
  1808. return ret;
  1809. }
  1810. static int keystone_set_link_ksettings(struct net_device *ndev,
  1811. const struct ethtool_link_ksettings *cmd)
  1812. {
  1813. struct netcp_intf *netcp = netdev_priv(ndev);
  1814. struct phy_device *phy = ndev->phydev;
  1815. struct gbe_intf *gbe_intf;
  1816. u8 port = cmd->base.port;
  1817. u32 advertising, supported;
  1818. u32 features;
  1819. ethtool_convert_link_mode_to_legacy_u32(&advertising,
  1820. cmd->link_modes.advertising);
  1821. ethtool_convert_link_mode_to_legacy_u32(&supported,
  1822. cmd->link_modes.supported);
  1823. features = advertising & supported;
  1824. if (!phy)
  1825. return -EINVAL;
  1826. gbe_intf = keystone_get_intf_data(netcp);
  1827. if (!gbe_intf)
  1828. return -EINVAL;
  1829. if (!gbe_intf->slave)
  1830. return -EINVAL;
  1831. if (port != gbe_intf->slave->phy_port_t) {
  1832. if ((port == PORT_TP) && !(features & ADVERTISED_TP))
  1833. return -EINVAL;
  1834. if ((port == PORT_AUI) && !(features & ADVERTISED_AUI))
  1835. return -EINVAL;
  1836. if ((port == PORT_BNC) && !(features & ADVERTISED_BNC))
  1837. return -EINVAL;
  1838. if ((port == PORT_MII) && !(features & ADVERTISED_MII))
  1839. return -EINVAL;
  1840. if ((port == PORT_FIBRE) && !(features & ADVERTISED_FIBRE))
  1841. return -EINVAL;
  1842. }
  1843. gbe_intf->slave->phy_port_t = port;
  1844. return phy_ethtool_ksettings_set(phy, cmd);
  1845. }
  1846. #if IS_ENABLED(CONFIG_TI_CPTS)
  1847. static int keystone_get_ts_info(struct net_device *ndev,
  1848. struct ethtool_ts_info *info)
  1849. {
  1850. struct netcp_intf *netcp = netdev_priv(ndev);
  1851. struct gbe_intf *gbe_intf;
  1852. gbe_intf = netcp_module_get_intf_data(&gbe_module, netcp);
  1853. if (!gbe_intf || !gbe_intf->gbe_dev->cpts)
  1854. return -EINVAL;
  1855. info->so_timestamping =
  1856. SOF_TIMESTAMPING_TX_HARDWARE |
  1857. SOF_TIMESTAMPING_TX_SOFTWARE |
  1858. SOF_TIMESTAMPING_RX_HARDWARE |
  1859. SOF_TIMESTAMPING_RX_SOFTWARE |
  1860. SOF_TIMESTAMPING_SOFTWARE |
  1861. SOF_TIMESTAMPING_RAW_HARDWARE;
  1862. info->phc_index = gbe_intf->gbe_dev->cpts->phc_index;
  1863. info->tx_types =
  1864. (1 << HWTSTAMP_TX_OFF) |
  1865. (1 << HWTSTAMP_TX_ON);
  1866. info->rx_filters =
  1867. (1 << HWTSTAMP_FILTER_NONE) |
  1868. (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
  1869. (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
  1870. return 0;
  1871. }
  1872. #else
  1873. static int keystone_get_ts_info(struct net_device *ndev,
  1874. struct ethtool_ts_info *info)
  1875. {
  1876. info->so_timestamping =
  1877. SOF_TIMESTAMPING_TX_SOFTWARE |
  1878. SOF_TIMESTAMPING_RX_SOFTWARE |
  1879. SOF_TIMESTAMPING_SOFTWARE;
  1880. info->phc_index = -1;
  1881. info->tx_types = 0;
  1882. info->rx_filters = 0;
  1883. return 0;
  1884. }
  1885. #endif /* CONFIG_TI_CPTS */
  1886. static const struct ethtool_ops keystone_ethtool_ops = {
  1887. .get_drvinfo = keystone_get_drvinfo,
  1888. .get_link = ethtool_op_get_link,
  1889. .get_msglevel = keystone_get_msglevel,
  1890. .set_msglevel = keystone_set_msglevel,
  1891. .get_strings = keystone_get_stat_strings,
  1892. .get_sset_count = keystone_get_sset_count,
  1893. .get_ethtool_stats = keystone_get_ethtool_stats,
  1894. .get_link_ksettings = keystone_get_link_ksettings,
  1895. .set_link_ksettings = keystone_set_link_ksettings,
  1896. .get_ts_info = keystone_get_ts_info,
  1897. };
  1898. #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
  1899. ((mac)[2] << 16) | ((mac)[3] << 24))
  1900. #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
  1901. static void gbe_set_slave_mac(struct gbe_slave *slave,
  1902. struct gbe_intf *gbe_intf)
  1903. {
  1904. struct net_device *ndev = gbe_intf->ndev;
  1905. writel(mac_hi(ndev->dev_addr), GBE_REG_ADDR(slave, port_regs, sa_hi));
  1906. writel(mac_lo(ndev->dev_addr), GBE_REG_ADDR(slave, port_regs, sa_lo));
  1907. }
  1908. static int gbe_get_slave_port(struct gbe_priv *priv, u32 slave_num)
  1909. {
  1910. if (priv->host_port == 0)
  1911. return slave_num + 1;
  1912. return slave_num;
  1913. }
  1914. static void netcp_ethss_link_state_action(struct gbe_priv *gbe_dev,
  1915. struct net_device *ndev,
  1916. struct gbe_slave *slave,
  1917. int up)
  1918. {
  1919. struct phy_device *phy = slave->phy;
  1920. u32 mac_control = 0;
  1921. if (up) {
  1922. mac_control = slave->mac_control;
  1923. if (phy && (phy->speed == SPEED_1000)) {
  1924. mac_control |= MACSL_GIG_MODE;
  1925. mac_control &= ~MACSL_XGIG_MODE;
  1926. } else if (phy && (phy->speed == SPEED_10000)) {
  1927. mac_control |= MACSL_XGIG_MODE;
  1928. mac_control &= ~MACSL_GIG_MODE;
  1929. }
  1930. writel(mac_control, GBE_REG_ADDR(slave, emac_regs,
  1931. mac_control));
  1932. cpsw_ale_control_set(gbe_dev->ale, slave->port_num,
  1933. ALE_PORT_STATE,
  1934. ALE_PORT_STATE_FORWARD);
  1935. if (ndev && slave->open &&
  1936. slave->link_interface != SGMII_LINK_MAC_PHY &&
  1937. slave->link_interface != XGMII_LINK_MAC_PHY)
  1938. netif_carrier_on(ndev);
  1939. } else {
  1940. writel(mac_control, GBE_REG_ADDR(slave, emac_regs,
  1941. mac_control));
  1942. cpsw_ale_control_set(gbe_dev->ale, slave->port_num,
  1943. ALE_PORT_STATE,
  1944. ALE_PORT_STATE_DISABLE);
  1945. if (ndev &&
  1946. slave->link_interface != SGMII_LINK_MAC_PHY &&
  1947. slave->link_interface != XGMII_LINK_MAC_PHY)
  1948. netif_carrier_off(ndev);
  1949. }
  1950. if (phy)
  1951. phy_print_status(phy);
  1952. }
  1953. static bool gbe_phy_link_status(struct gbe_slave *slave)
  1954. {
  1955. return !slave->phy || slave->phy->link;
  1956. }
  1957. static void netcp_ethss_update_link_state(struct gbe_priv *gbe_dev,
  1958. struct gbe_slave *slave,
  1959. struct net_device *ndev)
  1960. {
  1961. int sp = slave->slave_num;
  1962. int phy_link_state, sgmii_link_state = 1, link_state;
  1963. if (!slave->open)
  1964. return;
  1965. if (!SLAVE_LINK_IS_XGMII(slave)) {
  1966. sgmii_link_state =
  1967. netcp_sgmii_get_port_link(SGMII_BASE(gbe_dev, sp), sp);
  1968. }
  1969. phy_link_state = gbe_phy_link_status(slave);
  1970. link_state = phy_link_state & sgmii_link_state;
  1971. if (atomic_xchg(&slave->link_state, link_state) != link_state)
  1972. netcp_ethss_link_state_action(gbe_dev, ndev, slave,
  1973. link_state);
  1974. }
  1975. static void xgbe_adjust_link(struct net_device *ndev)
  1976. {
  1977. struct netcp_intf *netcp = netdev_priv(ndev);
  1978. struct gbe_intf *gbe_intf;
  1979. gbe_intf = netcp_module_get_intf_data(&xgbe_module, netcp);
  1980. if (!gbe_intf)
  1981. return;
  1982. netcp_ethss_update_link_state(gbe_intf->gbe_dev, gbe_intf->slave,
  1983. ndev);
  1984. }
  1985. static void gbe_adjust_link(struct net_device *ndev)
  1986. {
  1987. struct netcp_intf *netcp = netdev_priv(ndev);
  1988. struct gbe_intf *gbe_intf;
  1989. gbe_intf = netcp_module_get_intf_data(&gbe_module, netcp);
  1990. if (!gbe_intf)
  1991. return;
  1992. netcp_ethss_update_link_state(gbe_intf->gbe_dev, gbe_intf->slave,
  1993. ndev);
  1994. }
  1995. static void gbe_adjust_link_sec_slaves(struct net_device *ndev)
  1996. {
  1997. struct gbe_priv *gbe_dev = netdev_priv(ndev);
  1998. struct gbe_slave *slave;
  1999. for_each_sec_slave(slave, gbe_dev)
  2000. netcp_ethss_update_link_state(gbe_dev, slave, NULL);
  2001. }
  2002. /* Reset EMAC
  2003. * Soft reset is set and polled until clear, or until a timeout occurs
  2004. */
  2005. static int gbe_port_reset(struct gbe_slave *slave)
  2006. {
  2007. u32 i, v;
  2008. /* Set the soft reset bit */
  2009. writel(SOFT_RESET, GBE_REG_ADDR(slave, emac_regs, soft_reset));
  2010. /* Wait for the bit to clear */
  2011. for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
  2012. v = readl(GBE_REG_ADDR(slave, emac_regs, soft_reset));
  2013. if ((v & SOFT_RESET_MASK) != SOFT_RESET)
  2014. return 0;
  2015. }
  2016. /* Timeout on the reset */
  2017. return GMACSL_RET_WARN_RESET_INCOMPLETE;
  2018. }
  2019. /* Configure EMAC */
  2020. static void gbe_port_config(struct gbe_priv *gbe_dev, struct gbe_slave *slave,
  2021. int max_rx_len)
  2022. {
  2023. void __iomem *rx_maxlen_reg;
  2024. u32 xgmii_mode;
  2025. if (max_rx_len > NETCP_MAX_FRAME_SIZE)
  2026. max_rx_len = NETCP_MAX_FRAME_SIZE;
  2027. /* Enable correct MII mode at SS level */
  2028. if ((gbe_dev->ss_version == XGBE_SS_VERSION_10) &&
  2029. (slave->link_interface >= XGMII_LINK_MAC_PHY)) {
  2030. xgmii_mode = readl(GBE_REG_ADDR(gbe_dev, ss_regs, control));
  2031. xgmii_mode |= (1 << slave->slave_num);
  2032. writel(xgmii_mode, GBE_REG_ADDR(gbe_dev, ss_regs, control));
  2033. }
  2034. if (IS_SS_ID_MU(gbe_dev))
  2035. rx_maxlen_reg = GBE_REG_ADDR(slave, port_regs, rx_maxlen);
  2036. else
  2037. rx_maxlen_reg = GBE_REG_ADDR(slave, emac_regs, rx_maxlen);
  2038. writel(max_rx_len, rx_maxlen_reg);
  2039. writel(slave->mac_control, GBE_REG_ADDR(slave, emac_regs, mac_control));
  2040. }
  2041. static void gbe_sgmii_rtreset(struct gbe_priv *priv,
  2042. struct gbe_slave *slave, bool set)
  2043. {
  2044. if (SLAVE_LINK_IS_XGMII(slave))
  2045. return;
  2046. netcp_sgmii_rtreset(SGMII_BASE(priv, slave->slave_num),
  2047. slave->slave_num, set);
  2048. }
  2049. static void gbe_slave_stop(struct gbe_intf *intf)
  2050. {
  2051. struct gbe_priv *gbe_dev = intf->gbe_dev;
  2052. struct gbe_slave *slave = intf->slave;
  2053. gbe_sgmii_rtreset(gbe_dev, slave, true);
  2054. gbe_port_reset(slave);
  2055. /* Disable forwarding */
  2056. cpsw_ale_control_set(gbe_dev->ale, slave->port_num,
  2057. ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
  2058. cpsw_ale_del_mcast(gbe_dev->ale, intf->ndev->broadcast,
  2059. 1 << slave->port_num, 0, 0);
  2060. if (!slave->phy)
  2061. return;
  2062. phy_stop(slave->phy);
  2063. phy_disconnect(slave->phy);
  2064. slave->phy = NULL;
  2065. }
  2066. static void gbe_sgmii_config(struct gbe_priv *priv, struct gbe_slave *slave)
  2067. {
  2068. if (SLAVE_LINK_IS_XGMII(slave))
  2069. return;
  2070. netcp_sgmii_reset(SGMII_BASE(priv, slave->slave_num), slave->slave_num);
  2071. netcp_sgmii_config(SGMII_BASE(priv, slave->slave_num), slave->slave_num,
  2072. slave->link_interface);
  2073. }
  2074. static int gbe_slave_open(struct gbe_intf *gbe_intf)
  2075. {
  2076. struct gbe_priv *priv = gbe_intf->gbe_dev;
  2077. struct gbe_slave *slave = gbe_intf->slave;
  2078. phy_interface_t phy_mode;
  2079. bool has_phy = false;
  2080. void (*hndlr)(struct net_device *) = gbe_adjust_link;
  2081. gbe_sgmii_config(priv, slave);
  2082. gbe_port_reset(slave);
  2083. gbe_sgmii_rtreset(priv, slave, false);
  2084. gbe_port_config(priv, slave, priv->rx_packet_max);
  2085. gbe_set_slave_mac(slave, gbe_intf);
  2086. /* enable forwarding */
  2087. cpsw_ale_control_set(priv->ale, slave->port_num,
  2088. ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
  2089. cpsw_ale_add_mcast(priv->ale, gbe_intf->ndev->broadcast,
  2090. 1 << slave->port_num, 0, 0, ALE_MCAST_FWD_2);
  2091. if (slave->link_interface == SGMII_LINK_MAC_PHY) {
  2092. has_phy = true;
  2093. phy_mode = PHY_INTERFACE_MODE_SGMII;
  2094. slave->phy_port_t = PORT_MII;
  2095. } else if (slave->link_interface == XGMII_LINK_MAC_PHY) {
  2096. has_phy = true;
  2097. phy_mode = PHY_INTERFACE_MODE_NA;
  2098. slave->phy_port_t = PORT_FIBRE;
  2099. }
  2100. if (has_phy) {
  2101. if (priv->ss_version == XGBE_SS_VERSION_10)
  2102. hndlr = xgbe_adjust_link;
  2103. slave->phy = of_phy_connect(gbe_intf->ndev,
  2104. slave->phy_node,
  2105. hndlr, 0,
  2106. phy_mode);
  2107. if (!slave->phy) {
  2108. dev_err(priv->dev, "phy not found on slave %d\n",
  2109. slave->slave_num);
  2110. return -ENODEV;
  2111. }
  2112. dev_dbg(priv->dev, "phy found: id is: 0x%s\n",
  2113. phydev_name(slave->phy));
  2114. phy_start(slave->phy);
  2115. phy_read_status(slave->phy);
  2116. }
  2117. return 0;
  2118. }
  2119. static void gbe_init_host_port(struct gbe_priv *priv)
  2120. {
  2121. int bypass_en = 1;
  2122. /* Host Tx Pri */
  2123. if (IS_SS_ID_NU(priv) || IS_SS_ID_XGBE(priv))
  2124. writel(HOST_TX_PRI_MAP_DEFAULT,
  2125. GBE_REG_ADDR(priv, host_port_regs, tx_pri_map));
  2126. /* Max length register */
  2127. writel(NETCP_MAX_FRAME_SIZE, GBE_REG_ADDR(priv, host_port_regs,
  2128. rx_maxlen));
  2129. cpsw_ale_start(priv->ale);
  2130. if (priv->enable_ale)
  2131. bypass_en = 0;
  2132. cpsw_ale_control_set(priv->ale, 0, ALE_BYPASS, bypass_en);
  2133. cpsw_ale_control_set(priv->ale, 0, ALE_NO_PORT_VLAN, 1);
  2134. cpsw_ale_control_set(priv->ale, priv->host_port,
  2135. ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
  2136. cpsw_ale_control_set(priv->ale, 0,
  2137. ALE_PORT_UNKNOWN_VLAN_MEMBER,
  2138. GBE_PORT_MASK(priv->ale_ports));
  2139. cpsw_ale_control_set(priv->ale, 0,
  2140. ALE_PORT_UNKNOWN_MCAST_FLOOD,
  2141. GBE_PORT_MASK(priv->ale_ports - 1));
  2142. cpsw_ale_control_set(priv->ale, 0,
  2143. ALE_PORT_UNKNOWN_REG_MCAST_FLOOD,
  2144. GBE_PORT_MASK(priv->ale_ports));
  2145. cpsw_ale_control_set(priv->ale, 0,
  2146. ALE_PORT_UNTAGGED_EGRESS,
  2147. GBE_PORT_MASK(priv->ale_ports));
  2148. }
  2149. static void gbe_add_mcast_addr(struct gbe_intf *gbe_intf, u8 *addr)
  2150. {
  2151. struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
  2152. u16 vlan_id;
  2153. cpsw_ale_add_mcast(gbe_dev->ale, addr,
  2154. GBE_PORT_MASK(gbe_dev->ale_ports), 0, 0,
  2155. ALE_MCAST_FWD_2);
  2156. for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID) {
  2157. cpsw_ale_add_mcast(gbe_dev->ale, addr,
  2158. GBE_PORT_MASK(gbe_dev->ale_ports),
  2159. ALE_VLAN, vlan_id, ALE_MCAST_FWD_2);
  2160. }
  2161. }
  2162. static void gbe_add_ucast_addr(struct gbe_intf *gbe_intf, u8 *addr)
  2163. {
  2164. struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
  2165. u16 vlan_id;
  2166. cpsw_ale_add_ucast(gbe_dev->ale, addr, gbe_dev->host_port, 0, 0);
  2167. for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID)
  2168. cpsw_ale_add_ucast(gbe_dev->ale, addr, gbe_dev->host_port,
  2169. ALE_VLAN, vlan_id);
  2170. }
  2171. static void gbe_del_mcast_addr(struct gbe_intf *gbe_intf, u8 *addr)
  2172. {
  2173. struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
  2174. u16 vlan_id;
  2175. cpsw_ale_del_mcast(gbe_dev->ale, addr, 0, 0, 0);
  2176. for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID) {
  2177. cpsw_ale_del_mcast(gbe_dev->ale, addr, 0, ALE_VLAN, vlan_id);
  2178. }
  2179. }
  2180. static void gbe_del_ucast_addr(struct gbe_intf *gbe_intf, u8 *addr)
  2181. {
  2182. struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
  2183. u16 vlan_id;
  2184. cpsw_ale_del_ucast(gbe_dev->ale, addr, gbe_dev->host_port, 0, 0);
  2185. for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID) {
  2186. cpsw_ale_del_ucast(gbe_dev->ale, addr, gbe_dev->host_port,
  2187. ALE_VLAN, vlan_id);
  2188. }
  2189. }
  2190. static int gbe_add_addr(void *intf_priv, struct netcp_addr *naddr)
  2191. {
  2192. struct gbe_intf *gbe_intf = intf_priv;
  2193. struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
  2194. dev_dbg(gbe_dev->dev, "ethss adding address %pM, type %d\n",
  2195. naddr->addr, naddr->type);
  2196. switch (naddr->type) {
  2197. case ADDR_MCAST:
  2198. case ADDR_BCAST:
  2199. gbe_add_mcast_addr(gbe_intf, naddr->addr);
  2200. break;
  2201. case ADDR_UCAST:
  2202. case ADDR_DEV:
  2203. gbe_add_ucast_addr(gbe_intf, naddr->addr);
  2204. break;
  2205. case ADDR_ANY:
  2206. /* nothing to do for promiscuous */
  2207. default:
  2208. break;
  2209. }
  2210. return 0;
  2211. }
  2212. static int gbe_del_addr(void *intf_priv, struct netcp_addr *naddr)
  2213. {
  2214. struct gbe_intf *gbe_intf = intf_priv;
  2215. struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
  2216. dev_dbg(gbe_dev->dev, "ethss deleting address %pM, type %d\n",
  2217. naddr->addr, naddr->type);
  2218. switch (naddr->type) {
  2219. case ADDR_MCAST:
  2220. case ADDR_BCAST:
  2221. gbe_del_mcast_addr(gbe_intf, naddr->addr);
  2222. break;
  2223. case ADDR_UCAST:
  2224. case ADDR_DEV:
  2225. gbe_del_ucast_addr(gbe_intf, naddr->addr);
  2226. break;
  2227. case ADDR_ANY:
  2228. /* nothing to do for promiscuous */
  2229. default:
  2230. break;
  2231. }
  2232. return 0;
  2233. }
  2234. static int gbe_add_vid(void *intf_priv, int vid)
  2235. {
  2236. struct gbe_intf *gbe_intf = intf_priv;
  2237. struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
  2238. set_bit(vid, gbe_intf->active_vlans);
  2239. cpsw_ale_add_vlan(gbe_dev->ale, vid,
  2240. GBE_PORT_MASK(gbe_dev->ale_ports),
  2241. GBE_MASK_NO_PORTS,
  2242. GBE_PORT_MASK(gbe_dev->ale_ports),
  2243. GBE_PORT_MASK(gbe_dev->ale_ports - 1));
  2244. return 0;
  2245. }
  2246. static int gbe_del_vid(void *intf_priv, int vid)
  2247. {
  2248. struct gbe_intf *gbe_intf = intf_priv;
  2249. struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
  2250. cpsw_ale_del_vlan(gbe_dev->ale, vid, 0);
  2251. clear_bit(vid, gbe_intf->active_vlans);
  2252. return 0;
  2253. }
  2254. #if IS_ENABLED(CONFIG_TI_CPTS)
  2255. #define HAS_PHY_TXTSTAMP(p) ((p)->drv && (p)->drv->txtstamp)
  2256. #define HAS_PHY_RXTSTAMP(p) ((p)->drv && (p)->drv->rxtstamp)
  2257. static void gbe_txtstamp(void *context, struct sk_buff *skb)
  2258. {
  2259. struct gbe_intf *gbe_intf = context;
  2260. struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
  2261. cpts_tx_timestamp(gbe_dev->cpts, skb);
  2262. }
  2263. static bool gbe_need_txtstamp(struct gbe_intf *gbe_intf,
  2264. const struct netcp_packet *p_info)
  2265. {
  2266. struct sk_buff *skb = p_info->skb;
  2267. unsigned int class = ptp_classify_raw(skb);
  2268. if (class == PTP_CLASS_NONE)
  2269. return false;
  2270. switch (class) {
  2271. case PTP_CLASS_V1_IPV4:
  2272. case PTP_CLASS_V1_IPV6:
  2273. case PTP_CLASS_V2_IPV4:
  2274. case PTP_CLASS_V2_IPV6:
  2275. case PTP_CLASS_V2_L2:
  2276. case (PTP_CLASS_V2_VLAN | PTP_CLASS_L2):
  2277. case (PTP_CLASS_V2_VLAN | PTP_CLASS_IPV4):
  2278. case (PTP_CLASS_V2_VLAN | PTP_CLASS_IPV6):
  2279. return true;
  2280. }
  2281. return false;
  2282. }
  2283. static int gbe_txtstamp_mark_pkt(struct gbe_intf *gbe_intf,
  2284. struct netcp_packet *p_info)
  2285. {
  2286. struct phy_device *phydev = p_info->skb->dev->phydev;
  2287. struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
  2288. if (!(skb_shinfo(p_info->skb)->tx_flags & SKBTX_HW_TSTAMP) ||
  2289. !cpts_is_tx_enabled(gbe_dev->cpts))
  2290. return 0;
  2291. /* If phy has the txtstamp api, assume it will do it.
  2292. * We mark it here because skb_tx_timestamp() is called
  2293. * after all the txhooks are called.
  2294. */
  2295. if (phydev && HAS_PHY_TXTSTAMP(phydev)) {
  2296. skb_shinfo(p_info->skb)->tx_flags |= SKBTX_IN_PROGRESS;
  2297. return 0;
  2298. }
  2299. if (gbe_need_txtstamp(gbe_intf, p_info)) {
  2300. p_info->txtstamp = gbe_txtstamp;
  2301. p_info->ts_context = (void *)gbe_intf;
  2302. skb_shinfo(p_info->skb)->tx_flags |= SKBTX_IN_PROGRESS;
  2303. }
  2304. return 0;
  2305. }
  2306. static int gbe_rxtstamp(struct gbe_intf *gbe_intf, struct netcp_packet *p_info)
  2307. {
  2308. struct phy_device *phydev = p_info->skb->dev->phydev;
  2309. struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
  2310. if (p_info->rxtstamp_complete)
  2311. return 0;
  2312. if (phydev && HAS_PHY_RXTSTAMP(phydev)) {
  2313. p_info->rxtstamp_complete = true;
  2314. return 0;
  2315. }
  2316. cpts_rx_timestamp(gbe_dev->cpts, p_info->skb);
  2317. p_info->rxtstamp_complete = true;
  2318. return 0;
  2319. }
  2320. static int gbe_hwtstamp_get(struct gbe_intf *gbe_intf, struct ifreq *ifr)
  2321. {
  2322. struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
  2323. struct cpts *cpts = gbe_dev->cpts;
  2324. struct hwtstamp_config cfg;
  2325. if (!cpts)
  2326. return -EOPNOTSUPP;
  2327. cfg.flags = 0;
  2328. cfg.tx_type = cpts_is_tx_enabled(cpts) ?
  2329. HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
  2330. cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
  2331. cpts->rx_enable : HWTSTAMP_FILTER_NONE);
  2332. return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
  2333. }
  2334. static void gbe_hwtstamp(struct gbe_intf *gbe_intf)
  2335. {
  2336. struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
  2337. struct gbe_slave *slave = gbe_intf->slave;
  2338. u32 ts_en, seq_id, ctl;
  2339. if (!cpts_is_rx_enabled(gbe_dev->cpts) &&
  2340. !cpts_is_tx_enabled(gbe_dev->cpts)) {
  2341. writel(0, GBE_REG_ADDR(slave, port_regs, ts_ctl));
  2342. return;
  2343. }
  2344. seq_id = (30 << TS_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
  2345. ts_en = EVENT_MSG_BITS << TS_MSG_TYPE_EN_SHIFT;
  2346. ctl = ETH_P_1588 | TS_TTL_NONZERO |
  2347. (slave->ts_ctl.dst_port_map << TS_CTL_DST_PORT_SHIFT) |
  2348. (slave->ts_ctl.uni ? TS_UNI_EN :
  2349. slave->ts_ctl.maddr_map << TS_CTL_MADDR_SHIFT);
  2350. if (cpts_is_tx_enabled(gbe_dev->cpts))
  2351. ts_en |= (TS_TX_ANX_ALL_EN | TS_TX_VLAN_LT1_EN);
  2352. if (cpts_is_rx_enabled(gbe_dev->cpts))
  2353. ts_en |= (TS_RX_ANX_ALL_EN | TS_RX_VLAN_LT1_EN);
  2354. writel(ts_en, GBE_REG_ADDR(slave, port_regs, ts_ctl));
  2355. writel(seq_id, GBE_REG_ADDR(slave, port_regs, ts_seq_ltype));
  2356. writel(ctl, GBE_REG_ADDR(slave, port_regs, ts_ctl_ltype2));
  2357. }
  2358. static int gbe_hwtstamp_set(struct gbe_intf *gbe_intf, struct ifreq *ifr)
  2359. {
  2360. struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
  2361. struct cpts *cpts = gbe_dev->cpts;
  2362. struct hwtstamp_config cfg;
  2363. if (!cpts)
  2364. return -EOPNOTSUPP;
  2365. if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
  2366. return -EFAULT;
  2367. /* reserved for future extensions */
  2368. if (cfg.flags)
  2369. return -EINVAL;
  2370. switch (cfg.tx_type) {
  2371. case HWTSTAMP_TX_OFF:
  2372. cpts_tx_enable(cpts, 0);
  2373. break;
  2374. case HWTSTAMP_TX_ON:
  2375. cpts_tx_enable(cpts, 1);
  2376. break;
  2377. default:
  2378. return -ERANGE;
  2379. }
  2380. switch (cfg.rx_filter) {
  2381. case HWTSTAMP_FILTER_NONE:
  2382. cpts_rx_enable(cpts, 0);
  2383. break;
  2384. case HWTSTAMP_FILTER_ALL:
  2385. case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
  2386. case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
  2387. case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
  2388. cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT);
  2389. cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
  2390. break;
  2391. case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
  2392. case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
  2393. case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
  2394. case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
  2395. case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
  2396. case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
  2397. case HWTSTAMP_FILTER_PTP_V2_EVENT:
  2398. case HWTSTAMP_FILTER_PTP_V2_SYNC:
  2399. case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
  2400. cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT);
  2401. cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
  2402. break;
  2403. default:
  2404. return -ERANGE;
  2405. }
  2406. gbe_hwtstamp(gbe_intf);
  2407. return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
  2408. }
  2409. static void gbe_register_cpts(struct gbe_priv *gbe_dev)
  2410. {
  2411. if (!gbe_dev->cpts)
  2412. return;
  2413. if (gbe_dev->cpts_registered > 0)
  2414. goto done;
  2415. if (cpts_register(gbe_dev->cpts)) {
  2416. dev_err(gbe_dev->dev, "error registering cpts device\n");
  2417. return;
  2418. }
  2419. done:
  2420. ++gbe_dev->cpts_registered;
  2421. }
  2422. static void gbe_unregister_cpts(struct gbe_priv *gbe_dev)
  2423. {
  2424. if (!gbe_dev->cpts || (gbe_dev->cpts_registered <= 0))
  2425. return;
  2426. if (--gbe_dev->cpts_registered)
  2427. return;
  2428. cpts_unregister(gbe_dev->cpts);
  2429. }
  2430. #else
  2431. static inline int gbe_txtstamp_mark_pkt(struct gbe_intf *gbe_intf,
  2432. struct netcp_packet *p_info)
  2433. {
  2434. return 0;
  2435. }
  2436. static inline int gbe_rxtstamp(struct gbe_intf *gbe_intf,
  2437. struct netcp_packet *p_info)
  2438. {
  2439. return 0;
  2440. }
  2441. static inline int gbe_hwtstamp(struct gbe_intf *gbe_intf,
  2442. struct ifreq *ifr, int cmd)
  2443. {
  2444. return -EOPNOTSUPP;
  2445. }
  2446. static inline void gbe_register_cpts(struct gbe_priv *gbe_dev)
  2447. {
  2448. }
  2449. static inline void gbe_unregister_cpts(struct gbe_priv *gbe_dev)
  2450. {
  2451. }
  2452. static inline int gbe_hwtstamp_get(struct gbe_intf *gbe_intf, struct ifreq *req)
  2453. {
  2454. return -EOPNOTSUPP;
  2455. }
  2456. static inline int gbe_hwtstamp_set(struct gbe_intf *gbe_intf, struct ifreq *req)
  2457. {
  2458. return -EOPNOTSUPP;
  2459. }
  2460. #endif /* CONFIG_TI_CPTS */
  2461. static int gbe_ioctl(void *intf_priv, struct ifreq *req, int cmd)
  2462. {
  2463. struct gbe_intf *gbe_intf = intf_priv;
  2464. struct phy_device *phy = gbe_intf->slave->phy;
  2465. if (!phy || !phy->drv->hwtstamp) {
  2466. switch (cmd) {
  2467. case SIOCGHWTSTAMP:
  2468. return gbe_hwtstamp_get(gbe_intf, req);
  2469. case SIOCSHWTSTAMP:
  2470. return gbe_hwtstamp_set(gbe_intf, req);
  2471. }
  2472. }
  2473. if (phy)
  2474. return phy_mii_ioctl(phy, req, cmd);
  2475. return -EOPNOTSUPP;
  2476. }
  2477. static void netcp_ethss_timer(unsigned long arg)
  2478. {
  2479. struct gbe_priv *gbe_dev = (struct gbe_priv *)arg;
  2480. struct gbe_intf *gbe_intf;
  2481. struct gbe_slave *slave;
  2482. /* Check & update SGMII link state of interfaces */
  2483. for_each_intf(gbe_intf, gbe_dev) {
  2484. if (!gbe_intf->slave->open)
  2485. continue;
  2486. netcp_ethss_update_link_state(gbe_dev, gbe_intf->slave,
  2487. gbe_intf->ndev);
  2488. }
  2489. /* Check & update SGMII link state of secondary ports */
  2490. for_each_sec_slave(slave, gbe_dev) {
  2491. netcp_ethss_update_link_state(gbe_dev, slave, NULL);
  2492. }
  2493. /* A timer runs as a BH, no need to block them */
  2494. spin_lock(&gbe_dev->hw_stats_lock);
  2495. if (gbe_dev->ss_version == GBE_SS_VERSION_14)
  2496. gbe_update_stats_ver14(gbe_dev, NULL);
  2497. else
  2498. gbe_update_stats(gbe_dev, NULL);
  2499. spin_unlock(&gbe_dev->hw_stats_lock);
  2500. gbe_dev->timer.expires = jiffies + GBE_TIMER_INTERVAL;
  2501. add_timer(&gbe_dev->timer);
  2502. }
  2503. static int gbe_txhook(int order, void *data, struct netcp_packet *p_info)
  2504. {
  2505. struct gbe_intf *gbe_intf = data;
  2506. p_info->tx_pipe = &gbe_intf->tx_pipe;
  2507. return gbe_txtstamp_mark_pkt(gbe_intf, p_info);
  2508. }
  2509. static int gbe_rxhook(int order, void *data, struct netcp_packet *p_info)
  2510. {
  2511. struct gbe_intf *gbe_intf = data;
  2512. return gbe_rxtstamp(gbe_intf, p_info);
  2513. }
  2514. static int gbe_open(void *intf_priv, struct net_device *ndev)
  2515. {
  2516. struct gbe_intf *gbe_intf = intf_priv;
  2517. struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
  2518. struct netcp_intf *netcp = netdev_priv(ndev);
  2519. struct gbe_slave *slave = gbe_intf->slave;
  2520. int port_num = slave->port_num;
  2521. u32 reg;
  2522. int ret;
  2523. reg = readl(GBE_REG_ADDR(gbe_dev, switch_regs, id_ver));
  2524. dev_dbg(gbe_dev->dev, "initializing gbe version %d.%d (%d) GBE identification value 0x%x\n",
  2525. GBE_MAJOR_VERSION(reg), GBE_MINOR_VERSION(reg),
  2526. GBE_RTL_VERSION(reg), GBE_IDENT(reg));
  2527. /* For 10G and on NetCP 1.5, use directed to port */
  2528. if ((gbe_dev->ss_version == XGBE_SS_VERSION_10) || IS_SS_ID_MU(gbe_dev))
  2529. gbe_intf->tx_pipe.flags = SWITCH_TO_PORT_IN_TAGINFO;
  2530. if (gbe_dev->enable_ale)
  2531. gbe_intf->tx_pipe.switch_to_port = 0;
  2532. else
  2533. gbe_intf->tx_pipe.switch_to_port = port_num;
  2534. dev_dbg(gbe_dev->dev,
  2535. "opened TX channel %s: %p with to port %d, flags %d\n",
  2536. gbe_intf->tx_pipe.dma_chan_name,
  2537. gbe_intf->tx_pipe.dma_channel,
  2538. gbe_intf->tx_pipe.switch_to_port,
  2539. gbe_intf->tx_pipe.flags);
  2540. gbe_slave_stop(gbe_intf);
  2541. /* disable priority elevation and enable statistics on all ports */
  2542. writel(0, GBE_REG_ADDR(gbe_dev, switch_regs, ptype));
  2543. /* Control register */
  2544. writel(GBE_CTL_P0_ENABLE, GBE_REG_ADDR(gbe_dev, switch_regs, control));
  2545. /* All statistics enabled and STAT AB visible by default */
  2546. writel(gbe_dev->stats_en_mask, GBE_REG_ADDR(gbe_dev, switch_regs,
  2547. stat_port_en));
  2548. ret = gbe_slave_open(gbe_intf);
  2549. if (ret)
  2550. goto fail;
  2551. netcp_register_txhook(netcp, GBE_TXHOOK_ORDER, gbe_txhook, gbe_intf);
  2552. netcp_register_rxhook(netcp, GBE_RXHOOK_ORDER, gbe_rxhook, gbe_intf);
  2553. slave->open = true;
  2554. netcp_ethss_update_link_state(gbe_dev, slave, ndev);
  2555. gbe_register_cpts(gbe_dev);
  2556. return 0;
  2557. fail:
  2558. gbe_slave_stop(gbe_intf);
  2559. return ret;
  2560. }
  2561. static int gbe_close(void *intf_priv, struct net_device *ndev)
  2562. {
  2563. struct gbe_intf *gbe_intf = intf_priv;
  2564. struct netcp_intf *netcp = netdev_priv(ndev);
  2565. struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
  2566. gbe_unregister_cpts(gbe_dev);
  2567. gbe_slave_stop(gbe_intf);
  2568. netcp_unregister_rxhook(netcp, GBE_RXHOOK_ORDER, gbe_rxhook, gbe_intf);
  2569. netcp_unregister_txhook(netcp, GBE_TXHOOK_ORDER, gbe_txhook, gbe_intf);
  2570. gbe_intf->slave->open = false;
  2571. atomic_set(&gbe_intf->slave->link_state, NETCP_LINK_STATE_INVALID);
  2572. return 0;
  2573. }
  2574. #if IS_ENABLED(CONFIG_TI_CPTS)
  2575. static void init_slave_ts_ctl(struct gbe_slave *slave)
  2576. {
  2577. slave->ts_ctl.uni = 1;
  2578. slave->ts_ctl.dst_port_map =
  2579. (TS_CTL_DST_PORT >> TS_CTL_DST_PORT_SHIFT) & 0x3;
  2580. slave->ts_ctl.maddr_map =
  2581. (TS_CTL_MADDR_ALL >> TS_CTL_MADDR_SHIFT) & 0x1f;
  2582. }
  2583. #else
  2584. static void init_slave_ts_ctl(struct gbe_slave *slave)
  2585. {
  2586. }
  2587. #endif /* CONFIG_TI_CPTS */
  2588. static int init_slave(struct gbe_priv *gbe_dev, struct gbe_slave *slave,
  2589. struct device_node *node)
  2590. {
  2591. int port_reg_num;
  2592. u32 port_reg_ofs, emac_reg_ofs;
  2593. u32 port_reg_blk_sz, emac_reg_blk_sz;
  2594. if (of_property_read_u32(node, "slave-port", &slave->slave_num)) {
  2595. dev_err(gbe_dev->dev, "missing slave-port parameter\n");
  2596. return -EINVAL;
  2597. }
  2598. if (of_property_read_u32(node, "link-interface",
  2599. &slave->link_interface)) {
  2600. dev_warn(gbe_dev->dev,
  2601. "missing link-interface value defaulting to 1G mac-phy link\n");
  2602. slave->link_interface = SGMII_LINK_MAC_PHY;
  2603. }
  2604. slave->open = false;
  2605. slave->phy_node = of_parse_phandle(node, "phy-handle", 0);
  2606. slave->port_num = gbe_get_slave_port(gbe_dev, slave->slave_num);
  2607. if (slave->link_interface >= XGMII_LINK_MAC_PHY)
  2608. slave->mac_control = GBE_DEF_10G_MAC_CONTROL;
  2609. else
  2610. slave->mac_control = GBE_DEF_1G_MAC_CONTROL;
  2611. /* Emac regs memmap are contiguous but port regs are not */
  2612. port_reg_num = slave->slave_num;
  2613. if (gbe_dev->ss_version == GBE_SS_VERSION_14) {
  2614. if (slave->slave_num > 1) {
  2615. port_reg_ofs = GBE13_SLAVE_PORT2_OFFSET;
  2616. port_reg_num -= 2;
  2617. } else {
  2618. port_reg_ofs = GBE13_SLAVE_PORT_OFFSET;
  2619. }
  2620. emac_reg_ofs = GBE13_EMAC_OFFSET;
  2621. port_reg_blk_sz = 0x30;
  2622. emac_reg_blk_sz = 0x40;
  2623. } else if (IS_SS_ID_MU(gbe_dev)) {
  2624. port_reg_ofs = GBENU_SLAVE_PORT_OFFSET;
  2625. emac_reg_ofs = GBENU_EMAC_OFFSET;
  2626. port_reg_blk_sz = 0x1000;
  2627. emac_reg_blk_sz = 0x1000;
  2628. } else if (gbe_dev->ss_version == XGBE_SS_VERSION_10) {
  2629. port_reg_ofs = XGBE10_SLAVE_PORT_OFFSET;
  2630. emac_reg_ofs = XGBE10_EMAC_OFFSET;
  2631. port_reg_blk_sz = 0x30;
  2632. emac_reg_blk_sz = 0x40;
  2633. } else {
  2634. dev_err(gbe_dev->dev, "unknown ethss(0x%x)\n",
  2635. gbe_dev->ss_version);
  2636. return -EINVAL;
  2637. }
  2638. slave->port_regs = gbe_dev->switch_regs + port_reg_ofs +
  2639. (port_reg_blk_sz * port_reg_num);
  2640. slave->emac_regs = gbe_dev->switch_regs + emac_reg_ofs +
  2641. (emac_reg_blk_sz * slave->slave_num);
  2642. if (gbe_dev->ss_version == GBE_SS_VERSION_14) {
  2643. /* Initialize slave port register offsets */
  2644. GBE_SET_REG_OFS(slave, port_regs, port_vlan);
  2645. GBE_SET_REG_OFS(slave, port_regs, tx_pri_map);
  2646. GBE_SET_REG_OFS(slave, port_regs, sa_lo);
  2647. GBE_SET_REG_OFS(slave, port_regs, sa_hi);
  2648. GBE_SET_REG_OFS(slave, port_regs, ts_ctl);
  2649. GBE_SET_REG_OFS(slave, port_regs, ts_seq_ltype);
  2650. GBE_SET_REG_OFS(slave, port_regs, ts_vlan);
  2651. GBE_SET_REG_OFS(slave, port_regs, ts_ctl_ltype2);
  2652. GBE_SET_REG_OFS(slave, port_regs, ts_ctl2);
  2653. /* Initialize EMAC register offsets */
  2654. GBE_SET_REG_OFS(slave, emac_regs, mac_control);
  2655. GBE_SET_REG_OFS(slave, emac_regs, soft_reset);
  2656. GBE_SET_REG_OFS(slave, emac_regs, rx_maxlen);
  2657. } else if (IS_SS_ID_MU(gbe_dev)) {
  2658. /* Initialize slave port register offsets */
  2659. GBENU_SET_REG_OFS(slave, port_regs, port_vlan);
  2660. GBENU_SET_REG_OFS(slave, port_regs, tx_pri_map);
  2661. GBENU_SET_REG_OFS(slave, port_regs, sa_lo);
  2662. GBENU_SET_REG_OFS(slave, port_regs, sa_hi);
  2663. GBENU_SET_REG_OFS(slave, port_regs, ts_ctl);
  2664. GBENU_SET_REG_OFS(slave, port_regs, ts_seq_ltype);
  2665. GBENU_SET_REG_OFS(slave, port_regs, ts_vlan);
  2666. GBENU_SET_REG_OFS(slave, port_regs, ts_ctl_ltype2);
  2667. GBENU_SET_REG_OFS(slave, port_regs, ts_ctl2);
  2668. GBENU_SET_REG_OFS(slave, port_regs, rx_maxlen);
  2669. /* Initialize EMAC register offsets */
  2670. GBENU_SET_REG_OFS(slave, emac_regs, mac_control);
  2671. GBENU_SET_REG_OFS(slave, emac_regs, soft_reset);
  2672. } else if (gbe_dev->ss_version == XGBE_SS_VERSION_10) {
  2673. /* Initialize slave port register offsets */
  2674. XGBE_SET_REG_OFS(slave, port_regs, port_vlan);
  2675. XGBE_SET_REG_OFS(slave, port_regs, tx_pri_map);
  2676. XGBE_SET_REG_OFS(slave, port_regs, sa_lo);
  2677. XGBE_SET_REG_OFS(slave, port_regs, sa_hi);
  2678. XGBE_SET_REG_OFS(slave, port_regs, ts_ctl);
  2679. XGBE_SET_REG_OFS(slave, port_regs, ts_seq_ltype);
  2680. XGBE_SET_REG_OFS(slave, port_regs, ts_vlan);
  2681. XGBE_SET_REG_OFS(slave, port_regs, ts_ctl_ltype2);
  2682. XGBE_SET_REG_OFS(slave, port_regs, ts_ctl2);
  2683. /* Initialize EMAC register offsets */
  2684. XGBE_SET_REG_OFS(slave, emac_regs, mac_control);
  2685. XGBE_SET_REG_OFS(slave, emac_regs, soft_reset);
  2686. XGBE_SET_REG_OFS(slave, emac_regs, rx_maxlen);
  2687. }
  2688. atomic_set(&slave->link_state, NETCP_LINK_STATE_INVALID);
  2689. init_slave_ts_ctl(slave);
  2690. return 0;
  2691. }
  2692. static void init_secondary_ports(struct gbe_priv *gbe_dev,
  2693. struct device_node *node)
  2694. {
  2695. struct device *dev = gbe_dev->dev;
  2696. phy_interface_t phy_mode;
  2697. struct gbe_priv **priv;
  2698. struct device_node *port;
  2699. struct gbe_slave *slave;
  2700. bool mac_phy_link = false;
  2701. for_each_child_of_node(node, port) {
  2702. slave = devm_kzalloc(dev, sizeof(*slave), GFP_KERNEL);
  2703. if (!slave) {
  2704. dev_err(dev,
  2705. "memomry alloc failed for secondary port(%s), skipping...\n",
  2706. port->name);
  2707. continue;
  2708. }
  2709. if (init_slave(gbe_dev, slave, port)) {
  2710. dev_err(dev,
  2711. "Failed to initialize secondary port(%s), skipping...\n",
  2712. port->name);
  2713. devm_kfree(dev, slave);
  2714. continue;
  2715. }
  2716. gbe_sgmii_config(gbe_dev, slave);
  2717. gbe_port_reset(slave);
  2718. gbe_port_config(gbe_dev, slave, gbe_dev->rx_packet_max);
  2719. list_add_tail(&slave->slave_list, &gbe_dev->secondary_slaves);
  2720. gbe_dev->num_slaves++;
  2721. if ((slave->link_interface == SGMII_LINK_MAC_PHY) ||
  2722. (slave->link_interface == XGMII_LINK_MAC_PHY))
  2723. mac_phy_link = true;
  2724. slave->open = true;
  2725. if (gbe_dev->num_slaves >= gbe_dev->max_num_slaves) {
  2726. of_node_put(port);
  2727. break;
  2728. }
  2729. }
  2730. /* of_phy_connect() is needed only for MAC-PHY interface */
  2731. if (!mac_phy_link)
  2732. return;
  2733. /* Allocate dummy netdev device for attaching to phy device */
  2734. gbe_dev->dummy_ndev = alloc_netdev(sizeof(gbe_dev), "dummy",
  2735. NET_NAME_UNKNOWN, ether_setup);
  2736. if (!gbe_dev->dummy_ndev) {
  2737. dev_err(dev,
  2738. "Failed to allocate dummy netdev for secondary ports, skipping phy_connect()...\n");
  2739. return;
  2740. }
  2741. priv = netdev_priv(gbe_dev->dummy_ndev);
  2742. *priv = gbe_dev;
  2743. if (slave->link_interface == SGMII_LINK_MAC_PHY) {
  2744. phy_mode = PHY_INTERFACE_MODE_SGMII;
  2745. slave->phy_port_t = PORT_MII;
  2746. } else {
  2747. phy_mode = PHY_INTERFACE_MODE_NA;
  2748. slave->phy_port_t = PORT_FIBRE;
  2749. }
  2750. for_each_sec_slave(slave, gbe_dev) {
  2751. if ((slave->link_interface != SGMII_LINK_MAC_PHY) &&
  2752. (slave->link_interface != XGMII_LINK_MAC_PHY))
  2753. continue;
  2754. slave->phy =
  2755. of_phy_connect(gbe_dev->dummy_ndev,
  2756. slave->phy_node,
  2757. gbe_adjust_link_sec_slaves,
  2758. 0, phy_mode);
  2759. if (!slave->phy) {
  2760. dev_err(dev, "phy not found for slave %d\n",
  2761. slave->slave_num);
  2762. slave->phy = NULL;
  2763. } else {
  2764. dev_dbg(dev, "phy found: id is: 0x%s\n",
  2765. phydev_name(slave->phy));
  2766. phy_start(slave->phy);
  2767. phy_read_status(slave->phy);
  2768. }
  2769. }
  2770. }
  2771. static void free_secondary_ports(struct gbe_priv *gbe_dev)
  2772. {
  2773. struct gbe_slave *slave;
  2774. while (!list_empty(&gbe_dev->secondary_slaves)) {
  2775. slave = first_sec_slave(gbe_dev);
  2776. if (slave->phy)
  2777. phy_disconnect(slave->phy);
  2778. list_del(&slave->slave_list);
  2779. }
  2780. if (gbe_dev->dummy_ndev)
  2781. free_netdev(gbe_dev->dummy_ndev);
  2782. }
  2783. static int set_xgbe_ethss10_priv(struct gbe_priv *gbe_dev,
  2784. struct device_node *node)
  2785. {
  2786. struct resource res;
  2787. void __iomem *regs;
  2788. int ret, i;
  2789. ret = of_address_to_resource(node, XGBE_SS_REG_INDEX, &res);
  2790. if (ret) {
  2791. dev_err(gbe_dev->dev,
  2792. "Can't xlate xgbe of node(%s) ss address at %d\n",
  2793. node->name, XGBE_SS_REG_INDEX);
  2794. return ret;
  2795. }
  2796. regs = devm_ioremap_resource(gbe_dev->dev, &res);
  2797. if (IS_ERR(regs)) {
  2798. dev_err(gbe_dev->dev, "Failed to map xgbe ss register base\n");
  2799. return PTR_ERR(regs);
  2800. }
  2801. gbe_dev->ss_regs = regs;
  2802. ret = of_address_to_resource(node, XGBE_SM_REG_INDEX, &res);
  2803. if (ret) {
  2804. dev_err(gbe_dev->dev,
  2805. "Can't xlate xgbe of node(%s) sm address at %d\n",
  2806. node->name, XGBE_SM_REG_INDEX);
  2807. return ret;
  2808. }
  2809. regs = devm_ioremap_resource(gbe_dev->dev, &res);
  2810. if (IS_ERR(regs)) {
  2811. dev_err(gbe_dev->dev, "Failed to map xgbe sm register base\n");
  2812. return PTR_ERR(regs);
  2813. }
  2814. gbe_dev->switch_regs = regs;
  2815. ret = of_address_to_resource(node, XGBE_SERDES_REG_INDEX, &res);
  2816. if (ret) {
  2817. dev_err(gbe_dev->dev,
  2818. "Can't xlate xgbe serdes of node(%s) address at %d\n",
  2819. node->name, XGBE_SERDES_REG_INDEX);
  2820. return ret;
  2821. }
  2822. regs = devm_ioremap_resource(gbe_dev->dev, &res);
  2823. if (IS_ERR(regs)) {
  2824. dev_err(gbe_dev->dev, "Failed to map xgbe serdes register base\n");
  2825. return PTR_ERR(regs);
  2826. }
  2827. gbe_dev->xgbe_serdes_regs = regs;
  2828. gbe_dev->num_stats_mods = gbe_dev->max_num_ports;
  2829. gbe_dev->et_stats = xgbe10_et_stats;
  2830. gbe_dev->num_et_stats = ARRAY_SIZE(xgbe10_et_stats);
  2831. gbe_dev->hw_stats = devm_kzalloc(gbe_dev->dev,
  2832. gbe_dev->num_et_stats * sizeof(u64),
  2833. GFP_KERNEL);
  2834. if (!gbe_dev->hw_stats) {
  2835. dev_err(gbe_dev->dev, "hw_stats memory allocation failed\n");
  2836. return -ENOMEM;
  2837. }
  2838. gbe_dev->hw_stats_prev =
  2839. devm_kzalloc(gbe_dev->dev,
  2840. gbe_dev->num_et_stats * sizeof(u32),
  2841. GFP_KERNEL);
  2842. if (!gbe_dev->hw_stats_prev) {
  2843. dev_err(gbe_dev->dev,
  2844. "hw_stats_prev memory allocation failed\n");
  2845. return -ENOMEM;
  2846. }
  2847. gbe_dev->ss_version = XGBE_SS_VERSION_10;
  2848. gbe_dev->sgmii_port_regs = gbe_dev->ss_regs +
  2849. XGBE10_SGMII_MODULE_OFFSET;
  2850. gbe_dev->host_port_regs = gbe_dev->ss_regs + XGBE10_HOST_PORT_OFFSET;
  2851. for (i = 0; i < gbe_dev->max_num_ports; i++)
  2852. gbe_dev->hw_stats_regs[i] = gbe_dev->switch_regs +
  2853. XGBE10_HW_STATS_OFFSET + (GBE_HW_STATS_REG_MAP_SZ * i);
  2854. gbe_dev->ale_reg = gbe_dev->switch_regs + XGBE10_ALE_OFFSET;
  2855. gbe_dev->cpts_reg = gbe_dev->switch_regs + XGBE10_CPTS_OFFSET;
  2856. gbe_dev->ale_ports = gbe_dev->max_num_ports;
  2857. gbe_dev->host_port = XGBE10_HOST_PORT_NUM;
  2858. gbe_dev->ale_entries = XGBE10_NUM_ALE_ENTRIES;
  2859. gbe_dev->stats_en_mask = (1 << (gbe_dev->max_num_ports)) - 1;
  2860. /* Subsystem registers */
  2861. XGBE_SET_REG_OFS(gbe_dev, ss_regs, id_ver);
  2862. XGBE_SET_REG_OFS(gbe_dev, ss_regs, control);
  2863. /* Switch module registers */
  2864. XGBE_SET_REG_OFS(gbe_dev, switch_regs, id_ver);
  2865. XGBE_SET_REG_OFS(gbe_dev, switch_regs, control);
  2866. XGBE_SET_REG_OFS(gbe_dev, switch_regs, ptype);
  2867. XGBE_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en);
  2868. XGBE_SET_REG_OFS(gbe_dev, switch_regs, flow_control);
  2869. /* Host port registers */
  2870. XGBE_SET_REG_OFS(gbe_dev, host_port_regs, port_vlan);
  2871. XGBE_SET_REG_OFS(gbe_dev, host_port_regs, tx_pri_map);
  2872. XGBE_SET_REG_OFS(gbe_dev, host_port_regs, rx_maxlen);
  2873. return 0;
  2874. }
  2875. static int get_gbe_resource_version(struct gbe_priv *gbe_dev,
  2876. struct device_node *node)
  2877. {
  2878. struct resource res;
  2879. void __iomem *regs;
  2880. int ret;
  2881. ret = of_address_to_resource(node, GBE_SS_REG_INDEX, &res);
  2882. if (ret) {
  2883. dev_err(gbe_dev->dev,
  2884. "Can't translate of node(%s) of gbe ss address at %d\n",
  2885. node->name, GBE_SS_REG_INDEX);
  2886. return ret;
  2887. }
  2888. regs = devm_ioremap_resource(gbe_dev->dev, &res);
  2889. if (IS_ERR(regs)) {
  2890. dev_err(gbe_dev->dev, "Failed to map gbe register base\n");
  2891. return PTR_ERR(regs);
  2892. }
  2893. gbe_dev->ss_regs = regs;
  2894. gbe_dev->ss_version = readl(gbe_dev->ss_regs);
  2895. return 0;
  2896. }
  2897. static int set_gbe_ethss14_priv(struct gbe_priv *gbe_dev,
  2898. struct device_node *node)
  2899. {
  2900. struct resource res;
  2901. void __iomem *regs;
  2902. int i, ret;
  2903. ret = of_address_to_resource(node, GBE_SGMII34_REG_INDEX, &res);
  2904. if (ret) {
  2905. dev_err(gbe_dev->dev,
  2906. "Can't translate of gbe node(%s) address at index %d\n",
  2907. node->name, GBE_SGMII34_REG_INDEX);
  2908. return ret;
  2909. }
  2910. regs = devm_ioremap_resource(gbe_dev->dev, &res);
  2911. if (IS_ERR(regs)) {
  2912. dev_err(gbe_dev->dev,
  2913. "Failed to map gbe sgmii port34 register base\n");
  2914. return PTR_ERR(regs);
  2915. }
  2916. gbe_dev->sgmii_port34_regs = regs;
  2917. ret = of_address_to_resource(node, GBE_SM_REG_INDEX, &res);
  2918. if (ret) {
  2919. dev_err(gbe_dev->dev,
  2920. "Can't translate of gbe node(%s) address at index %d\n",
  2921. node->name, GBE_SM_REG_INDEX);
  2922. return ret;
  2923. }
  2924. regs = devm_ioremap_resource(gbe_dev->dev, &res);
  2925. if (IS_ERR(regs)) {
  2926. dev_err(gbe_dev->dev,
  2927. "Failed to map gbe switch module register base\n");
  2928. return PTR_ERR(regs);
  2929. }
  2930. gbe_dev->switch_regs = regs;
  2931. gbe_dev->num_stats_mods = gbe_dev->max_num_slaves;
  2932. gbe_dev->et_stats = gbe13_et_stats;
  2933. gbe_dev->num_et_stats = ARRAY_SIZE(gbe13_et_stats);
  2934. gbe_dev->hw_stats = devm_kzalloc(gbe_dev->dev,
  2935. gbe_dev->num_et_stats * sizeof(u64),
  2936. GFP_KERNEL);
  2937. if (!gbe_dev->hw_stats) {
  2938. dev_err(gbe_dev->dev, "hw_stats memory allocation failed\n");
  2939. return -ENOMEM;
  2940. }
  2941. gbe_dev->hw_stats_prev =
  2942. devm_kzalloc(gbe_dev->dev,
  2943. gbe_dev->num_et_stats * sizeof(u32),
  2944. GFP_KERNEL);
  2945. if (!gbe_dev->hw_stats_prev) {
  2946. dev_err(gbe_dev->dev,
  2947. "hw_stats_prev memory allocation failed\n");
  2948. return -ENOMEM;
  2949. }
  2950. gbe_dev->sgmii_port_regs = gbe_dev->ss_regs + GBE13_SGMII_MODULE_OFFSET;
  2951. gbe_dev->host_port_regs = gbe_dev->switch_regs + GBE13_HOST_PORT_OFFSET;
  2952. /* K2HK has only 2 hw stats modules visible at a time, so
  2953. * module 0 & 2 points to one base and
  2954. * module 1 & 3 points to the other base
  2955. */
  2956. for (i = 0; i < gbe_dev->max_num_slaves; i++) {
  2957. gbe_dev->hw_stats_regs[i] =
  2958. gbe_dev->switch_regs + GBE13_HW_STATS_OFFSET +
  2959. (GBE_HW_STATS_REG_MAP_SZ * (i & 0x1));
  2960. }
  2961. gbe_dev->cpts_reg = gbe_dev->switch_regs + GBE13_CPTS_OFFSET;
  2962. gbe_dev->ale_reg = gbe_dev->switch_regs + GBE13_ALE_OFFSET;
  2963. gbe_dev->ale_ports = gbe_dev->max_num_ports;
  2964. gbe_dev->host_port = GBE13_HOST_PORT_NUM;
  2965. gbe_dev->ale_entries = GBE13_NUM_ALE_ENTRIES;
  2966. gbe_dev->stats_en_mask = GBE13_REG_VAL_STAT_ENABLE_ALL;
  2967. /* Subsystem registers */
  2968. GBE_SET_REG_OFS(gbe_dev, ss_regs, id_ver);
  2969. /* Switch module registers */
  2970. GBE_SET_REG_OFS(gbe_dev, switch_regs, id_ver);
  2971. GBE_SET_REG_OFS(gbe_dev, switch_regs, control);
  2972. GBE_SET_REG_OFS(gbe_dev, switch_regs, soft_reset);
  2973. GBE_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en);
  2974. GBE_SET_REG_OFS(gbe_dev, switch_regs, ptype);
  2975. GBE_SET_REG_OFS(gbe_dev, switch_regs, flow_control);
  2976. /* Host port registers */
  2977. GBE_SET_REG_OFS(gbe_dev, host_port_regs, port_vlan);
  2978. GBE_SET_REG_OFS(gbe_dev, host_port_regs, rx_maxlen);
  2979. return 0;
  2980. }
  2981. static int set_gbenu_ethss_priv(struct gbe_priv *gbe_dev,
  2982. struct device_node *node)
  2983. {
  2984. struct resource res;
  2985. void __iomem *regs;
  2986. int i, ret;
  2987. gbe_dev->num_stats_mods = gbe_dev->max_num_ports;
  2988. gbe_dev->et_stats = gbenu_et_stats;
  2989. if (IS_SS_ID_NU(gbe_dev))
  2990. gbe_dev->num_et_stats = GBENU_ET_STATS_HOST_SIZE +
  2991. (gbe_dev->max_num_slaves * GBENU_ET_STATS_PORT_SIZE);
  2992. else
  2993. gbe_dev->num_et_stats = GBENU_ET_STATS_HOST_SIZE +
  2994. GBENU_ET_STATS_PORT_SIZE;
  2995. gbe_dev->hw_stats = devm_kzalloc(gbe_dev->dev,
  2996. gbe_dev->num_et_stats * sizeof(u64),
  2997. GFP_KERNEL);
  2998. if (!gbe_dev->hw_stats) {
  2999. dev_err(gbe_dev->dev, "hw_stats memory allocation failed\n");
  3000. return -ENOMEM;
  3001. }
  3002. gbe_dev->hw_stats_prev =
  3003. devm_kzalloc(gbe_dev->dev,
  3004. gbe_dev->num_et_stats * sizeof(u32),
  3005. GFP_KERNEL);
  3006. if (!gbe_dev->hw_stats_prev) {
  3007. dev_err(gbe_dev->dev,
  3008. "hw_stats_prev memory allocation failed\n");
  3009. return -ENOMEM;
  3010. }
  3011. ret = of_address_to_resource(node, GBENU_SM_REG_INDEX, &res);
  3012. if (ret) {
  3013. dev_err(gbe_dev->dev,
  3014. "Can't translate of gbenu node(%s) addr at index %d\n",
  3015. node->name, GBENU_SM_REG_INDEX);
  3016. return ret;
  3017. }
  3018. regs = devm_ioremap_resource(gbe_dev->dev, &res);
  3019. if (IS_ERR(regs)) {
  3020. dev_err(gbe_dev->dev,
  3021. "Failed to map gbenu switch module register base\n");
  3022. return PTR_ERR(regs);
  3023. }
  3024. gbe_dev->switch_regs = regs;
  3025. gbe_dev->sgmii_port_regs = gbe_dev->ss_regs + GBENU_SGMII_MODULE_OFFSET;
  3026. /* Although sgmii modules are mem mapped to one contiguous
  3027. * region on GBENU devices, setting sgmii_port34_regs allows
  3028. * consistent code when accessing sgmii api
  3029. */
  3030. gbe_dev->sgmii_port34_regs = gbe_dev->sgmii_port_regs +
  3031. (2 * GBENU_SGMII_MODULE_SIZE);
  3032. gbe_dev->host_port_regs = gbe_dev->switch_regs + GBENU_HOST_PORT_OFFSET;
  3033. for (i = 0; i < (gbe_dev->max_num_ports); i++)
  3034. gbe_dev->hw_stats_regs[i] = gbe_dev->switch_regs +
  3035. GBENU_HW_STATS_OFFSET + (GBENU_HW_STATS_REG_MAP_SZ * i);
  3036. gbe_dev->cpts_reg = gbe_dev->switch_regs + GBENU_CPTS_OFFSET;
  3037. gbe_dev->ale_reg = gbe_dev->switch_regs + GBENU_ALE_OFFSET;
  3038. gbe_dev->ale_ports = gbe_dev->max_num_ports;
  3039. gbe_dev->host_port = GBENU_HOST_PORT_NUM;
  3040. gbe_dev->ale_entries = GBE13_NUM_ALE_ENTRIES;
  3041. gbe_dev->stats_en_mask = (1 << (gbe_dev->max_num_ports)) - 1;
  3042. /* Subsystem registers */
  3043. GBENU_SET_REG_OFS(gbe_dev, ss_regs, id_ver);
  3044. /* Switch module registers */
  3045. GBENU_SET_REG_OFS(gbe_dev, switch_regs, id_ver);
  3046. GBENU_SET_REG_OFS(gbe_dev, switch_regs, control);
  3047. GBENU_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en);
  3048. GBENU_SET_REG_OFS(gbe_dev, switch_regs, ptype);
  3049. /* Host port registers */
  3050. GBENU_SET_REG_OFS(gbe_dev, host_port_regs, port_vlan);
  3051. GBENU_SET_REG_OFS(gbe_dev, host_port_regs, rx_maxlen);
  3052. /* For NU only. 2U does not need tx_pri_map.
  3053. * NU cppi port 0 tx pkt streaming interface has (n-1)*8 egress threads
  3054. * while 2U has only 1 such thread
  3055. */
  3056. GBENU_SET_REG_OFS(gbe_dev, host_port_regs, tx_pri_map);
  3057. return 0;
  3058. }
  3059. static int gbe_probe(struct netcp_device *netcp_device, struct device *dev,
  3060. struct device_node *node, void **inst_priv)
  3061. {
  3062. struct device_node *interfaces, *interface;
  3063. struct device_node *secondary_ports;
  3064. struct cpsw_ale_params ale_params;
  3065. struct gbe_priv *gbe_dev;
  3066. u32 slave_num;
  3067. int i, ret = 0;
  3068. if (!node) {
  3069. dev_err(dev, "device tree info unavailable\n");
  3070. return -ENODEV;
  3071. }
  3072. gbe_dev = devm_kzalloc(dev, sizeof(struct gbe_priv), GFP_KERNEL);
  3073. if (!gbe_dev)
  3074. return -ENOMEM;
  3075. if (of_device_is_compatible(node, "ti,netcp-gbe-5") ||
  3076. of_device_is_compatible(node, "ti,netcp-gbe")) {
  3077. gbe_dev->max_num_slaves = 4;
  3078. } else if (of_device_is_compatible(node, "ti,netcp-gbe-9")) {
  3079. gbe_dev->max_num_slaves = 8;
  3080. } else if (of_device_is_compatible(node, "ti,netcp-gbe-2")) {
  3081. gbe_dev->max_num_slaves = 1;
  3082. } else if (of_device_is_compatible(node, "ti,netcp-xgbe")) {
  3083. gbe_dev->max_num_slaves = 2;
  3084. } else {
  3085. dev_err(dev, "device tree node for unknown device\n");
  3086. return -EINVAL;
  3087. }
  3088. gbe_dev->max_num_ports = gbe_dev->max_num_slaves + 1;
  3089. gbe_dev->dev = dev;
  3090. gbe_dev->netcp_device = netcp_device;
  3091. gbe_dev->rx_packet_max = NETCP_MAX_FRAME_SIZE;
  3092. /* init the hw stats lock */
  3093. spin_lock_init(&gbe_dev->hw_stats_lock);
  3094. if (of_find_property(node, "enable-ale", NULL)) {
  3095. gbe_dev->enable_ale = true;
  3096. dev_info(dev, "ALE enabled\n");
  3097. } else {
  3098. gbe_dev->enable_ale = false;
  3099. dev_dbg(dev, "ALE bypass enabled*\n");
  3100. }
  3101. ret = of_property_read_u32(node, "tx-queue",
  3102. &gbe_dev->tx_queue_id);
  3103. if (ret < 0) {
  3104. dev_err(dev, "missing tx_queue parameter\n");
  3105. gbe_dev->tx_queue_id = GBE_TX_QUEUE;
  3106. }
  3107. ret = of_property_read_string(node, "tx-channel",
  3108. &gbe_dev->dma_chan_name);
  3109. if (ret < 0) {
  3110. dev_err(dev, "missing \"tx-channel\" parameter\n");
  3111. return -EINVAL;
  3112. }
  3113. if (!strcmp(node->name, "gbe")) {
  3114. ret = get_gbe_resource_version(gbe_dev, node);
  3115. if (ret)
  3116. return ret;
  3117. dev_dbg(dev, "ss_version: 0x%08x\n", gbe_dev->ss_version);
  3118. if (gbe_dev->ss_version == GBE_SS_VERSION_14)
  3119. ret = set_gbe_ethss14_priv(gbe_dev, node);
  3120. else if (IS_SS_ID_MU(gbe_dev))
  3121. ret = set_gbenu_ethss_priv(gbe_dev, node);
  3122. else
  3123. ret = -ENODEV;
  3124. } else if (!strcmp(node->name, "xgbe")) {
  3125. ret = set_xgbe_ethss10_priv(gbe_dev, node);
  3126. if (ret)
  3127. return ret;
  3128. ret = netcp_xgbe_serdes_init(gbe_dev->xgbe_serdes_regs,
  3129. gbe_dev->ss_regs);
  3130. } else {
  3131. dev_err(dev, "unknown GBE node(%s)\n", node->name);
  3132. ret = -ENODEV;
  3133. }
  3134. if (ret)
  3135. return ret;
  3136. interfaces = of_get_child_by_name(node, "interfaces");
  3137. if (!interfaces)
  3138. dev_err(dev, "could not find interfaces\n");
  3139. ret = netcp_txpipe_init(&gbe_dev->tx_pipe, netcp_device,
  3140. gbe_dev->dma_chan_name, gbe_dev->tx_queue_id);
  3141. if (ret)
  3142. return ret;
  3143. ret = netcp_txpipe_open(&gbe_dev->tx_pipe);
  3144. if (ret)
  3145. return ret;
  3146. /* Create network interfaces */
  3147. INIT_LIST_HEAD(&gbe_dev->gbe_intf_head);
  3148. for_each_child_of_node(interfaces, interface) {
  3149. ret = of_property_read_u32(interface, "slave-port", &slave_num);
  3150. if (ret) {
  3151. dev_err(dev, "missing slave-port parameter, skipping interface configuration for %s\n",
  3152. interface->name);
  3153. continue;
  3154. }
  3155. gbe_dev->num_slaves++;
  3156. if (gbe_dev->num_slaves >= gbe_dev->max_num_slaves) {
  3157. of_node_put(interface);
  3158. break;
  3159. }
  3160. }
  3161. of_node_put(interfaces);
  3162. if (!gbe_dev->num_slaves)
  3163. dev_warn(dev, "No network interface configured\n");
  3164. /* Initialize Secondary slave ports */
  3165. secondary_ports = of_get_child_by_name(node, "secondary-slave-ports");
  3166. INIT_LIST_HEAD(&gbe_dev->secondary_slaves);
  3167. if (secondary_ports && (gbe_dev->num_slaves < gbe_dev->max_num_slaves))
  3168. init_secondary_ports(gbe_dev, secondary_ports);
  3169. of_node_put(secondary_ports);
  3170. if (!gbe_dev->num_slaves) {
  3171. dev_err(dev,
  3172. "No network interface or secondary ports configured\n");
  3173. ret = -ENODEV;
  3174. goto free_sec_ports;
  3175. }
  3176. memset(&ale_params, 0, sizeof(ale_params));
  3177. ale_params.dev = gbe_dev->dev;
  3178. ale_params.ale_regs = gbe_dev->ale_reg;
  3179. ale_params.ale_ageout = GBE_DEFAULT_ALE_AGEOUT;
  3180. ale_params.ale_entries = gbe_dev->ale_entries;
  3181. ale_params.ale_ports = gbe_dev->ale_ports;
  3182. gbe_dev->ale = cpsw_ale_create(&ale_params);
  3183. if (!gbe_dev->ale) {
  3184. dev_err(gbe_dev->dev, "error initializing ale engine\n");
  3185. ret = -ENODEV;
  3186. goto free_sec_ports;
  3187. } else {
  3188. dev_dbg(gbe_dev->dev, "Created a gbe ale engine\n");
  3189. }
  3190. gbe_dev->cpts = cpts_create(gbe_dev->dev, gbe_dev->cpts_reg, node);
  3191. if (IS_ENABLED(CONFIG_TI_CPTS) && IS_ERR(gbe_dev->cpts)) {
  3192. ret = PTR_ERR(gbe_dev->cpts);
  3193. goto free_sec_ports;
  3194. }
  3195. /* initialize host port */
  3196. gbe_init_host_port(gbe_dev);
  3197. spin_lock_bh(&gbe_dev->hw_stats_lock);
  3198. for (i = 0; i < gbe_dev->num_stats_mods; i++) {
  3199. if (gbe_dev->ss_version == GBE_SS_VERSION_14)
  3200. gbe_reset_mod_stats_ver14(gbe_dev, i);
  3201. else
  3202. gbe_reset_mod_stats(gbe_dev, i);
  3203. }
  3204. spin_unlock_bh(&gbe_dev->hw_stats_lock);
  3205. init_timer(&gbe_dev->timer);
  3206. gbe_dev->timer.data = (unsigned long)gbe_dev;
  3207. gbe_dev->timer.function = netcp_ethss_timer;
  3208. gbe_dev->timer.expires = jiffies + GBE_TIMER_INTERVAL;
  3209. add_timer(&gbe_dev->timer);
  3210. *inst_priv = gbe_dev;
  3211. return 0;
  3212. free_sec_ports:
  3213. free_secondary_ports(gbe_dev);
  3214. return ret;
  3215. }
  3216. static int gbe_attach(void *inst_priv, struct net_device *ndev,
  3217. struct device_node *node, void **intf_priv)
  3218. {
  3219. struct gbe_priv *gbe_dev = inst_priv;
  3220. struct gbe_intf *gbe_intf;
  3221. int ret;
  3222. if (!node) {
  3223. dev_err(gbe_dev->dev, "interface node not available\n");
  3224. return -ENODEV;
  3225. }
  3226. gbe_intf = devm_kzalloc(gbe_dev->dev, sizeof(*gbe_intf), GFP_KERNEL);
  3227. if (!gbe_intf)
  3228. return -ENOMEM;
  3229. gbe_intf->ndev = ndev;
  3230. gbe_intf->dev = gbe_dev->dev;
  3231. gbe_intf->gbe_dev = gbe_dev;
  3232. gbe_intf->slave = devm_kzalloc(gbe_dev->dev,
  3233. sizeof(*gbe_intf->slave),
  3234. GFP_KERNEL);
  3235. if (!gbe_intf->slave) {
  3236. ret = -ENOMEM;
  3237. goto fail;
  3238. }
  3239. if (init_slave(gbe_dev, gbe_intf->slave, node)) {
  3240. ret = -ENODEV;
  3241. goto fail;
  3242. }
  3243. gbe_intf->tx_pipe = gbe_dev->tx_pipe;
  3244. ndev->ethtool_ops = &keystone_ethtool_ops;
  3245. list_add_tail(&gbe_intf->gbe_intf_list, &gbe_dev->gbe_intf_head);
  3246. *intf_priv = gbe_intf;
  3247. return 0;
  3248. fail:
  3249. if (gbe_intf->slave)
  3250. devm_kfree(gbe_dev->dev, gbe_intf->slave);
  3251. if (gbe_intf)
  3252. devm_kfree(gbe_dev->dev, gbe_intf);
  3253. return ret;
  3254. }
  3255. static int gbe_release(void *intf_priv)
  3256. {
  3257. struct gbe_intf *gbe_intf = intf_priv;
  3258. gbe_intf->ndev->ethtool_ops = NULL;
  3259. list_del(&gbe_intf->gbe_intf_list);
  3260. devm_kfree(gbe_intf->dev, gbe_intf->slave);
  3261. devm_kfree(gbe_intf->dev, gbe_intf);
  3262. return 0;
  3263. }
  3264. static int gbe_remove(struct netcp_device *netcp_device, void *inst_priv)
  3265. {
  3266. struct gbe_priv *gbe_dev = inst_priv;
  3267. del_timer_sync(&gbe_dev->timer);
  3268. cpts_release(gbe_dev->cpts);
  3269. cpsw_ale_stop(gbe_dev->ale);
  3270. cpsw_ale_destroy(gbe_dev->ale);
  3271. netcp_txpipe_close(&gbe_dev->tx_pipe);
  3272. free_secondary_ports(gbe_dev);
  3273. if (!list_empty(&gbe_dev->gbe_intf_head))
  3274. dev_alert(gbe_dev->dev,
  3275. "unreleased ethss interfaces present\n");
  3276. return 0;
  3277. }
  3278. static struct netcp_module gbe_module = {
  3279. .name = GBE_MODULE_NAME,
  3280. .owner = THIS_MODULE,
  3281. .primary = true,
  3282. .probe = gbe_probe,
  3283. .open = gbe_open,
  3284. .close = gbe_close,
  3285. .remove = gbe_remove,
  3286. .attach = gbe_attach,
  3287. .release = gbe_release,
  3288. .add_addr = gbe_add_addr,
  3289. .del_addr = gbe_del_addr,
  3290. .add_vid = gbe_add_vid,
  3291. .del_vid = gbe_del_vid,
  3292. .ioctl = gbe_ioctl,
  3293. };
  3294. static struct netcp_module xgbe_module = {
  3295. .name = XGBE_MODULE_NAME,
  3296. .owner = THIS_MODULE,
  3297. .primary = true,
  3298. .probe = gbe_probe,
  3299. .open = gbe_open,
  3300. .close = gbe_close,
  3301. .remove = gbe_remove,
  3302. .attach = gbe_attach,
  3303. .release = gbe_release,
  3304. .add_addr = gbe_add_addr,
  3305. .del_addr = gbe_del_addr,
  3306. .add_vid = gbe_add_vid,
  3307. .del_vid = gbe_del_vid,
  3308. .ioctl = gbe_ioctl,
  3309. };
  3310. static int __init keystone_gbe_init(void)
  3311. {
  3312. int ret;
  3313. ret = netcp_register_module(&gbe_module);
  3314. if (ret)
  3315. return ret;
  3316. ret = netcp_register_module(&xgbe_module);
  3317. if (ret)
  3318. return ret;
  3319. return 0;
  3320. }
  3321. module_init(keystone_gbe_init);
  3322. static void __exit keystone_gbe_exit(void)
  3323. {
  3324. netcp_unregister_module(&gbe_module);
  3325. netcp_unregister_module(&xgbe_module);
  3326. }
  3327. module_exit(keystone_gbe_exit);
  3328. MODULE_LICENSE("GPL v2");
  3329. MODULE_DESCRIPTION("TI NETCP ETHSS driver for Keystone SOCs");
  3330. MODULE_AUTHOR("Sandeep Nair <sandeep_n@ti.com");