qlcnic_dcb.c 28 KB

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  1. /*
  2. * QLogic qlcnic NIC Driver
  3. * Copyright (c) 2009-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qlcnic for copyright and licensing details.
  6. */
  7. #include <linux/types.h>
  8. #include "qlcnic.h"
  9. #define QLC_DCB_NUM_PARAM 3
  10. #define QLC_DCB_LOCAL_IDX 0
  11. #define QLC_DCB_OPER_IDX 1
  12. #define QLC_DCB_PEER_IDX 2
  13. #define QLC_DCB_GET_MAP(V) (1 << V)
  14. #define QLC_DCB_FW_VER 0x2
  15. #define QLC_DCB_MAX_TC 0x8
  16. #define QLC_DCB_MAX_APP 0x8
  17. #define QLC_DCB_MAX_PRIO QLC_DCB_MAX_TC
  18. #define QLC_DCB_MAX_PG QLC_DCB_MAX_TC
  19. #define QLC_DCB_TSA_SUPPORT(V) (V & 0x1)
  20. #define QLC_DCB_ETS_SUPPORT(V) ((V >> 1) & 0x1)
  21. #define QLC_DCB_VERSION_SUPPORT(V) ((V >> 2) & 0xf)
  22. #define QLC_DCB_MAX_NUM_TC(V) ((V >> 20) & 0xf)
  23. #define QLC_DCB_MAX_NUM_ETS_TC(V) ((V >> 24) & 0xf)
  24. #define QLC_DCB_MAX_NUM_PFC_TC(V) ((V >> 28) & 0xf)
  25. #define QLC_DCB_GET_TC_PRIO(X, P) ((X >> (P * 3)) & 0x7)
  26. #define QLC_DCB_GET_PGID_PRIO(X, P) ((X >> (P * 8)) & 0xff)
  27. #define QLC_DCB_GET_BWPER_PG(X, P) ((X >> (P * 8)) & 0xff)
  28. #define QLC_DCB_GET_TSA_PG(X, P) ((X >> (P * 8)) & 0xff)
  29. #define QLC_DCB_GET_PFC_PRIO(X, P) (((X >> 24) >> P) & 0x1)
  30. #define QLC_DCB_GET_PROTO_ID_APP(X) ((X >> 8) & 0xffff)
  31. #define QLC_DCB_GET_SELECTOR_APP(X) (X & 0xff)
  32. #define QLC_DCB_LOCAL_PARAM_FWID 0x3
  33. #define QLC_DCB_OPER_PARAM_FWID 0x1
  34. #define QLC_DCB_PEER_PARAM_FWID 0x2
  35. #define QLC_83XX_DCB_GET_NUMAPP(X) ((X >> 2) & 0xf)
  36. #define QLC_83XX_DCB_TSA_VALID(X) (X & 0x1)
  37. #define QLC_83XX_DCB_PFC_VALID(X) ((X >> 1) & 0x1)
  38. #define QLC_83XX_DCB_GET_PRIOMAP_APP(X) (X >> 24)
  39. #define QLC_82XX_DCB_GET_NUMAPP(X) ((X >> 12) & 0xf)
  40. #define QLC_82XX_DCB_TSA_VALID(X) ((X >> 4) & 0x1)
  41. #define QLC_82XX_DCB_PFC_VALID(X) ((X >> 5) & 0x1)
  42. #define QLC_82XX_DCB_GET_PRIOVAL_APP(X) ((X >> 24) & 0x7)
  43. #define QLC_82XX_DCB_GET_PRIOMAP_APP(X) (1 << X)
  44. #define QLC_82XX_DCB_PRIO_TC_MAP (0x76543210)
  45. static const struct dcbnl_rtnl_ops qlcnic_dcbnl_ops;
  46. static void qlcnic_dcb_aen_work(struct work_struct *);
  47. static void qlcnic_dcb_data_cee_param_map(struct qlcnic_adapter *);
  48. static inline void __qlcnic_init_dcbnl_ops(struct qlcnic_dcb *);
  49. static void __qlcnic_dcb_free(struct qlcnic_dcb *);
  50. static int __qlcnic_dcb_attach(struct qlcnic_dcb *);
  51. static int __qlcnic_dcb_query_hw_capability(struct qlcnic_dcb *, char *);
  52. static void __qlcnic_dcb_get_info(struct qlcnic_dcb *);
  53. static int qlcnic_82xx_dcb_get_hw_capability(struct qlcnic_dcb *);
  54. static int qlcnic_82xx_dcb_query_cee_param(struct qlcnic_dcb *, char *, u8);
  55. static int qlcnic_82xx_dcb_get_cee_cfg(struct qlcnic_dcb *);
  56. static void qlcnic_82xx_dcb_aen_handler(struct qlcnic_dcb *, void *);
  57. static int qlcnic_83xx_dcb_get_hw_capability(struct qlcnic_dcb *);
  58. static int qlcnic_83xx_dcb_query_cee_param(struct qlcnic_dcb *, char *, u8);
  59. static int qlcnic_83xx_dcb_get_cee_cfg(struct qlcnic_dcb *);
  60. static void qlcnic_83xx_dcb_aen_handler(struct qlcnic_dcb *, void *);
  61. struct qlcnic_dcb_capability {
  62. bool tsa_capability;
  63. bool ets_capability;
  64. u8 max_num_tc;
  65. u8 max_ets_tc;
  66. u8 max_pfc_tc;
  67. u8 dcb_capability;
  68. };
  69. struct qlcnic_dcb_param {
  70. u32 hdr_prio_pfc_map[2];
  71. u32 prio_pg_map[2];
  72. u32 pg_bw_map[2];
  73. u32 pg_tsa_map[2];
  74. u32 app[QLC_DCB_MAX_APP];
  75. };
  76. struct qlcnic_dcb_mbx_params {
  77. /* 1st local, 2nd operational 3rd remote */
  78. struct qlcnic_dcb_param type[3];
  79. u32 prio_tc_map;
  80. };
  81. struct qlcnic_82xx_dcb_param_mbx_le {
  82. __le32 hdr_prio_pfc_map[2];
  83. __le32 prio_pg_map[2];
  84. __le32 pg_bw_map[2];
  85. __le32 pg_tsa_map[2];
  86. __le32 app[QLC_DCB_MAX_APP];
  87. };
  88. enum qlcnic_dcb_selector {
  89. QLC_SELECTOR_DEF = 0x0,
  90. QLC_SELECTOR_ETHER,
  91. QLC_SELECTOR_TCP,
  92. QLC_SELECTOR_UDP,
  93. };
  94. enum qlcnic_dcb_prio_type {
  95. QLC_PRIO_NONE = 0,
  96. QLC_PRIO_GROUP,
  97. QLC_PRIO_LINK,
  98. };
  99. enum qlcnic_dcb_pfc_type {
  100. QLC_PFC_DISABLED = 0,
  101. QLC_PFC_FULL,
  102. QLC_PFC_TX,
  103. QLC_PFC_RX
  104. };
  105. struct qlcnic_dcb_prio_cfg {
  106. bool valid;
  107. enum qlcnic_dcb_pfc_type pfc_type;
  108. };
  109. struct qlcnic_dcb_pg_cfg {
  110. bool valid;
  111. u8 total_bw_percent; /* of Link/ port BW */
  112. u8 prio_count;
  113. u8 tsa_type;
  114. };
  115. struct qlcnic_dcb_tc_cfg {
  116. bool valid;
  117. struct qlcnic_dcb_prio_cfg prio_cfg[QLC_DCB_MAX_PRIO];
  118. enum qlcnic_dcb_prio_type prio_type; /* always prio_link */
  119. u8 link_percent; /* % of link bandwidth */
  120. u8 bwg_percent; /* % of BWG's bandwidth */
  121. u8 up_tc_map;
  122. u8 pgid;
  123. };
  124. struct qlcnic_dcb_app {
  125. bool valid;
  126. enum qlcnic_dcb_selector selector;
  127. u16 protocol;
  128. u8 priority;
  129. };
  130. struct qlcnic_dcb_cee {
  131. struct qlcnic_dcb_tc_cfg tc_cfg[QLC_DCB_MAX_TC];
  132. struct qlcnic_dcb_pg_cfg pg_cfg[QLC_DCB_MAX_PG];
  133. struct qlcnic_dcb_app app[QLC_DCB_MAX_APP];
  134. bool tc_param_valid;
  135. bool pfc_mode_enable;
  136. };
  137. struct qlcnic_dcb_cfg {
  138. /* 0 - local, 1 - operational, 2 - remote */
  139. struct qlcnic_dcb_cee type[QLC_DCB_NUM_PARAM];
  140. struct qlcnic_dcb_capability capability;
  141. u32 version;
  142. };
  143. static const struct qlcnic_dcb_ops qlcnic_83xx_dcb_ops = {
  144. .init_dcbnl_ops = __qlcnic_init_dcbnl_ops,
  145. .free = __qlcnic_dcb_free,
  146. .attach = __qlcnic_dcb_attach,
  147. .query_hw_capability = __qlcnic_dcb_query_hw_capability,
  148. .get_info = __qlcnic_dcb_get_info,
  149. .get_hw_capability = qlcnic_83xx_dcb_get_hw_capability,
  150. .query_cee_param = qlcnic_83xx_dcb_query_cee_param,
  151. .get_cee_cfg = qlcnic_83xx_dcb_get_cee_cfg,
  152. .aen_handler = qlcnic_83xx_dcb_aen_handler,
  153. };
  154. static const struct qlcnic_dcb_ops qlcnic_82xx_dcb_ops = {
  155. .init_dcbnl_ops = __qlcnic_init_dcbnl_ops,
  156. .free = __qlcnic_dcb_free,
  157. .attach = __qlcnic_dcb_attach,
  158. .query_hw_capability = __qlcnic_dcb_query_hw_capability,
  159. .get_info = __qlcnic_dcb_get_info,
  160. .get_hw_capability = qlcnic_82xx_dcb_get_hw_capability,
  161. .query_cee_param = qlcnic_82xx_dcb_query_cee_param,
  162. .get_cee_cfg = qlcnic_82xx_dcb_get_cee_cfg,
  163. .aen_handler = qlcnic_82xx_dcb_aen_handler,
  164. };
  165. static u8 qlcnic_dcb_get_num_app(struct qlcnic_adapter *adapter, u32 val)
  166. {
  167. if (qlcnic_82xx_check(adapter))
  168. return QLC_82XX_DCB_GET_NUMAPP(val);
  169. else
  170. return QLC_83XX_DCB_GET_NUMAPP(val);
  171. }
  172. static inline u8 qlcnic_dcb_pfc_hdr_valid(struct qlcnic_adapter *adapter,
  173. u32 val)
  174. {
  175. if (qlcnic_82xx_check(adapter))
  176. return QLC_82XX_DCB_PFC_VALID(val);
  177. else
  178. return QLC_83XX_DCB_PFC_VALID(val);
  179. }
  180. static inline u8 qlcnic_dcb_tsa_hdr_valid(struct qlcnic_adapter *adapter,
  181. u32 val)
  182. {
  183. if (qlcnic_82xx_check(adapter))
  184. return QLC_82XX_DCB_TSA_VALID(val);
  185. else
  186. return QLC_83XX_DCB_TSA_VALID(val);
  187. }
  188. static inline u8 qlcnic_dcb_get_prio_map_app(struct qlcnic_adapter *adapter,
  189. u32 val)
  190. {
  191. if (qlcnic_82xx_check(adapter))
  192. return QLC_82XX_DCB_GET_PRIOMAP_APP(val);
  193. else
  194. return QLC_83XX_DCB_GET_PRIOMAP_APP(val);
  195. }
  196. static int qlcnic_dcb_prio_count(u8 up_tc_map)
  197. {
  198. int j;
  199. for (j = 0; j < QLC_DCB_MAX_TC; j++)
  200. if (up_tc_map & QLC_DCB_GET_MAP(j))
  201. break;
  202. return j;
  203. }
  204. static inline void __qlcnic_init_dcbnl_ops(struct qlcnic_dcb *dcb)
  205. {
  206. if (test_bit(QLCNIC_DCB_STATE, &dcb->state))
  207. dcb->adapter->netdev->dcbnl_ops = &qlcnic_dcbnl_ops;
  208. }
  209. static void qlcnic_set_dcb_ops(struct qlcnic_adapter *adapter)
  210. {
  211. if (qlcnic_82xx_check(adapter))
  212. adapter->dcb->ops = &qlcnic_82xx_dcb_ops;
  213. else if (qlcnic_83xx_check(adapter))
  214. adapter->dcb->ops = &qlcnic_83xx_dcb_ops;
  215. }
  216. int qlcnic_register_dcb(struct qlcnic_adapter *adapter)
  217. {
  218. struct qlcnic_dcb *dcb;
  219. if (qlcnic_sriov_vf_check(adapter))
  220. return 0;
  221. dcb = kzalloc(sizeof(struct qlcnic_dcb), GFP_ATOMIC);
  222. if (!dcb)
  223. return -ENOMEM;
  224. adapter->dcb = dcb;
  225. dcb->adapter = adapter;
  226. qlcnic_set_dcb_ops(adapter);
  227. dcb->state = 0;
  228. return 0;
  229. }
  230. static void __qlcnic_dcb_free(struct qlcnic_dcb *dcb)
  231. {
  232. struct qlcnic_adapter *adapter;
  233. if (!dcb)
  234. return;
  235. adapter = dcb->adapter;
  236. while (test_bit(QLCNIC_DCB_AEN_MODE, &dcb->state))
  237. usleep_range(10000, 11000);
  238. cancel_delayed_work_sync(&dcb->aen_work);
  239. if (dcb->wq) {
  240. destroy_workqueue(dcb->wq);
  241. dcb->wq = NULL;
  242. }
  243. kfree(dcb->cfg);
  244. dcb->cfg = NULL;
  245. kfree(dcb->param);
  246. dcb->param = NULL;
  247. kfree(dcb);
  248. adapter->dcb = NULL;
  249. }
  250. static void __qlcnic_dcb_get_info(struct qlcnic_dcb *dcb)
  251. {
  252. qlcnic_dcb_get_hw_capability(dcb);
  253. qlcnic_dcb_get_cee_cfg(dcb);
  254. }
  255. static int __qlcnic_dcb_attach(struct qlcnic_dcb *dcb)
  256. {
  257. int err = 0;
  258. INIT_DELAYED_WORK(&dcb->aen_work, qlcnic_dcb_aen_work);
  259. dcb->wq = create_singlethread_workqueue("qlcnic-dcb");
  260. if (!dcb->wq) {
  261. dev_err(&dcb->adapter->pdev->dev,
  262. "DCB workqueue allocation failed. DCB will be disabled\n");
  263. return -1;
  264. }
  265. dcb->cfg = kzalloc(sizeof(struct qlcnic_dcb_cfg), GFP_ATOMIC);
  266. if (!dcb->cfg) {
  267. err = -ENOMEM;
  268. goto out_free_wq;
  269. }
  270. dcb->param = kzalloc(sizeof(struct qlcnic_dcb_mbx_params), GFP_ATOMIC);
  271. if (!dcb->param) {
  272. err = -ENOMEM;
  273. goto out_free_cfg;
  274. }
  275. return 0;
  276. out_free_cfg:
  277. kfree(dcb->cfg);
  278. dcb->cfg = NULL;
  279. out_free_wq:
  280. destroy_workqueue(dcb->wq);
  281. dcb->wq = NULL;
  282. return err;
  283. }
  284. static int __qlcnic_dcb_query_hw_capability(struct qlcnic_dcb *dcb, char *buf)
  285. {
  286. struct qlcnic_adapter *adapter = dcb->adapter;
  287. struct qlcnic_cmd_args cmd;
  288. u32 mbx_out;
  289. int err;
  290. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DCB_QUERY_CAP);
  291. if (err)
  292. return err;
  293. err = qlcnic_issue_cmd(adapter, &cmd);
  294. if (err) {
  295. dev_err(&adapter->pdev->dev,
  296. "Failed to query DCBX capability, err %d\n", err);
  297. } else {
  298. mbx_out = cmd.rsp.arg[1];
  299. if (buf)
  300. memcpy(buf, &mbx_out, sizeof(u32));
  301. }
  302. qlcnic_free_mbx_args(&cmd);
  303. return err;
  304. }
  305. static int __qlcnic_dcb_get_capability(struct qlcnic_dcb *dcb, u32 *val)
  306. {
  307. struct qlcnic_dcb_capability *cap = &dcb->cfg->capability;
  308. u32 mbx_out;
  309. int err;
  310. memset(cap, 0, sizeof(struct qlcnic_dcb_capability));
  311. err = qlcnic_dcb_query_hw_capability(dcb, (char *)val);
  312. if (err)
  313. return err;
  314. mbx_out = *val;
  315. if (QLC_DCB_TSA_SUPPORT(mbx_out))
  316. cap->tsa_capability = true;
  317. if (QLC_DCB_ETS_SUPPORT(mbx_out))
  318. cap->ets_capability = true;
  319. cap->max_num_tc = QLC_DCB_MAX_NUM_TC(mbx_out);
  320. cap->max_ets_tc = QLC_DCB_MAX_NUM_ETS_TC(mbx_out);
  321. cap->max_pfc_tc = QLC_DCB_MAX_NUM_PFC_TC(mbx_out);
  322. if (cap->max_num_tc > QLC_DCB_MAX_TC ||
  323. cap->max_ets_tc > cap->max_num_tc ||
  324. cap->max_pfc_tc > cap->max_num_tc) {
  325. dev_err(&dcb->adapter->pdev->dev, "Invalid DCB configuration\n");
  326. return -EINVAL;
  327. }
  328. return err;
  329. }
  330. static int qlcnic_82xx_dcb_get_hw_capability(struct qlcnic_dcb *dcb)
  331. {
  332. struct qlcnic_dcb_cfg *cfg = dcb->cfg;
  333. struct qlcnic_dcb_capability *cap;
  334. u32 mbx_out;
  335. int err;
  336. err = __qlcnic_dcb_get_capability(dcb, &mbx_out);
  337. if (err)
  338. return err;
  339. cap = &cfg->capability;
  340. cap->dcb_capability = DCB_CAP_DCBX_VER_CEE | DCB_CAP_DCBX_LLD_MANAGED;
  341. if (cap->dcb_capability && cap->tsa_capability && cap->ets_capability)
  342. set_bit(QLCNIC_DCB_STATE, &dcb->state);
  343. return err;
  344. }
  345. static int qlcnic_82xx_dcb_query_cee_param(struct qlcnic_dcb *dcb,
  346. char *buf, u8 type)
  347. {
  348. u16 size = sizeof(struct qlcnic_82xx_dcb_param_mbx_le);
  349. struct qlcnic_adapter *adapter = dcb->adapter;
  350. struct qlcnic_82xx_dcb_param_mbx_le *prsp_le;
  351. struct device *dev = &adapter->pdev->dev;
  352. dma_addr_t cardrsp_phys_addr;
  353. struct qlcnic_dcb_param rsp;
  354. struct qlcnic_cmd_args cmd;
  355. u64 phys_addr;
  356. void *addr;
  357. int err, i;
  358. switch (type) {
  359. case QLC_DCB_LOCAL_PARAM_FWID:
  360. case QLC_DCB_OPER_PARAM_FWID:
  361. case QLC_DCB_PEER_PARAM_FWID:
  362. break;
  363. default:
  364. dev_err(dev, "Invalid parameter type %d\n", type);
  365. return -EINVAL;
  366. }
  367. addr = dma_alloc_coherent(dev, size, &cardrsp_phys_addr, GFP_KERNEL);
  368. if (addr == NULL)
  369. return -ENOMEM;
  370. prsp_le = addr;
  371. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DCB_QUERY_PARAM);
  372. if (err)
  373. goto out_free_rsp;
  374. phys_addr = cardrsp_phys_addr;
  375. cmd.req.arg[1] = size | (type << 16);
  376. cmd.req.arg[2] = MSD(phys_addr);
  377. cmd.req.arg[3] = LSD(phys_addr);
  378. err = qlcnic_issue_cmd(adapter, &cmd);
  379. if (err) {
  380. dev_err(dev, "Failed to query DCBX parameter, err %d\n", err);
  381. goto out;
  382. }
  383. memset(&rsp, 0, sizeof(struct qlcnic_dcb_param));
  384. rsp.hdr_prio_pfc_map[0] = le32_to_cpu(prsp_le->hdr_prio_pfc_map[0]);
  385. rsp.hdr_prio_pfc_map[1] = le32_to_cpu(prsp_le->hdr_prio_pfc_map[1]);
  386. rsp.prio_pg_map[0] = le32_to_cpu(prsp_le->prio_pg_map[0]);
  387. rsp.prio_pg_map[1] = le32_to_cpu(prsp_le->prio_pg_map[1]);
  388. rsp.pg_bw_map[0] = le32_to_cpu(prsp_le->pg_bw_map[0]);
  389. rsp.pg_bw_map[1] = le32_to_cpu(prsp_le->pg_bw_map[1]);
  390. rsp.pg_tsa_map[0] = le32_to_cpu(prsp_le->pg_tsa_map[0]);
  391. rsp.pg_tsa_map[1] = le32_to_cpu(prsp_le->pg_tsa_map[1]);
  392. for (i = 0; i < QLC_DCB_MAX_APP; i++)
  393. rsp.app[i] = le32_to_cpu(prsp_le->app[i]);
  394. if (buf)
  395. memcpy(buf, &rsp, size);
  396. out:
  397. qlcnic_free_mbx_args(&cmd);
  398. out_free_rsp:
  399. dma_free_coherent(dev, size, addr, cardrsp_phys_addr);
  400. return err;
  401. }
  402. static int qlcnic_82xx_dcb_get_cee_cfg(struct qlcnic_dcb *dcb)
  403. {
  404. struct qlcnic_dcb_mbx_params *mbx;
  405. int err;
  406. mbx = dcb->param;
  407. if (!mbx)
  408. return 0;
  409. err = qlcnic_dcb_query_cee_param(dcb, (char *)&mbx->type[0],
  410. QLC_DCB_LOCAL_PARAM_FWID);
  411. if (err)
  412. return err;
  413. err = qlcnic_dcb_query_cee_param(dcb, (char *)&mbx->type[1],
  414. QLC_DCB_OPER_PARAM_FWID);
  415. if (err)
  416. return err;
  417. err = qlcnic_dcb_query_cee_param(dcb, (char *)&mbx->type[2],
  418. QLC_DCB_PEER_PARAM_FWID);
  419. if (err)
  420. return err;
  421. mbx->prio_tc_map = QLC_82XX_DCB_PRIO_TC_MAP;
  422. qlcnic_dcb_data_cee_param_map(dcb->adapter);
  423. return err;
  424. }
  425. static void qlcnic_dcb_aen_work(struct work_struct *work)
  426. {
  427. struct qlcnic_dcb *dcb;
  428. dcb = container_of(work, struct qlcnic_dcb, aen_work.work);
  429. qlcnic_dcb_get_cee_cfg(dcb);
  430. clear_bit(QLCNIC_DCB_AEN_MODE, &dcb->state);
  431. }
  432. static void qlcnic_82xx_dcb_aen_handler(struct qlcnic_dcb *dcb, void *data)
  433. {
  434. if (test_and_set_bit(QLCNIC_DCB_AEN_MODE, &dcb->state))
  435. return;
  436. queue_delayed_work(dcb->wq, &dcb->aen_work, 0);
  437. }
  438. static int qlcnic_83xx_dcb_get_hw_capability(struct qlcnic_dcb *dcb)
  439. {
  440. struct qlcnic_dcb_capability *cap = &dcb->cfg->capability;
  441. u32 mbx_out;
  442. int err;
  443. err = __qlcnic_dcb_get_capability(dcb, &mbx_out);
  444. if (err)
  445. return err;
  446. if (mbx_out & BIT_2)
  447. cap->dcb_capability = DCB_CAP_DCBX_VER_CEE;
  448. if (mbx_out & BIT_3)
  449. cap->dcb_capability |= DCB_CAP_DCBX_VER_IEEE;
  450. if (cap->dcb_capability)
  451. cap->dcb_capability |= DCB_CAP_DCBX_LLD_MANAGED;
  452. if (cap->dcb_capability && cap->tsa_capability && cap->ets_capability)
  453. set_bit(QLCNIC_DCB_STATE, &dcb->state);
  454. return err;
  455. }
  456. static int qlcnic_83xx_dcb_query_cee_param(struct qlcnic_dcb *dcb,
  457. char *buf, u8 idx)
  458. {
  459. struct qlcnic_adapter *adapter = dcb->adapter;
  460. struct qlcnic_dcb_mbx_params mbx_out;
  461. int err, i, j, k, max_app, size;
  462. struct qlcnic_dcb_param *each;
  463. struct qlcnic_cmd_args cmd;
  464. u32 val;
  465. char *p;
  466. size = 0;
  467. memset(&mbx_out, 0, sizeof(struct qlcnic_dcb_mbx_params));
  468. memset(buf, 0, sizeof(struct qlcnic_dcb_mbx_params));
  469. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DCB_QUERY_PARAM);
  470. if (err)
  471. return err;
  472. cmd.req.arg[0] |= QLC_DCB_FW_VER << 29;
  473. err = qlcnic_issue_cmd(adapter, &cmd);
  474. if (err) {
  475. dev_err(&adapter->pdev->dev,
  476. "Failed to query DCBX param, err %d\n", err);
  477. goto out;
  478. }
  479. mbx_out.prio_tc_map = cmd.rsp.arg[1];
  480. p = memcpy(buf, &mbx_out, sizeof(u32));
  481. k = 2;
  482. p += sizeof(u32);
  483. for (j = 0; j < QLC_DCB_NUM_PARAM; j++) {
  484. each = &mbx_out.type[j];
  485. each->hdr_prio_pfc_map[0] = cmd.rsp.arg[k++];
  486. each->hdr_prio_pfc_map[1] = cmd.rsp.arg[k++];
  487. each->prio_pg_map[0] = cmd.rsp.arg[k++];
  488. each->prio_pg_map[1] = cmd.rsp.arg[k++];
  489. each->pg_bw_map[0] = cmd.rsp.arg[k++];
  490. each->pg_bw_map[1] = cmd.rsp.arg[k++];
  491. each->pg_tsa_map[0] = cmd.rsp.arg[k++];
  492. each->pg_tsa_map[1] = cmd.rsp.arg[k++];
  493. val = each->hdr_prio_pfc_map[0];
  494. max_app = qlcnic_dcb_get_num_app(adapter, val);
  495. for (i = 0; i < max_app; i++)
  496. each->app[i] = cmd.rsp.arg[i + k];
  497. size = 16 * sizeof(u32);
  498. memcpy(p, &each->hdr_prio_pfc_map[0], size);
  499. p += size;
  500. if (j == 0)
  501. k = 18;
  502. else
  503. k = 34;
  504. }
  505. out:
  506. qlcnic_free_mbx_args(&cmd);
  507. return err;
  508. }
  509. static int qlcnic_83xx_dcb_get_cee_cfg(struct qlcnic_dcb *dcb)
  510. {
  511. int err;
  512. err = qlcnic_dcb_query_cee_param(dcb, (char *)dcb->param, 0);
  513. if (err)
  514. return err;
  515. qlcnic_dcb_data_cee_param_map(dcb->adapter);
  516. return err;
  517. }
  518. static void qlcnic_83xx_dcb_aen_handler(struct qlcnic_dcb *dcb, void *data)
  519. {
  520. u32 *val = data;
  521. if (test_and_set_bit(QLCNIC_DCB_AEN_MODE, &dcb->state))
  522. return;
  523. if (*val & BIT_8)
  524. set_bit(QLCNIC_DCB_STATE, &dcb->state);
  525. else
  526. clear_bit(QLCNIC_DCB_STATE, &dcb->state);
  527. queue_delayed_work(dcb->wq, &dcb->aen_work, 0);
  528. }
  529. static void qlcnic_dcb_fill_cee_tc_params(struct qlcnic_dcb_mbx_params *mbx,
  530. struct qlcnic_dcb_param *each,
  531. struct qlcnic_dcb_cee *type)
  532. {
  533. struct qlcnic_dcb_tc_cfg *tc_cfg;
  534. u8 i, tc, pgid;
  535. for (i = 0; i < QLC_DCB_MAX_PRIO; i++) {
  536. tc = QLC_DCB_GET_TC_PRIO(mbx->prio_tc_map, i);
  537. tc_cfg = &type->tc_cfg[tc];
  538. tc_cfg->valid = true;
  539. tc_cfg->up_tc_map |= QLC_DCB_GET_MAP(i);
  540. if (QLC_DCB_GET_PFC_PRIO(each->hdr_prio_pfc_map[1], i) &&
  541. type->pfc_mode_enable) {
  542. tc_cfg->prio_cfg[i].valid = true;
  543. tc_cfg->prio_cfg[i].pfc_type = QLC_PFC_FULL;
  544. }
  545. if (i < 4)
  546. pgid = QLC_DCB_GET_PGID_PRIO(each->prio_pg_map[0], i);
  547. else
  548. pgid = QLC_DCB_GET_PGID_PRIO(each->prio_pg_map[1], i);
  549. tc_cfg->pgid = pgid;
  550. tc_cfg->prio_type = QLC_PRIO_LINK;
  551. type->pg_cfg[tc_cfg->pgid].prio_count++;
  552. }
  553. }
  554. static void qlcnic_dcb_fill_cee_pg_params(struct qlcnic_dcb_param *each,
  555. struct qlcnic_dcb_cee *type)
  556. {
  557. struct qlcnic_dcb_pg_cfg *pg_cfg;
  558. u8 i, tsa, bw_per;
  559. for (i = 0; i < QLC_DCB_MAX_PG; i++) {
  560. pg_cfg = &type->pg_cfg[i];
  561. pg_cfg->valid = true;
  562. if (i < 4) {
  563. bw_per = QLC_DCB_GET_BWPER_PG(each->pg_bw_map[0], i);
  564. tsa = QLC_DCB_GET_TSA_PG(each->pg_tsa_map[0], i);
  565. } else {
  566. bw_per = QLC_DCB_GET_BWPER_PG(each->pg_bw_map[1], i);
  567. tsa = QLC_DCB_GET_TSA_PG(each->pg_tsa_map[1], i);
  568. }
  569. pg_cfg->total_bw_percent = bw_per;
  570. pg_cfg->tsa_type = tsa;
  571. }
  572. }
  573. static void
  574. qlcnic_dcb_fill_cee_app_params(struct qlcnic_adapter *adapter, u8 idx,
  575. struct qlcnic_dcb_param *each,
  576. struct qlcnic_dcb_cee *type)
  577. {
  578. struct qlcnic_dcb_app *app;
  579. u8 i, num_app, map, cnt;
  580. struct dcb_app new_app;
  581. num_app = qlcnic_dcb_get_num_app(adapter, each->hdr_prio_pfc_map[0]);
  582. for (i = 0; i < num_app; i++) {
  583. app = &type->app[i];
  584. app->valid = true;
  585. /* Only for CEE (-1) */
  586. app->selector = QLC_DCB_GET_SELECTOR_APP(each->app[i]) - 1;
  587. new_app.selector = app->selector;
  588. app->protocol = QLC_DCB_GET_PROTO_ID_APP(each->app[i]);
  589. new_app.protocol = app->protocol;
  590. map = qlcnic_dcb_get_prio_map_app(adapter, each->app[i]);
  591. cnt = qlcnic_dcb_prio_count(map);
  592. if (cnt >= QLC_DCB_MAX_TC)
  593. cnt = 0;
  594. app->priority = cnt;
  595. new_app.priority = cnt;
  596. if (idx == QLC_DCB_OPER_IDX && adapter->netdev->dcbnl_ops)
  597. dcb_setapp(adapter->netdev, &new_app);
  598. }
  599. }
  600. static void qlcnic_dcb_map_cee_params(struct qlcnic_adapter *adapter, u8 idx)
  601. {
  602. struct qlcnic_dcb_mbx_params *mbx = adapter->dcb->param;
  603. struct qlcnic_dcb_param *each = &mbx->type[idx];
  604. struct qlcnic_dcb_cfg *cfg = adapter->dcb->cfg;
  605. struct qlcnic_dcb_cee *type = &cfg->type[idx];
  606. type->tc_param_valid = false;
  607. type->pfc_mode_enable = false;
  608. memset(type->tc_cfg, 0,
  609. sizeof(struct qlcnic_dcb_tc_cfg) * QLC_DCB_MAX_TC);
  610. memset(type->pg_cfg, 0,
  611. sizeof(struct qlcnic_dcb_pg_cfg) * QLC_DCB_MAX_TC);
  612. if (qlcnic_dcb_pfc_hdr_valid(adapter, each->hdr_prio_pfc_map[0]) &&
  613. cfg->capability.max_pfc_tc)
  614. type->pfc_mode_enable = true;
  615. if (qlcnic_dcb_tsa_hdr_valid(adapter, each->hdr_prio_pfc_map[0]) &&
  616. cfg->capability.max_ets_tc)
  617. type->tc_param_valid = true;
  618. qlcnic_dcb_fill_cee_tc_params(mbx, each, type);
  619. qlcnic_dcb_fill_cee_pg_params(each, type);
  620. qlcnic_dcb_fill_cee_app_params(adapter, idx, each, type);
  621. }
  622. static void qlcnic_dcb_data_cee_param_map(struct qlcnic_adapter *adapter)
  623. {
  624. int i;
  625. for (i = 0; i < QLC_DCB_NUM_PARAM; i++)
  626. qlcnic_dcb_map_cee_params(adapter, i);
  627. dcbnl_cee_notify(adapter->netdev, RTM_GETDCB, DCB_CMD_CEE_GET, 0, 0);
  628. }
  629. static u8 qlcnic_dcb_get_state(struct net_device *netdev)
  630. {
  631. struct qlcnic_adapter *adapter = netdev_priv(netdev);
  632. return test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state);
  633. }
  634. static void qlcnic_dcb_get_perm_hw_addr(struct net_device *netdev, u8 *addr)
  635. {
  636. memcpy(addr, netdev->perm_addr, netdev->addr_len);
  637. }
  638. static void
  639. qlcnic_dcb_get_pg_tc_cfg_tx(struct net_device *netdev, int tc, u8 *prio,
  640. u8 *pgid, u8 *bw_per, u8 *up_tc_map)
  641. {
  642. struct qlcnic_adapter *adapter = netdev_priv(netdev);
  643. struct qlcnic_dcb_tc_cfg *tc_cfg, *temp;
  644. struct qlcnic_dcb_cee *type;
  645. u8 i, cnt, pg;
  646. type = &adapter->dcb->cfg->type[QLC_DCB_OPER_IDX];
  647. *prio = *pgid = *bw_per = *up_tc_map = 0;
  648. if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state) ||
  649. !type->tc_param_valid)
  650. return;
  651. if (tc < 0 || (tc >= QLC_DCB_MAX_TC))
  652. return;
  653. tc_cfg = &type->tc_cfg[tc];
  654. if (!tc_cfg->valid)
  655. return;
  656. *pgid = tc_cfg->pgid;
  657. *prio = tc_cfg->prio_type;
  658. *up_tc_map = tc_cfg->up_tc_map;
  659. pg = *pgid;
  660. for (i = 0, cnt = 0; i < QLC_DCB_MAX_TC; i++) {
  661. temp = &type->tc_cfg[i];
  662. if (temp->valid && (pg == temp->pgid))
  663. cnt++;
  664. }
  665. tc_cfg->bwg_percent = (100 / cnt);
  666. *bw_per = tc_cfg->bwg_percent;
  667. }
  668. static void qlcnic_dcb_get_pg_bwg_cfg_tx(struct net_device *netdev, int pgid,
  669. u8 *bw_pct)
  670. {
  671. struct qlcnic_adapter *adapter = netdev_priv(netdev);
  672. struct qlcnic_dcb_pg_cfg *pgcfg;
  673. struct qlcnic_dcb_cee *type;
  674. *bw_pct = 0;
  675. type = &adapter->dcb->cfg->type[QLC_DCB_OPER_IDX];
  676. if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state) ||
  677. !type->tc_param_valid)
  678. return;
  679. if (pgid < 0 || pgid >= QLC_DCB_MAX_PG)
  680. return;
  681. pgcfg = &type->pg_cfg[pgid];
  682. if (!pgcfg->valid)
  683. return;
  684. *bw_pct = pgcfg->total_bw_percent;
  685. }
  686. static void qlcnic_dcb_get_pfc_cfg(struct net_device *netdev, int prio,
  687. u8 *setting)
  688. {
  689. struct qlcnic_adapter *adapter = netdev_priv(netdev);
  690. struct qlcnic_dcb_tc_cfg *tc_cfg;
  691. u8 val = QLC_DCB_GET_MAP(prio);
  692. struct qlcnic_dcb_cee *type;
  693. u8 i;
  694. *setting = 0;
  695. type = &adapter->dcb->cfg->type[QLC_DCB_OPER_IDX];
  696. if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state) ||
  697. !type->pfc_mode_enable)
  698. return;
  699. for (i = 0; i < QLC_DCB_MAX_TC; i++) {
  700. tc_cfg = &type->tc_cfg[i];
  701. if (!tc_cfg->valid)
  702. continue;
  703. if ((val & tc_cfg->up_tc_map) && (tc_cfg->prio_cfg[prio].valid))
  704. *setting = tc_cfg->prio_cfg[prio].pfc_type;
  705. }
  706. }
  707. static u8 qlcnic_dcb_get_capability(struct net_device *netdev, int capid,
  708. u8 *cap)
  709. {
  710. struct qlcnic_adapter *adapter = netdev_priv(netdev);
  711. if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
  712. return 0;
  713. switch (capid) {
  714. case DCB_CAP_ATTR_PG:
  715. case DCB_CAP_ATTR_UP2TC:
  716. case DCB_CAP_ATTR_PFC:
  717. case DCB_CAP_ATTR_GSP:
  718. *cap = true;
  719. break;
  720. case DCB_CAP_ATTR_PG_TCS:
  721. case DCB_CAP_ATTR_PFC_TCS:
  722. *cap = 0x80; /* 8 priorities for PGs */
  723. break;
  724. case DCB_CAP_ATTR_DCBX:
  725. *cap = adapter->dcb->cfg->capability.dcb_capability;
  726. break;
  727. default:
  728. *cap = false;
  729. }
  730. return 0;
  731. }
  732. static int qlcnic_dcb_get_num_tcs(struct net_device *netdev, int attr, u8 *num)
  733. {
  734. struct qlcnic_adapter *adapter = netdev_priv(netdev);
  735. struct qlcnic_dcb_cfg *cfg = adapter->dcb->cfg;
  736. if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
  737. return -EINVAL;
  738. switch (attr) {
  739. case DCB_NUMTCS_ATTR_PG:
  740. *num = cfg->capability.max_ets_tc;
  741. return 0;
  742. case DCB_NUMTCS_ATTR_PFC:
  743. *num = cfg->capability.max_pfc_tc;
  744. return 0;
  745. default:
  746. return -EINVAL;
  747. }
  748. }
  749. static int qlcnic_dcb_get_app(struct net_device *netdev, u8 idtype, u16 id)
  750. {
  751. struct qlcnic_adapter *adapter = netdev_priv(netdev);
  752. struct dcb_app app = {
  753. .selector = idtype,
  754. .protocol = id,
  755. };
  756. if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
  757. return -EINVAL;
  758. return dcb_getapp(netdev, &app);
  759. }
  760. static u8 qlcnic_dcb_get_pfc_state(struct net_device *netdev)
  761. {
  762. struct qlcnic_adapter *adapter = netdev_priv(netdev);
  763. struct qlcnic_dcb *dcb = adapter->dcb;
  764. if (!test_bit(QLCNIC_DCB_STATE, &dcb->state))
  765. return 0;
  766. return dcb->cfg->type[QLC_DCB_OPER_IDX].pfc_mode_enable;
  767. }
  768. static u8 qlcnic_dcb_get_dcbx(struct net_device *netdev)
  769. {
  770. struct qlcnic_adapter *adapter = netdev_priv(netdev);
  771. struct qlcnic_dcb_cfg *cfg = adapter->dcb->cfg;
  772. if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
  773. return 0;
  774. return cfg->capability.dcb_capability;
  775. }
  776. static u8 qlcnic_dcb_get_feat_cfg(struct net_device *netdev, int fid, u8 *flag)
  777. {
  778. struct qlcnic_adapter *adapter = netdev_priv(netdev);
  779. struct qlcnic_dcb_cee *type;
  780. if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
  781. return 1;
  782. type = &adapter->dcb->cfg->type[QLC_DCB_OPER_IDX];
  783. *flag = 0;
  784. switch (fid) {
  785. case DCB_FEATCFG_ATTR_PG:
  786. if (type->tc_param_valid)
  787. *flag |= DCB_FEATCFG_ENABLE;
  788. else
  789. *flag |= DCB_FEATCFG_ERROR;
  790. break;
  791. case DCB_FEATCFG_ATTR_PFC:
  792. if (type->pfc_mode_enable) {
  793. if (type->tc_cfg[0].prio_cfg[0].pfc_type)
  794. *flag |= DCB_FEATCFG_ENABLE;
  795. } else {
  796. *flag |= DCB_FEATCFG_ERROR;
  797. }
  798. break;
  799. case DCB_FEATCFG_ATTR_APP:
  800. *flag |= DCB_FEATCFG_ENABLE;
  801. break;
  802. default:
  803. netdev_err(netdev, "Invalid Feature ID %d\n", fid);
  804. return 1;
  805. }
  806. return 0;
  807. }
  808. static inline void
  809. qlcnic_dcb_get_pg_tc_cfg_rx(struct net_device *netdev, int prio, u8 *prio_type,
  810. u8 *pgid, u8 *bw_pct, u8 *up_map)
  811. {
  812. *prio_type = *pgid = *bw_pct = *up_map = 0;
  813. }
  814. static inline void
  815. qlcnic_dcb_get_pg_bwg_cfg_rx(struct net_device *netdev, int pgid, u8 *bw_pct)
  816. {
  817. *bw_pct = 0;
  818. }
  819. static int qlcnic_dcb_peer_app_info(struct net_device *netdev,
  820. struct dcb_peer_app_info *info,
  821. u16 *app_count)
  822. {
  823. struct qlcnic_adapter *adapter = netdev_priv(netdev);
  824. struct qlcnic_dcb_cee *peer;
  825. int i;
  826. memset(info, 0, sizeof(*info));
  827. *app_count = 0;
  828. if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
  829. return 0;
  830. peer = &adapter->dcb->cfg->type[QLC_DCB_PEER_IDX];
  831. for (i = 0; i < QLC_DCB_MAX_APP; i++) {
  832. if (peer->app[i].valid)
  833. (*app_count)++;
  834. }
  835. return 0;
  836. }
  837. static int qlcnic_dcb_peer_app_table(struct net_device *netdev,
  838. struct dcb_app *table)
  839. {
  840. struct qlcnic_adapter *adapter = netdev_priv(netdev);
  841. struct qlcnic_dcb_cee *peer;
  842. struct qlcnic_dcb_app *app;
  843. int i, j;
  844. if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
  845. return 0;
  846. peer = &adapter->dcb->cfg->type[QLC_DCB_PEER_IDX];
  847. for (i = 0, j = 0; i < QLC_DCB_MAX_APP; i++) {
  848. app = &peer->app[i];
  849. if (!app->valid)
  850. continue;
  851. table[j].selector = app->selector;
  852. table[j].priority = app->priority;
  853. table[j++].protocol = app->protocol;
  854. }
  855. return 0;
  856. }
  857. static int qlcnic_dcb_cee_peer_get_pg(struct net_device *netdev,
  858. struct cee_pg *pg)
  859. {
  860. struct qlcnic_adapter *adapter = netdev_priv(netdev);
  861. struct qlcnic_dcb_cee *peer;
  862. u8 i, j, k, map;
  863. if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
  864. return 0;
  865. peer = &adapter->dcb->cfg->type[QLC_DCB_PEER_IDX];
  866. for (i = 0, j = 0; i < QLC_DCB_MAX_PG; i++) {
  867. if (!peer->pg_cfg[i].valid)
  868. continue;
  869. pg->pg_bw[j] = peer->pg_cfg[i].total_bw_percent;
  870. for (k = 0; k < QLC_DCB_MAX_TC; k++) {
  871. if (peer->tc_cfg[i].valid &&
  872. (peer->tc_cfg[i].pgid == i)) {
  873. map = peer->tc_cfg[i].up_tc_map;
  874. pg->prio_pg[j++] = map;
  875. break;
  876. }
  877. }
  878. }
  879. return 0;
  880. }
  881. static int qlcnic_dcb_cee_peer_get_pfc(struct net_device *netdev,
  882. struct cee_pfc *pfc)
  883. {
  884. struct qlcnic_adapter *adapter = netdev_priv(netdev);
  885. struct qlcnic_dcb_cfg *cfg = adapter->dcb->cfg;
  886. struct qlcnic_dcb_tc_cfg *tc;
  887. struct qlcnic_dcb_cee *peer;
  888. u8 i, setting, prio;
  889. pfc->pfc_en = 0;
  890. if (!test_bit(QLCNIC_DCB_STATE, &adapter->dcb->state))
  891. return 0;
  892. peer = &cfg->type[QLC_DCB_PEER_IDX];
  893. for (i = 0; i < QLC_DCB_MAX_TC; i++) {
  894. tc = &peer->tc_cfg[i];
  895. prio = qlcnic_dcb_prio_count(tc->up_tc_map);
  896. setting = 0;
  897. qlcnic_dcb_get_pfc_cfg(netdev, prio, &setting);
  898. if (setting)
  899. pfc->pfc_en |= QLC_DCB_GET_MAP(i);
  900. }
  901. pfc->tcs_supported = cfg->capability.max_pfc_tc;
  902. return 0;
  903. }
  904. static const struct dcbnl_rtnl_ops qlcnic_dcbnl_ops = {
  905. .getstate = qlcnic_dcb_get_state,
  906. .getpermhwaddr = qlcnic_dcb_get_perm_hw_addr,
  907. .getpgtccfgtx = qlcnic_dcb_get_pg_tc_cfg_tx,
  908. .getpgbwgcfgtx = qlcnic_dcb_get_pg_bwg_cfg_tx,
  909. .getpfccfg = qlcnic_dcb_get_pfc_cfg,
  910. .getcap = qlcnic_dcb_get_capability,
  911. .getnumtcs = qlcnic_dcb_get_num_tcs,
  912. .getapp = qlcnic_dcb_get_app,
  913. .getpfcstate = qlcnic_dcb_get_pfc_state,
  914. .getdcbx = qlcnic_dcb_get_dcbx,
  915. .getfeatcfg = qlcnic_dcb_get_feat_cfg,
  916. .getpgtccfgrx = qlcnic_dcb_get_pg_tc_cfg_rx,
  917. .getpgbwgcfgrx = qlcnic_dcb_get_pg_bwg_cfg_rx,
  918. .peer_getappinfo = qlcnic_dcb_peer_app_info,
  919. .peer_getapptable = qlcnic_dcb_peer_app_table,
  920. .cee_peer_getpg = qlcnic_dcb_cee_peer_get_pg,
  921. .cee_peer_getpfc = qlcnic_dcb_cee_peer_get_pfc,
  922. };