dl2k.c 48 KB

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  1. /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
  2. /*
  3. Copyright (c) 2001, 2002 by D-Link Corporation
  4. Written by Edward Peng.<edward_peng@dlink.com.tw>
  5. Created 03-May-2001, base on Linux' sundance.c.
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; either version 2 of the License, or
  9. (at your option) any later version.
  10. */
  11. #define DRV_NAME "DL2000/TC902x-based linux driver"
  12. #define DRV_VERSION "v1.19"
  13. #define DRV_RELDATE "2007/08/12"
  14. #include "dl2k.h"
  15. #include <linux/dma-mapping.h>
  16. #define dw32(reg, val) iowrite32(val, ioaddr + (reg))
  17. #define dw16(reg, val) iowrite16(val, ioaddr + (reg))
  18. #define dw8(reg, val) iowrite8(val, ioaddr + (reg))
  19. #define dr32(reg) ioread32(ioaddr + (reg))
  20. #define dr16(reg) ioread16(ioaddr + (reg))
  21. #define dr8(reg) ioread8(ioaddr + (reg))
  22. static char version[] =
  23. KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
  24. #define MAX_UNITS 8
  25. static int mtu[MAX_UNITS];
  26. static int vlan[MAX_UNITS];
  27. static int jumbo[MAX_UNITS];
  28. static char *media[MAX_UNITS];
  29. static int tx_flow=-1;
  30. static int rx_flow=-1;
  31. static int copy_thresh;
  32. static int rx_coalesce=10; /* Rx frame count each interrupt */
  33. static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
  34. static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
  35. MODULE_AUTHOR ("Edward Peng");
  36. MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
  37. MODULE_LICENSE("GPL");
  38. module_param_array(mtu, int, NULL, 0);
  39. module_param_array(media, charp, NULL, 0);
  40. module_param_array(vlan, int, NULL, 0);
  41. module_param_array(jumbo, int, NULL, 0);
  42. module_param(tx_flow, int, 0);
  43. module_param(rx_flow, int, 0);
  44. module_param(copy_thresh, int, 0);
  45. module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
  46. module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
  47. module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
  48. /* Enable the default interrupts */
  49. #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
  50. UpdateStats | LinkEvent)
  51. static void dl2k_enable_int(struct netdev_private *np)
  52. {
  53. void __iomem *ioaddr = np->ioaddr;
  54. dw16(IntEnable, DEFAULT_INTR);
  55. }
  56. static const int max_intrloop = 50;
  57. static const int multicast_filter_limit = 0x40;
  58. static int rio_open (struct net_device *dev);
  59. static void rio_timer (unsigned long data);
  60. static void rio_tx_timeout (struct net_device *dev);
  61. static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev);
  62. static irqreturn_t rio_interrupt (int irq, void *dev_instance);
  63. static void rio_free_tx (struct net_device *dev, int irq);
  64. static void tx_error (struct net_device *dev, int tx_status);
  65. static int receive_packet (struct net_device *dev);
  66. static void rio_error (struct net_device *dev, int int_status);
  67. static void set_multicast (struct net_device *dev);
  68. static struct net_device_stats *get_stats (struct net_device *dev);
  69. static int clear_stats (struct net_device *dev);
  70. static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
  71. static int rio_close (struct net_device *dev);
  72. static int find_miiphy (struct net_device *dev);
  73. static int parse_eeprom (struct net_device *dev);
  74. static int read_eeprom (struct netdev_private *, int eep_addr);
  75. static int mii_wait_link (struct net_device *dev, int wait);
  76. static int mii_set_media (struct net_device *dev);
  77. static int mii_get_media (struct net_device *dev);
  78. static int mii_set_media_pcs (struct net_device *dev);
  79. static int mii_get_media_pcs (struct net_device *dev);
  80. static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
  81. static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
  82. u16 data);
  83. static const struct ethtool_ops ethtool_ops;
  84. static const struct net_device_ops netdev_ops = {
  85. .ndo_open = rio_open,
  86. .ndo_start_xmit = start_xmit,
  87. .ndo_stop = rio_close,
  88. .ndo_get_stats = get_stats,
  89. .ndo_validate_addr = eth_validate_addr,
  90. .ndo_set_mac_address = eth_mac_addr,
  91. .ndo_set_rx_mode = set_multicast,
  92. .ndo_do_ioctl = rio_ioctl,
  93. .ndo_tx_timeout = rio_tx_timeout,
  94. };
  95. static int
  96. rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
  97. {
  98. struct net_device *dev;
  99. struct netdev_private *np;
  100. static int card_idx;
  101. int chip_idx = ent->driver_data;
  102. int err, irq;
  103. void __iomem *ioaddr;
  104. static int version_printed;
  105. void *ring_space;
  106. dma_addr_t ring_dma;
  107. if (!version_printed++)
  108. printk ("%s", version);
  109. err = pci_enable_device (pdev);
  110. if (err)
  111. return err;
  112. irq = pdev->irq;
  113. err = pci_request_regions (pdev, "dl2k");
  114. if (err)
  115. goto err_out_disable;
  116. pci_set_master (pdev);
  117. err = -ENOMEM;
  118. dev = alloc_etherdev (sizeof (*np));
  119. if (!dev)
  120. goto err_out_res;
  121. SET_NETDEV_DEV(dev, &pdev->dev);
  122. np = netdev_priv(dev);
  123. /* IO registers range. */
  124. ioaddr = pci_iomap(pdev, 0, 0);
  125. if (!ioaddr)
  126. goto err_out_dev;
  127. np->eeprom_addr = ioaddr;
  128. #ifdef MEM_MAPPING
  129. /* MM registers range. */
  130. ioaddr = pci_iomap(pdev, 1, 0);
  131. if (!ioaddr)
  132. goto err_out_iounmap;
  133. #endif
  134. np->ioaddr = ioaddr;
  135. np->chip_id = chip_idx;
  136. np->pdev = pdev;
  137. spin_lock_init (&np->tx_lock);
  138. spin_lock_init (&np->rx_lock);
  139. /* Parse manual configuration */
  140. np->an_enable = 1;
  141. np->tx_coalesce = 1;
  142. if (card_idx < MAX_UNITS) {
  143. if (media[card_idx] != NULL) {
  144. np->an_enable = 0;
  145. if (strcmp (media[card_idx], "auto") == 0 ||
  146. strcmp (media[card_idx], "autosense") == 0 ||
  147. strcmp (media[card_idx], "0") == 0 ) {
  148. np->an_enable = 2;
  149. } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
  150. strcmp (media[card_idx], "4") == 0) {
  151. np->speed = 100;
  152. np->full_duplex = 1;
  153. } else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
  154. strcmp (media[card_idx], "3") == 0) {
  155. np->speed = 100;
  156. np->full_duplex = 0;
  157. } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
  158. strcmp (media[card_idx], "2") == 0) {
  159. np->speed = 10;
  160. np->full_duplex = 1;
  161. } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
  162. strcmp (media[card_idx], "1") == 0) {
  163. np->speed = 10;
  164. np->full_duplex = 0;
  165. } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
  166. strcmp (media[card_idx], "6") == 0) {
  167. np->speed=1000;
  168. np->full_duplex=1;
  169. } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
  170. strcmp (media[card_idx], "5") == 0) {
  171. np->speed = 1000;
  172. np->full_duplex = 0;
  173. } else {
  174. np->an_enable = 1;
  175. }
  176. }
  177. if (jumbo[card_idx] != 0) {
  178. np->jumbo = 1;
  179. dev->mtu = MAX_JUMBO;
  180. } else {
  181. np->jumbo = 0;
  182. if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
  183. dev->mtu = mtu[card_idx];
  184. }
  185. np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
  186. vlan[card_idx] : 0;
  187. if (rx_coalesce > 0 && rx_timeout > 0) {
  188. np->rx_coalesce = rx_coalesce;
  189. np->rx_timeout = rx_timeout;
  190. np->coalesce = 1;
  191. }
  192. np->tx_flow = (tx_flow == 0) ? 0 : 1;
  193. np->rx_flow = (rx_flow == 0) ? 0 : 1;
  194. if (tx_coalesce < 1)
  195. tx_coalesce = 1;
  196. else if (tx_coalesce > TX_RING_SIZE-1)
  197. tx_coalesce = TX_RING_SIZE - 1;
  198. }
  199. dev->netdev_ops = &netdev_ops;
  200. dev->watchdog_timeo = TX_TIMEOUT;
  201. dev->ethtool_ops = &ethtool_ops;
  202. #if 0
  203. dev->features = NETIF_F_IP_CSUM;
  204. #endif
  205. /* MTU range: 68 - 1536 or 8000 */
  206. dev->min_mtu = ETH_MIN_MTU;
  207. dev->max_mtu = np->jumbo ? MAX_JUMBO : PACKET_SIZE;
  208. pci_set_drvdata (pdev, dev);
  209. ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
  210. if (!ring_space)
  211. goto err_out_iounmap;
  212. np->tx_ring = ring_space;
  213. np->tx_ring_dma = ring_dma;
  214. ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
  215. if (!ring_space)
  216. goto err_out_unmap_tx;
  217. np->rx_ring = ring_space;
  218. np->rx_ring_dma = ring_dma;
  219. /* Parse eeprom data */
  220. parse_eeprom (dev);
  221. /* Find PHY address */
  222. err = find_miiphy (dev);
  223. if (err)
  224. goto err_out_unmap_rx;
  225. /* Fiber device? */
  226. np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0;
  227. np->link_status = 0;
  228. /* Set media and reset PHY */
  229. if (np->phy_media) {
  230. /* default Auto-Negotiation for fiber deivices */
  231. if (np->an_enable == 2) {
  232. np->an_enable = 1;
  233. }
  234. } else {
  235. /* Auto-Negotiation is mandatory for 1000BASE-T,
  236. IEEE 802.3ab Annex 28D page 14 */
  237. if (np->speed == 1000)
  238. np->an_enable = 1;
  239. }
  240. err = register_netdev (dev);
  241. if (err)
  242. goto err_out_unmap_rx;
  243. card_idx++;
  244. printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
  245. dev->name, np->name, dev->dev_addr, irq);
  246. if (tx_coalesce > 1)
  247. printk(KERN_INFO "tx_coalesce:\t%d packets\n",
  248. tx_coalesce);
  249. if (np->coalesce)
  250. printk(KERN_INFO
  251. "rx_coalesce:\t%d packets\n"
  252. "rx_timeout: \t%d ns\n",
  253. np->rx_coalesce, np->rx_timeout*640);
  254. if (np->vlan)
  255. printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
  256. return 0;
  257. err_out_unmap_rx:
  258. pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
  259. err_out_unmap_tx:
  260. pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
  261. err_out_iounmap:
  262. #ifdef MEM_MAPPING
  263. pci_iounmap(pdev, np->ioaddr);
  264. #endif
  265. pci_iounmap(pdev, np->eeprom_addr);
  266. err_out_dev:
  267. free_netdev (dev);
  268. err_out_res:
  269. pci_release_regions (pdev);
  270. err_out_disable:
  271. pci_disable_device (pdev);
  272. return err;
  273. }
  274. static int
  275. find_miiphy (struct net_device *dev)
  276. {
  277. struct netdev_private *np = netdev_priv(dev);
  278. int i, phy_found = 0;
  279. np = netdev_priv(dev);
  280. np->phy_addr = 1;
  281. for (i = 31; i >= 0; i--) {
  282. int mii_status = mii_read (dev, i, 1);
  283. if (mii_status != 0xffff && mii_status != 0x0000) {
  284. np->phy_addr = i;
  285. phy_found++;
  286. }
  287. }
  288. if (!phy_found) {
  289. printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
  290. return -ENODEV;
  291. }
  292. return 0;
  293. }
  294. static int
  295. parse_eeprom (struct net_device *dev)
  296. {
  297. struct netdev_private *np = netdev_priv(dev);
  298. void __iomem *ioaddr = np->ioaddr;
  299. int i, j;
  300. u8 sromdata[256];
  301. u8 *psib;
  302. u32 crc;
  303. PSROM_t psrom = (PSROM_t) sromdata;
  304. int cid, next;
  305. for (i = 0; i < 128; i++)
  306. ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom(np, i));
  307. if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
  308. /* Check CRC */
  309. crc = ~ether_crc_le (256 - 4, sromdata);
  310. if (psrom->crc != cpu_to_le32(crc)) {
  311. printk (KERN_ERR "%s: EEPROM data CRC error.\n",
  312. dev->name);
  313. return -1;
  314. }
  315. }
  316. /* Set MAC address */
  317. for (i = 0; i < 6; i++)
  318. dev->dev_addr[i] = psrom->mac_addr[i];
  319. if (np->chip_id == CHIP_IP1000A) {
  320. np->led_mode = psrom->led_mode;
  321. return 0;
  322. }
  323. if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
  324. return 0;
  325. }
  326. /* Parse Software Information Block */
  327. i = 0x30;
  328. psib = (u8 *) sromdata;
  329. do {
  330. cid = psib[i++];
  331. next = psib[i++];
  332. if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
  333. printk (KERN_ERR "Cell data error\n");
  334. return -1;
  335. }
  336. switch (cid) {
  337. case 0: /* Format version */
  338. break;
  339. case 1: /* End of cell */
  340. return 0;
  341. case 2: /* Duplex Polarity */
  342. np->duplex_polarity = psib[i];
  343. dw8(PhyCtrl, dr8(PhyCtrl) | psib[i]);
  344. break;
  345. case 3: /* Wake Polarity */
  346. np->wake_polarity = psib[i];
  347. break;
  348. case 9: /* Adapter description */
  349. j = (next - i > 255) ? 255 : next - i;
  350. memcpy (np->name, &(psib[i]), j);
  351. break;
  352. case 4:
  353. case 5:
  354. case 6:
  355. case 7:
  356. case 8: /* Reversed */
  357. break;
  358. default: /* Unknown cell */
  359. return -1;
  360. }
  361. i = next;
  362. } while (1);
  363. return 0;
  364. }
  365. static void rio_set_led_mode(struct net_device *dev)
  366. {
  367. struct netdev_private *np = netdev_priv(dev);
  368. void __iomem *ioaddr = np->ioaddr;
  369. u32 mode;
  370. if (np->chip_id != CHIP_IP1000A)
  371. return;
  372. mode = dr32(ASICCtrl);
  373. mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
  374. if (np->led_mode & 0x01)
  375. mode |= IPG_AC_LED_MODE;
  376. if (np->led_mode & 0x02)
  377. mode |= IPG_AC_LED_MODE_BIT_1;
  378. if (np->led_mode & 0x08)
  379. mode |= IPG_AC_LED_SPEED;
  380. dw32(ASICCtrl, mode);
  381. }
  382. static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
  383. {
  384. return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48);
  385. }
  386. static void free_list(struct net_device *dev)
  387. {
  388. struct netdev_private *np = netdev_priv(dev);
  389. struct sk_buff *skb;
  390. int i;
  391. /* Free all the skbuffs in the queue. */
  392. for (i = 0; i < RX_RING_SIZE; i++) {
  393. skb = np->rx_skbuff[i];
  394. if (skb) {
  395. pci_unmap_single(np->pdev, desc_to_dma(&np->rx_ring[i]),
  396. skb->len, PCI_DMA_FROMDEVICE);
  397. dev_kfree_skb(skb);
  398. np->rx_skbuff[i] = NULL;
  399. }
  400. np->rx_ring[i].status = 0;
  401. np->rx_ring[i].fraginfo = 0;
  402. }
  403. for (i = 0; i < TX_RING_SIZE; i++) {
  404. skb = np->tx_skbuff[i];
  405. if (skb) {
  406. pci_unmap_single(np->pdev, desc_to_dma(&np->tx_ring[i]),
  407. skb->len, PCI_DMA_TODEVICE);
  408. dev_kfree_skb(skb);
  409. np->tx_skbuff[i] = NULL;
  410. }
  411. }
  412. }
  413. static void rio_reset_ring(struct netdev_private *np)
  414. {
  415. int i;
  416. np->cur_rx = 0;
  417. np->cur_tx = 0;
  418. np->old_rx = 0;
  419. np->old_tx = 0;
  420. for (i = 0; i < TX_RING_SIZE; i++)
  421. np->tx_ring[i].status = cpu_to_le64(TFDDone);
  422. for (i = 0; i < RX_RING_SIZE; i++)
  423. np->rx_ring[i].status = 0;
  424. }
  425. /* allocate and initialize Tx and Rx descriptors */
  426. static int alloc_list(struct net_device *dev)
  427. {
  428. struct netdev_private *np = netdev_priv(dev);
  429. int i;
  430. rio_reset_ring(np);
  431. np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
  432. /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
  433. for (i = 0; i < TX_RING_SIZE; i++) {
  434. np->tx_skbuff[i] = NULL;
  435. np->tx_ring[i].next_desc = cpu_to_le64(np->tx_ring_dma +
  436. ((i + 1) % TX_RING_SIZE) *
  437. sizeof(struct netdev_desc));
  438. }
  439. /* Initialize Rx descriptors & allocate buffers */
  440. for (i = 0; i < RX_RING_SIZE; i++) {
  441. /* Allocated fixed size of skbuff */
  442. struct sk_buff *skb;
  443. skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
  444. np->rx_skbuff[i] = skb;
  445. if (!skb) {
  446. free_list(dev);
  447. return -ENOMEM;
  448. }
  449. np->rx_ring[i].next_desc = cpu_to_le64(np->rx_ring_dma +
  450. ((i + 1) % RX_RING_SIZE) *
  451. sizeof(struct netdev_desc));
  452. /* Rubicon now supports 40 bits of addressing space. */
  453. np->rx_ring[i].fraginfo =
  454. cpu_to_le64(pci_map_single(
  455. np->pdev, skb->data, np->rx_buf_sz,
  456. PCI_DMA_FROMDEVICE));
  457. np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
  458. }
  459. return 0;
  460. }
  461. static void rio_hw_init(struct net_device *dev)
  462. {
  463. struct netdev_private *np = netdev_priv(dev);
  464. void __iomem *ioaddr = np->ioaddr;
  465. int i;
  466. u16 macctrl;
  467. /* Reset all logic functions */
  468. dw16(ASICCtrl + 2,
  469. GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset);
  470. mdelay(10);
  471. rio_set_led_mode(dev);
  472. /* DebugCtrl bit 4, 5, 9 must set */
  473. dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230);
  474. if (np->chip_id == CHIP_IP1000A &&
  475. (np->pdev->revision == 0x40 || np->pdev->revision == 0x41)) {
  476. /* PHY magic taken from ipg driver, undocumented registers */
  477. mii_write(dev, np->phy_addr, 31, 0x0001);
  478. mii_write(dev, np->phy_addr, 27, 0x01e0);
  479. mii_write(dev, np->phy_addr, 31, 0x0002);
  480. mii_write(dev, np->phy_addr, 27, 0xeb8e);
  481. mii_write(dev, np->phy_addr, 31, 0x0000);
  482. mii_write(dev, np->phy_addr, 30, 0x005e);
  483. /* advertise 1000BASE-T half & full duplex, prefer MASTER */
  484. mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700);
  485. }
  486. if (np->phy_media)
  487. mii_set_media_pcs(dev);
  488. else
  489. mii_set_media(dev);
  490. /* Jumbo frame */
  491. if (np->jumbo != 0)
  492. dw16(MaxFrameSize, MAX_JUMBO+14);
  493. /* Set RFDListPtr */
  494. dw32(RFDListPtr0, np->rx_ring_dma);
  495. dw32(RFDListPtr1, 0);
  496. /* Set station address */
  497. /* 16 or 32-bit access is required by TC9020 datasheet but 8-bit works
  498. * too. However, it doesn't work on IP1000A so we use 16-bit access.
  499. */
  500. for (i = 0; i < 3; i++)
  501. dw16(StationAddr0 + 2 * i,
  502. cpu_to_le16(((u16 *)dev->dev_addr)[i]));
  503. set_multicast (dev);
  504. if (np->coalesce) {
  505. dw32(RxDMAIntCtrl, np->rx_coalesce | np->rx_timeout << 16);
  506. }
  507. /* Set RIO to poll every N*320nsec. */
  508. dw8(RxDMAPollPeriod, 0x20);
  509. dw8(TxDMAPollPeriod, 0xff);
  510. dw8(RxDMABurstThresh, 0x30);
  511. dw8(RxDMAUrgentThresh, 0x30);
  512. dw32(RmonStatMask, 0x0007ffff);
  513. /* clear statistics */
  514. clear_stats (dev);
  515. /* VLAN supported */
  516. if (np->vlan) {
  517. /* priority field in RxDMAIntCtrl */
  518. dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10);
  519. /* VLANId */
  520. dw16(VLANId, np->vlan);
  521. /* Length/Type should be 0x8100 */
  522. dw32(VLANTag, 0x8100 << 16 | np->vlan);
  523. /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
  524. VLAN information tagged by TFC' VID, CFI fields. */
  525. dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging);
  526. }
  527. /* Start Tx/Rx */
  528. dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable);
  529. macctrl = 0;
  530. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  531. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  532. macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
  533. macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
  534. dw16(MACCtrl, macctrl);
  535. }
  536. static void rio_hw_stop(struct net_device *dev)
  537. {
  538. struct netdev_private *np = netdev_priv(dev);
  539. void __iomem *ioaddr = np->ioaddr;
  540. /* Disable interrupts */
  541. dw16(IntEnable, 0);
  542. /* Stop Tx and Rx logics */
  543. dw32(MACCtrl, TxDisable | RxDisable | StatsDisable);
  544. }
  545. static int rio_open(struct net_device *dev)
  546. {
  547. struct netdev_private *np = netdev_priv(dev);
  548. const int irq = np->pdev->irq;
  549. int i;
  550. i = alloc_list(dev);
  551. if (i)
  552. return i;
  553. rio_hw_init(dev);
  554. i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev);
  555. if (i) {
  556. rio_hw_stop(dev);
  557. free_list(dev);
  558. return i;
  559. }
  560. setup_timer(&np->timer, rio_timer, (unsigned long)dev);
  561. np->timer.expires = jiffies + 1 * HZ;
  562. add_timer(&np->timer);
  563. netif_start_queue (dev);
  564. dl2k_enable_int(np);
  565. return 0;
  566. }
  567. static void
  568. rio_timer (unsigned long data)
  569. {
  570. struct net_device *dev = (struct net_device *)data;
  571. struct netdev_private *np = netdev_priv(dev);
  572. unsigned int entry;
  573. int next_tick = 1*HZ;
  574. unsigned long flags;
  575. spin_lock_irqsave(&np->rx_lock, flags);
  576. /* Recover rx ring exhausted error */
  577. if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
  578. printk(KERN_INFO "Try to recover rx ring exhausted...\n");
  579. /* Re-allocate skbuffs to fill the descriptor ring */
  580. for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
  581. struct sk_buff *skb;
  582. entry = np->old_rx % RX_RING_SIZE;
  583. /* Dropped packets don't need to re-allocate */
  584. if (np->rx_skbuff[entry] == NULL) {
  585. skb = netdev_alloc_skb_ip_align(dev,
  586. np->rx_buf_sz);
  587. if (skb == NULL) {
  588. np->rx_ring[entry].fraginfo = 0;
  589. printk (KERN_INFO
  590. "%s: Still unable to re-allocate Rx skbuff.#%d\n",
  591. dev->name, entry);
  592. break;
  593. }
  594. np->rx_skbuff[entry] = skb;
  595. np->rx_ring[entry].fraginfo =
  596. cpu_to_le64 (pci_map_single
  597. (np->pdev, skb->data, np->rx_buf_sz,
  598. PCI_DMA_FROMDEVICE));
  599. }
  600. np->rx_ring[entry].fraginfo |=
  601. cpu_to_le64((u64)np->rx_buf_sz << 48);
  602. np->rx_ring[entry].status = 0;
  603. } /* end for */
  604. } /* end if */
  605. spin_unlock_irqrestore (&np->rx_lock, flags);
  606. np->timer.expires = jiffies + next_tick;
  607. add_timer(&np->timer);
  608. }
  609. static void
  610. rio_tx_timeout (struct net_device *dev)
  611. {
  612. struct netdev_private *np = netdev_priv(dev);
  613. void __iomem *ioaddr = np->ioaddr;
  614. printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
  615. dev->name, dr32(TxStatus));
  616. rio_free_tx(dev, 0);
  617. dev->if_port = 0;
  618. netif_trans_update(dev); /* prevent tx timeout */
  619. }
  620. static netdev_tx_t
  621. start_xmit (struct sk_buff *skb, struct net_device *dev)
  622. {
  623. struct netdev_private *np = netdev_priv(dev);
  624. void __iomem *ioaddr = np->ioaddr;
  625. struct netdev_desc *txdesc;
  626. unsigned entry;
  627. u64 tfc_vlan_tag = 0;
  628. if (np->link_status == 0) { /* Link Down */
  629. dev_kfree_skb(skb);
  630. return NETDEV_TX_OK;
  631. }
  632. entry = np->cur_tx % TX_RING_SIZE;
  633. np->tx_skbuff[entry] = skb;
  634. txdesc = &np->tx_ring[entry];
  635. #if 0
  636. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  637. txdesc->status |=
  638. cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
  639. IPChecksumEnable);
  640. }
  641. #endif
  642. if (np->vlan) {
  643. tfc_vlan_tag = VLANTagInsert |
  644. ((u64)np->vlan << 32) |
  645. ((u64)skb->priority << 45);
  646. }
  647. txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
  648. skb->len,
  649. PCI_DMA_TODEVICE));
  650. txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
  651. /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
  652. * Work around: Always use 1 descriptor in 10Mbps mode */
  653. if (entry % np->tx_coalesce == 0 || np->speed == 10)
  654. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  655. WordAlignDisable |
  656. TxDMAIndicate |
  657. (1 << FragCountShift));
  658. else
  659. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  660. WordAlignDisable |
  661. (1 << FragCountShift));
  662. /* TxDMAPollNow */
  663. dw32(DMACtrl, dr32(DMACtrl) | 0x00001000);
  664. /* Schedule ISR */
  665. dw32(CountDown, 10000);
  666. np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
  667. if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  668. < TX_QUEUE_LEN - 1 && np->speed != 10) {
  669. /* do nothing */
  670. } else if (!netif_queue_stopped(dev)) {
  671. netif_stop_queue (dev);
  672. }
  673. /* The first TFDListPtr */
  674. if (!dr32(TFDListPtr0)) {
  675. dw32(TFDListPtr0, np->tx_ring_dma +
  676. entry * sizeof (struct netdev_desc));
  677. dw32(TFDListPtr1, 0);
  678. }
  679. return NETDEV_TX_OK;
  680. }
  681. static irqreturn_t
  682. rio_interrupt (int irq, void *dev_instance)
  683. {
  684. struct net_device *dev = dev_instance;
  685. struct netdev_private *np = netdev_priv(dev);
  686. void __iomem *ioaddr = np->ioaddr;
  687. unsigned int_status;
  688. int cnt = max_intrloop;
  689. int handled = 0;
  690. while (1) {
  691. int_status = dr16(IntStatus);
  692. dw16(IntStatus, int_status);
  693. int_status &= DEFAULT_INTR;
  694. if (int_status == 0 || --cnt < 0)
  695. break;
  696. handled = 1;
  697. /* Processing received packets */
  698. if (int_status & RxDMAComplete)
  699. receive_packet (dev);
  700. /* TxDMAComplete interrupt */
  701. if ((int_status & (TxDMAComplete|IntRequested))) {
  702. int tx_status;
  703. tx_status = dr32(TxStatus);
  704. if (tx_status & 0x01)
  705. tx_error (dev, tx_status);
  706. /* Free used tx skbuffs */
  707. rio_free_tx (dev, 1);
  708. }
  709. /* Handle uncommon events */
  710. if (int_status &
  711. (HostError | LinkEvent | UpdateStats))
  712. rio_error (dev, int_status);
  713. }
  714. if (np->cur_tx != np->old_tx)
  715. dw32(CountDown, 100);
  716. return IRQ_RETVAL(handled);
  717. }
  718. static void
  719. rio_free_tx (struct net_device *dev, int irq)
  720. {
  721. struct netdev_private *np = netdev_priv(dev);
  722. int entry = np->old_tx % TX_RING_SIZE;
  723. int tx_use = 0;
  724. unsigned long flag = 0;
  725. if (irq)
  726. spin_lock(&np->tx_lock);
  727. else
  728. spin_lock_irqsave(&np->tx_lock, flag);
  729. /* Free used tx skbuffs */
  730. while (entry != np->cur_tx) {
  731. struct sk_buff *skb;
  732. if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
  733. break;
  734. skb = np->tx_skbuff[entry];
  735. pci_unmap_single (np->pdev,
  736. desc_to_dma(&np->tx_ring[entry]),
  737. skb->len, PCI_DMA_TODEVICE);
  738. if (irq)
  739. dev_kfree_skb_irq (skb);
  740. else
  741. dev_kfree_skb (skb);
  742. np->tx_skbuff[entry] = NULL;
  743. entry = (entry + 1) % TX_RING_SIZE;
  744. tx_use++;
  745. }
  746. if (irq)
  747. spin_unlock(&np->tx_lock);
  748. else
  749. spin_unlock_irqrestore(&np->tx_lock, flag);
  750. np->old_tx = entry;
  751. /* If the ring is no longer full, clear tx_full and
  752. call netif_wake_queue() */
  753. if (netif_queue_stopped(dev) &&
  754. ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  755. < TX_QUEUE_LEN - 1 || np->speed == 10)) {
  756. netif_wake_queue (dev);
  757. }
  758. }
  759. static void
  760. tx_error (struct net_device *dev, int tx_status)
  761. {
  762. struct netdev_private *np = netdev_priv(dev);
  763. void __iomem *ioaddr = np->ioaddr;
  764. int frame_id;
  765. int i;
  766. frame_id = (tx_status & 0xffff0000);
  767. printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
  768. dev->name, tx_status, frame_id);
  769. np->stats.tx_errors++;
  770. /* Ttransmit Underrun */
  771. if (tx_status & 0x10) {
  772. np->stats.tx_fifo_errors++;
  773. dw16(TxStartThresh, dr16(TxStartThresh) + 0x10);
  774. /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
  775. dw16(ASICCtrl + 2,
  776. TxReset | DMAReset | FIFOReset | NetworkReset);
  777. /* Wait for ResetBusy bit clear */
  778. for (i = 50; i > 0; i--) {
  779. if (!(dr16(ASICCtrl + 2) & ResetBusy))
  780. break;
  781. mdelay (1);
  782. }
  783. rio_set_led_mode(dev);
  784. rio_free_tx (dev, 1);
  785. /* Reset TFDListPtr */
  786. dw32(TFDListPtr0, np->tx_ring_dma +
  787. np->old_tx * sizeof (struct netdev_desc));
  788. dw32(TFDListPtr1, 0);
  789. /* Let TxStartThresh stay default value */
  790. }
  791. /* Late Collision */
  792. if (tx_status & 0x04) {
  793. np->stats.tx_fifo_errors++;
  794. /* TxReset and clear FIFO */
  795. dw16(ASICCtrl + 2, TxReset | FIFOReset);
  796. /* Wait reset done */
  797. for (i = 50; i > 0; i--) {
  798. if (!(dr16(ASICCtrl + 2) & ResetBusy))
  799. break;
  800. mdelay (1);
  801. }
  802. rio_set_led_mode(dev);
  803. /* Let TxStartThresh stay default value */
  804. }
  805. /* Maximum Collisions */
  806. #ifdef ETHER_STATS
  807. if (tx_status & 0x08)
  808. np->stats.collisions16++;
  809. #else
  810. if (tx_status & 0x08)
  811. np->stats.collisions++;
  812. #endif
  813. /* Restart the Tx */
  814. dw32(MACCtrl, dr16(MACCtrl) | TxEnable);
  815. }
  816. static int
  817. receive_packet (struct net_device *dev)
  818. {
  819. struct netdev_private *np = netdev_priv(dev);
  820. int entry = np->cur_rx % RX_RING_SIZE;
  821. int cnt = 30;
  822. /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
  823. while (1) {
  824. struct netdev_desc *desc = &np->rx_ring[entry];
  825. int pkt_len;
  826. u64 frame_status;
  827. if (!(desc->status & cpu_to_le64(RFDDone)) ||
  828. !(desc->status & cpu_to_le64(FrameStart)) ||
  829. !(desc->status & cpu_to_le64(FrameEnd)))
  830. break;
  831. /* Chip omits the CRC. */
  832. frame_status = le64_to_cpu(desc->status);
  833. pkt_len = frame_status & 0xffff;
  834. if (--cnt < 0)
  835. break;
  836. /* Update rx error statistics, drop packet. */
  837. if (frame_status & RFS_Errors) {
  838. np->stats.rx_errors++;
  839. if (frame_status & (RxRuntFrame | RxLengthError))
  840. np->stats.rx_length_errors++;
  841. if (frame_status & RxFCSError)
  842. np->stats.rx_crc_errors++;
  843. if (frame_status & RxAlignmentError && np->speed != 1000)
  844. np->stats.rx_frame_errors++;
  845. if (frame_status & RxFIFOOverrun)
  846. np->stats.rx_fifo_errors++;
  847. } else {
  848. struct sk_buff *skb;
  849. /* Small skbuffs for short packets */
  850. if (pkt_len > copy_thresh) {
  851. pci_unmap_single (np->pdev,
  852. desc_to_dma(desc),
  853. np->rx_buf_sz,
  854. PCI_DMA_FROMDEVICE);
  855. skb_put (skb = np->rx_skbuff[entry], pkt_len);
  856. np->rx_skbuff[entry] = NULL;
  857. } else if ((skb = netdev_alloc_skb_ip_align(dev, pkt_len))) {
  858. pci_dma_sync_single_for_cpu(np->pdev,
  859. desc_to_dma(desc),
  860. np->rx_buf_sz,
  861. PCI_DMA_FROMDEVICE);
  862. skb_copy_to_linear_data (skb,
  863. np->rx_skbuff[entry]->data,
  864. pkt_len);
  865. skb_put (skb, pkt_len);
  866. pci_dma_sync_single_for_device(np->pdev,
  867. desc_to_dma(desc),
  868. np->rx_buf_sz,
  869. PCI_DMA_FROMDEVICE);
  870. }
  871. skb->protocol = eth_type_trans (skb, dev);
  872. #if 0
  873. /* Checksum done by hw, but csum value unavailable. */
  874. if (np->pdev->pci_rev_id >= 0x0c &&
  875. !(frame_status & (TCPError | UDPError | IPError))) {
  876. skb->ip_summed = CHECKSUM_UNNECESSARY;
  877. }
  878. #endif
  879. netif_rx (skb);
  880. }
  881. entry = (entry + 1) % RX_RING_SIZE;
  882. }
  883. spin_lock(&np->rx_lock);
  884. np->cur_rx = entry;
  885. /* Re-allocate skbuffs to fill the descriptor ring */
  886. entry = np->old_rx;
  887. while (entry != np->cur_rx) {
  888. struct sk_buff *skb;
  889. /* Dropped packets don't need to re-allocate */
  890. if (np->rx_skbuff[entry] == NULL) {
  891. skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
  892. if (skb == NULL) {
  893. np->rx_ring[entry].fraginfo = 0;
  894. printk (KERN_INFO
  895. "%s: receive_packet: "
  896. "Unable to re-allocate Rx skbuff.#%d\n",
  897. dev->name, entry);
  898. break;
  899. }
  900. np->rx_skbuff[entry] = skb;
  901. np->rx_ring[entry].fraginfo =
  902. cpu_to_le64 (pci_map_single
  903. (np->pdev, skb->data, np->rx_buf_sz,
  904. PCI_DMA_FROMDEVICE));
  905. }
  906. np->rx_ring[entry].fraginfo |=
  907. cpu_to_le64((u64)np->rx_buf_sz << 48);
  908. np->rx_ring[entry].status = 0;
  909. entry = (entry + 1) % RX_RING_SIZE;
  910. }
  911. np->old_rx = entry;
  912. spin_unlock(&np->rx_lock);
  913. return 0;
  914. }
  915. static void
  916. rio_error (struct net_device *dev, int int_status)
  917. {
  918. struct netdev_private *np = netdev_priv(dev);
  919. void __iomem *ioaddr = np->ioaddr;
  920. u16 macctrl;
  921. /* Link change event */
  922. if (int_status & LinkEvent) {
  923. if (mii_wait_link (dev, 10) == 0) {
  924. printk (KERN_INFO "%s: Link up\n", dev->name);
  925. if (np->phy_media)
  926. mii_get_media_pcs (dev);
  927. else
  928. mii_get_media (dev);
  929. if (np->speed == 1000)
  930. np->tx_coalesce = tx_coalesce;
  931. else
  932. np->tx_coalesce = 1;
  933. macctrl = 0;
  934. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  935. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  936. macctrl |= (np->tx_flow) ?
  937. TxFlowControlEnable : 0;
  938. macctrl |= (np->rx_flow) ?
  939. RxFlowControlEnable : 0;
  940. dw16(MACCtrl, macctrl);
  941. np->link_status = 1;
  942. netif_carrier_on(dev);
  943. } else {
  944. printk (KERN_INFO "%s: Link off\n", dev->name);
  945. np->link_status = 0;
  946. netif_carrier_off(dev);
  947. }
  948. }
  949. /* UpdateStats statistics registers */
  950. if (int_status & UpdateStats) {
  951. get_stats (dev);
  952. }
  953. /* PCI Error, a catastronphic error related to the bus interface
  954. occurs, set GlobalReset and HostReset to reset. */
  955. if (int_status & HostError) {
  956. printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
  957. dev->name, int_status);
  958. dw16(ASICCtrl + 2, GlobalReset | HostReset);
  959. mdelay (500);
  960. rio_set_led_mode(dev);
  961. }
  962. }
  963. static struct net_device_stats *
  964. get_stats (struct net_device *dev)
  965. {
  966. struct netdev_private *np = netdev_priv(dev);
  967. void __iomem *ioaddr = np->ioaddr;
  968. #ifdef MEM_MAPPING
  969. int i;
  970. #endif
  971. unsigned int stat_reg;
  972. /* All statistics registers need to be acknowledged,
  973. else statistic overflow could cause problems */
  974. np->stats.rx_packets += dr32(FramesRcvOk);
  975. np->stats.tx_packets += dr32(FramesXmtOk);
  976. np->stats.rx_bytes += dr32(OctetRcvOk);
  977. np->stats.tx_bytes += dr32(OctetXmtOk);
  978. np->stats.multicast = dr32(McstFramesRcvdOk);
  979. np->stats.collisions += dr32(SingleColFrames)
  980. + dr32(MultiColFrames);
  981. /* detailed tx errors */
  982. stat_reg = dr16(FramesAbortXSColls);
  983. np->stats.tx_aborted_errors += stat_reg;
  984. np->stats.tx_errors += stat_reg;
  985. stat_reg = dr16(CarrierSenseErrors);
  986. np->stats.tx_carrier_errors += stat_reg;
  987. np->stats.tx_errors += stat_reg;
  988. /* Clear all other statistic register. */
  989. dr32(McstOctetXmtOk);
  990. dr16(BcstFramesXmtdOk);
  991. dr32(McstFramesXmtdOk);
  992. dr16(BcstFramesRcvdOk);
  993. dr16(MacControlFramesRcvd);
  994. dr16(FrameTooLongErrors);
  995. dr16(InRangeLengthErrors);
  996. dr16(FramesCheckSeqErrors);
  997. dr16(FramesLostRxErrors);
  998. dr32(McstOctetXmtOk);
  999. dr32(BcstOctetXmtOk);
  1000. dr32(McstFramesXmtdOk);
  1001. dr32(FramesWDeferredXmt);
  1002. dr32(LateCollisions);
  1003. dr16(BcstFramesXmtdOk);
  1004. dr16(MacControlFramesXmtd);
  1005. dr16(FramesWEXDeferal);
  1006. #ifdef MEM_MAPPING
  1007. for (i = 0x100; i <= 0x150; i += 4)
  1008. dr32(i);
  1009. #endif
  1010. dr16(TxJumboFrames);
  1011. dr16(RxJumboFrames);
  1012. dr16(TCPCheckSumErrors);
  1013. dr16(UDPCheckSumErrors);
  1014. dr16(IPCheckSumErrors);
  1015. return &np->stats;
  1016. }
  1017. static int
  1018. clear_stats (struct net_device *dev)
  1019. {
  1020. struct netdev_private *np = netdev_priv(dev);
  1021. void __iomem *ioaddr = np->ioaddr;
  1022. #ifdef MEM_MAPPING
  1023. int i;
  1024. #endif
  1025. /* All statistics registers need to be acknowledged,
  1026. else statistic overflow could cause problems */
  1027. dr32(FramesRcvOk);
  1028. dr32(FramesXmtOk);
  1029. dr32(OctetRcvOk);
  1030. dr32(OctetXmtOk);
  1031. dr32(McstFramesRcvdOk);
  1032. dr32(SingleColFrames);
  1033. dr32(MultiColFrames);
  1034. dr32(LateCollisions);
  1035. /* detailed rx errors */
  1036. dr16(FrameTooLongErrors);
  1037. dr16(InRangeLengthErrors);
  1038. dr16(FramesCheckSeqErrors);
  1039. dr16(FramesLostRxErrors);
  1040. /* detailed tx errors */
  1041. dr16(FramesAbortXSColls);
  1042. dr16(CarrierSenseErrors);
  1043. /* Clear all other statistic register. */
  1044. dr32(McstOctetXmtOk);
  1045. dr16(BcstFramesXmtdOk);
  1046. dr32(McstFramesXmtdOk);
  1047. dr16(BcstFramesRcvdOk);
  1048. dr16(MacControlFramesRcvd);
  1049. dr32(McstOctetXmtOk);
  1050. dr32(BcstOctetXmtOk);
  1051. dr32(McstFramesXmtdOk);
  1052. dr32(FramesWDeferredXmt);
  1053. dr16(BcstFramesXmtdOk);
  1054. dr16(MacControlFramesXmtd);
  1055. dr16(FramesWEXDeferal);
  1056. #ifdef MEM_MAPPING
  1057. for (i = 0x100; i <= 0x150; i += 4)
  1058. dr32(i);
  1059. #endif
  1060. dr16(TxJumboFrames);
  1061. dr16(RxJumboFrames);
  1062. dr16(TCPCheckSumErrors);
  1063. dr16(UDPCheckSumErrors);
  1064. dr16(IPCheckSumErrors);
  1065. return 0;
  1066. }
  1067. static void
  1068. set_multicast (struct net_device *dev)
  1069. {
  1070. struct netdev_private *np = netdev_priv(dev);
  1071. void __iomem *ioaddr = np->ioaddr;
  1072. u32 hash_table[2];
  1073. u16 rx_mode = 0;
  1074. hash_table[0] = hash_table[1] = 0;
  1075. /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
  1076. hash_table[1] |= 0x02000000;
  1077. if (dev->flags & IFF_PROMISC) {
  1078. /* Receive all frames promiscuously. */
  1079. rx_mode = ReceiveAllFrames;
  1080. } else if ((dev->flags & IFF_ALLMULTI) ||
  1081. (netdev_mc_count(dev) > multicast_filter_limit)) {
  1082. /* Receive broadcast and multicast frames */
  1083. rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
  1084. } else if (!netdev_mc_empty(dev)) {
  1085. struct netdev_hw_addr *ha;
  1086. /* Receive broadcast frames and multicast frames filtering
  1087. by Hashtable */
  1088. rx_mode =
  1089. ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
  1090. netdev_for_each_mc_addr(ha, dev) {
  1091. int bit, index = 0;
  1092. int crc = ether_crc_le(ETH_ALEN, ha->addr);
  1093. /* The inverted high significant 6 bits of CRC are
  1094. used as an index to hashtable */
  1095. for (bit = 0; bit < 6; bit++)
  1096. if (crc & (1 << (31 - bit)))
  1097. index |= (1 << bit);
  1098. hash_table[index / 32] |= (1 << (index % 32));
  1099. }
  1100. } else {
  1101. rx_mode = ReceiveBroadcast | ReceiveUnicast;
  1102. }
  1103. if (np->vlan) {
  1104. /* ReceiveVLANMatch field in ReceiveMode */
  1105. rx_mode |= ReceiveVLANMatch;
  1106. }
  1107. dw32(HashTable0, hash_table[0]);
  1108. dw32(HashTable1, hash_table[1]);
  1109. dw16(ReceiveMode, rx_mode);
  1110. }
  1111. static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  1112. {
  1113. struct netdev_private *np = netdev_priv(dev);
  1114. strlcpy(info->driver, "dl2k", sizeof(info->driver));
  1115. strlcpy(info->version, DRV_VERSION, sizeof(info->version));
  1116. strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
  1117. }
  1118. static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1119. {
  1120. struct netdev_private *np = netdev_priv(dev);
  1121. if (np->phy_media) {
  1122. /* fiber device */
  1123. cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
  1124. cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE;
  1125. cmd->port = PORT_FIBRE;
  1126. cmd->transceiver = XCVR_INTERNAL;
  1127. } else {
  1128. /* copper device */
  1129. cmd->supported = SUPPORTED_10baseT_Half |
  1130. SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
  1131. | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
  1132. SUPPORTED_Autoneg | SUPPORTED_MII;
  1133. cmd->advertising = ADVERTISED_10baseT_Half |
  1134. ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
  1135. ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
  1136. ADVERTISED_Autoneg | ADVERTISED_MII;
  1137. cmd->port = PORT_MII;
  1138. cmd->transceiver = XCVR_INTERNAL;
  1139. }
  1140. if ( np->link_status ) {
  1141. ethtool_cmd_speed_set(cmd, np->speed);
  1142. cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
  1143. } else {
  1144. ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
  1145. cmd->duplex = DUPLEX_UNKNOWN;
  1146. }
  1147. if ( np->an_enable)
  1148. cmd->autoneg = AUTONEG_ENABLE;
  1149. else
  1150. cmd->autoneg = AUTONEG_DISABLE;
  1151. cmd->phy_address = np->phy_addr;
  1152. return 0;
  1153. }
  1154. static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1155. {
  1156. struct netdev_private *np = netdev_priv(dev);
  1157. netif_carrier_off(dev);
  1158. if (cmd->autoneg == AUTONEG_ENABLE) {
  1159. if (np->an_enable)
  1160. return 0;
  1161. else {
  1162. np->an_enable = 1;
  1163. mii_set_media(dev);
  1164. return 0;
  1165. }
  1166. } else {
  1167. np->an_enable = 0;
  1168. if (np->speed == 1000) {
  1169. ethtool_cmd_speed_set(cmd, SPEED_100);
  1170. cmd->duplex = DUPLEX_FULL;
  1171. printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
  1172. }
  1173. switch (ethtool_cmd_speed(cmd)) {
  1174. case SPEED_10:
  1175. np->speed = 10;
  1176. np->full_duplex = (cmd->duplex == DUPLEX_FULL);
  1177. break;
  1178. case SPEED_100:
  1179. np->speed = 100;
  1180. np->full_duplex = (cmd->duplex == DUPLEX_FULL);
  1181. break;
  1182. case SPEED_1000: /* not supported */
  1183. default:
  1184. return -EINVAL;
  1185. }
  1186. mii_set_media(dev);
  1187. }
  1188. return 0;
  1189. }
  1190. static u32 rio_get_link(struct net_device *dev)
  1191. {
  1192. struct netdev_private *np = netdev_priv(dev);
  1193. return np->link_status;
  1194. }
  1195. static const struct ethtool_ops ethtool_ops = {
  1196. .get_drvinfo = rio_get_drvinfo,
  1197. .get_settings = rio_get_settings,
  1198. .set_settings = rio_set_settings,
  1199. .get_link = rio_get_link,
  1200. };
  1201. static int
  1202. rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
  1203. {
  1204. int phy_addr;
  1205. struct netdev_private *np = netdev_priv(dev);
  1206. struct mii_ioctl_data *miidata = if_mii(rq);
  1207. phy_addr = np->phy_addr;
  1208. switch (cmd) {
  1209. case SIOCGMIIPHY:
  1210. miidata->phy_id = phy_addr;
  1211. break;
  1212. case SIOCGMIIREG:
  1213. miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num);
  1214. break;
  1215. case SIOCSMIIREG:
  1216. if (!capable(CAP_NET_ADMIN))
  1217. return -EPERM;
  1218. mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in);
  1219. break;
  1220. default:
  1221. return -EOPNOTSUPP;
  1222. }
  1223. return 0;
  1224. }
  1225. #define EEP_READ 0x0200
  1226. #define EEP_BUSY 0x8000
  1227. /* Read the EEPROM word */
  1228. /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
  1229. static int read_eeprom(struct netdev_private *np, int eep_addr)
  1230. {
  1231. void __iomem *ioaddr = np->eeprom_addr;
  1232. int i = 1000;
  1233. dw16(EepromCtrl, EEP_READ | (eep_addr & 0xff));
  1234. while (i-- > 0) {
  1235. if (!(dr16(EepromCtrl) & EEP_BUSY))
  1236. return dr16(EepromData);
  1237. }
  1238. return 0;
  1239. }
  1240. enum phy_ctrl_bits {
  1241. MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
  1242. MII_DUPLEX = 0x08,
  1243. };
  1244. #define mii_delay() dr8(PhyCtrl)
  1245. static void
  1246. mii_sendbit (struct net_device *dev, u32 data)
  1247. {
  1248. struct netdev_private *np = netdev_priv(dev);
  1249. void __iomem *ioaddr = np->ioaddr;
  1250. data = ((data) ? MII_DATA1 : 0) | (dr8(PhyCtrl) & 0xf8) | MII_WRITE;
  1251. dw8(PhyCtrl, data);
  1252. mii_delay ();
  1253. dw8(PhyCtrl, data | MII_CLK);
  1254. mii_delay ();
  1255. }
  1256. static int
  1257. mii_getbit (struct net_device *dev)
  1258. {
  1259. struct netdev_private *np = netdev_priv(dev);
  1260. void __iomem *ioaddr = np->ioaddr;
  1261. u8 data;
  1262. data = (dr8(PhyCtrl) & 0xf8) | MII_READ;
  1263. dw8(PhyCtrl, data);
  1264. mii_delay ();
  1265. dw8(PhyCtrl, data | MII_CLK);
  1266. mii_delay ();
  1267. return (dr8(PhyCtrl) >> 1) & 1;
  1268. }
  1269. static void
  1270. mii_send_bits (struct net_device *dev, u32 data, int len)
  1271. {
  1272. int i;
  1273. for (i = len - 1; i >= 0; i--) {
  1274. mii_sendbit (dev, data & (1 << i));
  1275. }
  1276. }
  1277. static int
  1278. mii_read (struct net_device *dev, int phy_addr, int reg_num)
  1279. {
  1280. u32 cmd;
  1281. int i;
  1282. u32 retval = 0;
  1283. /* Preamble */
  1284. mii_send_bits (dev, 0xffffffff, 32);
  1285. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1286. /* ST,OP = 0110'b for read operation */
  1287. cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
  1288. mii_send_bits (dev, cmd, 14);
  1289. /* Turnaround */
  1290. if (mii_getbit (dev))
  1291. goto err_out;
  1292. /* Read data */
  1293. for (i = 0; i < 16; i++) {
  1294. retval |= mii_getbit (dev);
  1295. retval <<= 1;
  1296. }
  1297. /* End cycle */
  1298. mii_getbit (dev);
  1299. return (retval >> 1) & 0xffff;
  1300. err_out:
  1301. return 0;
  1302. }
  1303. static int
  1304. mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
  1305. {
  1306. u32 cmd;
  1307. /* Preamble */
  1308. mii_send_bits (dev, 0xffffffff, 32);
  1309. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1310. /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
  1311. cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
  1312. mii_send_bits (dev, cmd, 32);
  1313. /* End cycle */
  1314. mii_getbit (dev);
  1315. return 0;
  1316. }
  1317. static int
  1318. mii_wait_link (struct net_device *dev, int wait)
  1319. {
  1320. __u16 bmsr;
  1321. int phy_addr;
  1322. struct netdev_private *np;
  1323. np = netdev_priv(dev);
  1324. phy_addr = np->phy_addr;
  1325. do {
  1326. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1327. if (bmsr & BMSR_LSTATUS)
  1328. return 0;
  1329. mdelay (1);
  1330. } while (--wait > 0);
  1331. return -1;
  1332. }
  1333. static int
  1334. mii_get_media (struct net_device *dev)
  1335. {
  1336. __u16 negotiate;
  1337. __u16 bmsr;
  1338. __u16 mscr;
  1339. __u16 mssr;
  1340. int phy_addr;
  1341. struct netdev_private *np;
  1342. np = netdev_priv(dev);
  1343. phy_addr = np->phy_addr;
  1344. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1345. if (np->an_enable) {
  1346. if (!(bmsr & BMSR_ANEGCOMPLETE)) {
  1347. /* Auto-Negotiation not completed */
  1348. return -1;
  1349. }
  1350. negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1351. mii_read (dev, phy_addr, MII_LPA);
  1352. mscr = mii_read (dev, phy_addr, MII_CTRL1000);
  1353. mssr = mii_read (dev, phy_addr, MII_STAT1000);
  1354. if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) {
  1355. np->speed = 1000;
  1356. np->full_duplex = 1;
  1357. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1358. } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) {
  1359. np->speed = 1000;
  1360. np->full_duplex = 0;
  1361. printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
  1362. } else if (negotiate & ADVERTISE_100FULL) {
  1363. np->speed = 100;
  1364. np->full_duplex = 1;
  1365. printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
  1366. } else if (negotiate & ADVERTISE_100HALF) {
  1367. np->speed = 100;
  1368. np->full_duplex = 0;
  1369. printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
  1370. } else if (negotiate & ADVERTISE_10FULL) {
  1371. np->speed = 10;
  1372. np->full_duplex = 1;
  1373. printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
  1374. } else if (negotiate & ADVERTISE_10HALF) {
  1375. np->speed = 10;
  1376. np->full_duplex = 0;
  1377. printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
  1378. }
  1379. if (negotiate & ADVERTISE_PAUSE_CAP) {
  1380. np->tx_flow &= 1;
  1381. np->rx_flow &= 1;
  1382. } else if (negotiate & ADVERTISE_PAUSE_ASYM) {
  1383. np->tx_flow = 0;
  1384. np->rx_flow &= 1;
  1385. }
  1386. /* else tx_flow, rx_flow = user select */
  1387. } else {
  1388. __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
  1389. switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) {
  1390. case BMCR_SPEED1000:
  1391. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1392. break;
  1393. case BMCR_SPEED100:
  1394. printk (KERN_INFO "Operating at 100 Mbps, ");
  1395. break;
  1396. case 0:
  1397. printk (KERN_INFO "Operating at 10 Mbps, ");
  1398. }
  1399. if (bmcr & BMCR_FULLDPLX) {
  1400. printk (KERN_CONT "Full duplex\n");
  1401. } else {
  1402. printk (KERN_CONT "Half duplex\n");
  1403. }
  1404. }
  1405. if (np->tx_flow)
  1406. printk(KERN_INFO "Enable Tx Flow Control\n");
  1407. else
  1408. printk(KERN_INFO "Disable Tx Flow Control\n");
  1409. if (np->rx_flow)
  1410. printk(KERN_INFO "Enable Rx Flow Control\n");
  1411. else
  1412. printk(KERN_INFO "Disable Rx Flow Control\n");
  1413. return 0;
  1414. }
  1415. static int
  1416. mii_set_media (struct net_device *dev)
  1417. {
  1418. __u16 pscr;
  1419. __u16 bmcr;
  1420. __u16 bmsr;
  1421. __u16 anar;
  1422. int phy_addr;
  1423. struct netdev_private *np;
  1424. np = netdev_priv(dev);
  1425. phy_addr = np->phy_addr;
  1426. /* Does user set speed? */
  1427. if (np->an_enable) {
  1428. /* Advertise capabilities */
  1429. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1430. anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1431. ~(ADVERTISE_100FULL | ADVERTISE_10FULL |
  1432. ADVERTISE_100HALF | ADVERTISE_10HALF |
  1433. ADVERTISE_100BASE4);
  1434. if (bmsr & BMSR_100FULL)
  1435. anar |= ADVERTISE_100FULL;
  1436. if (bmsr & BMSR_100HALF)
  1437. anar |= ADVERTISE_100HALF;
  1438. if (bmsr & BMSR_100BASE4)
  1439. anar |= ADVERTISE_100BASE4;
  1440. if (bmsr & BMSR_10FULL)
  1441. anar |= ADVERTISE_10FULL;
  1442. if (bmsr & BMSR_10HALF)
  1443. anar |= ADVERTISE_10HALF;
  1444. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1445. mii_write (dev, phy_addr, MII_ADVERTISE, anar);
  1446. /* Enable Auto crossover */
  1447. pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
  1448. pscr |= 3 << 5; /* 11'b */
  1449. mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
  1450. /* Soft reset PHY */
  1451. mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
  1452. bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
  1453. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1454. mdelay(1);
  1455. } else {
  1456. /* Force speed setting */
  1457. /* 1) Disable Auto crossover */
  1458. pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
  1459. pscr &= ~(3 << 5);
  1460. mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
  1461. /* 2) PHY Reset */
  1462. bmcr = mii_read (dev, phy_addr, MII_BMCR);
  1463. bmcr |= BMCR_RESET;
  1464. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1465. /* 3) Power Down */
  1466. bmcr = 0x1940; /* must be 0x1940 */
  1467. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1468. mdelay (100); /* wait a certain time */
  1469. /* 4) Advertise nothing */
  1470. mii_write (dev, phy_addr, MII_ADVERTISE, 0);
  1471. /* 5) Set media and Power Up */
  1472. bmcr = BMCR_PDOWN;
  1473. if (np->speed == 100) {
  1474. bmcr |= BMCR_SPEED100;
  1475. printk (KERN_INFO "Manual 100 Mbps, ");
  1476. } else if (np->speed == 10) {
  1477. printk (KERN_INFO "Manual 10 Mbps, ");
  1478. }
  1479. if (np->full_duplex) {
  1480. bmcr |= BMCR_FULLDPLX;
  1481. printk (KERN_CONT "Full duplex\n");
  1482. } else {
  1483. printk (KERN_CONT "Half duplex\n");
  1484. }
  1485. #if 0
  1486. /* Set 1000BaseT Master/Slave setting */
  1487. mscr = mii_read (dev, phy_addr, MII_CTRL1000);
  1488. mscr |= MII_MSCR_CFG_ENABLE;
  1489. mscr &= ~MII_MSCR_CFG_VALUE = 0;
  1490. #endif
  1491. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1492. mdelay(10);
  1493. }
  1494. return 0;
  1495. }
  1496. static int
  1497. mii_get_media_pcs (struct net_device *dev)
  1498. {
  1499. __u16 negotiate;
  1500. __u16 bmsr;
  1501. int phy_addr;
  1502. struct netdev_private *np;
  1503. np = netdev_priv(dev);
  1504. phy_addr = np->phy_addr;
  1505. bmsr = mii_read (dev, phy_addr, PCS_BMSR);
  1506. if (np->an_enable) {
  1507. if (!(bmsr & BMSR_ANEGCOMPLETE)) {
  1508. /* Auto-Negotiation not completed */
  1509. return -1;
  1510. }
  1511. negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
  1512. mii_read (dev, phy_addr, PCS_ANLPAR);
  1513. np->speed = 1000;
  1514. if (negotiate & PCS_ANAR_FULL_DUPLEX) {
  1515. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1516. np->full_duplex = 1;
  1517. } else {
  1518. printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
  1519. np->full_duplex = 0;
  1520. }
  1521. if (negotiate & PCS_ANAR_PAUSE) {
  1522. np->tx_flow &= 1;
  1523. np->rx_flow &= 1;
  1524. } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
  1525. np->tx_flow = 0;
  1526. np->rx_flow &= 1;
  1527. }
  1528. /* else tx_flow, rx_flow = user select */
  1529. } else {
  1530. __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
  1531. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1532. if (bmcr & BMCR_FULLDPLX) {
  1533. printk (KERN_CONT "Full duplex\n");
  1534. } else {
  1535. printk (KERN_CONT "Half duplex\n");
  1536. }
  1537. }
  1538. if (np->tx_flow)
  1539. printk(KERN_INFO "Enable Tx Flow Control\n");
  1540. else
  1541. printk(KERN_INFO "Disable Tx Flow Control\n");
  1542. if (np->rx_flow)
  1543. printk(KERN_INFO "Enable Rx Flow Control\n");
  1544. else
  1545. printk(KERN_INFO "Disable Rx Flow Control\n");
  1546. return 0;
  1547. }
  1548. static int
  1549. mii_set_media_pcs (struct net_device *dev)
  1550. {
  1551. __u16 bmcr;
  1552. __u16 esr;
  1553. __u16 anar;
  1554. int phy_addr;
  1555. struct netdev_private *np;
  1556. np = netdev_priv(dev);
  1557. phy_addr = np->phy_addr;
  1558. /* Auto-Negotiation? */
  1559. if (np->an_enable) {
  1560. /* Advertise capabilities */
  1561. esr = mii_read (dev, phy_addr, PCS_ESR);
  1562. anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1563. ~PCS_ANAR_HALF_DUPLEX &
  1564. ~PCS_ANAR_FULL_DUPLEX;
  1565. if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
  1566. anar |= PCS_ANAR_HALF_DUPLEX;
  1567. if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
  1568. anar |= PCS_ANAR_FULL_DUPLEX;
  1569. anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
  1570. mii_write (dev, phy_addr, MII_ADVERTISE, anar);
  1571. /* Soft reset PHY */
  1572. mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
  1573. bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
  1574. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1575. mdelay(1);
  1576. } else {
  1577. /* Force speed setting */
  1578. /* PHY Reset */
  1579. bmcr = BMCR_RESET;
  1580. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1581. mdelay(10);
  1582. if (np->full_duplex) {
  1583. bmcr = BMCR_FULLDPLX;
  1584. printk (KERN_INFO "Manual full duplex\n");
  1585. } else {
  1586. bmcr = 0;
  1587. printk (KERN_INFO "Manual half duplex\n");
  1588. }
  1589. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1590. mdelay(10);
  1591. /* Advertise nothing */
  1592. mii_write (dev, phy_addr, MII_ADVERTISE, 0);
  1593. }
  1594. return 0;
  1595. }
  1596. static int
  1597. rio_close (struct net_device *dev)
  1598. {
  1599. struct netdev_private *np = netdev_priv(dev);
  1600. struct pci_dev *pdev = np->pdev;
  1601. netif_stop_queue (dev);
  1602. rio_hw_stop(dev);
  1603. free_irq(pdev->irq, dev);
  1604. del_timer_sync (&np->timer);
  1605. free_list(dev);
  1606. return 0;
  1607. }
  1608. static void
  1609. rio_remove1 (struct pci_dev *pdev)
  1610. {
  1611. struct net_device *dev = pci_get_drvdata (pdev);
  1612. if (dev) {
  1613. struct netdev_private *np = netdev_priv(dev);
  1614. unregister_netdev (dev);
  1615. pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
  1616. np->rx_ring_dma);
  1617. pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
  1618. np->tx_ring_dma);
  1619. #ifdef MEM_MAPPING
  1620. pci_iounmap(pdev, np->ioaddr);
  1621. #endif
  1622. pci_iounmap(pdev, np->eeprom_addr);
  1623. free_netdev (dev);
  1624. pci_release_regions (pdev);
  1625. pci_disable_device (pdev);
  1626. }
  1627. }
  1628. #ifdef CONFIG_PM_SLEEP
  1629. static int rio_suspend(struct device *device)
  1630. {
  1631. struct net_device *dev = dev_get_drvdata(device);
  1632. struct netdev_private *np = netdev_priv(dev);
  1633. if (!netif_running(dev))
  1634. return 0;
  1635. netif_device_detach(dev);
  1636. del_timer_sync(&np->timer);
  1637. rio_hw_stop(dev);
  1638. return 0;
  1639. }
  1640. static int rio_resume(struct device *device)
  1641. {
  1642. struct net_device *dev = dev_get_drvdata(device);
  1643. struct netdev_private *np = netdev_priv(dev);
  1644. if (!netif_running(dev))
  1645. return 0;
  1646. rio_reset_ring(np);
  1647. rio_hw_init(dev);
  1648. np->timer.expires = jiffies + 1 * HZ;
  1649. add_timer(&np->timer);
  1650. netif_device_attach(dev);
  1651. dl2k_enable_int(np);
  1652. return 0;
  1653. }
  1654. static SIMPLE_DEV_PM_OPS(rio_pm_ops, rio_suspend, rio_resume);
  1655. #define RIO_PM_OPS (&rio_pm_ops)
  1656. #else
  1657. #define RIO_PM_OPS NULL
  1658. #endif /* CONFIG_PM_SLEEP */
  1659. static struct pci_driver rio_driver = {
  1660. .name = "dl2k",
  1661. .id_table = rio_pci_tbl,
  1662. .probe = rio_probe1,
  1663. .remove = rio_remove1,
  1664. .driver.pm = RIO_PM_OPS,
  1665. };
  1666. module_pci_driver(rio_driver);
  1667. /*
  1668. Compile command:
  1669. gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
  1670. Read Documentation/networking/dl2k.txt for details.
  1671. */