atl1c_main.c 77 KB

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  1. /*
  2. * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
  3. *
  4. * Derived from Intel e1000 driver
  5. * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 2 of the License, or (at your option)
  10. * any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc., 59
  19. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20. */
  21. #include "atl1c.h"
  22. #define ATL1C_DRV_VERSION "1.0.1.1-NAPI"
  23. char atl1c_driver_name[] = "atl1c";
  24. char atl1c_driver_version[] = ATL1C_DRV_VERSION;
  25. /*
  26. * atl1c_pci_tbl - PCI Device ID Table
  27. *
  28. * Wildcard entries (PCI_ANY_ID) should come last
  29. * Last entry must be all 0s
  30. *
  31. * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  32. * Class, Class Mask, private data (not used) }
  33. */
  34. static const struct pci_device_id atl1c_pci_tbl[] = {
  35. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1C)},
  36. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2C)},
  37. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B)},
  38. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B2)},
  39. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D)},
  40. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D_2_0)},
  41. /* required last entry */
  42. { 0 }
  43. };
  44. MODULE_DEVICE_TABLE(pci, atl1c_pci_tbl);
  45. MODULE_AUTHOR("Jie Yang");
  46. MODULE_AUTHOR("Qualcomm Atheros Inc., <nic-devel@qualcomm.com>");
  47. MODULE_DESCRIPTION("Qualcomm Atheros 100/1000M Ethernet Network Driver");
  48. MODULE_LICENSE("GPL");
  49. MODULE_VERSION(ATL1C_DRV_VERSION);
  50. static int atl1c_stop_mac(struct atl1c_hw *hw);
  51. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw);
  52. static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed);
  53. static void atl1c_start_mac(struct atl1c_adapter *adapter);
  54. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
  55. int *work_done, int work_to_do);
  56. static int atl1c_up(struct atl1c_adapter *adapter);
  57. static void atl1c_down(struct atl1c_adapter *adapter);
  58. static int atl1c_reset_mac(struct atl1c_hw *hw);
  59. static void atl1c_reset_dma_ring(struct atl1c_adapter *adapter);
  60. static int atl1c_configure(struct atl1c_adapter *adapter);
  61. static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter);
  62. static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
  63. NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
  64. static void atl1c_pcie_patch(struct atl1c_hw *hw)
  65. {
  66. u32 mst_data, data;
  67. /* pclk sel could switch to 25M */
  68. AT_READ_REG(hw, REG_MASTER_CTRL, &mst_data);
  69. mst_data &= ~MASTER_CTRL_CLK_SEL_DIS;
  70. AT_WRITE_REG(hw, REG_MASTER_CTRL, mst_data);
  71. /* WoL/PCIE related settings */
  72. if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) {
  73. AT_READ_REG(hw, REG_PCIE_PHYMISC, &data);
  74. data |= PCIE_PHYMISC_FORCE_RCV_DET;
  75. AT_WRITE_REG(hw, REG_PCIE_PHYMISC, data);
  76. } else { /* new dev set bit5 of MASTER */
  77. if (!(mst_data & MASTER_CTRL_WAKEN_25M))
  78. AT_WRITE_REG(hw, REG_MASTER_CTRL,
  79. mst_data | MASTER_CTRL_WAKEN_25M);
  80. }
  81. /* aspm/PCIE setting only for l2cb 1.0 */
  82. if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10) {
  83. AT_READ_REG(hw, REG_PCIE_PHYMISC2, &data);
  84. data = FIELD_SETX(data, PCIE_PHYMISC2_CDR_BW,
  85. L2CB1_PCIE_PHYMISC2_CDR_BW);
  86. data = FIELD_SETX(data, PCIE_PHYMISC2_L0S_TH,
  87. L2CB1_PCIE_PHYMISC2_L0S_TH);
  88. AT_WRITE_REG(hw, REG_PCIE_PHYMISC2, data);
  89. /* extend L1 sync timer */
  90. AT_READ_REG(hw, REG_LINK_CTRL, &data);
  91. data |= LINK_CTRL_EXT_SYNC;
  92. AT_WRITE_REG(hw, REG_LINK_CTRL, data);
  93. }
  94. /* l2cb 1.x & l1d 1.x */
  95. if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d) {
  96. AT_READ_REG(hw, REG_PM_CTRL, &data);
  97. data |= PM_CTRL_L0S_BUFSRX_EN;
  98. AT_WRITE_REG(hw, REG_PM_CTRL, data);
  99. /* clear vendor msg */
  100. AT_READ_REG(hw, REG_DMA_DBG, &data);
  101. AT_WRITE_REG(hw, REG_DMA_DBG, data & ~DMA_DBG_VENDOR_MSG);
  102. }
  103. }
  104. /* FIXME: no need any more ? */
  105. /*
  106. * atl1c_init_pcie - init PCIE module
  107. */
  108. static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
  109. {
  110. u32 data;
  111. u32 pci_cmd;
  112. struct pci_dev *pdev = hw->adapter->pdev;
  113. int pos;
  114. AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
  115. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  116. pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  117. PCI_COMMAND_IO);
  118. AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd);
  119. /*
  120. * Clear any PowerSaveing Settings
  121. */
  122. pci_enable_wake(pdev, PCI_D3hot, 0);
  123. pci_enable_wake(pdev, PCI_D3cold, 0);
  124. /* wol sts read-clear */
  125. AT_READ_REG(hw, REG_WOL_CTRL, &data);
  126. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  127. /*
  128. * Mask some pcie error bits
  129. */
  130. pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
  131. if (pos) {
  132. pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, &data);
  133. data &= ~(PCI_ERR_UNC_DLP | PCI_ERR_UNC_FCP);
  134. pci_write_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, data);
  135. }
  136. /* clear error status */
  137. pcie_capability_write_word(pdev, PCI_EXP_DEVSTA,
  138. PCI_EXP_DEVSTA_NFED |
  139. PCI_EXP_DEVSTA_FED |
  140. PCI_EXP_DEVSTA_CED |
  141. PCI_EXP_DEVSTA_URD);
  142. AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &data);
  143. data &= ~LTSSM_ID_EN_WRO;
  144. AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, data);
  145. atl1c_pcie_patch(hw);
  146. if (flag & ATL1C_PCIE_L0S_L1_DISABLE)
  147. atl1c_disable_l0s_l1(hw);
  148. msleep(5);
  149. }
  150. /**
  151. * atl1c_irq_enable - Enable default interrupt generation settings
  152. * @adapter: board private structure
  153. */
  154. static inline void atl1c_irq_enable(struct atl1c_adapter *adapter)
  155. {
  156. if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
  157. AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF);
  158. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  159. AT_WRITE_FLUSH(&adapter->hw);
  160. }
  161. }
  162. /**
  163. * atl1c_irq_disable - Mask off interrupt generation on the NIC
  164. * @adapter: board private structure
  165. */
  166. static inline void atl1c_irq_disable(struct atl1c_adapter *adapter)
  167. {
  168. atomic_inc(&adapter->irq_sem);
  169. AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
  170. AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_INT);
  171. AT_WRITE_FLUSH(&adapter->hw);
  172. synchronize_irq(adapter->pdev->irq);
  173. }
  174. /**
  175. * atl1c_irq_reset - reset interrupt confiure on the NIC
  176. * @adapter: board private structure
  177. */
  178. static inline void atl1c_irq_reset(struct atl1c_adapter *adapter)
  179. {
  180. atomic_set(&adapter->irq_sem, 1);
  181. atl1c_irq_enable(adapter);
  182. }
  183. /*
  184. * atl1c_wait_until_idle - wait up to AT_HW_MAX_IDLE_DELAY reads
  185. * of the idle status register until the device is actually idle
  186. */
  187. static u32 atl1c_wait_until_idle(struct atl1c_hw *hw, u32 modu_ctrl)
  188. {
  189. int timeout;
  190. u32 data;
  191. for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
  192. AT_READ_REG(hw, REG_IDLE_STATUS, &data);
  193. if ((data & modu_ctrl) == 0)
  194. return 0;
  195. msleep(1);
  196. }
  197. return data;
  198. }
  199. /**
  200. * atl1c_phy_config - Timer Call-back
  201. * @data: pointer to netdev cast into an unsigned long
  202. */
  203. static void atl1c_phy_config(unsigned long data)
  204. {
  205. struct atl1c_adapter *adapter = (struct atl1c_adapter *) data;
  206. struct atl1c_hw *hw = &adapter->hw;
  207. unsigned long flags;
  208. spin_lock_irqsave(&adapter->mdio_lock, flags);
  209. atl1c_restart_autoneg(hw);
  210. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  211. }
  212. void atl1c_reinit_locked(struct atl1c_adapter *adapter)
  213. {
  214. WARN_ON(in_interrupt());
  215. atl1c_down(adapter);
  216. atl1c_up(adapter);
  217. clear_bit(__AT_RESETTING, &adapter->flags);
  218. }
  219. static void atl1c_check_link_status(struct atl1c_adapter *adapter)
  220. {
  221. struct atl1c_hw *hw = &adapter->hw;
  222. struct net_device *netdev = adapter->netdev;
  223. struct pci_dev *pdev = adapter->pdev;
  224. int err;
  225. unsigned long flags;
  226. u16 speed, duplex, phy_data;
  227. spin_lock_irqsave(&adapter->mdio_lock, flags);
  228. /* MII_BMSR must read twise */
  229. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  230. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  231. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  232. if ((phy_data & BMSR_LSTATUS) == 0) {
  233. /* link down */
  234. netif_carrier_off(netdev);
  235. hw->hibernate = true;
  236. if (atl1c_reset_mac(hw) != 0)
  237. if (netif_msg_hw(adapter))
  238. dev_warn(&pdev->dev, "reset mac failed\n");
  239. atl1c_set_aspm(hw, SPEED_0);
  240. atl1c_post_phy_linkchg(hw, SPEED_0);
  241. atl1c_reset_dma_ring(adapter);
  242. atl1c_configure(adapter);
  243. } else {
  244. /* Link Up */
  245. hw->hibernate = false;
  246. spin_lock_irqsave(&adapter->mdio_lock, flags);
  247. err = atl1c_get_speed_and_duplex(hw, &speed, &duplex);
  248. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  249. if (unlikely(err))
  250. return;
  251. /* link result is our setting */
  252. if (adapter->link_speed != speed ||
  253. adapter->link_duplex != duplex) {
  254. adapter->link_speed = speed;
  255. adapter->link_duplex = duplex;
  256. atl1c_set_aspm(hw, speed);
  257. atl1c_post_phy_linkchg(hw, speed);
  258. atl1c_start_mac(adapter);
  259. if (netif_msg_link(adapter))
  260. dev_info(&pdev->dev,
  261. "%s: %s NIC Link is Up<%d Mbps %s>\n",
  262. atl1c_driver_name, netdev->name,
  263. adapter->link_speed,
  264. adapter->link_duplex == FULL_DUPLEX ?
  265. "Full Duplex" : "Half Duplex");
  266. }
  267. if (!netif_carrier_ok(netdev))
  268. netif_carrier_on(netdev);
  269. }
  270. }
  271. static void atl1c_link_chg_event(struct atl1c_adapter *adapter)
  272. {
  273. struct net_device *netdev = adapter->netdev;
  274. struct pci_dev *pdev = adapter->pdev;
  275. u16 phy_data;
  276. u16 link_up;
  277. spin_lock(&adapter->mdio_lock);
  278. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  279. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  280. spin_unlock(&adapter->mdio_lock);
  281. link_up = phy_data & BMSR_LSTATUS;
  282. /* notify upper layer link down ASAP */
  283. if (!link_up) {
  284. if (netif_carrier_ok(netdev)) {
  285. /* old link state: Up */
  286. netif_carrier_off(netdev);
  287. if (netif_msg_link(adapter))
  288. dev_info(&pdev->dev,
  289. "%s: %s NIC Link is Down\n",
  290. atl1c_driver_name, netdev->name);
  291. adapter->link_speed = SPEED_0;
  292. }
  293. }
  294. set_bit(ATL1C_WORK_EVENT_LINK_CHANGE, &adapter->work_event);
  295. schedule_work(&adapter->common_task);
  296. }
  297. static void atl1c_common_task(struct work_struct *work)
  298. {
  299. struct atl1c_adapter *adapter;
  300. struct net_device *netdev;
  301. adapter = container_of(work, struct atl1c_adapter, common_task);
  302. netdev = adapter->netdev;
  303. if (test_bit(__AT_DOWN, &adapter->flags))
  304. return;
  305. if (test_and_clear_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event)) {
  306. netif_device_detach(netdev);
  307. atl1c_down(adapter);
  308. atl1c_up(adapter);
  309. netif_device_attach(netdev);
  310. }
  311. if (test_and_clear_bit(ATL1C_WORK_EVENT_LINK_CHANGE,
  312. &adapter->work_event)) {
  313. atl1c_irq_disable(adapter);
  314. atl1c_check_link_status(adapter);
  315. atl1c_irq_enable(adapter);
  316. }
  317. }
  318. static void atl1c_del_timer(struct atl1c_adapter *adapter)
  319. {
  320. del_timer_sync(&adapter->phy_config_timer);
  321. }
  322. /**
  323. * atl1c_tx_timeout - Respond to a Tx Hang
  324. * @netdev: network interface device structure
  325. */
  326. static void atl1c_tx_timeout(struct net_device *netdev)
  327. {
  328. struct atl1c_adapter *adapter = netdev_priv(netdev);
  329. /* Do the reset outside of interrupt context */
  330. set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
  331. schedule_work(&adapter->common_task);
  332. }
  333. /**
  334. * atl1c_set_multi - Multicast and Promiscuous mode set
  335. * @netdev: network interface device structure
  336. *
  337. * The set_multi entry point is called whenever the multicast address
  338. * list or the network interface flags are updated. This routine is
  339. * responsible for configuring the hardware for proper multicast,
  340. * promiscuous mode, and all-multi behavior.
  341. */
  342. static void atl1c_set_multi(struct net_device *netdev)
  343. {
  344. struct atl1c_adapter *adapter = netdev_priv(netdev);
  345. struct atl1c_hw *hw = &adapter->hw;
  346. struct netdev_hw_addr *ha;
  347. u32 mac_ctrl_data;
  348. u32 hash_value;
  349. /* Check for Promiscuous and All Multicast modes */
  350. AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
  351. if (netdev->flags & IFF_PROMISC) {
  352. mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
  353. } else if (netdev->flags & IFF_ALLMULTI) {
  354. mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
  355. mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
  356. } else {
  357. mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
  358. }
  359. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  360. /* clear the old settings from the multicast hash table */
  361. AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
  362. AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
  363. /* comoute mc addresses' hash value ,and put it into hash table */
  364. netdev_for_each_mc_addr(ha, netdev) {
  365. hash_value = atl1c_hash_mc_addr(hw, ha->addr);
  366. atl1c_hash_set(hw, hash_value);
  367. }
  368. }
  369. static void __atl1c_vlan_mode(netdev_features_t features, u32 *mac_ctrl_data)
  370. {
  371. if (features & NETIF_F_HW_VLAN_CTAG_RX) {
  372. /* enable VLAN tag insert/strip */
  373. *mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
  374. } else {
  375. /* disable VLAN tag insert/strip */
  376. *mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
  377. }
  378. }
  379. static void atl1c_vlan_mode(struct net_device *netdev,
  380. netdev_features_t features)
  381. {
  382. struct atl1c_adapter *adapter = netdev_priv(netdev);
  383. struct pci_dev *pdev = adapter->pdev;
  384. u32 mac_ctrl_data = 0;
  385. if (netif_msg_pktdata(adapter))
  386. dev_dbg(&pdev->dev, "atl1c_vlan_mode\n");
  387. atl1c_irq_disable(adapter);
  388. AT_READ_REG(&adapter->hw, REG_MAC_CTRL, &mac_ctrl_data);
  389. __atl1c_vlan_mode(features, &mac_ctrl_data);
  390. AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
  391. atl1c_irq_enable(adapter);
  392. }
  393. static void atl1c_restore_vlan(struct atl1c_adapter *adapter)
  394. {
  395. struct pci_dev *pdev = adapter->pdev;
  396. if (netif_msg_pktdata(adapter))
  397. dev_dbg(&pdev->dev, "atl1c_restore_vlan\n");
  398. atl1c_vlan_mode(adapter->netdev, adapter->netdev->features);
  399. }
  400. /**
  401. * atl1c_set_mac - Change the Ethernet Address of the NIC
  402. * @netdev: network interface device structure
  403. * @p: pointer to an address structure
  404. *
  405. * Returns 0 on success, negative on failure
  406. */
  407. static int atl1c_set_mac_addr(struct net_device *netdev, void *p)
  408. {
  409. struct atl1c_adapter *adapter = netdev_priv(netdev);
  410. struct sockaddr *addr = p;
  411. if (!is_valid_ether_addr(addr->sa_data))
  412. return -EADDRNOTAVAIL;
  413. if (netif_running(netdev))
  414. return -EBUSY;
  415. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  416. memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
  417. atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.mac_addr);
  418. return 0;
  419. }
  420. static void atl1c_set_rxbufsize(struct atl1c_adapter *adapter,
  421. struct net_device *dev)
  422. {
  423. unsigned int head_size;
  424. int mtu = dev->mtu;
  425. adapter->rx_buffer_len = mtu > AT_RX_BUF_SIZE ?
  426. roundup(mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN, 8) : AT_RX_BUF_SIZE;
  427. head_size = SKB_DATA_ALIGN(adapter->rx_buffer_len + NET_SKB_PAD) +
  428. SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
  429. adapter->rx_frag_size = roundup_pow_of_two(head_size);
  430. }
  431. static netdev_features_t atl1c_fix_features(struct net_device *netdev,
  432. netdev_features_t features)
  433. {
  434. /*
  435. * Since there is no support for separate rx/tx vlan accel
  436. * enable/disable make sure tx flag is always in same state as rx.
  437. */
  438. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  439. features |= NETIF_F_HW_VLAN_CTAG_TX;
  440. else
  441. features &= ~NETIF_F_HW_VLAN_CTAG_TX;
  442. if (netdev->mtu > MAX_TSO_FRAME_SIZE)
  443. features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
  444. return features;
  445. }
  446. static int atl1c_set_features(struct net_device *netdev,
  447. netdev_features_t features)
  448. {
  449. netdev_features_t changed = netdev->features ^ features;
  450. if (changed & NETIF_F_HW_VLAN_CTAG_RX)
  451. atl1c_vlan_mode(netdev, features);
  452. return 0;
  453. }
  454. static void atl1c_set_max_mtu(struct net_device *netdev)
  455. {
  456. struct atl1c_adapter *adapter = netdev_priv(netdev);
  457. struct atl1c_hw *hw = &adapter->hw;
  458. switch (hw->nic_type) {
  459. /* These (GbE) devices support jumbo packets, max_mtu 6122 */
  460. case athr_l1c:
  461. case athr_l1d:
  462. case athr_l1d_2:
  463. netdev->max_mtu = MAX_JUMBO_FRAME_SIZE -
  464. (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
  465. break;
  466. /* The 10/100 devices don't support jumbo packets, max_mtu 1500 */
  467. default:
  468. netdev->max_mtu = ETH_DATA_LEN;
  469. break;
  470. }
  471. }
  472. /**
  473. * atl1c_change_mtu - Change the Maximum Transfer Unit
  474. * @netdev: network interface device structure
  475. * @new_mtu: new value for maximum frame size
  476. *
  477. * Returns 0 on success, negative on failure
  478. */
  479. static int atl1c_change_mtu(struct net_device *netdev, int new_mtu)
  480. {
  481. struct atl1c_adapter *adapter = netdev_priv(netdev);
  482. /* set MTU */
  483. if (netif_running(netdev)) {
  484. while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
  485. msleep(1);
  486. netdev->mtu = new_mtu;
  487. adapter->hw.max_frame_size = new_mtu;
  488. atl1c_set_rxbufsize(adapter, netdev);
  489. atl1c_down(adapter);
  490. netdev_update_features(netdev);
  491. atl1c_up(adapter);
  492. clear_bit(__AT_RESETTING, &adapter->flags);
  493. }
  494. return 0;
  495. }
  496. /*
  497. * caller should hold mdio_lock
  498. */
  499. static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
  500. {
  501. struct atl1c_adapter *adapter = netdev_priv(netdev);
  502. u16 result;
  503. atl1c_read_phy_reg(&adapter->hw, reg_num, &result);
  504. return result;
  505. }
  506. static void atl1c_mdio_write(struct net_device *netdev, int phy_id,
  507. int reg_num, int val)
  508. {
  509. struct atl1c_adapter *adapter = netdev_priv(netdev);
  510. atl1c_write_phy_reg(&adapter->hw, reg_num, val);
  511. }
  512. static int atl1c_mii_ioctl(struct net_device *netdev,
  513. struct ifreq *ifr, int cmd)
  514. {
  515. struct atl1c_adapter *adapter = netdev_priv(netdev);
  516. struct pci_dev *pdev = adapter->pdev;
  517. struct mii_ioctl_data *data = if_mii(ifr);
  518. unsigned long flags;
  519. int retval = 0;
  520. if (!netif_running(netdev))
  521. return -EINVAL;
  522. spin_lock_irqsave(&adapter->mdio_lock, flags);
  523. switch (cmd) {
  524. case SIOCGMIIPHY:
  525. data->phy_id = 0;
  526. break;
  527. case SIOCGMIIREG:
  528. if (atl1c_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
  529. &data->val_out)) {
  530. retval = -EIO;
  531. goto out;
  532. }
  533. break;
  534. case SIOCSMIIREG:
  535. if (data->reg_num & ~(0x1F)) {
  536. retval = -EFAULT;
  537. goto out;
  538. }
  539. dev_dbg(&pdev->dev, "<atl1c_mii_ioctl> write %x %x",
  540. data->reg_num, data->val_in);
  541. if (atl1c_write_phy_reg(&adapter->hw,
  542. data->reg_num, data->val_in)) {
  543. retval = -EIO;
  544. goto out;
  545. }
  546. break;
  547. default:
  548. retval = -EOPNOTSUPP;
  549. break;
  550. }
  551. out:
  552. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  553. return retval;
  554. }
  555. static int atl1c_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  556. {
  557. switch (cmd) {
  558. case SIOCGMIIPHY:
  559. case SIOCGMIIREG:
  560. case SIOCSMIIREG:
  561. return atl1c_mii_ioctl(netdev, ifr, cmd);
  562. default:
  563. return -EOPNOTSUPP;
  564. }
  565. }
  566. /**
  567. * atl1c_alloc_queues - Allocate memory for all rings
  568. * @adapter: board private structure to initialize
  569. *
  570. */
  571. static int atl1c_alloc_queues(struct atl1c_adapter *adapter)
  572. {
  573. return 0;
  574. }
  575. static void atl1c_set_mac_type(struct atl1c_hw *hw)
  576. {
  577. switch (hw->device_id) {
  578. case PCI_DEVICE_ID_ATTANSIC_L2C:
  579. hw->nic_type = athr_l2c;
  580. break;
  581. case PCI_DEVICE_ID_ATTANSIC_L1C:
  582. hw->nic_type = athr_l1c;
  583. break;
  584. case PCI_DEVICE_ID_ATHEROS_L2C_B:
  585. hw->nic_type = athr_l2c_b;
  586. break;
  587. case PCI_DEVICE_ID_ATHEROS_L2C_B2:
  588. hw->nic_type = athr_l2c_b2;
  589. break;
  590. case PCI_DEVICE_ID_ATHEROS_L1D:
  591. hw->nic_type = athr_l1d;
  592. break;
  593. case PCI_DEVICE_ID_ATHEROS_L1D_2_0:
  594. hw->nic_type = athr_l1d_2;
  595. break;
  596. default:
  597. break;
  598. }
  599. }
  600. static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
  601. {
  602. u32 link_ctrl_data;
  603. atl1c_set_mac_type(hw);
  604. AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
  605. hw->ctrl_flags = ATL1C_INTR_MODRT_ENABLE |
  606. ATL1C_TXQ_MODE_ENHANCE;
  607. hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT |
  608. ATL1C_ASPM_L1_SUPPORT;
  609. hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON;
  610. if (hw->nic_type == athr_l1c ||
  611. hw->nic_type == athr_l1d ||
  612. hw->nic_type == athr_l1d_2)
  613. hw->link_cap_flags |= ATL1C_LINK_CAP_1000M;
  614. return 0;
  615. }
  616. struct atl1c_platform_patch {
  617. u16 pci_did;
  618. u8 pci_revid;
  619. u16 subsystem_vid;
  620. u16 subsystem_did;
  621. u32 patch_flag;
  622. #define ATL1C_LINK_PATCH 0x1
  623. };
  624. static const struct atl1c_platform_patch plats[] = {
  625. {0x2060, 0xC1, 0x1019, 0x8152, 0x1},
  626. {0x2060, 0xC1, 0x1019, 0x2060, 0x1},
  627. {0x2060, 0xC1, 0x1019, 0xE000, 0x1},
  628. {0x2062, 0xC0, 0x1019, 0x8152, 0x1},
  629. {0x2062, 0xC0, 0x1019, 0x2062, 0x1},
  630. {0x2062, 0xC0, 0x1458, 0xE000, 0x1},
  631. {0x2062, 0xC1, 0x1019, 0x8152, 0x1},
  632. {0x2062, 0xC1, 0x1019, 0x2062, 0x1},
  633. {0x2062, 0xC1, 0x1458, 0xE000, 0x1},
  634. {0x2062, 0xC1, 0x1565, 0x2802, 0x1},
  635. {0x2062, 0xC1, 0x1565, 0x2801, 0x1},
  636. {0x1073, 0xC0, 0x1019, 0x8151, 0x1},
  637. {0x1073, 0xC0, 0x1019, 0x1073, 0x1},
  638. {0x1073, 0xC0, 0x1458, 0xE000, 0x1},
  639. {0x1083, 0xC0, 0x1458, 0xE000, 0x1},
  640. {0x1083, 0xC0, 0x1019, 0x8151, 0x1},
  641. {0x1083, 0xC0, 0x1019, 0x1083, 0x1},
  642. {0x1083, 0xC0, 0x1462, 0x7680, 0x1},
  643. {0x1083, 0xC0, 0x1565, 0x2803, 0x1},
  644. {0},
  645. };
  646. static void atl1c_patch_assign(struct atl1c_hw *hw)
  647. {
  648. struct pci_dev *pdev = hw->adapter->pdev;
  649. u32 misc_ctrl;
  650. int i = 0;
  651. hw->msi_lnkpatch = false;
  652. while (plats[i].pci_did != 0) {
  653. if (plats[i].pci_did == hw->device_id &&
  654. plats[i].pci_revid == hw->revision_id &&
  655. plats[i].subsystem_vid == hw->subsystem_vendor_id &&
  656. plats[i].subsystem_did == hw->subsystem_id) {
  657. if (plats[i].patch_flag & ATL1C_LINK_PATCH)
  658. hw->msi_lnkpatch = true;
  659. }
  660. i++;
  661. }
  662. if (hw->device_id == PCI_DEVICE_ID_ATHEROS_L2C_B2 &&
  663. hw->revision_id == L2CB_V21) {
  664. /* config access mode */
  665. pci_write_config_dword(pdev, REG_PCIE_IND_ACC_ADDR,
  666. REG_PCIE_DEV_MISC_CTRL);
  667. pci_read_config_dword(pdev, REG_PCIE_IND_ACC_DATA, &misc_ctrl);
  668. misc_ctrl &= ~0x100;
  669. pci_write_config_dword(pdev, REG_PCIE_IND_ACC_ADDR,
  670. REG_PCIE_DEV_MISC_CTRL);
  671. pci_write_config_dword(pdev, REG_PCIE_IND_ACC_DATA, misc_ctrl);
  672. }
  673. }
  674. /**
  675. * atl1c_sw_init - Initialize general software structures (struct atl1c_adapter)
  676. * @adapter: board private structure to initialize
  677. *
  678. * atl1c_sw_init initializes the Adapter private data structure.
  679. * Fields are initialized based on PCI device information and
  680. * OS network device settings (MTU size).
  681. */
  682. static int atl1c_sw_init(struct atl1c_adapter *adapter)
  683. {
  684. struct atl1c_hw *hw = &adapter->hw;
  685. struct pci_dev *pdev = adapter->pdev;
  686. u32 revision;
  687. adapter->wol = 0;
  688. device_set_wakeup_enable(&pdev->dev, false);
  689. adapter->link_speed = SPEED_0;
  690. adapter->link_duplex = FULL_DUPLEX;
  691. adapter->tpd_ring[0].count = 1024;
  692. adapter->rfd_ring.count = 512;
  693. hw->vendor_id = pdev->vendor;
  694. hw->device_id = pdev->device;
  695. hw->subsystem_vendor_id = pdev->subsystem_vendor;
  696. hw->subsystem_id = pdev->subsystem_device;
  697. pci_read_config_dword(pdev, PCI_CLASS_REVISION, &revision);
  698. hw->revision_id = revision & 0xFF;
  699. /* before link up, we assume hibernate is true */
  700. hw->hibernate = true;
  701. hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
  702. if (atl1c_setup_mac_funcs(hw) != 0) {
  703. dev_err(&pdev->dev, "set mac function pointers failed\n");
  704. return -1;
  705. }
  706. atl1c_patch_assign(hw);
  707. hw->intr_mask = IMR_NORMAL_MASK;
  708. hw->phy_configured = false;
  709. hw->preamble_len = 7;
  710. hw->max_frame_size = adapter->netdev->mtu;
  711. hw->autoneg_advertised = ADVERTISED_Autoneg;
  712. hw->indirect_tab = 0xE4E4E4E4;
  713. hw->base_cpu = 0;
  714. hw->ict = 50000; /* 100ms */
  715. hw->smb_timer = 200000; /* 400ms */
  716. hw->rx_imt = 200;
  717. hw->tx_imt = 1000;
  718. hw->tpd_burst = 5;
  719. hw->rfd_burst = 8;
  720. hw->dma_order = atl1c_dma_ord_out;
  721. hw->dmar_block = atl1c_dma_req_1024;
  722. if (atl1c_alloc_queues(adapter)) {
  723. dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
  724. return -ENOMEM;
  725. }
  726. /* TODO */
  727. atl1c_set_rxbufsize(adapter, adapter->netdev);
  728. atomic_set(&adapter->irq_sem, 1);
  729. spin_lock_init(&adapter->mdio_lock);
  730. set_bit(__AT_DOWN, &adapter->flags);
  731. return 0;
  732. }
  733. static inline void atl1c_clean_buffer(struct pci_dev *pdev,
  734. struct atl1c_buffer *buffer_info)
  735. {
  736. u16 pci_driection;
  737. if (buffer_info->flags & ATL1C_BUFFER_FREE)
  738. return;
  739. if (buffer_info->dma) {
  740. if (buffer_info->flags & ATL1C_PCIMAP_FROMDEVICE)
  741. pci_driection = PCI_DMA_FROMDEVICE;
  742. else
  743. pci_driection = PCI_DMA_TODEVICE;
  744. if (buffer_info->flags & ATL1C_PCIMAP_SINGLE)
  745. pci_unmap_single(pdev, buffer_info->dma,
  746. buffer_info->length, pci_driection);
  747. else if (buffer_info->flags & ATL1C_PCIMAP_PAGE)
  748. pci_unmap_page(pdev, buffer_info->dma,
  749. buffer_info->length, pci_driection);
  750. }
  751. if (buffer_info->skb)
  752. dev_consume_skb_any(buffer_info->skb);
  753. buffer_info->dma = 0;
  754. buffer_info->skb = NULL;
  755. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  756. }
  757. /**
  758. * atl1c_clean_tx_ring - Free Tx-skb
  759. * @adapter: board private structure
  760. */
  761. static void atl1c_clean_tx_ring(struct atl1c_adapter *adapter,
  762. enum atl1c_trans_queue type)
  763. {
  764. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  765. struct atl1c_buffer *buffer_info;
  766. struct pci_dev *pdev = adapter->pdev;
  767. u16 index, ring_count;
  768. ring_count = tpd_ring->count;
  769. for (index = 0; index < ring_count; index++) {
  770. buffer_info = &tpd_ring->buffer_info[index];
  771. atl1c_clean_buffer(pdev, buffer_info);
  772. }
  773. netdev_reset_queue(adapter->netdev);
  774. /* Zero out Tx-buffers */
  775. memset(tpd_ring->desc, 0, sizeof(struct atl1c_tpd_desc) *
  776. ring_count);
  777. atomic_set(&tpd_ring->next_to_clean, 0);
  778. tpd_ring->next_to_use = 0;
  779. }
  780. /**
  781. * atl1c_clean_rx_ring - Free rx-reservation skbs
  782. * @adapter: board private structure
  783. */
  784. static void atl1c_clean_rx_ring(struct atl1c_adapter *adapter)
  785. {
  786. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  787. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  788. struct atl1c_buffer *buffer_info;
  789. struct pci_dev *pdev = adapter->pdev;
  790. int j;
  791. for (j = 0; j < rfd_ring->count; j++) {
  792. buffer_info = &rfd_ring->buffer_info[j];
  793. atl1c_clean_buffer(pdev, buffer_info);
  794. }
  795. /* zero out the descriptor ring */
  796. memset(rfd_ring->desc, 0, rfd_ring->size);
  797. rfd_ring->next_to_clean = 0;
  798. rfd_ring->next_to_use = 0;
  799. rrd_ring->next_to_use = 0;
  800. rrd_ring->next_to_clean = 0;
  801. }
  802. /*
  803. * Read / Write Ptr Initialize:
  804. */
  805. static void atl1c_init_ring_ptrs(struct atl1c_adapter *adapter)
  806. {
  807. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  808. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  809. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  810. struct atl1c_buffer *buffer_info;
  811. int i, j;
  812. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  813. tpd_ring[i].next_to_use = 0;
  814. atomic_set(&tpd_ring[i].next_to_clean, 0);
  815. buffer_info = tpd_ring[i].buffer_info;
  816. for (j = 0; j < tpd_ring->count; j++)
  817. ATL1C_SET_BUFFER_STATE(&buffer_info[i],
  818. ATL1C_BUFFER_FREE);
  819. }
  820. rfd_ring->next_to_use = 0;
  821. rfd_ring->next_to_clean = 0;
  822. rrd_ring->next_to_use = 0;
  823. rrd_ring->next_to_clean = 0;
  824. for (j = 0; j < rfd_ring->count; j++) {
  825. buffer_info = &rfd_ring->buffer_info[j];
  826. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  827. }
  828. }
  829. /**
  830. * atl1c_free_ring_resources - Free Tx / RX descriptor Resources
  831. * @adapter: board private structure
  832. *
  833. * Free all transmit software resources
  834. */
  835. static void atl1c_free_ring_resources(struct atl1c_adapter *adapter)
  836. {
  837. struct pci_dev *pdev = adapter->pdev;
  838. pci_free_consistent(pdev, adapter->ring_header.size,
  839. adapter->ring_header.desc,
  840. adapter->ring_header.dma);
  841. adapter->ring_header.desc = NULL;
  842. /* Note: just free tdp_ring.buffer_info,
  843. * it contain rfd_ring.buffer_info, do not double free */
  844. if (adapter->tpd_ring[0].buffer_info) {
  845. kfree(adapter->tpd_ring[0].buffer_info);
  846. adapter->tpd_ring[0].buffer_info = NULL;
  847. }
  848. if (adapter->rx_page) {
  849. put_page(adapter->rx_page);
  850. adapter->rx_page = NULL;
  851. }
  852. }
  853. /**
  854. * atl1c_setup_mem_resources - allocate Tx / RX descriptor resources
  855. * @adapter: board private structure
  856. *
  857. * Return 0 on success, negative on failure
  858. */
  859. static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter)
  860. {
  861. struct pci_dev *pdev = adapter->pdev;
  862. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  863. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  864. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  865. struct atl1c_ring_header *ring_header = &adapter->ring_header;
  866. int size;
  867. int i;
  868. int count = 0;
  869. int rx_desc_count = 0;
  870. u32 offset = 0;
  871. rrd_ring->count = rfd_ring->count;
  872. for (i = 1; i < AT_MAX_TRANSMIT_QUEUE; i++)
  873. tpd_ring[i].count = tpd_ring[0].count;
  874. /* 2 tpd queue, one high priority queue,
  875. * another normal priority queue */
  876. size = sizeof(struct atl1c_buffer) * (tpd_ring->count * 2 +
  877. rfd_ring->count);
  878. tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
  879. if (unlikely(!tpd_ring->buffer_info))
  880. goto err_nomem;
  881. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  882. tpd_ring[i].buffer_info =
  883. (tpd_ring->buffer_info + count);
  884. count += tpd_ring[i].count;
  885. }
  886. rfd_ring->buffer_info =
  887. (tpd_ring->buffer_info + count);
  888. count += rfd_ring->count;
  889. rx_desc_count += rfd_ring->count;
  890. /*
  891. * real ring DMA buffer
  892. * each ring/block may need up to 8 bytes for alignment, hence the
  893. * additional bytes tacked onto the end.
  894. */
  895. ring_header->size = size =
  896. sizeof(struct atl1c_tpd_desc) * tpd_ring->count * 2 +
  897. sizeof(struct atl1c_rx_free_desc) * rx_desc_count +
  898. sizeof(struct atl1c_recv_ret_status) * rx_desc_count +
  899. 8 * 4;
  900. ring_header->desc = dma_zalloc_coherent(&pdev->dev, ring_header->size,
  901. &ring_header->dma, GFP_KERNEL);
  902. if (unlikely(!ring_header->desc)) {
  903. dev_err(&pdev->dev, "could not get memory for DMA buffer\n");
  904. goto err_nomem;
  905. }
  906. /* init TPD ring */
  907. tpd_ring[0].dma = roundup(ring_header->dma, 8);
  908. offset = tpd_ring[0].dma - ring_header->dma;
  909. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  910. tpd_ring[i].dma = ring_header->dma + offset;
  911. tpd_ring[i].desc = (u8 *) ring_header->desc + offset;
  912. tpd_ring[i].size =
  913. sizeof(struct atl1c_tpd_desc) * tpd_ring[i].count;
  914. offset += roundup(tpd_ring[i].size, 8);
  915. }
  916. /* init RFD ring */
  917. rfd_ring->dma = ring_header->dma + offset;
  918. rfd_ring->desc = (u8 *) ring_header->desc + offset;
  919. rfd_ring->size = sizeof(struct atl1c_rx_free_desc) * rfd_ring->count;
  920. offset += roundup(rfd_ring->size, 8);
  921. /* init RRD ring */
  922. rrd_ring->dma = ring_header->dma + offset;
  923. rrd_ring->desc = (u8 *) ring_header->desc + offset;
  924. rrd_ring->size = sizeof(struct atl1c_recv_ret_status) *
  925. rrd_ring->count;
  926. offset += roundup(rrd_ring->size, 8);
  927. return 0;
  928. err_nomem:
  929. kfree(tpd_ring->buffer_info);
  930. return -ENOMEM;
  931. }
  932. static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
  933. {
  934. struct atl1c_hw *hw = &adapter->hw;
  935. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  936. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  937. struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
  938. adapter->tpd_ring;
  939. /* TPD */
  940. AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
  941. (u32)((tpd_ring[atl1c_trans_normal].dma &
  942. AT_DMA_HI_ADDR_MASK) >> 32));
  943. /* just enable normal priority TX queue */
  944. AT_WRITE_REG(hw, REG_TPD_PRI0_ADDR_LO,
  945. (u32)(tpd_ring[atl1c_trans_normal].dma &
  946. AT_DMA_LO_ADDR_MASK));
  947. AT_WRITE_REG(hw, REG_TPD_PRI1_ADDR_LO,
  948. (u32)(tpd_ring[atl1c_trans_high].dma &
  949. AT_DMA_LO_ADDR_MASK));
  950. AT_WRITE_REG(hw, REG_TPD_RING_SIZE,
  951. (u32)(tpd_ring[0].count & TPD_RING_SIZE_MASK));
  952. /* RFD */
  953. AT_WRITE_REG(hw, REG_RX_BASE_ADDR_HI,
  954. (u32)((rfd_ring->dma & AT_DMA_HI_ADDR_MASK) >> 32));
  955. AT_WRITE_REG(hw, REG_RFD0_HEAD_ADDR_LO,
  956. (u32)(rfd_ring->dma & AT_DMA_LO_ADDR_MASK));
  957. AT_WRITE_REG(hw, REG_RFD_RING_SIZE,
  958. rfd_ring->count & RFD_RING_SIZE_MASK);
  959. AT_WRITE_REG(hw, REG_RX_BUF_SIZE,
  960. adapter->rx_buffer_len & RX_BUF_SIZE_MASK);
  961. /* RRD */
  962. AT_WRITE_REG(hw, REG_RRD0_HEAD_ADDR_LO,
  963. (u32)(rrd_ring->dma & AT_DMA_LO_ADDR_MASK));
  964. AT_WRITE_REG(hw, REG_RRD_RING_SIZE,
  965. (rrd_ring->count & RRD_RING_SIZE_MASK));
  966. if (hw->nic_type == athr_l2c_b) {
  967. AT_WRITE_REG(hw, REG_SRAM_RXF_LEN, 0x02a0L);
  968. AT_WRITE_REG(hw, REG_SRAM_TXF_LEN, 0x0100L);
  969. AT_WRITE_REG(hw, REG_SRAM_RXF_ADDR, 0x029f0000L);
  970. AT_WRITE_REG(hw, REG_SRAM_RFD0_INFO, 0x02bf02a0L);
  971. AT_WRITE_REG(hw, REG_SRAM_TXF_ADDR, 0x03bf02c0L);
  972. AT_WRITE_REG(hw, REG_SRAM_TRD_ADDR, 0x03df03c0L);
  973. AT_WRITE_REG(hw, REG_TXF_WATER_MARK, 0); /* TX watermark, to enter l1 state.*/
  974. AT_WRITE_REG(hw, REG_RXD_DMA_CTRL, 0); /* RXD threshold.*/
  975. }
  976. /* Load all of base address above */
  977. AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
  978. }
  979. static void atl1c_configure_tx(struct atl1c_adapter *adapter)
  980. {
  981. struct atl1c_hw *hw = &adapter->hw;
  982. int max_pay_load;
  983. u16 tx_offload_thresh;
  984. u32 txq_ctrl_data;
  985. tx_offload_thresh = MAX_TSO_FRAME_SIZE;
  986. AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH,
  987. (tx_offload_thresh >> 3) & TX_TSO_OFFLOAD_THRESH_MASK);
  988. max_pay_load = pcie_get_readrq(adapter->pdev) >> 8;
  989. hw->dmar_block = min_t(u32, max_pay_load, hw->dmar_block);
  990. /*
  991. * if BIOS had changed the dam-read-max-length to an invalid value,
  992. * restore it to default value
  993. */
  994. if (hw->dmar_block < DEVICE_CTRL_MAXRRS_MIN) {
  995. pcie_set_readrq(adapter->pdev, 128 << DEVICE_CTRL_MAXRRS_MIN);
  996. hw->dmar_block = DEVICE_CTRL_MAXRRS_MIN;
  997. }
  998. txq_ctrl_data =
  999. hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2 ?
  1000. L2CB_TXQ_CFGV : L1C_TXQ_CFGV;
  1001. AT_WRITE_REG(hw, REG_TXQ_CTRL, txq_ctrl_data);
  1002. }
  1003. static void atl1c_configure_rx(struct atl1c_adapter *adapter)
  1004. {
  1005. struct atl1c_hw *hw = &adapter->hw;
  1006. u32 rxq_ctrl_data;
  1007. rxq_ctrl_data = (hw->rfd_burst & RXQ_RFD_BURST_NUM_MASK) <<
  1008. RXQ_RFD_BURST_NUM_SHIFT;
  1009. if (hw->ctrl_flags & ATL1C_RX_IPV6_CHKSUM)
  1010. rxq_ctrl_data |= IPV6_CHKSUM_CTRL_EN;
  1011. /* aspm for gigabit */
  1012. if (hw->nic_type != athr_l1d_2 && (hw->device_id & 1) != 0)
  1013. rxq_ctrl_data = FIELD_SETX(rxq_ctrl_data, ASPM_THRUPUT_LIMIT,
  1014. ASPM_THRUPUT_LIMIT_100M);
  1015. AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
  1016. }
  1017. static void atl1c_configure_dma(struct atl1c_adapter *adapter)
  1018. {
  1019. struct atl1c_hw *hw = &adapter->hw;
  1020. u32 dma_ctrl_data;
  1021. dma_ctrl_data = FIELDX(DMA_CTRL_RORDER_MODE, DMA_CTRL_RORDER_MODE_OUT) |
  1022. DMA_CTRL_RREQ_PRI_DATA |
  1023. FIELDX(DMA_CTRL_RREQ_BLEN, hw->dmar_block) |
  1024. FIELDX(DMA_CTRL_WDLY_CNT, DMA_CTRL_WDLY_CNT_DEF) |
  1025. FIELDX(DMA_CTRL_RDLY_CNT, DMA_CTRL_RDLY_CNT_DEF);
  1026. AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
  1027. }
  1028. /*
  1029. * Stop the mac, transmit and receive units
  1030. * hw - Struct containing variables accessed by shared code
  1031. * return : 0 or idle status (if error)
  1032. */
  1033. static int atl1c_stop_mac(struct atl1c_hw *hw)
  1034. {
  1035. u32 data;
  1036. AT_READ_REG(hw, REG_RXQ_CTRL, &data);
  1037. data &= ~RXQ_CTRL_EN;
  1038. AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
  1039. AT_READ_REG(hw, REG_TXQ_CTRL, &data);
  1040. data &= ~TXQ_CTRL_EN;
  1041. AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
  1042. atl1c_wait_until_idle(hw, IDLE_STATUS_RXQ_BUSY | IDLE_STATUS_TXQ_BUSY);
  1043. AT_READ_REG(hw, REG_MAC_CTRL, &data);
  1044. data &= ~(MAC_CTRL_TX_EN | MAC_CTRL_RX_EN);
  1045. AT_WRITE_REG(hw, REG_MAC_CTRL, data);
  1046. return (int)atl1c_wait_until_idle(hw,
  1047. IDLE_STATUS_TXMAC_BUSY | IDLE_STATUS_RXMAC_BUSY);
  1048. }
  1049. static void atl1c_start_mac(struct atl1c_adapter *adapter)
  1050. {
  1051. struct atl1c_hw *hw = &adapter->hw;
  1052. u32 mac, txq, rxq;
  1053. hw->mac_duplex = adapter->link_duplex == FULL_DUPLEX ? true : false;
  1054. hw->mac_speed = adapter->link_speed == SPEED_1000 ?
  1055. atl1c_mac_speed_1000 : atl1c_mac_speed_10_100;
  1056. AT_READ_REG(hw, REG_TXQ_CTRL, &txq);
  1057. AT_READ_REG(hw, REG_RXQ_CTRL, &rxq);
  1058. AT_READ_REG(hw, REG_MAC_CTRL, &mac);
  1059. txq |= TXQ_CTRL_EN;
  1060. rxq |= RXQ_CTRL_EN;
  1061. mac |= MAC_CTRL_TX_EN | MAC_CTRL_TX_FLOW |
  1062. MAC_CTRL_RX_EN | MAC_CTRL_RX_FLOW |
  1063. MAC_CTRL_ADD_CRC | MAC_CTRL_PAD |
  1064. MAC_CTRL_BC_EN | MAC_CTRL_SINGLE_PAUSE_EN |
  1065. MAC_CTRL_HASH_ALG_CRC32;
  1066. if (hw->mac_duplex)
  1067. mac |= MAC_CTRL_DUPLX;
  1068. else
  1069. mac &= ~MAC_CTRL_DUPLX;
  1070. mac = FIELD_SETX(mac, MAC_CTRL_SPEED, hw->mac_speed);
  1071. mac = FIELD_SETX(mac, MAC_CTRL_PRMLEN, hw->preamble_len);
  1072. AT_WRITE_REG(hw, REG_TXQ_CTRL, txq);
  1073. AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq);
  1074. AT_WRITE_REG(hw, REG_MAC_CTRL, mac);
  1075. }
  1076. /*
  1077. * Reset the transmit and receive units; mask and clear all interrupts.
  1078. * hw - Struct containing variables accessed by shared code
  1079. * return : 0 or idle status (if error)
  1080. */
  1081. static int atl1c_reset_mac(struct atl1c_hw *hw)
  1082. {
  1083. struct atl1c_adapter *adapter = hw->adapter;
  1084. struct pci_dev *pdev = adapter->pdev;
  1085. u32 ctrl_data = 0;
  1086. atl1c_stop_mac(hw);
  1087. /*
  1088. * Issue Soft Reset to the MAC. This will reset the chip's
  1089. * transmit, receive, DMA. It will not effect
  1090. * the current PCI configuration. The global reset bit is self-
  1091. * clearing, and should clear within a microsecond.
  1092. */
  1093. AT_READ_REG(hw, REG_MASTER_CTRL, &ctrl_data);
  1094. ctrl_data |= MASTER_CTRL_OOB_DIS;
  1095. AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data | MASTER_CTRL_SOFT_RST);
  1096. AT_WRITE_FLUSH(hw);
  1097. msleep(10);
  1098. /* Wait at least 10ms for All module to be Idle */
  1099. if (atl1c_wait_until_idle(hw, IDLE_STATUS_MASK)) {
  1100. dev_err(&pdev->dev,
  1101. "MAC state machine can't be idle since"
  1102. " disabled for 10ms second\n");
  1103. return -1;
  1104. }
  1105. AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data);
  1106. /* driver control speed/duplex */
  1107. AT_READ_REG(hw, REG_MAC_CTRL, &ctrl_data);
  1108. AT_WRITE_REG(hw, REG_MAC_CTRL, ctrl_data | MAC_CTRL_SPEED_MODE_SW);
  1109. /* clk switch setting */
  1110. AT_READ_REG(hw, REG_SERDES, &ctrl_data);
  1111. switch (hw->nic_type) {
  1112. case athr_l2c_b:
  1113. ctrl_data &= ~(SERDES_PHY_CLK_SLOWDOWN |
  1114. SERDES_MAC_CLK_SLOWDOWN);
  1115. AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
  1116. break;
  1117. case athr_l2c_b2:
  1118. case athr_l1d_2:
  1119. ctrl_data |= SERDES_PHY_CLK_SLOWDOWN | SERDES_MAC_CLK_SLOWDOWN;
  1120. AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
  1121. break;
  1122. default:
  1123. break;
  1124. }
  1125. return 0;
  1126. }
  1127. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw)
  1128. {
  1129. u16 ctrl_flags = hw->ctrl_flags;
  1130. hw->ctrl_flags &= ~(ATL1C_ASPM_L0S_SUPPORT | ATL1C_ASPM_L1_SUPPORT);
  1131. atl1c_set_aspm(hw, SPEED_0);
  1132. hw->ctrl_flags = ctrl_flags;
  1133. }
  1134. /*
  1135. * Set ASPM state.
  1136. * Enable/disable L0s/L1 depend on link state.
  1137. */
  1138. static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed)
  1139. {
  1140. u32 pm_ctrl_data;
  1141. u32 link_l1_timer;
  1142. AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
  1143. pm_ctrl_data &= ~(PM_CTRL_ASPM_L1_EN |
  1144. PM_CTRL_ASPM_L0S_EN |
  1145. PM_CTRL_MAC_ASPM_CHK);
  1146. /* L1 timer */
  1147. if (hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
  1148. pm_ctrl_data &= ~PMCTRL_TXL1_AFTER_L0S;
  1149. link_l1_timer =
  1150. link_speed == SPEED_1000 || link_speed == SPEED_100 ?
  1151. L1D_PMCTRL_L1_ENTRY_TM_16US : 1;
  1152. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1153. L1D_PMCTRL_L1_ENTRY_TM, link_l1_timer);
  1154. } else {
  1155. link_l1_timer = hw->nic_type == athr_l2c_b ?
  1156. L2CB1_PM_CTRL_L1_ENTRY_TM : L1C_PM_CTRL_L1_ENTRY_TM;
  1157. if (link_speed != SPEED_1000 && link_speed != SPEED_100)
  1158. link_l1_timer = 1;
  1159. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1160. PM_CTRL_L1_ENTRY_TIMER, link_l1_timer);
  1161. }
  1162. /* L0S/L1 enable */
  1163. if ((hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT) && link_speed != SPEED_0)
  1164. pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN | PM_CTRL_MAC_ASPM_CHK;
  1165. if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
  1166. pm_ctrl_data |= PM_CTRL_ASPM_L1_EN | PM_CTRL_MAC_ASPM_CHK;
  1167. /* l2cb & l1d & l2cb2 & l1d2 */
  1168. if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
  1169. hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
  1170. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1171. PM_CTRL_PM_REQ_TIMER, PM_CTRL_PM_REQ_TO_DEF);
  1172. pm_ctrl_data |= PM_CTRL_RCVR_WT_TIMER |
  1173. PM_CTRL_SERDES_PD_EX_L1 |
  1174. PM_CTRL_CLK_SWH_L1;
  1175. pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
  1176. PM_CTRL_SERDES_PLL_L1_EN |
  1177. PM_CTRL_SERDES_BUFS_RX_L1_EN |
  1178. PM_CTRL_SA_DLY_EN |
  1179. PM_CTRL_HOTRST);
  1180. /* disable l0s if link down or l2cb */
  1181. if (link_speed == SPEED_0 || hw->nic_type == athr_l2c_b)
  1182. pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
  1183. } else { /* l1c */
  1184. pm_ctrl_data =
  1185. FIELD_SETX(pm_ctrl_data, PM_CTRL_L1_ENTRY_TIMER, 0);
  1186. if (link_speed != SPEED_0) {
  1187. pm_ctrl_data |= PM_CTRL_SERDES_L1_EN |
  1188. PM_CTRL_SERDES_PLL_L1_EN |
  1189. PM_CTRL_SERDES_BUFS_RX_L1_EN;
  1190. pm_ctrl_data &= ~(PM_CTRL_SERDES_PD_EX_L1 |
  1191. PM_CTRL_CLK_SWH_L1 |
  1192. PM_CTRL_ASPM_L0S_EN |
  1193. PM_CTRL_ASPM_L1_EN);
  1194. } else { /* link down */
  1195. pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
  1196. pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
  1197. PM_CTRL_SERDES_PLL_L1_EN |
  1198. PM_CTRL_SERDES_BUFS_RX_L1_EN |
  1199. PM_CTRL_ASPM_L0S_EN);
  1200. }
  1201. }
  1202. AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
  1203. return;
  1204. }
  1205. /**
  1206. * atl1c_configure - Configure Transmit&Receive Unit after Reset
  1207. * @adapter: board private structure
  1208. *
  1209. * Configure the Tx /Rx unit of the MAC after a reset.
  1210. */
  1211. static int atl1c_configure_mac(struct atl1c_adapter *adapter)
  1212. {
  1213. struct atl1c_hw *hw = &adapter->hw;
  1214. u32 master_ctrl_data = 0;
  1215. u32 intr_modrt_data;
  1216. u32 data;
  1217. AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
  1218. master_ctrl_data &= ~(MASTER_CTRL_TX_ITIMER_EN |
  1219. MASTER_CTRL_RX_ITIMER_EN |
  1220. MASTER_CTRL_INT_RDCLR);
  1221. /* clear interrupt status */
  1222. AT_WRITE_REG(hw, REG_ISR, 0xFFFFFFFF);
  1223. /* Clear any WOL status */
  1224. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  1225. /* set Interrupt Clear Timer
  1226. * HW will enable self to assert interrupt event to system after
  1227. * waiting x-time for software to notify it accept interrupt.
  1228. */
  1229. data = CLK_GATING_EN_ALL;
  1230. if (hw->ctrl_flags & ATL1C_CLK_GATING_EN) {
  1231. if (hw->nic_type == athr_l2c_b)
  1232. data &= ~CLK_GATING_RXMAC_EN;
  1233. } else
  1234. data = 0;
  1235. AT_WRITE_REG(hw, REG_CLK_GATING_CTRL, data);
  1236. AT_WRITE_REG(hw, REG_INT_RETRIG_TIMER,
  1237. hw->ict & INT_RETRIG_TIMER_MASK);
  1238. atl1c_configure_des_ring(adapter);
  1239. if (hw->ctrl_flags & ATL1C_INTR_MODRT_ENABLE) {
  1240. intr_modrt_data = (hw->tx_imt & IRQ_MODRT_TIMER_MASK) <<
  1241. IRQ_MODRT_TX_TIMER_SHIFT;
  1242. intr_modrt_data |= (hw->rx_imt & IRQ_MODRT_TIMER_MASK) <<
  1243. IRQ_MODRT_RX_TIMER_SHIFT;
  1244. AT_WRITE_REG(hw, REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);
  1245. master_ctrl_data |=
  1246. MASTER_CTRL_TX_ITIMER_EN | MASTER_CTRL_RX_ITIMER_EN;
  1247. }
  1248. if (hw->ctrl_flags & ATL1C_INTR_CLEAR_ON_READ)
  1249. master_ctrl_data |= MASTER_CTRL_INT_RDCLR;
  1250. master_ctrl_data |= MASTER_CTRL_SA_TIMER_EN;
  1251. AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
  1252. AT_WRITE_REG(hw, REG_SMB_STAT_TIMER,
  1253. hw->smb_timer & SMB_STAT_TIMER_MASK);
  1254. /* set MTU */
  1255. AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
  1256. VLAN_HLEN + ETH_FCS_LEN);
  1257. atl1c_configure_tx(adapter);
  1258. atl1c_configure_rx(adapter);
  1259. atl1c_configure_dma(adapter);
  1260. return 0;
  1261. }
  1262. static int atl1c_configure(struct atl1c_adapter *adapter)
  1263. {
  1264. struct net_device *netdev = adapter->netdev;
  1265. int num;
  1266. atl1c_init_ring_ptrs(adapter);
  1267. atl1c_set_multi(netdev);
  1268. atl1c_restore_vlan(adapter);
  1269. num = atl1c_alloc_rx_buffer(adapter);
  1270. if (unlikely(num == 0))
  1271. return -ENOMEM;
  1272. if (atl1c_configure_mac(adapter))
  1273. return -EIO;
  1274. return 0;
  1275. }
  1276. static void atl1c_update_hw_stats(struct atl1c_adapter *adapter)
  1277. {
  1278. u16 hw_reg_addr = 0;
  1279. unsigned long *stats_item = NULL;
  1280. u32 data;
  1281. /* update rx status */
  1282. hw_reg_addr = REG_MAC_RX_STATUS_BIN;
  1283. stats_item = &adapter->hw_stats.rx_ok;
  1284. while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
  1285. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1286. *stats_item += data;
  1287. stats_item++;
  1288. hw_reg_addr += 4;
  1289. }
  1290. /* update tx status */
  1291. hw_reg_addr = REG_MAC_TX_STATUS_BIN;
  1292. stats_item = &adapter->hw_stats.tx_ok;
  1293. while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
  1294. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1295. *stats_item += data;
  1296. stats_item++;
  1297. hw_reg_addr += 4;
  1298. }
  1299. }
  1300. /**
  1301. * atl1c_get_stats - Get System Network Statistics
  1302. * @netdev: network interface device structure
  1303. *
  1304. * Returns the address of the device statistics structure.
  1305. * The statistics are actually updated from the timer callback.
  1306. */
  1307. static struct net_device_stats *atl1c_get_stats(struct net_device *netdev)
  1308. {
  1309. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1310. struct atl1c_hw_stats *hw_stats = &adapter->hw_stats;
  1311. struct net_device_stats *net_stats = &netdev->stats;
  1312. atl1c_update_hw_stats(adapter);
  1313. net_stats->rx_bytes = hw_stats->rx_byte_cnt;
  1314. net_stats->tx_bytes = hw_stats->tx_byte_cnt;
  1315. net_stats->multicast = hw_stats->rx_mcast;
  1316. net_stats->collisions = hw_stats->tx_1_col +
  1317. hw_stats->tx_2_col +
  1318. hw_stats->tx_late_col +
  1319. hw_stats->tx_abort_col;
  1320. net_stats->rx_errors = hw_stats->rx_frag +
  1321. hw_stats->rx_fcs_err +
  1322. hw_stats->rx_len_err +
  1323. hw_stats->rx_sz_ov +
  1324. hw_stats->rx_rrd_ov +
  1325. hw_stats->rx_align_err +
  1326. hw_stats->rx_rxf_ov;
  1327. net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
  1328. net_stats->rx_length_errors = hw_stats->rx_len_err;
  1329. net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
  1330. net_stats->rx_frame_errors = hw_stats->rx_align_err;
  1331. net_stats->rx_dropped = hw_stats->rx_rrd_ov;
  1332. net_stats->tx_errors = hw_stats->tx_late_col +
  1333. hw_stats->tx_abort_col +
  1334. hw_stats->tx_underrun +
  1335. hw_stats->tx_trunc;
  1336. net_stats->tx_fifo_errors = hw_stats->tx_underrun;
  1337. net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
  1338. net_stats->tx_window_errors = hw_stats->tx_late_col;
  1339. net_stats->rx_packets = hw_stats->rx_ok + net_stats->rx_errors;
  1340. net_stats->tx_packets = hw_stats->tx_ok + net_stats->tx_errors;
  1341. return net_stats;
  1342. }
  1343. static inline void atl1c_clear_phy_int(struct atl1c_adapter *adapter)
  1344. {
  1345. u16 phy_data;
  1346. spin_lock(&adapter->mdio_lock);
  1347. atl1c_read_phy_reg(&adapter->hw, MII_ISR, &phy_data);
  1348. spin_unlock(&adapter->mdio_lock);
  1349. }
  1350. static bool atl1c_clean_tx_irq(struct atl1c_adapter *adapter,
  1351. enum atl1c_trans_queue type)
  1352. {
  1353. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1354. struct atl1c_buffer *buffer_info;
  1355. struct pci_dev *pdev = adapter->pdev;
  1356. u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1357. u16 hw_next_to_clean;
  1358. u16 reg;
  1359. unsigned int total_bytes = 0, total_packets = 0;
  1360. reg = type == atl1c_trans_high ? REG_TPD_PRI1_CIDX : REG_TPD_PRI0_CIDX;
  1361. AT_READ_REGW(&adapter->hw, reg, &hw_next_to_clean);
  1362. while (next_to_clean != hw_next_to_clean) {
  1363. buffer_info = &tpd_ring->buffer_info[next_to_clean];
  1364. if (buffer_info->skb) {
  1365. total_bytes += buffer_info->skb->len;
  1366. total_packets++;
  1367. }
  1368. atl1c_clean_buffer(pdev, buffer_info);
  1369. if (++next_to_clean == tpd_ring->count)
  1370. next_to_clean = 0;
  1371. atomic_set(&tpd_ring->next_to_clean, next_to_clean);
  1372. }
  1373. netdev_completed_queue(adapter->netdev, total_packets, total_bytes);
  1374. if (netif_queue_stopped(adapter->netdev) &&
  1375. netif_carrier_ok(adapter->netdev)) {
  1376. netif_wake_queue(adapter->netdev);
  1377. }
  1378. return true;
  1379. }
  1380. /**
  1381. * atl1c_intr - Interrupt Handler
  1382. * @irq: interrupt number
  1383. * @data: pointer to a network interface device structure
  1384. */
  1385. static irqreturn_t atl1c_intr(int irq, void *data)
  1386. {
  1387. struct net_device *netdev = data;
  1388. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1389. struct pci_dev *pdev = adapter->pdev;
  1390. struct atl1c_hw *hw = &adapter->hw;
  1391. int max_ints = AT_MAX_INT_WORK;
  1392. int handled = IRQ_NONE;
  1393. u32 status;
  1394. u32 reg_data;
  1395. do {
  1396. AT_READ_REG(hw, REG_ISR, &reg_data);
  1397. status = reg_data & hw->intr_mask;
  1398. if (status == 0 || (status & ISR_DIS_INT) != 0) {
  1399. if (max_ints != AT_MAX_INT_WORK)
  1400. handled = IRQ_HANDLED;
  1401. break;
  1402. }
  1403. /* link event */
  1404. if (status & ISR_GPHY)
  1405. atl1c_clear_phy_int(adapter);
  1406. /* Ack ISR */
  1407. AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
  1408. if (status & ISR_RX_PKT) {
  1409. if (likely(napi_schedule_prep(&adapter->napi))) {
  1410. hw->intr_mask &= ~ISR_RX_PKT;
  1411. AT_WRITE_REG(hw, REG_IMR, hw->intr_mask);
  1412. __napi_schedule(&adapter->napi);
  1413. }
  1414. }
  1415. if (status & ISR_TX_PKT)
  1416. atl1c_clean_tx_irq(adapter, atl1c_trans_normal);
  1417. handled = IRQ_HANDLED;
  1418. /* check if PCIE PHY Link down */
  1419. if (status & ISR_ERROR) {
  1420. if (netif_msg_hw(adapter))
  1421. dev_err(&pdev->dev,
  1422. "atl1c hardware error (status = 0x%x)\n",
  1423. status & ISR_ERROR);
  1424. /* reset MAC */
  1425. set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
  1426. schedule_work(&adapter->common_task);
  1427. return IRQ_HANDLED;
  1428. }
  1429. if (status & ISR_OVER)
  1430. if (netif_msg_intr(adapter))
  1431. dev_warn(&pdev->dev,
  1432. "TX/RX overflow (status = 0x%x)\n",
  1433. status & ISR_OVER);
  1434. /* link event */
  1435. if (status & (ISR_GPHY | ISR_MANUAL)) {
  1436. netdev->stats.tx_carrier_errors++;
  1437. atl1c_link_chg_event(adapter);
  1438. break;
  1439. }
  1440. } while (--max_ints > 0);
  1441. /* re-enable Interrupt*/
  1442. AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
  1443. return handled;
  1444. }
  1445. static inline void atl1c_rx_checksum(struct atl1c_adapter *adapter,
  1446. struct sk_buff *skb, struct atl1c_recv_ret_status *prrs)
  1447. {
  1448. /*
  1449. * The pid field in RRS in not correct sometimes, so we
  1450. * cannot figure out if the packet is fragmented or not,
  1451. * so we tell the KERNEL CHECKSUM_NONE
  1452. */
  1453. skb_checksum_none_assert(skb);
  1454. }
  1455. static struct sk_buff *atl1c_alloc_skb(struct atl1c_adapter *adapter)
  1456. {
  1457. struct sk_buff *skb;
  1458. struct page *page;
  1459. if (adapter->rx_frag_size > PAGE_SIZE)
  1460. return netdev_alloc_skb(adapter->netdev,
  1461. adapter->rx_buffer_len);
  1462. page = adapter->rx_page;
  1463. if (!page) {
  1464. adapter->rx_page = page = alloc_page(GFP_ATOMIC);
  1465. if (unlikely(!page))
  1466. return NULL;
  1467. adapter->rx_page_offset = 0;
  1468. }
  1469. skb = build_skb(page_address(page) + adapter->rx_page_offset,
  1470. adapter->rx_frag_size);
  1471. if (likely(skb)) {
  1472. adapter->rx_page_offset += adapter->rx_frag_size;
  1473. if (adapter->rx_page_offset >= PAGE_SIZE)
  1474. adapter->rx_page = NULL;
  1475. else
  1476. get_page(page);
  1477. }
  1478. return skb;
  1479. }
  1480. static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter)
  1481. {
  1482. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1483. struct pci_dev *pdev = adapter->pdev;
  1484. struct atl1c_buffer *buffer_info, *next_info;
  1485. struct sk_buff *skb;
  1486. void *vir_addr = NULL;
  1487. u16 num_alloc = 0;
  1488. u16 rfd_next_to_use, next_next;
  1489. struct atl1c_rx_free_desc *rfd_desc;
  1490. dma_addr_t mapping;
  1491. next_next = rfd_next_to_use = rfd_ring->next_to_use;
  1492. if (++next_next == rfd_ring->count)
  1493. next_next = 0;
  1494. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1495. next_info = &rfd_ring->buffer_info[next_next];
  1496. while (next_info->flags & ATL1C_BUFFER_FREE) {
  1497. rfd_desc = ATL1C_RFD_DESC(rfd_ring, rfd_next_to_use);
  1498. skb = atl1c_alloc_skb(adapter);
  1499. if (unlikely(!skb)) {
  1500. if (netif_msg_rx_err(adapter))
  1501. dev_warn(&pdev->dev, "alloc rx buffer failed\n");
  1502. break;
  1503. }
  1504. /*
  1505. * Make buffer alignment 2 beyond a 16 byte boundary
  1506. * this will result in a 16 byte aligned IP header after
  1507. * the 14 byte MAC header is removed
  1508. */
  1509. vir_addr = skb->data;
  1510. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1511. buffer_info->skb = skb;
  1512. buffer_info->length = adapter->rx_buffer_len;
  1513. mapping = pci_map_single(pdev, vir_addr,
  1514. buffer_info->length,
  1515. PCI_DMA_FROMDEVICE);
  1516. if (unlikely(pci_dma_mapping_error(pdev, mapping))) {
  1517. dev_kfree_skb(skb);
  1518. buffer_info->skb = NULL;
  1519. buffer_info->length = 0;
  1520. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  1521. netif_warn(adapter, rx_err, adapter->netdev, "RX pci_map_single failed");
  1522. break;
  1523. }
  1524. buffer_info->dma = mapping;
  1525. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1526. ATL1C_PCIMAP_FROMDEVICE);
  1527. rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
  1528. rfd_next_to_use = next_next;
  1529. if (++next_next == rfd_ring->count)
  1530. next_next = 0;
  1531. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1532. next_info = &rfd_ring->buffer_info[next_next];
  1533. num_alloc++;
  1534. }
  1535. if (num_alloc) {
  1536. /* TODO: update mailbox here */
  1537. wmb();
  1538. rfd_ring->next_to_use = rfd_next_to_use;
  1539. AT_WRITE_REG(&adapter->hw, REG_MB_RFD0_PROD_IDX,
  1540. rfd_ring->next_to_use & MB_RFDX_PROD_IDX_MASK);
  1541. }
  1542. return num_alloc;
  1543. }
  1544. static void atl1c_clean_rrd(struct atl1c_rrd_ring *rrd_ring,
  1545. struct atl1c_recv_ret_status *rrs, u16 num)
  1546. {
  1547. u16 i;
  1548. /* the relationship between rrd and rfd is one map one */
  1549. for (i = 0; i < num; i++, rrs = ATL1C_RRD_DESC(rrd_ring,
  1550. rrd_ring->next_to_clean)) {
  1551. rrs->word3 &= ~RRS_RXD_UPDATED;
  1552. if (++rrd_ring->next_to_clean == rrd_ring->count)
  1553. rrd_ring->next_to_clean = 0;
  1554. }
  1555. }
  1556. static void atl1c_clean_rfd(struct atl1c_rfd_ring *rfd_ring,
  1557. struct atl1c_recv_ret_status *rrs, u16 num)
  1558. {
  1559. u16 i;
  1560. u16 rfd_index;
  1561. struct atl1c_buffer *buffer_info = rfd_ring->buffer_info;
  1562. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1563. RRS_RX_RFD_INDEX_MASK;
  1564. for (i = 0; i < num; i++) {
  1565. buffer_info[rfd_index].skb = NULL;
  1566. ATL1C_SET_BUFFER_STATE(&buffer_info[rfd_index],
  1567. ATL1C_BUFFER_FREE);
  1568. if (++rfd_index == rfd_ring->count)
  1569. rfd_index = 0;
  1570. }
  1571. rfd_ring->next_to_clean = rfd_index;
  1572. }
  1573. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
  1574. int *work_done, int work_to_do)
  1575. {
  1576. u16 rfd_num, rfd_index;
  1577. u16 count = 0;
  1578. u16 length;
  1579. struct pci_dev *pdev = adapter->pdev;
  1580. struct net_device *netdev = adapter->netdev;
  1581. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1582. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  1583. struct sk_buff *skb;
  1584. struct atl1c_recv_ret_status *rrs;
  1585. struct atl1c_buffer *buffer_info;
  1586. while (1) {
  1587. if (*work_done >= work_to_do)
  1588. break;
  1589. rrs = ATL1C_RRD_DESC(rrd_ring, rrd_ring->next_to_clean);
  1590. if (likely(RRS_RXD_IS_VALID(rrs->word3))) {
  1591. rfd_num = (rrs->word0 >> RRS_RX_RFD_CNT_SHIFT) &
  1592. RRS_RX_RFD_CNT_MASK;
  1593. if (unlikely(rfd_num != 1))
  1594. /* TODO support mul rfd*/
  1595. if (netif_msg_rx_err(adapter))
  1596. dev_warn(&pdev->dev,
  1597. "Multi rfd not support yet!\n");
  1598. goto rrs_checked;
  1599. } else {
  1600. break;
  1601. }
  1602. rrs_checked:
  1603. atl1c_clean_rrd(rrd_ring, rrs, rfd_num);
  1604. if (rrs->word3 & (RRS_RX_ERR_SUM | RRS_802_3_LEN_ERR)) {
  1605. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1606. if (netif_msg_rx_err(adapter))
  1607. dev_warn(&pdev->dev,
  1608. "wrong packet! rrs word3 is %x\n",
  1609. rrs->word3);
  1610. continue;
  1611. }
  1612. length = le16_to_cpu((rrs->word3 >> RRS_PKT_SIZE_SHIFT) &
  1613. RRS_PKT_SIZE_MASK);
  1614. /* Good Receive */
  1615. if (likely(rfd_num == 1)) {
  1616. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1617. RRS_RX_RFD_INDEX_MASK;
  1618. buffer_info = &rfd_ring->buffer_info[rfd_index];
  1619. pci_unmap_single(pdev, buffer_info->dma,
  1620. buffer_info->length, PCI_DMA_FROMDEVICE);
  1621. skb = buffer_info->skb;
  1622. } else {
  1623. /* TODO */
  1624. if (netif_msg_rx_err(adapter))
  1625. dev_warn(&pdev->dev,
  1626. "Multi rfd not support yet!\n");
  1627. break;
  1628. }
  1629. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1630. skb_put(skb, length - ETH_FCS_LEN);
  1631. skb->protocol = eth_type_trans(skb, netdev);
  1632. atl1c_rx_checksum(adapter, skb, rrs);
  1633. if (rrs->word3 & RRS_VLAN_INS) {
  1634. u16 vlan;
  1635. AT_TAG_TO_VLAN(rrs->vlan_tag, vlan);
  1636. vlan = le16_to_cpu(vlan);
  1637. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan);
  1638. }
  1639. netif_receive_skb(skb);
  1640. (*work_done)++;
  1641. count++;
  1642. }
  1643. if (count)
  1644. atl1c_alloc_rx_buffer(adapter);
  1645. }
  1646. /**
  1647. * atl1c_clean - NAPI Rx polling callback
  1648. */
  1649. static int atl1c_clean(struct napi_struct *napi, int budget)
  1650. {
  1651. struct atl1c_adapter *adapter =
  1652. container_of(napi, struct atl1c_adapter, napi);
  1653. int work_done = 0;
  1654. /* Keep link state information with original netdev */
  1655. if (!netif_carrier_ok(adapter->netdev))
  1656. goto quit_polling;
  1657. /* just enable one RXQ */
  1658. atl1c_clean_rx_irq(adapter, &work_done, budget);
  1659. if (work_done < budget) {
  1660. quit_polling:
  1661. napi_complete(napi);
  1662. adapter->hw.intr_mask |= ISR_RX_PKT;
  1663. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  1664. }
  1665. return work_done;
  1666. }
  1667. #ifdef CONFIG_NET_POLL_CONTROLLER
  1668. /*
  1669. * Polling 'interrupt' - used by things like netconsole to send skbs
  1670. * without having to re-enable interrupts. It's not called while
  1671. * the interrupt routine is executing.
  1672. */
  1673. static void atl1c_netpoll(struct net_device *netdev)
  1674. {
  1675. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1676. disable_irq(adapter->pdev->irq);
  1677. atl1c_intr(adapter->pdev->irq, netdev);
  1678. enable_irq(adapter->pdev->irq);
  1679. }
  1680. #endif
  1681. static inline u16 atl1c_tpd_avail(struct atl1c_adapter *adapter, enum atl1c_trans_queue type)
  1682. {
  1683. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1684. u16 next_to_use = 0;
  1685. u16 next_to_clean = 0;
  1686. next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1687. next_to_use = tpd_ring->next_to_use;
  1688. return (u16)(next_to_clean > next_to_use) ?
  1689. (next_to_clean - next_to_use - 1) :
  1690. (tpd_ring->count + next_to_clean - next_to_use - 1);
  1691. }
  1692. /*
  1693. * get next usable tpd
  1694. * Note: should call atl1c_tdp_avail to make sure
  1695. * there is enough tpd to use
  1696. */
  1697. static struct atl1c_tpd_desc *atl1c_get_tpd(struct atl1c_adapter *adapter,
  1698. enum atl1c_trans_queue type)
  1699. {
  1700. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1701. struct atl1c_tpd_desc *tpd_desc;
  1702. u16 next_to_use = 0;
  1703. next_to_use = tpd_ring->next_to_use;
  1704. if (++tpd_ring->next_to_use == tpd_ring->count)
  1705. tpd_ring->next_to_use = 0;
  1706. tpd_desc = ATL1C_TPD_DESC(tpd_ring, next_to_use);
  1707. memset(tpd_desc, 0, sizeof(struct atl1c_tpd_desc));
  1708. return tpd_desc;
  1709. }
  1710. static struct atl1c_buffer *
  1711. atl1c_get_tx_buffer(struct atl1c_adapter *adapter, struct atl1c_tpd_desc *tpd)
  1712. {
  1713. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  1714. return &tpd_ring->buffer_info[tpd -
  1715. (struct atl1c_tpd_desc *)tpd_ring->desc];
  1716. }
  1717. /* Calculate the transmit packet descript needed*/
  1718. static u16 atl1c_cal_tpd_req(const struct sk_buff *skb)
  1719. {
  1720. u16 tpd_req;
  1721. u16 proto_hdr_len = 0;
  1722. tpd_req = skb_shinfo(skb)->nr_frags + 1;
  1723. if (skb_is_gso(skb)) {
  1724. proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1725. if (proto_hdr_len < skb_headlen(skb))
  1726. tpd_req++;
  1727. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
  1728. tpd_req++;
  1729. }
  1730. return tpd_req;
  1731. }
  1732. static int atl1c_tso_csum(struct atl1c_adapter *adapter,
  1733. struct sk_buff *skb,
  1734. struct atl1c_tpd_desc **tpd,
  1735. enum atl1c_trans_queue type)
  1736. {
  1737. struct pci_dev *pdev = adapter->pdev;
  1738. unsigned short offload_type;
  1739. u8 hdr_len;
  1740. u32 real_len;
  1741. if (skb_is_gso(skb)) {
  1742. int err;
  1743. err = skb_cow_head(skb, 0);
  1744. if (err < 0)
  1745. return err;
  1746. offload_type = skb_shinfo(skb)->gso_type;
  1747. if (offload_type & SKB_GSO_TCPV4) {
  1748. real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
  1749. + ntohs(ip_hdr(skb)->tot_len));
  1750. if (real_len < skb->len)
  1751. pskb_trim(skb, real_len);
  1752. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1753. if (unlikely(skb->len == hdr_len)) {
  1754. /* only xsum need */
  1755. if (netif_msg_tx_queued(adapter))
  1756. dev_warn(&pdev->dev,
  1757. "IPV4 tso with zero data??\n");
  1758. goto check_sum;
  1759. } else {
  1760. ip_hdr(skb)->check = 0;
  1761. tcp_hdr(skb)->check = ~csum_tcpudp_magic(
  1762. ip_hdr(skb)->saddr,
  1763. ip_hdr(skb)->daddr,
  1764. 0, IPPROTO_TCP, 0);
  1765. (*tpd)->word1 |= 1 << TPD_IPV4_PACKET_SHIFT;
  1766. }
  1767. }
  1768. if (offload_type & SKB_GSO_TCPV6) {
  1769. struct atl1c_tpd_ext_desc *etpd =
  1770. *(struct atl1c_tpd_ext_desc **)(tpd);
  1771. memset(etpd, 0, sizeof(struct atl1c_tpd_ext_desc));
  1772. *tpd = atl1c_get_tpd(adapter, type);
  1773. ipv6_hdr(skb)->payload_len = 0;
  1774. /* check payload == 0 byte ? */
  1775. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1776. if (unlikely(skb->len == hdr_len)) {
  1777. /* only xsum need */
  1778. if (netif_msg_tx_queued(adapter))
  1779. dev_warn(&pdev->dev,
  1780. "IPV6 tso with zero data??\n");
  1781. goto check_sum;
  1782. } else
  1783. tcp_hdr(skb)->check = ~csum_ipv6_magic(
  1784. &ipv6_hdr(skb)->saddr,
  1785. &ipv6_hdr(skb)->daddr,
  1786. 0, IPPROTO_TCP, 0);
  1787. etpd->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1788. etpd->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1789. etpd->pkt_len = cpu_to_le32(skb->len);
  1790. (*tpd)->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1791. }
  1792. (*tpd)->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1793. (*tpd)->word1 |= (skb_transport_offset(skb) & TPD_TCPHDR_OFFSET_MASK) <<
  1794. TPD_TCPHDR_OFFSET_SHIFT;
  1795. (*tpd)->word1 |= (skb_shinfo(skb)->gso_size & TPD_MSS_MASK) <<
  1796. TPD_MSS_SHIFT;
  1797. return 0;
  1798. }
  1799. check_sum:
  1800. if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
  1801. u8 css, cso;
  1802. cso = skb_checksum_start_offset(skb);
  1803. if (unlikely(cso & 0x1)) {
  1804. if (netif_msg_tx_err(adapter))
  1805. dev_err(&adapter->pdev->dev,
  1806. "payload offset should not an event number\n");
  1807. return -1;
  1808. } else {
  1809. css = cso + skb->csum_offset;
  1810. (*tpd)->word1 |= ((cso >> 1) & TPD_PLOADOFFSET_MASK) <<
  1811. TPD_PLOADOFFSET_SHIFT;
  1812. (*tpd)->word1 |= ((css >> 1) & TPD_CCSUM_OFFSET_MASK) <<
  1813. TPD_CCSUM_OFFSET_SHIFT;
  1814. (*tpd)->word1 |= 1 << TPD_CCSUM_EN_SHIFT;
  1815. }
  1816. }
  1817. return 0;
  1818. }
  1819. static void atl1c_tx_rollback(struct atl1c_adapter *adpt,
  1820. struct atl1c_tpd_desc *first_tpd,
  1821. enum atl1c_trans_queue type)
  1822. {
  1823. struct atl1c_tpd_ring *tpd_ring = &adpt->tpd_ring[type];
  1824. struct atl1c_buffer *buffer_info;
  1825. struct atl1c_tpd_desc *tpd;
  1826. u16 first_index, index;
  1827. first_index = first_tpd - (struct atl1c_tpd_desc *)tpd_ring->desc;
  1828. index = first_index;
  1829. while (index != tpd_ring->next_to_use) {
  1830. tpd = ATL1C_TPD_DESC(tpd_ring, index);
  1831. buffer_info = &tpd_ring->buffer_info[index];
  1832. atl1c_clean_buffer(adpt->pdev, buffer_info);
  1833. memset(tpd, 0, sizeof(struct atl1c_tpd_desc));
  1834. if (++index == tpd_ring->count)
  1835. index = 0;
  1836. }
  1837. tpd_ring->next_to_use = first_index;
  1838. }
  1839. static int atl1c_tx_map(struct atl1c_adapter *adapter,
  1840. struct sk_buff *skb, struct atl1c_tpd_desc *tpd,
  1841. enum atl1c_trans_queue type)
  1842. {
  1843. struct atl1c_tpd_desc *use_tpd = NULL;
  1844. struct atl1c_buffer *buffer_info = NULL;
  1845. u16 buf_len = skb_headlen(skb);
  1846. u16 map_len = 0;
  1847. u16 mapped_len = 0;
  1848. u16 hdr_len = 0;
  1849. u16 nr_frags;
  1850. u16 f;
  1851. int tso;
  1852. nr_frags = skb_shinfo(skb)->nr_frags;
  1853. tso = (tpd->word1 >> TPD_LSO_EN_SHIFT) & TPD_LSO_EN_MASK;
  1854. if (tso) {
  1855. /* TSO */
  1856. map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1857. use_tpd = tpd;
  1858. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1859. buffer_info->length = map_len;
  1860. buffer_info->dma = pci_map_single(adapter->pdev,
  1861. skb->data, hdr_len, PCI_DMA_TODEVICE);
  1862. if (unlikely(pci_dma_mapping_error(adapter->pdev,
  1863. buffer_info->dma)))
  1864. goto err_dma;
  1865. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1866. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1867. ATL1C_PCIMAP_TODEVICE);
  1868. mapped_len += map_len;
  1869. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1870. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1871. }
  1872. if (mapped_len < buf_len) {
  1873. /* mapped_len == 0, means we should use the first tpd,
  1874. which is given by caller */
  1875. if (mapped_len == 0)
  1876. use_tpd = tpd;
  1877. else {
  1878. use_tpd = atl1c_get_tpd(adapter, type);
  1879. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1880. }
  1881. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1882. buffer_info->length = buf_len - mapped_len;
  1883. buffer_info->dma =
  1884. pci_map_single(adapter->pdev, skb->data + mapped_len,
  1885. buffer_info->length, PCI_DMA_TODEVICE);
  1886. if (unlikely(pci_dma_mapping_error(adapter->pdev,
  1887. buffer_info->dma)))
  1888. goto err_dma;
  1889. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1890. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1891. ATL1C_PCIMAP_TODEVICE);
  1892. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1893. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1894. }
  1895. for (f = 0; f < nr_frags; f++) {
  1896. struct skb_frag_struct *frag;
  1897. frag = &skb_shinfo(skb)->frags[f];
  1898. use_tpd = atl1c_get_tpd(adapter, type);
  1899. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1900. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1901. buffer_info->length = skb_frag_size(frag);
  1902. buffer_info->dma = skb_frag_dma_map(&adapter->pdev->dev,
  1903. frag, 0,
  1904. buffer_info->length,
  1905. DMA_TO_DEVICE);
  1906. if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma))
  1907. goto err_dma;
  1908. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1909. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_PAGE,
  1910. ATL1C_PCIMAP_TODEVICE);
  1911. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1912. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1913. }
  1914. /* The last tpd */
  1915. use_tpd->word1 |= 1 << TPD_EOP_SHIFT;
  1916. /* The last buffer info contain the skb address,
  1917. so it will be free after unmap */
  1918. buffer_info->skb = skb;
  1919. return 0;
  1920. err_dma:
  1921. buffer_info->dma = 0;
  1922. buffer_info->length = 0;
  1923. return -1;
  1924. }
  1925. static void atl1c_tx_queue(struct atl1c_adapter *adapter, struct sk_buff *skb,
  1926. struct atl1c_tpd_desc *tpd, enum atl1c_trans_queue type)
  1927. {
  1928. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1929. u16 reg;
  1930. reg = type == atl1c_trans_high ? REG_TPD_PRI1_PIDX : REG_TPD_PRI0_PIDX;
  1931. AT_WRITE_REGW(&adapter->hw, reg, tpd_ring->next_to_use);
  1932. }
  1933. static netdev_tx_t atl1c_xmit_frame(struct sk_buff *skb,
  1934. struct net_device *netdev)
  1935. {
  1936. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1937. u16 tpd_req = 1;
  1938. struct atl1c_tpd_desc *tpd;
  1939. enum atl1c_trans_queue type = atl1c_trans_normal;
  1940. if (test_bit(__AT_DOWN, &adapter->flags)) {
  1941. dev_kfree_skb_any(skb);
  1942. return NETDEV_TX_OK;
  1943. }
  1944. tpd_req = atl1c_cal_tpd_req(skb);
  1945. if (atl1c_tpd_avail(adapter, type) < tpd_req) {
  1946. /* no enough descriptor, just stop queue */
  1947. netif_stop_queue(netdev);
  1948. return NETDEV_TX_BUSY;
  1949. }
  1950. tpd = atl1c_get_tpd(adapter, type);
  1951. /* do TSO and check sum */
  1952. if (atl1c_tso_csum(adapter, skb, &tpd, type) != 0) {
  1953. dev_kfree_skb_any(skb);
  1954. return NETDEV_TX_OK;
  1955. }
  1956. if (unlikely(skb_vlan_tag_present(skb))) {
  1957. u16 vlan = skb_vlan_tag_get(skb);
  1958. __le16 tag;
  1959. vlan = cpu_to_le16(vlan);
  1960. AT_VLAN_TO_TAG(vlan, tag);
  1961. tpd->word1 |= 1 << TPD_INS_VTAG_SHIFT;
  1962. tpd->vlan_tag = tag;
  1963. }
  1964. if (skb_network_offset(skb) != ETH_HLEN)
  1965. tpd->word1 |= 1 << TPD_ETH_TYPE_SHIFT; /* Ethernet frame */
  1966. if (atl1c_tx_map(adapter, skb, tpd, type) < 0) {
  1967. netif_info(adapter, tx_done, adapter->netdev,
  1968. "tx-skb droppted due to dma error\n");
  1969. /* roll back tpd/buffer */
  1970. atl1c_tx_rollback(adapter, tpd, type);
  1971. dev_kfree_skb_any(skb);
  1972. } else {
  1973. netdev_sent_queue(adapter->netdev, skb->len);
  1974. atl1c_tx_queue(adapter, skb, tpd, type);
  1975. }
  1976. return NETDEV_TX_OK;
  1977. }
  1978. static void atl1c_free_irq(struct atl1c_adapter *adapter)
  1979. {
  1980. struct net_device *netdev = adapter->netdev;
  1981. free_irq(adapter->pdev->irq, netdev);
  1982. if (adapter->have_msi)
  1983. pci_disable_msi(adapter->pdev);
  1984. }
  1985. static int atl1c_request_irq(struct atl1c_adapter *adapter)
  1986. {
  1987. struct pci_dev *pdev = adapter->pdev;
  1988. struct net_device *netdev = adapter->netdev;
  1989. int flags = 0;
  1990. int err = 0;
  1991. adapter->have_msi = true;
  1992. err = pci_enable_msi(adapter->pdev);
  1993. if (err) {
  1994. if (netif_msg_ifup(adapter))
  1995. dev_err(&pdev->dev,
  1996. "Unable to allocate MSI interrupt Error: %d\n",
  1997. err);
  1998. adapter->have_msi = false;
  1999. }
  2000. if (!adapter->have_msi)
  2001. flags |= IRQF_SHARED;
  2002. err = request_irq(adapter->pdev->irq, atl1c_intr, flags,
  2003. netdev->name, netdev);
  2004. if (err) {
  2005. if (netif_msg_ifup(adapter))
  2006. dev_err(&pdev->dev,
  2007. "Unable to allocate interrupt Error: %d\n",
  2008. err);
  2009. if (adapter->have_msi)
  2010. pci_disable_msi(adapter->pdev);
  2011. return err;
  2012. }
  2013. if (netif_msg_ifup(adapter))
  2014. dev_dbg(&pdev->dev, "atl1c_request_irq OK\n");
  2015. return err;
  2016. }
  2017. static void atl1c_reset_dma_ring(struct atl1c_adapter *adapter)
  2018. {
  2019. /* release tx-pending skbs and reset tx/rx ring index */
  2020. atl1c_clean_tx_ring(adapter, atl1c_trans_normal);
  2021. atl1c_clean_tx_ring(adapter, atl1c_trans_high);
  2022. atl1c_clean_rx_ring(adapter);
  2023. }
  2024. static int atl1c_up(struct atl1c_adapter *adapter)
  2025. {
  2026. struct net_device *netdev = adapter->netdev;
  2027. int err;
  2028. netif_carrier_off(netdev);
  2029. err = atl1c_configure(adapter);
  2030. if (unlikely(err))
  2031. goto err_up;
  2032. err = atl1c_request_irq(adapter);
  2033. if (unlikely(err))
  2034. goto err_up;
  2035. atl1c_check_link_status(adapter);
  2036. clear_bit(__AT_DOWN, &adapter->flags);
  2037. napi_enable(&adapter->napi);
  2038. atl1c_irq_enable(adapter);
  2039. netif_start_queue(netdev);
  2040. return err;
  2041. err_up:
  2042. atl1c_clean_rx_ring(adapter);
  2043. return err;
  2044. }
  2045. static void atl1c_down(struct atl1c_adapter *adapter)
  2046. {
  2047. struct net_device *netdev = adapter->netdev;
  2048. atl1c_del_timer(adapter);
  2049. adapter->work_event = 0; /* clear all event */
  2050. /* signal that we're down so the interrupt handler does not
  2051. * reschedule our watchdog timer */
  2052. set_bit(__AT_DOWN, &adapter->flags);
  2053. netif_carrier_off(netdev);
  2054. napi_disable(&adapter->napi);
  2055. atl1c_irq_disable(adapter);
  2056. atl1c_free_irq(adapter);
  2057. /* disable ASPM if device inactive */
  2058. atl1c_disable_l0s_l1(&adapter->hw);
  2059. /* reset MAC to disable all RX/TX */
  2060. atl1c_reset_mac(&adapter->hw);
  2061. msleep(1);
  2062. adapter->link_speed = SPEED_0;
  2063. adapter->link_duplex = -1;
  2064. atl1c_reset_dma_ring(adapter);
  2065. }
  2066. /**
  2067. * atl1c_open - Called when a network interface is made active
  2068. * @netdev: network interface device structure
  2069. *
  2070. * Returns 0 on success, negative value on failure
  2071. *
  2072. * The open entry point is called when a network interface is made
  2073. * active by the system (IFF_UP). At this point all resources needed
  2074. * for transmit and receive operations are allocated, the interrupt
  2075. * handler is registered with the OS, the watchdog timer is started,
  2076. * and the stack is notified that the interface is ready.
  2077. */
  2078. static int atl1c_open(struct net_device *netdev)
  2079. {
  2080. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2081. int err;
  2082. /* disallow open during test */
  2083. if (test_bit(__AT_TESTING, &adapter->flags))
  2084. return -EBUSY;
  2085. /* allocate rx/tx dma buffer & descriptors */
  2086. err = atl1c_setup_ring_resources(adapter);
  2087. if (unlikely(err))
  2088. return err;
  2089. err = atl1c_up(adapter);
  2090. if (unlikely(err))
  2091. goto err_up;
  2092. return 0;
  2093. err_up:
  2094. atl1c_free_irq(adapter);
  2095. atl1c_free_ring_resources(adapter);
  2096. atl1c_reset_mac(&adapter->hw);
  2097. return err;
  2098. }
  2099. /**
  2100. * atl1c_close - Disables a network interface
  2101. * @netdev: network interface device structure
  2102. *
  2103. * Returns 0, this is not allowed to fail
  2104. *
  2105. * The close entry point is called when an interface is de-activated
  2106. * by the OS. The hardware is still under the drivers control, but
  2107. * needs to be disabled. A global MAC reset is issued to stop the
  2108. * hardware, and all transmit and receive resources are freed.
  2109. */
  2110. static int atl1c_close(struct net_device *netdev)
  2111. {
  2112. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2113. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  2114. set_bit(__AT_DOWN, &adapter->flags);
  2115. cancel_work_sync(&adapter->common_task);
  2116. atl1c_down(adapter);
  2117. atl1c_free_ring_resources(adapter);
  2118. return 0;
  2119. }
  2120. static int atl1c_suspend(struct device *dev)
  2121. {
  2122. struct pci_dev *pdev = to_pci_dev(dev);
  2123. struct net_device *netdev = pci_get_drvdata(pdev);
  2124. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2125. struct atl1c_hw *hw = &adapter->hw;
  2126. u32 wufc = adapter->wol;
  2127. atl1c_disable_l0s_l1(hw);
  2128. if (netif_running(netdev)) {
  2129. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  2130. atl1c_down(adapter);
  2131. }
  2132. netif_device_detach(netdev);
  2133. if (wufc)
  2134. if (atl1c_phy_to_ps_link(hw) != 0)
  2135. dev_dbg(&pdev->dev, "phy power saving failed");
  2136. atl1c_power_saving(hw, wufc);
  2137. return 0;
  2138. }
  2139. #ifdef CONFIG_PM_SLEEP
  2140. static int atl1c_resume(struct device *dev)
  2141. {
  2142. struct pci_dev *pdev = to_pci_dev(dev);
  2143. struct net_device *netdev = pci_get_drvdata(pdev);
  2144. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2145. AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
  2146. atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
  2147. atl1c_phy_reset(&adapter->hw);
  2148. atl1c_reset_mac(&adapter->hw);
  2149. atl1c_phy_init(&adapter->hw);
  2150. #if 0
  2151. AT_READ_REG(&adapter->hw, REG_PM_CTRLSTAT, &pm_data);
  2152. pm_data &= ~PM_CTRLSTAT_PME_EN;
  2153. AT_WRITE_REG(&adapter->hw, REG_PM_CTRLSTAT, pm_data);
  2154. #endif
  2155. netif_device_attach(netdev);
  2156. if (netif_running(netdev))
  2157. atl1c_up(adapter);
  2158. return 0;
  2159. }
  2160. #endif
  2161. static void atl1c_shutdown(struct pci_dev *pdev)
  2162. {
  2163. struct net_device *netdev = pci_get_drvdata(pdev);
  2164. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2165. atl1c_suspend(&pdev->dev);
  2166. pci_wake_from_d3(pdev, adapter->wol);
  2167. pci_set_power_state(pdev, PCI_D3hot);
  2168. }
  2169. static const struct net_device_ops atl1c_netdev_ops = {
  2170. .ndo_open = atl1c_open,
  2171. .ndo_stop = atl1c_close,
  2172. .ndo_validate_addr = eth_validate_addr,
  2173. .ndo_start_xmit = atl1c_xmit_frame,
  2174. .ndo_set_mac_address = atl1c_set_mac_addr,
  2175. .ndo_set_rx_mode = atl1c_set_multi,
  2176. .ndo_change_mtu = atl1c_change_mtu,
  2177. .ndo_fix_features = atl1c_fix_features,
  2178. .ndo_set_features = atl1c_set_features,
  2179. .ndo_do_ioctl = atl1c_ioctl,
  2180. .ndo_tx_timeout = atl1c_tx_timeout,
  2181. .ndo_get_stats = atl1c_get_stats,
  2182. #ifdef CONFIG_NET_POLL_CONTROLLER
  2183. .ndo_poll_controller = atl1c_netpoll,
  2184. #endif
  2185. };
  2186. static int atl1c_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
  2187. {
  2188. SET_NETDEV_DEV(netdev, &pdev->dev);
  2189. pci_set_drvdata(pdev, netdev);
  2190. netdev->netdev_ops = &atl1c_netdev_ops;
  2191. netdev->watchdog_timeo = AT_TX_WATCHDOG;
  2192. netdev->min_mtu = ETH_ZLEN - (ETH_HLEN + VLAN_HLEN);
  2193. atl1c_set_ethtool_ops(netdev);
  2194. /* TODO: add when ready */
  2195. netdev->hw_features = NETIF_F_SG |
  2196. NETIF_F_HW_CSUM |
  2197. NETIF_F_HW_VLAN_CTAG_RX |
  2198. NETIF_F_TSO |
  2199. NETIF_F_TSO6;
  2200. netdev->features = netdev->hw_features |
  2201. NETIF_F_HW_VLAN_CTAG_TX;
  2202. return 0;
  2203. }
  2204. /**
  2205. * atl1c_probe - Device Initialization Routine
  2206. * @pdev: PCI device information struct
  2207. * @ent: entry in atl1c_pci_tbl
  2208. *
  2209. * Returns 0 on success, negative on failure
  2210. *
  2211. * atl1c_probe initializes an adapter identified by a pci_dev structure.
  2212. * The OS initialization, configuring of the adapter private structure,
  2213. * and a hardware reset occur.
  2214. */
  2215. static int atl1c_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2216. {
  2217. struct net_device *netdev;
  2218. struct atl1c_adapter *adapter;
  2219. static int cards_found;
  2220. int err = 0;
  2221. /* enable device (incl. PCI PM wakeup and hotplug setup) */
  2222. err = pci_enable_device_mem(pdev);
  2223. if (err) {
  2224. dev_err(&pdev->dev, "cannot enable PCI device\n");
  2225. return err;
  2226. }
  2227. /*
  2228. * The atl1c chip can DMA to 64-bit addresses, but it uses a single
  2229. * shared register for the high 32 bits, so only a single, aligned,
  2230. * 4 GB physical address range can be used at a time.
  2231. *
  2232. * Supporting 64-bit DMA on this hardware is more trouble than it's
  2233. * worth. It is far easier to limit to 32-bit DMA than update
  2234. * various kernel subsystems to support the mechanics required by a
  2235. * fixed-high-32-bit system.
  2236. */
  2237. if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
  2238. (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
  2239. dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
  2240. goto err_dma;
  2241. }
  2242. err = pci_request_regions(pdev, atl1c_driver_name);
  2243. if (err) {
  2244. dev_err(&pdev->dev, "cannot obtain PCI resources\n");
  2245. goto err_pci_reg;
  2246. }
  2247. pci_set_master(pdev);
  2248. netdev = alloc_etherdev(sizeof(struct atl1c_adapter));
  2249. if (netdev == NULL) {
  2250. err = -ENOMEM;
  2251. goto err_alloc_etherdev;
  2252. }
  2253. err = atl1c_init_netdev(netdev, pdev);
  2254. if (err) {
  2255. dev_err(&pdev->dev, "init netdevice failed\n");
  2256. goto err_init_netdev;
  2257. }
  2258. adapter = netdev_priv(netdev);
  2259. adapter->bd_number = cards_found;
  2260. adapter->netdev = netdev;
  2261. adapter->pdev = pdev;
  2262. adapter->hw.adapter = adapter;
  2263. adapter->msg_enable = netif_msg_init(-1, atl1c_default_msg);
  2264. adapter->hw.hw_addr = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  2265. if (!adapter->hw.hw_addr) {
  2266. err = -EIO;
  2267. dev_err(&pdev->dev, "cannot map device registers\n");
  2268. goto err_ioremap;
  2269. }
  2270. /* init mii data */
  2271. adapter->mii.dev = netdev;
  2272. adapter->mii.mdio_read = atl1c_mdio_read;
  2273. adapter->mii.mdio_write = atl1c_mdio_write;
  2274. adapter->mii.phy_id_mask = 0x1f;
  2275. adapter->mii.reg_num_mask = MDIO_CTRL_REG_MASK;
  2276. netif_napi_add(netdev, &adapter->napi, atl1c_clean, 64);
  2277. setup_timer(&adapter->phy_config_timer, atl1c_phy_config,
  2278. (unsigned long)adapter);
  2279. /* setup the private structure */
  2280. err = atl1c_sw_init(adapter);
  2281. if (err) {
  2282. dev_err(&pdev->dev, "net device private data init failed\n");
  2283. goto err_sw_init;
  2284. }
  2285. /* set max MTU */
  2286. atl1c_set_max_mtu(netdev);
  2287. atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
  2288. /* Init GPHY as early as possible due to power saving issue */
  2289. atl1c_phy_reset(&adapter->hw);
  2290. err = atl1c_reset_mac(&adapter->hw);
  2291. if (err) {
  2292. err = -EIO;
  2293. goto err_reset;
  2294. }
  2295. /* reset the controller to
  2296. * put the device in a known good starting state */
  2297. err = atl1c_phy_init(&adapter->hw);
  2298. if (err) {
  2299. err = -EIO;
  2300. goto err_reset;
  2301. }
  2302. if (atl1c_read_mac_addr(&adapter->hw)) {
  2303. /* got a random MAC address, set NET_ADDR_RANDOM to netdev */
  2304. netdev->addr_assign_type = NET_ADDR_RANDOM;
  2305. }
  2306. memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
  2307. if (netif_msg_probe(adapter))
  2308. dev_dbg(&pdev->dev, "mac address : %pM\n",
  2309. adapter->hw.mac_addr);
  2310. atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.mac_addr);
  2311. INIT_WORK(&adapter->common_task, atl1c_common_task);
  2312. adapter->work_event = 0;
  2313. err = register_netdev(netdev);
  2314. if (err) {
  2315. dev_err(&pdev->dev, "register netdevice failed\n");
  2316. goto err_register;
  2317. }
  2318. if (netif_msg_probe(adapter))
  2319. dev_info(&pdev->dev, "version %s\n", ATL1C_DRV_VERSION);
  2320. cards_found++;
  2321. return 0;
  2322. err_reset:
  2323. err_register:
  2324. err_sw_init:
  2325. iounmap(adapter->hw.hw_addr);
  2326. err_init_netdev:
  2327. err_ioremap:
  2328. free_netdev(netdev);
  2329. err_alloc_etherdev:
  2330. pci_release_regions(pdev);
  2331. err_pci_reg:
  2332. err_dma:
  2333. pci_disable_device(pdev);
  2334. return err;
  2335. }
  2336. /**
  2337. * atl1c_remove - Device Removal Routine
  2338. * @pdev: PCI device information struct
  2339. *
  2340. * atl1c_remove is called by the PCI subsystem to alert the driver
  2341. * that it should release a PCI device. The could be caused by a
  2342. * Hot-Plug event, or because the driver is going to be removed from
  2343. * memory.
  2344. */
  2345. static void atl1c_remove(struct pci_dev *pdev)
  2346. {
  2347. struct net_device *netdev = pci_get_drvdata(pdev);
  2348. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2349. unregister_netdev(netdev);
  2350. /* restore permanent address */
  2351. atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.perm_mac_addr);
  2352. atl1c_phy_disable(&adapter->hw);
  2353. iounmap(adapter->hw.hw_addr);
  2354. pci_release_regions(pdev);
  2355. pci_disable_device(pdev);
  2356. free_netdev(netdev);
  2357. }
  2358. /**
  2359. * atl1c_io_error_detected - called when PCI error is detected
  2360. * @pdev: Pointer to PCI device
  2361. * @state: The current pci connection state
  2362. *
  2363. * This function is called after a PCI bus error affecting
  2364. * this device has been detected.
  2365. */
  2366. static pci_ers_result_t atl1c_io_error_detected(struct pci_dev *pdev,
  2367. pci_channel_state_t state)
  2368. {
  2369. struct net_device *netdev = pci_get_drvdata(pdev);
  2370. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2371. netif_device_detach(netdev);
  2372. if (state == pci_channel_io_perm_failure)
  2373. return PCI_ERS_RESULT_DISCONNECT;
  2374. if (netif_running(netdev))
  2375. atl1c_down(adapter);
  2376. pci_disable_device(pdev);
  2377. /* Request a slot slot reset. */
  2378. return PCI_ERS_RESULT_NEED_RESET;
  2379. }
  2380. /**
  2381. * atl1c_io_slot_reset - called after the pci bus has been reset.
  2382. * @pdev: Pointer to PCI device
  2383. *
  2384. * Restart the card from scratch, as if from a cold-boot. Implementation
  2385. * resembles the first-half of the e1000_resume routine.
  2386. */
  2387. static pci_ers_result_t atl1c_io_slot_reset(struct pci_dev *pdev)
  2388. {
  2389. struct net_device *netdev = pci_get_drvdata(pdev);
  2390. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2391. if (pci_enable_device(pdev)) {
  2392. if (netif_msg_hw(adapter))
  2393. dev_err(&pdev->dev,
  2394. "Cannot re-enable PCI device after reset\n");
  2395. return PCI_ERS_RESULT_DISCONNECT;
  2396. }
  2397. pci_set_master(pdev);
  2398. pci_enable_wake(pdev, PCI_D3hot, 0);
  2399. pci_enable_wake(pdev, PCI_D3cold, 0);
  2400. atl1c_reset_mac(&adapter->hw);
  2401. return PCI_ERS_RESULT_RECOVERED;
  2402. }
  2403. /**
  2404. * atl1c_io_resume - called when traffic can start flowing again.
  2405. * @pdev: Pointer to PCI device
  2406. *
  2407. * This callback is called when the error recovery driver tells us that
  2408. * its OK to resume normal operation. Implementation resembles the
  2409. * second-half of the atl1c_resume routine.
  2410. */
  2411. static void atl1c_io_resume(struct pci_dev *pdev)
  2412. {
  2413. struct net_device *netdev = pci_get_drvdata(pdev);
  2414. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2415. if (netif_running(netdev)) {
  2416. if (atl1c_up(adapter)) {
  2417. if (netif_msg_hw(adapter))
  2418. dev_err(&pdev->dev,
  2419. "Cannot bring device back up after reset\n");
  2420. return;
  2421. }
  2422. }
  2423. netif_device_attach(netdev);
  2424. }
  2425. static const struct pci_error_handlers atl1c_err_handler = {
  2426. .error_detected = atl1c_io_error_detected,
  2427. .slot_reset = atl1c_io_slot_reset,
  2428. .resume = atl1c_io_resume,
  2429. };
  2430. static SIMPLE_DEV_PM_OPS(atl1c_pm_ops, atl1c_suspend, atl1c_resume);
  2431. static struct pci_driver atl1c_driver = {
  2432. .name = atl1c_driver_name,
  2433. .id_table = atl1c_pci_tbl,
  2434. .probe = atl1c_probe,
  2435. .remove = atl1c_remove,
  2436. .shutdown = atl1c_shutdown,
  2437. .err_handler = &atl1c_err_handler,
  2438. .driver.pm = &atl1c_pm_ops,
  2439. };
  2440. module_pci_driver(atl1c_driver);