ena_netdev.h 8.0 KB

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  1. /*
  2. * Copyright 2015 Amazon.com, Inc. or its affiliates.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #ifndef ENA_H
  33. #define ENA_H
  34. #include <linux/bitops.h>
  35. #include <linux/etherdevice.h>
  36. #include <linux/inetdevice.h>
  37. #include <linux/interrupt.h>
  38. #include <linux/netdevice.h>
  39. #include <linux/skbuff.h>
  40. #include "ena_com.h"
  41. #include "ena_eth_com.h"
  42. #define DRV_MODULE_VER_MAJOR 1
  43. #define DRV_MODULE_VER_MINOR 0
  44. #define DRV_MODULE_VER_SUBMINOR 2
  45. #define DRV_MODULE_NAME "ena"
  46. #ifndef DRV_MODULE_VERSION
  47. #define DRV_MODULE_VERSION \
  48. __stringify(DRV_MODULE_VER_MAJOR) "." \
  49. __stringify(DRV_MODULE_VER_MINOR) "." \
  50. __stringify(DRV_MODULE_VER_SUBMINOR)
  51. #endif
  52. #define DEVICE_NAME "Elastic Network Adapter (ENA)"
  53. /* 1 for AENQ + ADMIN */
  54. #define ENA_MAX_MSIX_VEC(io_queues) (1 + (io_queues))
  55. #define ENA_REG_BAR 0
  56. #define ENA_MEM_BAR 2
  57. #define ENA_BAR_MASK (BIT(ENA_REG_BAR) | BIT(ENA_MEM_BAR))
  58. #define ENA_DEFAULT_RING_SIZE (1024)
  59. #define ENA_TX_WAKEUP_THRESH (MAX_SKB_FRAGS + 2)
  60. #define ENA_DEFAULT_RX_COPYBREAK (128 - NET_IP_ALIGN)
  61. /* limit the buffer size to 600 bytes to handle MTU changes from very
  62. * small to very large, in which case the number of buffers per packet
  63. * could exceed ENA_PKT_MAX_BUFS
  64. */
  65. #define ENA_DEFAULT_MIN_RX_BUFF_ALLOC_SIZE 600
  66. #define ENA_MIN_MTU 128
  67. #define ENA_NAME_MAX_LEN 20
  68. #define ENA_IRQNAME_SIZE 40
  69. #define ENA_PKT_MAX_BUFS 19
  70. #define ENA_RX_RSS_TABLE_LOG_SIZE 7
  71. #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  72. #define ENA_HASH_KEY_SIZE 40
  73. /* The number of tx packet completions that will be handled each NAPI poll
  74. * cycle is ring_size / ENA_TX_POLL_BUDGET_DIVIDER.
  75. */
  76. #define ENA_TX_POLL_BUDGET_DIVIDER 4
  77. /* Refill Rx queue when number of available descriptors is below
  78. * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER
  79. */
  80. #define ENA_RX_REFILL_THRESH_DIVIDER 8
  81. /* Number of queues to check for missing queues per timer service */
  82. #define ENA_MONITORED_TX_QUEUES 4
  83. /* Max timeout packets before device reset */
  84. #define MAX_NUM_OF_TIMEOUTED_PACKETS 32
  85. #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
  86. #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
  87. #define ENA_RX_RING_IDX_ADD(idx, n, ring_size) \
  88. (((idx) + (n)) & ((ring_size) - 1))
  89. #define ENA_IO_TXQ_IDX(q) (2 * (q))
  90. #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
  91. #define ENA_MGMNT_IRQ_IDX 0
  92. #define ENA_IO_IRQ_FIRST_IDX 1
  93. #define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q))
  94. /* ENA device should send keep alive msg every 1 sec.
  95. * We wait for 3 sec just to be on the safe side.
  96. */
  97. #define ENA_DEVICE_KALIVE_TIMEOUT (3 * HZ)
  98. #define ENA_MMIO_DISABLE_REG_READ BIT(0)
  99. struct ena_irq {
  100. irq_handler_t handler;
  101. void *data;
  102. int cpu;
  103. u32 vector;
  104. cpumask_t affinity_hint_mask;
  105. char name[ENA_IRQNAME_SIZE];
  106. };
  107. struct ena_napi {
  108. struct napi_struct napi ____cacheline_aligned;
  109. struct ena_ring *tx_ring;
  110. struct ena_ring *rx_ring;
  111. u32 qid;
  112. };
  113. struct ena_tx_buffer {
  114. struct sk_buff *skb;
  115. /* num of ena desc for this specific skb
  116. * (includes data desc and metadata desc)
  117. */
  118. u32 tx_descs;
  119. /* num of buffers used by this skb */
  120. u32 num_of_bufs;
  121. /* Save the last jiffies to detect missing tx packets */
  122. unsigned long last_jiffies;
  123. struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
  124. } ____cacheline_aligned;
  125. struct ena_rx_buffer {
  126. struct sk_buff *skb;
  127. struct page *page;
  128. u32 page_offset;
  129. struct ena_com_buf ena_buf;
  130. } ____cacheline_aligned;
  131. struct ena_stats_tx {
  132. u64 cnt;
  133. u64 bytes;
  134. u64 queue_stop;
  135. u64 prepare_ctx_err;
  136. u64 queue_wakeup;
  137. u64 dma_mapping_err;
  138. u64 linearize;
  139. u64 linearize_failed;
  140. u64 napi_comp;
  141. u64 tx_poll;
  142. u64 doorbells;
  143. u64 missing_tx_comp;
  144. u64 bad_req_id;
  145. };
  146. struct ena_stats_rx {
  147. u64 cnt;
  148. u64 bytes;
  149. u64 refil_partial;
  150. u64 bad_csum;
  151. u64 page_alloc_fail;
  152. u64 skb_alloc_fail;
  153. u64 dma_mapping_err;
  154. u64 bad_desc_num;
  155. u64 rx_copybreak_pkt;
  156. };
  157. struct ena_ring {
  158. /* Holds the empty requests for TX out of order completions */
  159. u16 *free_tx_ids;
  160. union {
  161. struct ena_tx_buffer *tx_buffer_info;
  162. struct ena_rx_buffer *rx_buffer_info;
  163. };
  164. /* cache ptr to avoid using the adapter */
  165. struct device *dev;
  166. struct pci_dev *pdev;
  167. struct napi_struct *napi;
  168. struct net_device *netdev;
  169. struct ena_com_dev *ena_dev;
  170. struct ena_adapter *adapter;
  171. struct ena_com_io_cq *ena_com_io_cq;
  172. struct ena_com_io_sq *ena_com_io_sq;
  173. u16 next_to_use;
  174. u16 next_to_clean;
  175. u16 rx_copybreak;
  176. u16 qid;
  177. u16 mtu;
  178. u16 sgl_size;
  179. /* The maximum header length the device can handle */
  180. u8 tx_max_header_size;
  181. /* cpu for TPH */
  182. int cpu;
  183. /* number of tx/rx_buffer_info's entries */
  184. int ring_size;
  185. enum ena_admin_placement_policy_type tx_mem_queue_type;
  186. struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS];
  187. u32 smoothed_interval;
  188. u32 per_napi_packets;
  189. u32 per_napi_bytes;
  190. enum ena_intr_moder_level moder_tbl_idx;
  191. struct u64_stats_sync syncp;
  192. union {
  193. struct ena_stats_tx tx_stats;
  194. struct ena_stats_rx rx_stats;
  195. };
  196. } ____cacheline_aligned;
  197. struct ena_stats_dev {
  198. u64 tx_timeout;
  199. u64 io_suspend;
  200. u64 io_resume;
  201. u64 wd_expired;
  202. u64 interface_up;
  203. u64 interface_down;
  204. u64 admin_q_pause;
  205. };
  206. enum ena_flags_t {
  207. ENA_FLAG_DEVICE_RUNNING,
  208. ENA_FLAG_DEV_UP,
  209. ENA_FLAG_LINK_UP,
  210. ENA_FLAG_MSIX_ENABLED,
  211. ENA_FLAG_TRIGGER_RESET
  212. };
  213. /* adapter specific private data structure */
  214. struct ena_adapter {
  215. struct ena_com_dev *ena_dev;
  216. /* OS defined structs */
  217. struct net_device *netdev;
  218. struct pci_dev *pdev;
  219. /* rx packets that shorter that this len will be copied to the skb
  220. * header
  221. */
  222. u32 rx_copybreak;
  223. u32 max_mtu;
  224. int num_queues;
  225. struct msix_entry *msix_entries;
  226. int msix_vecs;
  227. u32 tx_usecs, rx_usecs; /* interrupt moderation */
  228. u32 tx_frames, rx_frames; /* interrupt moderation */
  229. u32 tx_ring_size;
  230. u32 rx_ring_size;
  231. u32 msg_enable;
  232. u16 max_tx_sgl_size;
  233. u16 max_rx_sgl_size;
  234. u8 mac_addr[ETH_ALEN];
  235. char name[ENA_NAME_MAX_LEN];
  236. unsigned long flags;
  237. /* TX */
  238. struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES]
  239. ____cacheline_aligned_in_smp;
  240. /* RX */
  241. struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES]
  242. ____cacheline_aligned_in_smp;
  243. struct ena_napi ena_napi[ENA_MAX_NUM_IO_QUEUES];
  244. struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)];
  245. /* timer service */
  246. struct work_struct reset_task;
  247. struct work_struct suspend_io_task;
  248. struct work_struct resume_io_task;
  249. struct timer_list timer_service;
  250. bool wd_state;
  251. unsigned long last_keep_alive_jiffies;
  252. struct u64_stats_sync syncp;
  253. struct ena_stats_dev dev_stats;
  254. /* last queue index that was checked for uncompleted tx packets */
  255. u32 last_monitored_tx_qid;
  256. };
  257. void ena_set_ethtool_ops(struct net_device *netdev);
  258. void ena_dump_stats_to_dmesg(struct ena_adapter *adapter);
  259. void ena_dump_stats_to_buf(struct ena_adapter *adapter, u8 *buf);
  260. int ena_get_sset_count(struct net_device *netdev, int sset);
  261. #endif /* !(ENA_H) */