sdhci-cadence.c 7.7 KB

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  1. /*
  2. * Copyright (C) 2016 Socionext Inc.
  3. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/bitops.h>
  16. #include <linux/iopoll.h>
  17. #include <linux/module.h>
  18. #include <linux/mmc/host.h>
  19. #include "sdhci-pltfm.h"
  20. /* HRS - Host Register Set (specific to Cadence) */
  21. #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
  22. #define SDHCI_CDNS_HRS04_ACK BIT(26)
  23. #define SDHCI_CDNS_HRS04_RD BIT(25)
  24. #define SDHCI_CDNS_HRS04_WR BIT(24)
  25. #define SDHCI_CDNS_HRS04_RDATA_SHIFT 12
  26. #define SDHCI_CDNS_HRS04_WDATA_SHIFT 8
  27. #define SDHCI_CDNS_HRS04_ADDR_SHIFT 0
  28. #define SDHCI_CDNS_HRS06 0x18 /* eMMC control */
  29. #define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
  30. #define SDHCI_CDNS_HRS06_TUNE_SHIFT 8
  31. #define SDHCI_CDNS_HRS06_TUNE_MASK 0x3f
  32. #define SDHCI_CDNS_HRS06_MODE_MASK 0x7
  33. #define SDHCI_CDNS_HRS06_MODE_SD 0x0
  34. #define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
  35. #define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
  36. #define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4
  37. #define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
  38. /* SRS - Slot Register Set (SDHCI-compatible) */
  39. #define SDHCI_CDNS_SRS_BASE 0x200
  40. /* PHY */
  41. #define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
  42. #define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
  43. #define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
  44. #define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
  45. #define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
  46. #define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
  47. #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
  48. #define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07
  49. #define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08
  50. /*
  51. * The tuned val register is 6 bit-wide, but not the whole of the range is
  52. * available. The range 0-42 seems to be available (then 43 wraps around to 0)
  53. * but I am not quite sure if it is official. Use only 0 to 39 for safety.
  54. */
  55. #define SDHCI_CDNS_MAX_TUNING_LOOP 40
  56. struct sdhci_cdns_priv {
  57. void __iomem *hrs_addr;
  58. };
  59. static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
  60. u8 addr, u8 data)
  61. {
  62. void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
  63. u32 tmp;
  64. tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) |
  65. (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
  66. writel(tmp, reg);
  67. tmp |= SDHCI_CDNS_HRS04_WR;
  68. writel(tmp, reg);
  69. tmp &= ~SDHCI_CDNS_HRS04_WR;
  70. writel(tmp, reg);
  71. }
  72. static void sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv)
  73. {
  74. sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_SD_HS, 4);
  75. sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_SD_DEFAULT, 4);
  76. sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_EMMC_LEGACY, 9);
  77. sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_EMMC_SDR, 2);
  78. sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_EMMC_DDR, 3);
  79. }
  80. static inline void *sdhci_cdns_priv(struct sdhci_host *host)
  81. {
  82. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  83. return sdhci_pltfm_priv(pltfm_host);
  84. }
  85. static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host)
  86. {
  87. /*
  88. * Cadence's spec says the Timeout Clock Frequency is the same as the
  89. * Base Clock Frequency. Divide it by 1000 to return a value in kHz.
  90. */
  91. return host->max_clk / 1000;
  92. }
  93. static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
  94. unsigned int timing)
  95. {
  96. struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
  97. u32 mode, tmp;
  98. switch (timing) {
  99. case MMC_TIMING_MMC_HS:
  100. mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
  101. break;
  102. case MMC_TIMING_MMC_DDR52:
  103. mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
  104. break;
  105. case MMC_TIMING_MMC_HS200:
  106. mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
  107. break;
  108. case MMC_TIMING_MMC_HS400:
  109. mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
  110. break;
  111. default:
  112. mode = SDHCI_CDNS_HRS06_MODE_SD;
  113. break;
  114. }
  115. /* The speed mode for eMMC is selected by HRS06 register */
  116. tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
  117. tmp &= ~SDHCI_CDNS_HRS06_MODE_MASK;
  118. tmp |= mode;
  119. writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);
  120. /* For SD, fall back to the default handler */
  121. if (mode == SDHCI_CDNS_HRS06_MODE_SD)
  122. sdhci_set_uhs_signaling(host, timing);
  123. }
  124. static const struct sdhci_ops sdhci_cdns_ops = {
  125. .set_clock = sdhci_set_clock,
  126. .get_timeout_clock = sdhci_cdns_get_timeout_clock,
  127. .set_bus_width = sdhci_set_bus_width,
  128. .reset = sdhci_reset,
  129. .set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
  130. };
  131. static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = {
  132. .ops = &sdhci_cdns_ops,
  133. };
  134. static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val)
  135. {
  136. struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
  137. void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06;
  138. u32 tmp;
  139. if (WARN_ON(val > SDHCI_CDNS_HRS06_TUNE_MASK))
  140. return -EINVAL;
  141. tmp = readl(reg);
  142. tmp &= ~(SDHCI_CDNS_HRS06_TUNE_MASK << SDHCI_CDNS_HRS06_TUNE_SHIFT);
  143. tmp |= val << SDHCI_CDNS_HRS06_TUNE_SHIFT;
  144. tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
  145. writel(tmp, reg);
  146. return readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
  147. 0, 1);
  148. }
  149. static int sdhci_cdns_execute_tuning(struct mmc_host *mmc, u32 opcode)
  150. {
  151. struct sdhci_host *host = mmc_priv(mmc);
  152. int cur_streak = 0;
  153. int max_streak = 0;
  154. int end_of_streak = 0;
  155. int i;
  156. /*
  157. * This handler only implements the eMMC tuning that is specific to
  158. * this controller. Fall back to the standard method for SD timing.
  159. */
  160. if (host->timing != MMC_TIMING_MMC_HS200)
  161. return sdhci_execute_tuning(mmc, opcode);
  162. if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
  163. return -EINVAL;
  164. for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
  165. if (sdhci_cdns_set_tune_val(host, i) ||
  166. mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */
  167. cur_streak = 0;
  168. } else { /* good */
  169. cur_streak++;
  170. if (cur_streak > max_streak) {
  171. max_streak = cur_streak;
  172. end_of_streak = i;
  173. }
  174. }
  175. }
  176. if (!max_streak) {
  177. dev_err(mmc_dev(host->mmc), "no tuning point found\n");
  178. return -EIO;
  179. }
  180. return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2);
  181. }
  182. static int sdhci_cdns_probe(struct platform_device *pdev)
  183. {
  184. struct sdhci_host *host;
  185. struct sdhci_pltfm_host *pltfm_host;
  186. struct sdhci_cdns_priv *priv;
  187. struct clk *clk;
  188. int ret;
  189. clk = devm_clk_get(&pdev->dev, NULL);
  190. if (IS_ERR(clk))
  191. return PTR_ERR(clk);
  192. ret = clk_prepare_enable(clk);
  193. if (ret)
  194. return ret;
  195. host = sdhci_pltfm_init(pdev, &sdhci_cdns_pltfm_data, sizeof(*priv));
  196. if (IS_ERR(host)) {
  197. ret = PTR_ERR(host);
  198. goto disable_clk;
  199. }
  200. pltfm_host = sdhci_priv(host);
  201. pltfm_host->clk = clk;
  202. priv = sdhci_cdns_priv(host);
  203. priv->hrs_addr = host->ioaddr;
  204. host->ioaddr += SDHCI_CDNS_SRS_BASE;
  205. host->mmc_host_ops.execute_tuning = sdhci_cdns_execute_tuning;
  206. ret = mmc_of_parse(host->mmc);
  207. if (ret)
  208. goto free;
  209. sdhci_cdns_phy_init(priv);
  210. ret = sdhci_add_host(host);
  211. if (ret)
  212. goto free;
  213. return 0;
  214. free:
  215. sdhci_pltfm_free(pdev);
  216. disable_clk:
  217. clk_disable_unprepare(clk);
  218. return ret;
  219. }
  220. static const struct of_device_id sdhci_cdns_match[] = {
  221. { .compatible = "socionext,uniphier-sd4hc" },
  222. { .compatible = "cdns,sd4hc" },
  223. { /* sentinel */ }
  224. };
  225. MODULE_DEVICE_TABLE(of, sdhci_cdns_match);
  226. static struct platform_driver sdhci_cdns_driver = {
  227. .driver = {
  228. .name = "sdhci-cdns",
  229. .pm = &sdhci_pltfm_pmops,
  230. .of_match_table = sdhci_cdns_match,
  231. },
  232. .probe = sdhci_cdns_probe,
  233. .remove = sdhci_pltfm_unregister,
  234. };
  235. module_platform_driver(sdhci_cdns_driver);
  236. MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
  237. MODULE_DESCRIPTION("Cadence SD/SDIO/eMMC Host Controller Driver");
  238. MODULE_LICENSE("GPL");