scif_dma.c 53 KB

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  1. /*
  2. * Intel MIC Platform Software Stack (MPSS)
  3. *
  4. * Copyright(c) 2015 Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License, version 2, as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * Intel SCIF driver.
  16. *
  17. */
  18. #include "scif_main.h"
  19. #include "scif_map.h"
  20. /*
  21. * struct scif_dma_comp_cb - SCIF DMA completion callback
  22. *
  23. * @dma_completion_func: DMA completion callback
  24. * @cb_cookie: DMA completion callback cookie
  25. * @temp_buf: Temporary buffer
  26. * @temp_buf_to_free: Temporary buffer to be freed
  27. * @is_cache: Is a kmem_cache allocated buffer
  28. * @dst_offset: Destination registration offset
  29. * @dst_window: Destination registration window
  30. * @len: Length of the temp buffer
  31. * @temp_phys: DMA address of the temp buffer
  32. * @sdev: The SCIF device
  33. * @header_padding: padding for cache line alignment
  34. */
  35. struct scif_dma_comp_cb {
  36. void (*dma_completion_func)(void *cookie);
  37. void *cb_cookie;
  38. u8 *temp_buf;
  39. u8 *temp_buf_to_free;
  40. bool is_cache;
  41. s64 dst_offset;
  42. struct scif_window *dst_window;
  43. size_t len;
  44. dma_addr_t temp_phys;
  45. struct scif_dev *sdev;
  46. int header_padding;
  47. };
  48. /**
  49. * struct scif_copy_work - Work for DMA copy
  50. *
  51. * @src_offset: Starting source offset
  52. * @dst_offset: Starting destination offset
  53. * @src_window: Starting src registered window
  54. * @dst_window: Starting dst registered window
  55. * @loopback: true if this is a loopback DMA transfer
  56. * @len: Length of the transfer
  57. * @comp_cb: DMA copy completion callback
  58. * @remote_dev: The remote SCIF peer device
  59. * @fence_type: polling or interrupt based
  60. * @ordered: is this a tail byte ordered DMA transfer
  61. */
  62. struct scif_copy_work {
  63. s64 src_offset;
  64. s64 dst_offset;
  65. struct scif_window *src_window;
  66. struct scif_window *dst_window;
  67. int loopback;
  68. size_t len;
  69. struct scif_dma_comp_cb *comp_cb;
  70. struct scif_dev *remote_dev;
  71. int fence_type;
  72. bool ordered;
  73. };
  74. /**
  75. * scif_reserve_dma_chan:
  76. * @ep: Endpoint Descriptor.
  77. *
  78. * This routine reserves a DMA channel for a particular
  79. * endpoint. All DMA transfers for an endpoint are always
  80. * programmed on the same DMA channel.
  81. */
  82. int scif_reserve_dma_chan(struct scif_endpt *ep)
  83. {
  84. int err = 0;
  85. struct scif_dev *scifdev;
  86. struct scif_hw_dev *sdev;
  87. struct dma_chan *chan;
  88. /* Loopback DMAs are not supported on the management node */
  89. if (!scif_info.nodeid && scifdev_self(ep->remote_dev))
  90. return 0;
  91. if (scif_info.nodeid)
  92. scifdev = &scif_dev[0];
  93. else
  94. scifdev = ep->remote_dev;
  95. sdev = scifdev->sdev;
  96. if (!sdev->num_dma_ch)
  97. return -ENODEV;
  98. chan = sdev->dma_ch[scifdev->dma_ch_idx];
  99. scifdev->dma_ch_idx = (scifdev->dma_ch_idx + 1) % sdev->num_dma_ch;
  100. mutex_lock(&ep->rma_info.rma_lock);
  101. ep->rma_info.dma_chan = chan;
  102. mutex_unlock(&ep->rma_info.rma_lock);
  103. return err;
  104. }
  105. #ifdef CONFIG_MMU_NOTIFIER
  106. /**
  107. * scif_rma_destroy_tcw:
  108. *
  109. * This routine destroys temporary cached windows
  110. */
  111. static
  112. void __scif_rma_destroy_tcw(struct scif_mmu_notif *mmn,
  113. u64 start, u64 len)
  114. {
  115. struct list_head *item, *tmp;
  116. struct scif_window *window;
  117. u64 start_va, end_va;
  118. u64 end = start + len;
  119. if (end <= start)
  120. return;
  121. list_for_each_safe(item, tmp, &mmn->tc_reg_list) {
  122. window = list_entry(item, struct scif_window, list);
  123. if (!len)
  124. break;
  125. start_va = window->va_for_temp;
  126. end_va = start_va + (window->nr_pages << PAGE_SHIFT);
  127. if (start < start_va && end <= start_va)
  128. break;
  129. if (start >= end_va)
  130. continue;
  131. __scif_rma_destroy_tcw_helper(window);
  132. }
  133. }
  134. static void scif_rma_destroy_tcw(struct scif_mmu_notif *mmn, u64 start, u64 len)
  135. {
  136. struct scif_endpt *ep = mmn->ep;
  137. spin_lock(&ep->rma_info.tc_lock);
  138. __scif_rma_destroy_tcw(mmn, start, len);
  139. spin_unlock(&ep->rma_info.tc_lock);
  140. }
  141. static void scif_rma_destroy_tcw_ep(struct scif_endpt *ep)
  142. {
  143. struct list_head *item, *tmp;
  144. struct scif_mmu_notif *mmn;
  145. list_for_each_safe(item, tmp, &ep->rma_info.mmn_list) {
  146. mmn = list_entry(item, struct scif_mmu_notif, list);
  147. scif_rma_destroy_tcw(mmn, 0, ULONG_MAX);
  148. }
  149. }
  150. static void __scif_rma_destroy_tcw_ep(struct scif_endpt *ep)
  151. {
  152. struct list_head *item, *tmp;
  153. struct scif_mmu_notif *mmn;
  154. spin_lock(&ep->rma_info.tc_lock);
  155. list_for_each_safe(item, tmp, &ep->rma_info.mmn_list) {
  156. mmn = list_entry(item, struct scif_mmu_notif, list);
  157. __scif_rma_destroy_tcw(mmn, 0, ULONG_MAX);
  158. }
  159. spin_unlock(&ep->rma_info.tc_lock);
  160. }
  161. static bool scif_rma_tc_can_cache(struct scif_endpt *ep, size_t cur_bytes)
  162. {
  163. if ((cur_bytes >> PAGE_SHIFT) > scif_info.rma_tc_limit)
  164. return false;
  165. if ((atomic_read(&ep->rma_info.tcw_total_pages)
  166. + (cur_bytes >> PAGE_SHIFT)) >
  167. scif_info.rma_tc_limit) {
  168. dev_info(scif_info.mdev.this_device,
  169. "%s %d total=%d, current=%zu reached max\n",
  170. __func__, __LINE__,
  171. atomic_read(&ep->rma_info.tcw_total_pages),
  172. (1 + (cur_bytes >> PAGE_SHIFT)));
  173. scif_rma_destroy_tcw_invalid();
  174. __scif_rma_destroy_tcw_ep(ep);
  175. }
  176. return true;
  177. }
  178. static void scif_mmu_notifier_release(struct mmu_notifier *mn,
  179. struct mm_struct *mm)
  180. {
  181. struct scif_mmu_notif *mmn;
  182. mmn = container_of(mn, struct scif_mmu_notif, ep_mmu_notifier);
  183. scif_rma_destroy_tcw(mmn, 0, ULONG_MAX);
  184. schedule_work(&scif_info.misc_work);
  185. }
  186. static void scif_mmu_notifier_invalidate_page(struct mmu_notifier *mn,
  187. struct mm_struct *mm,
  188. unsigned long address)
  189. {
  190. struct scif_mmu_notif *mmn;
  191. mmn = container_of(mn, struct scif_mmu_notif, ep_mmu_notifier);
  192. scif_rma_destroy_tcw(mmn, address, PAGE_SIZE);
  193. }
  194. static void scif_mmu_notifier_invalidate_range_start(struct mmu_notifier *mn,
  195. struct mm_struct *mm,
  196. unsigned long start,
  197. unsigned long end)
  198. {
  199. struct scif_mmu_notif *mmn;
  200. mmn = container_of(mn, struct scif_mmu_notif, ep_mmu_notifier);
  201. scif_rma_destroy_tcw(mmn, start, end - start);
  202. }
  203. static void scif_mmu_notifier_invalidate_range_end(struct mmu_notifier *mn,
  204. struct mm_struct *mm,
  205. unsigned long start,
  206. unsigned long end)
  207. {
  208. /*
  209. * Nothing to do here, everything needed was done in
  210. * invalidate_range_start.
  211. */
  212. }
  213. static const struct mmu_notifier_ops scif_mmu_notifier_ops = {
  214. .release = scif_mmu_notifier_release,
  215. .clear_flush_young = NULL,
  216. .invalidate_page = scif_mmu_notifier_invalidate_page,
  217. .invalidate_range_start = scif_mmu_notifier_invalidate_range_start,
  218. .invalidate_range_end = scif_mmu_notifier_invalidate_range_end};
  219. static void scif_ep_unregister_mmu_notifier(struct scif_endpt *ep)
  220. {
  221. struct scif_endpt_rma_info *rma = &ep->rma_info;
  222. struct scif_mmu_notif *mmn = NULL;
  223. struct list_head *item, *tmp;
  224. mutex_lock(&ep->rma_info.mmn_lock);
  225. list_for_each_safe(item, tmp, &rma->mmn_list) {
  226. mmn = list_entry(item, struct scif_mmu_notif, list);
  227. mmu_notifier_unregister(&mmn->ep_mmu_notifier, mmn->mm);
  228. list_del(item);
  229. kfree(mmn);
  230. }
  231. mutex_unlock(&ep->rma_info.mmn_lock);
  232. }
  233. static void scif_init_mmu_notifier(struct scif_mmu_notif *mmn,
  234. struct mm_struct *mm, struct scif_endpt *ep)
  235. {
  236. mmn->ep = ep;
  237. mmn->mm = mm;
  238. mmn->ep_mmu_notifier.ops = &scif_mmu_notifier_ops;
  239. INIT_LIST_HEAD(&mmn->list);
  240. INIT_LIST_HEAD(&mmn->tc_reg_list);
  241. }
  242. static struct scif_mmu_notif *
  243. scif_find_mmu_notifier(struct mm_struct *mm, struct scif_endpt_rma_info *rma)
  244. {
  245. struct scif_mmu_notif *mmn;
  246. list_for_each_entry(mmn, &rma->mmn_list, list)
  247. if (mmn->mm == mm)
  248. return mmn;
  249. return NULL;
  250. }
  251. static struct scif_mmu_notif *
  252. scif_add_mmu_notifier(struct mm_struct *mm, struct scif_endpt *ep)
  253. {
  254. struct scif_mmu_notif *mmn
  255. = kzalloc(sizeof(*mmn), GFP_KERNEL);
  256. if (!mmn)
  257. return ERR_PTR(-ENOMEM);
  258. scif_init_mmu_notifier(mmn, current->mm, ep);
  259. if (mmu_notifier_register(&mmn->ep_mmu_notifier, current->mm)) {
  260. kfree(mmn);
  261. return ERR_PTR(-EBUSY);
  262. }
  263. list_add(&mmn->list, &ep->rma_info.mmn_list);
  264. return mmn;
  265. }
  266. /*
  267. * Called from the misc thread to destroy temporary cached windows and
  268. * unregister the MMU notifier for the SCIF endpoint.
  269. */
  270. void scif_mmu_notif_handler(struct work_struct *work)
  271. {
  272. struct list_head *pos, *tmpq;
  273. struct scif_endpt *ep;
  274. restart:
  275. scif_rma_destroy_tcw_invalid();
  276. spin_lock(&scif_info.rmalock);
  277. list_for_each_safe(pos, tmpq, &scif_info.mmu_notif_cleanup) {
  278. ep = list_entry(pos, struct scif_endpt, mmu_list);
  279. list_del(&ep->mmu_list);
  280. spin_unlock(&scif_info.rmalock);
  281. scif_rma_destroy_tcw_ep(ep);
  282. scif_ep_unregister_mmu_notifier(ep);
  283. goto restart;
  284. }
  285. spin_unlock(&scif_info.rmalock);
  286. }
  287. static bool scif_is_set_reg_cache(int flags)
  288. {
  289. return !!(flags & SCIF_RMA_USECACHE);
  290. }
  291. #else
  292. static struct scif_mmu_notif *
  293. scif_find_mmu_notifier(struct mm_struct *mm,
  294. struct scif_endpt_rma_info *rma)
  295. {
  296. return NULL;
  297. }
  298. static struct scif_mmu_notif *
  299. scif_add_mmu_notifier(struct mm_struct *mm, struct scif_endpt *ep)
  300. {
  301. return NULL;
  302. }
  303. void scif_mmu_notif_handler(struct work_struct *work)
  304. {
  305. }
  306. static bool scif_is_set_reg_cache(int flags)
  307. {
  308. return false;
  309. }
  310. static bool scif_rma_tc_can_cache(struct scif_endpt *ep, size_t cur_bytes)
  311. {
  312. return false;
  313. }
  314. #endif
  315. /**
  316. * scif_register_temp:
  317. * @epd: End Point Descriptor.
  318. * @addr: virtual address to/from which to copy
  319. * @len: length of range to copy
  320. * @out_offset: computed offset returned by reference.
  321. * @out_window: allocated registered window returned by reference.
  322. *
  323. * Create a temporary registered window. The peer will not know about this
  324. * window. This API is used for scif_vreadfrom()/scif_vwriteto() API's.
  325. */
  326. static int
  327. scif_register_temp(scif_epd_t epd, unsigned long addr, size_t len, int prot,
  328. off_t *out_offset, struct scif_window **out_window)
  329. {
  330. struct scif_endpt *ep = (struct scif_endpt *)epd;
  331. int err;
  332. scif_pinned_pages_t pinned_pages;
  333. size_t aligned_len;
  334. aligned_len = ALIGN(len, PAGE_SIZE);
  335. err = __scif_pin_pages((void *)(addr & PAGE_MASK),
  336. aligned_len, &prot, 0, &pinned_pages);
  337. if (err)
  338. return err;
  339. pinned_pages->prot = prot;
  340. /* Compute the offset for this registration */
  341. err = scif_get_window_offset(ep, 0, 0,
  342. aligned_len >> PAGE_SHIFT,
  343. (s64 *)out_offset);
  344. if (err)
  345. goto error_unpin;
  346. /* Allocate and prepare self registration window */
  347. *out_window = scif_create_window(ep, aligned_len >> PAGE_SHIFT,
  348. *out_offset, true);
  349. if (!*out_window) {
  350. scif_free_window_offset(ep, NULL, *out_offset);
  351. err = -ENOMEM;
  352. goto error_unpin;
  353. }
  354. (*out_window)->pinned_pages = pinned_pages;
  355. (*out_window)->nr_pages = pinned_pages->nr_pages;
  356. (*out_window)->prot = pinned_pages->prot;
  357. (*out_window)->va_for_temp = addr & PAGE_MASK;
  358. err = scif_map_window(ep->remote_dev, *out_window);
  359. if (err) {
  360. /* Something went wrong! Rollback */
  361. scif_destroy_window(ep, *out_window);
  362. *out_window = NULL;
  363. } else {
  364. *out_offset |= (addr - (*out_window)->va_for_temp);
  365. }
  366. return err;
  367. error_unpin:
  368. if (err)
  369. dev_err(&ep->remote_dev->sdev->dev,
  370. "%s %d err %d\n", __func__, __LINE__, err);
  371. scif_unpin_pages(pinned_pages);
  372. return err;
  373. }
  374. #define SCIF_DMA_TO (3 * HZ)
  375. /*
  376. * scif_sync_dma - Program a DMA without an interrupt descriptor
  377. *
  378. * @dev - The address of the pointer to the device instance used
  379. * for DMA registration.
  380. * @chan - DMA channel to be used.
  381. * @sync_wait: Wait for DMA to complete?
  382. *
  383. * Return 0 on success and -errno on error.
  384. */
  385. static int scif_sync_dma(struct scif_hw_dev *sdev, struct dma_chan *chan,
  386. bool sync_wait)
  387. {
  388. int err = 0;
  389. struct dma_async_tx_descriptor *tx = NULL;
  390. enum dma_ctrl_flags flags = DMA_PREP_FENCE;
  391. dma_cookie_t cookie;
  392. struct dma_device *ddev;
  393. if (!chan) {
  394. err = -EIO;
  395. dev_err(&sdev->dev, "%s %d err %d\n",
  396. __func__, __LINE__, err);
  397. return err;
  398. }
  399. ddev = chan->device;
  400. tx = ddev->device_prep_dma_memcpy(chan, 0, 0, 0, flags);
  401. if (!tx) {
  402. err = -ENOMEM;
  403. dev_err(&sdev->dev, "%s %d err %d\n",
  404. __func__, __LINE__, err);
  405. goto release;
  406. }
  407. cookie = tx->tx_submit(tx);
  408. if (dma_submit_error(cookie)) {
  409. err = -ENOMEM;
  410. dev_err(&sdev->dev, "%s %d err %d\n",
  411. __func__, __LINE__, err);
  412. goto release;
  413. }
  414. if (!sync_wait) {
  415. dma_async_issue_pending(chan);
  416. } else {
  417. if (dma_sync_wait(chan, cookie) == DMA_COMPLETE) {
  418. err = 0;
  419. } else {
  420. err = -EIO;
  421. dev_err(&sdev->dev, "%s %d err %d\n",
  422. __func__, __LINE__, err);
  423. }
  424. }
  425. release:
  426. return err;
  427. }
  428. static void scif_dma_callback(void *arg)
  429. {
  430. struct completion *done = (struct completion *)arg;
  431. complete(done);
  432. }
  433. #define SCIF_DMA_SYNC_WAIT true
  434. #define SCIF_DMA_POLL BIT(0)
  435. #define SCIF_DMA_INTR BIT(1)
  436. /*
  437. * scif_async_dma - Program a DMA with an interrupt descriptor
  438. *
  439. * @dev - The address of the pointer to the device instance used
  440. * for DMA registration.
  441. * @chan - DMA channel to be used.
  442. * Return 0 on success and -errno on error.
  443. */
  444. static int scif_async_dma(struct scif_hw_dev *sdev, struct dma_chan *chan)
  445. {
  446. int err = 0;
  447. struct dma_device *ddev;
  448. struct dma_async_tx_descriptor *tx = NULL;
  449. enum dma_ctrl_flags flags = DMA_PREP_INTERRUPT | DMA_PREP_FENCE;
  450. DECLARE_COMPLETION_ONSTACK(done_wait);
  451. dma_cookie_t cookie;
  452. enum dma_status status;
  453. if (!chan) {
  454. err = -EIO;
  455. dev_err(&sdev->dev, "%s %d err %d\n",
  456. __func__, __LINE__, err);
  457. return err;
  458. }
  459. ddev = chan->device;
  460. tx = ddev->device_prep_dma_memcpy(chan, 0, 0, 0, flags);
  461. if (!tx) {
  462. err = -ENOMEM;
  463. dev_err(&sdev->dev, "%s %d err %d\n",
  464. __func__, __LINE__, err);
  465. goto release;
  466. }
  467. reinit_completion(&done_wait);
  468. tx->callback = scif_dma_callback;
  469. tx->callback_param = &done_wait;
  470. cookie = tx->tx_submit(tx);
  471. if (dma_submit_error(cookie)) {
  472. err = -ENOMEM;
  473. dev_err(&sdev->dev, "%s %d err %d\n",
  474. __func__, __LINE__, err);
  475. goto release;
  476. }
  477. dma_async_issue_pending(chan);
  478. err = wait_for_completion_timeout(&done_wait, SCIF_DMA_TO);
  479. if (!err) {
  480. err = -EIO;
  481. dev_err(&sdev->dev, "%s %d err %d\n",
  482. __func__, __LINE__, err);
  483. goto release;
  484. }
  485. err = 0;
  486. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  487. if (status != DMA_COMPLETE) {
  488. err = -EIO;
  489. dev_err(&sdev->dev, "%s %d err %d\n",
  490. __func__, __LINE__, err);
  491. goto release;
  492. }
  493. release:
  494. return err;
  495. }
  496. /*
  497. * scif_drain_dma_poll - Drain all outstanding DMA operations for a particular
  498. * DMA channel via polling.
  499. *
  500. * @sdev - The SCIF device
  501. * @chan - DMA channel
  502. * Return 0 on success and -errno on error.
  503. */
  504. static int scif_drain_dma_poll(struct scif_hw_dev *sdev, struct dma_chan *chan)
  505. {
  506. if (!chan)
  507. return -EINVAL;
  508. return scif_sync_dma(sdev, chan, SCIF_DMA_SYNC_WAIT);
  509. }
  510. /*
  511. * scif_drain_dma_intr - Drain all outstanding DMA operations for a particular
  512. * DMA channel via interrupt based blocking wait.
  513. *
  514. * @sdev - The SCIF device
  515. * @chan - DMA channel
  516. * Return 0 on success and -errno on error.
  517. */
  518. int scif_drain_dma_intr(struct scif_hw_dev *sdev, struct dma_chan *chan)
  519. {
  520. if (!chan)
  521. return -EINVAL;
  522. return scif_async_dma(sdev, chan);
  523. }
  524. /**
  525. * scif_rma_destroy_windows:
  526. *
  527. * This routine destroys all windows queued for cleanup
  528. */
  529. void scif_rma_destroy_windows(void)
  530. {
  531. struct list_head *item, *tmp;
  532. struct scif_window *window;
  533. struct scif_endpt *ep;
  534. struct dma_chan *chan;
  535. might_sleep();
  536. restart:
  537. spin_lock(&scif_info.rmalock);
  538. list_for_each_safe(item, tmp, &scif_info.rma) {
  539. window = list_entry(item, struct scif_window,
  540. list);
  541. ep = (struct scif_endpt *)window->ep;
  542. chan = ep->rma_info.dma_chan;
  543. list_del_init(&window->list);
  544. spin_unlock(&scif_info.rmalock);
  545. if (!chan || !scifdev_alive(ep) ||
  546. !scif_drain_dma_intr(ep->remote_dev->sdev,
  547. ep->rma_info.dma_chan))
  548. /* Remove window from global list */
  549. window->unreg_state = OP_COMPLETED;
  550. else
  551. dev_warn(&ep->remote_dev->sdev->dev,
  552. "DMA engine hung?\n");
  553. if (window->unreg_state == OP_COMPLETED) {
  554. if (window->type == SCIF_WINDOW_SELF)
  555. scif_destroy_window(ep, window);
  556. else
  557. scif_destroy_remote_window(window);
  558. atomic_dec(&ep->rma_info.tw_refcount);
  559. }
  560. goto restart;
  561. }
  562. spin_unlock(&scif_info.rmalock);
  563. }
  564. /**
  565. * scif_rma_destroy_tcw:
  566. *
  567. * This routine destroys temporary cached registered windows
  568. * which have been queued for cleanup.
  569. */
  570. void scif_rma_destroy_tcw_invalid(void)
  571. {
  572. struct list_head *item, *tmp;
  573. struct scif_window *window;
  574. struct scif_endpt *ep;
  575. struct dma_chan *chan;
  576. might_sleep();
  577. restart:
  578. spin_lock(&scif_info.rmalock);
  579. list_for_each_safe(item, tmp, &scif_info.rma_tc) {
  580. window = list_entry(item, struct scif_window, list);
  581. ep = (struct scif_endpt *)window->ep;
  582. chan = ep->rma_info.dma_chan;
  583. list_del_init(&window->list);
  584. spin_unlock(&scif_info.rmalock);
  585. mutex_lock(&ep->rma_info.rma_lock);
  586. if (!chan || !scifdev_alive(ep) ||
  587. !scif_drain_dma_intr(ep->remote_dev->sdev,
  588. ep->rma_info.dma_chan)) {
  589. atomic_sub(window->nr_pages,
  590. &ep->rma_info.tcw_total_pages);
  591. scif_destroy_window(ep, window);
  592. atomic_dec(&ep->rma_info.tcw_refcount);
  593. } else {
  594. dev_warn(&ep->remote_dev->sdev->dev,
  595. "DMA engine hung?\n");
  596. }
  597. mutex_unlock(&ep->rma_info.rma_lock);
  598. goto restart;
  599. }
  600. spin_unlock(&scif_info.rmalock);
  601. }
  602. static inline
  603. void *_get_local_va(off_t off, struct scif_window *window, size_t len)
  604. {
  605. int page_nr = (off - window->offset) >> PAGE_SHIFT;
  606. off_t page_off = off & ~PAGE_MASK;
  607. void *va = NULL;
  608. if (window->type == SCIF_WINDOW_SELF) {
  609. struct page **pages = window->pinned_pages->pages;
  610. va = page_address(pages[page_nr]) + page_off;
  611. }
  612. return va;
  613. }
  614. static inline
  615. void *ioremap_remote(off_t off, struct scif_window *window,
  616. size_t len, struct scif_dev *dev,
  617. struct scif_window_iter *iter)
  618. {
  619. dma_addr_t phys = scif_off_to_dma_addr(window, off, NULL, iter);
  620. /*
  621. * If the DMA address is not card relative then we need the DMA
  622. * addresses to be an offset into the bar. The aperture base was already
  623. * added so subtract it here since scif_ioremap is going to add it again
  624. */
  625. if (!scifdev_self(dev) && window->type == SCIF_WINDOW_PEER &&
  626. dev->sdev->aper && !dev->sdev->card_rel_da)
  627. phys = phys - dev->sdev->aper->pa;
  628. return scif_ioremap(phys, len, dev);
  629. }
  630. static inline void
  631. iounmap_remote(void *virt, size_t size, struct scif_copy_work *work)
  632. {
  633. scif_iounmap(virt, size, work->remote_dev);
  634. }
  635. /*
  636. * Takes care of ordering issue caused by
  637. * 1. Hardware: Only in the case of cpu copy from mgmt node to card
  638. * because of WC memory.
  639. * 2. Software: If memcpy reorders copy instructions for optimization.
  640. * This could happen at both mgmt node and card.
  641. */
  642. static inline void
  643. scif_ordered_memcpy_toio(char *dst, const char *src, size_t count)
  644. {
  645. if (!count)
  646. return;
  647. memcpy_toio((void __iomem __force *)dst, src, --count);
  648. /* Order the last byte with the previous stores */
  649. wmb();
  650. *(dst + count) = *(src + count);
  651. }
  652. static inline void scif_unaligned_cpy_toio(char *dst, const char *src,
  653. size_t count, bool ordered)
  654. {
  655. if (ordered)
  656. scif_ordered_memcpy_toio(dst, src, count);
  657. else
  658. memcpy_toio((void __iomem __force *)dst, src, count);
  659. }
  660. static inline
  661. void scif_ordered_memcpy_fromio(char *dst, const char *src, size_t count)
  662. {
  663. if (!count)
  664. return;
  665. memcpy_fromio(dst, (void __iomem __force *)src, --count);
  666. /* Order the last byte with the previous loads */
  667. rmb();
  668. *(dst + count) = *(src + count);
  669. }
  670. static inline void scif_unaligned_cpy_fromio(char *dst, const char *src,
  671. size_t count, bool ordered)
  672. {
  673. if (ordered)
  674. scif_ordered_memcpy_fromio(dst, src, count);
  675. else
  676. memcpy_fromio(dst, (void __iomem __force *)src, count);
  677. }
  678. #define SCIF_RMA_ERROR_CODE (~(dma_addr_t)0x0)
  679. /*
  680. * scif_off_to_dma_addr:
  681. * Obtain the dma_addr given the window and the offset.
  682. * @window: Registered window.
  683. * @off: Window offset.
  684. * @nr_bytes: Return the number of contiguous bytes till next DMA addr index.
  685. * @index: Return the index of the dma_addr array found.
  686. * @start_off: start offset of index of the dma addr array found.
  687. * The nr_bytes provides the callee an estimate of the maximum possible
  688. * DMA xfer possible while the index/start_off provide faster lookups
  689. * for the next iteration.
  690. */
  691. dma_addr_t scif_off_to_dma_addr(struct scif_window *window, s64 off,
  692. size_t *nr_bytes, struct scif_window_iter *iter)
  693. {
  694. int i, page_nr;
  695. s64 start, end;
  696. off_t page_off;
  697. if (window->nr_pages == window->nr_contig_chunks) {
  698. page_nr = (off - window->offset) >> PAGE_SHIFT;
  699. page_off = off & ~PAGE_MASK;
  700. if (nr_bytes)
  701. *nr_bytes = PAGE_SIZE - page_off;
  702. return window->dma_addr[page_nr] | page_off;
  703. }
  704. if (iter) {
  705. i = iter->index;
  706. start = iter->offset;
  707. } else {
  708. i = 0;
  709. start = window->offset;
  710. }
  711. for (; i < window->nr_contig_chunks; i++) {
  712. end = start + (window->num_pages[i] << PAGE_SHIFT);
  713. if (off >= start && off < end) {
  714. if (iter) {
  715. iter->index = i;
  716. iter->offset = start;
  717. }
  718. if (nr_bytes)
  719. *nr_bytes = end - off;
  720. return (window->dma_addr[i] + (off - start));
  721. }
  722. start += (window->num_pages[i] << PAGE_SHIFT);
  723. }
  724. dev_err(scif_info.mdev.this_device,
  725. "%s %d BUG. Addr not found? window %p off 0x%llx\n",
  726. __func__, __LINE__, window, off);
  727. return SCIF_RMA_ERROR_CODE;
  728. }
  729. /*
  730. * Copy between rma window and temporary buffer
  731. */
  732. static void scif_rma_local_cpu_copy(s64 offset, struct scif_window *window,
  733. u8 *temp, size_t rem_len, bool to_temp)
  734. {
  735. void *window_virt;
  736. size_t loop_len;
  737. int offset_in_page;
  738. s64 end_offset;
  739. offset_in_page = offset & ~PAGE_MASK;
  740. loop_len = PAGE_SIZE - offset_in_page;
  741. if (rem_len < loop_len)
  742. loop_len = rem_len;
  743. window_virt = _get_local_va(offset, window, loop_len);
  744. if (!window_virt)
  745. return;
  746. if (to_temp)
  747. memcpy(temp, window_virt, loop_len);
  748. else
  749. memcpy(window_virt, temp, loop_len);
  750. offset += loop_len;
  751. temp += loop_len;
  752. rem_len -= loop_len;
  753. end_offset = window->offset +
  754. (window->nr_pages << PAGE_SHIFT);
  755. while (rem_len) {
  756. if (offset == end_offset) {
  757. window = list_next_entry(window, list);
  758. end_offset = window->offset +
  759. (window->nr_pages << PAGE_SHIFT);
  760. }
  761. loop_len = min(PAGE_SIZE, rem_len);
  762. window_virt = _get_local_va(offset, window, loop_len);
  763. if (!window_virt)
  764. return;
  765. if (to_temp)
  766. memcpy(temp, window_virt, loop_len);
  767. else
  768. memcpy(window_virt, temp, loop_len);
  769. offset += loop_len;
  770. temp += loop_len;
  771. rem_len -= loop_len;
  772. }
  773. }
  774. /**
  775. * scif_rma_completion_cb:
  776. * @data: RMA cookie
  777. *
  778. * RMA interrupt completion callback.
  779. */
  780. static void scif_rma_completion_cb(void *data)
  781. {
  782. struct scif_dma_comp_cb *comp_cb = data;
  783. /* Free DMA Completion CB. */
  784. if (comp_cb->dst_window)
  785. scif_rma_local_cpu_copy(comp_cb->dst_offset,
  786. comp_cb->dst_window,
  787. comp_cb->temp_buf +
  788. comp_cb->header_padding,
  789. comp_cb->len, false);
  790. scif_unmap_single(comp_cb->temp_phys, comp_cb->sdev,
  791. SCIF_KMEM_UNALIGNED_BUF_SIZE);
  792. if (comp_cb->is_cache)
  793. kmem_cache_free(unaligned_cache,
  794. comp_cb->temp_buf_to_free);
  795. else
  796. kfree(comp_cb->temp_buf_to_free);
  797. }
  798. /* Copies between temporary buffer and offsets provided in work */
  799. static int
  800. scif_rma_list_dma_copy_unaligned(struct scif_copy_work *work,
  801. u8 *temp, struct dma_chan *chan,
  802. bool src_local)
  803. {
  804. struct scif_dma_comp_cb *comp_cb = work->comp_cb;
  805. dma_addr_t window_dma_addr, temp_dma_addr;
  806. dma_addr_t temp_phys = comp_cb->temp_phys;
  807. size_t loop_len, nr_contig_bytes = 0, remaining_len = work->len;
  808. int offset_in_ca, ret = 0;
  809. s64 end_offset, offset;
  810. struct scif_window *window;
  811. void *window_virt_addr;
  812. size_t tail_len;
  813. struct dma_async_tx_descriptor *tx;
  814. struct dma_device *dev = chan->device;
  815. dma_cookie_t cookie;
  816. if (src_local) {
  817. offset = work->dst_offset;
  818. window = work->dst_window;
  819. } else {
  820. offset = work->src_offset;
  821. window = work->src_window;
  822. }
  823. offset_in_ca = offset & (L1_CACHE_BYTES - 1);
  824. if (offset_in_ca) {
  825. loop_len = L1_CACHE_BYTES - offset_in_ca;
  826. loop_len = min(loop_len, remaining_len);
  827. window_virt_addr = ioremap_remote(offset, window,
  828. loop_len,
  829. work->remote_dev,
  830. NULL);
  831. if (!window_virt_addr)
  832. return -ENOMEM;
  833. if (src_local)
  834. scif_unaligned_cpy_toio(window_virt_addr, temp,
  835. loop_len,
  836. work->ordered &&
  837. !(remaining_len - loop_len));
  838. else
  839. scif_unaligned_cpy_fromio(temp, window_virt_addr,
  840. loop_len, work->ordered &&
  841. !(remaining_len - loop_len));
  842. iounmap_remote(window_virt_addr, loop_len, work);
  843. offset += loop_len;
  844. temp += loop_len;
  845. temp_phys += loop_len;
  846. remaining_len -= loop_len;
  847. }
  848. offset_in_ca = offset & ~PAGE_MASK;
  849. end_offset = window->offset +
  850. (window->nr_pages << PAGE_SHIFT);
  851. tail_len = remaining_len & (L1_CACHE_BYTES - 1);
  852. remaining_len -= tail_len;
  853. while (remaining_len) {
  854. if (offset == end_offset) {
  855. window = list_next_entry(window, list);
  856. end_offset = window->offset +
  857. (window->nr_pages << PAGE_SHIFT);
  858. }
  859. if (scif_is_mgmt_node())
  860. temp_dma_addr = temp_phys;
  861. else
  862. /* Fix if we ever enable IOMMU on the card */
  863. temp_dma_addr = (dma_addr_t)virt_to_phys(temp);
  864. window_dma_addr = scif_off_to_dma_addr(window, offset,
  865. &nr_contig_bytes,
  866. NULL);
  867. loop_len = min(nr_contig_bytes, remaining_len);
  868. if (src_local) {
  869. if (work->ordered && !tail_len &&
  870. !(remaining_len - loop_len) &&
  871. loop_len != L1_CACHE_BYTES) {
  872. /*
  873. * Break up the last chunk of the transfer into
  874. * two steps. if there is no tail to guarantee
  875. * DMA ordering. SCIF_DMA_POLLING inserts
  876. * a status update descriptor in step 1 which
  877. * acts as a double sided synchronization fence
  878. * for the DMA engine to ensure that the last
  879. * cache line in step 2 is updated last.
  880. */
  881. /* Step 1) DMA: Body Length - L1_CACHE_BYTES. */
  882. tx =
  883. dev->device_prep_dma_memcpy(chan,
  884. window_dma_addr,
  885. temp_dma_addr,
  886. loop_len -
  887. L1_CACHE_BYTES,
  888. DMA_PREP_FENCE);
  889. if (!tx) {
  890. ret = -ENOMEM;
  891. goto err;
  892. }
  893. cookie = tx->tx_submit(tx);
  894. if (dma_submit_error(cookie)) {
  895. ret = -ENOMEM;
  896. goto err;
  897. }
  898. dma_async_issue_pending(chan);
  899. offset += (loop_len - L1_CACHE_BYTES);
  900. temp_dma_addr += (loop_len - L1_CACHE_BYTES);
  901. window_dma_addr += (loop_len - L1_CACHE_BYTES);
  902. remaining_len -= (loop_len - L1_CACHE_BYTES);
  903. loop_len = remaining_len;
  904. /* Step 2) DMA: L1_CACHE_BYTES */
  905. tx =
  906. dev->device_prep_dma_memcpy(chan,
  907. window_dma_addr,
  908. temp_dma_addr,
  909. loop_len, 0);
  910. if (!tx) {
  911. ret = -ENOMEM;
  912. goto err;
  913. }
  914. cookie = tx->tx_submit(tx);
  915. if (dma_submit_error(cookie)) {
  916. ret = -ENOMEM;
  917. goto err;
  918. }
  919. dma_async_issue_pending(chan);
  920. } else {
  921. tx =
  922. dev->device_prep_dma_memcpy(chan,
  923. window_dma_addr,
  924. temp_dma_addr,
  925. loop_len, 0);
  926. if (!tx) {
  927. ret = -ENOMEM;
  928. goto err;
  929. }
  930. cookie = tx->tx_submit(tx);
  931. if (dma_submit_error(cookie)) {
  932. ret = -ENOMEM;
  933. goto err;
  934. }
  935. dma_async_issue_pending(chan);
  936. }
  937. } else {
  938. tx = dev->device_prep_dma_memcpy(chan, temp_dma_addr,
  939. window_dma_addr, loop_len, 0);
  940. if (!tx) {
  941. ret = -ENOMEM;
  942. goto err;
  943. }
  944. cookie = tx->tx_submit(tx);
  945. if (dma_submit_error(cookie)) {
  946. ret = -ENOMEM;
  947. goto err;
  948. }
  949. dma_async_issue_pending(chan);
  950. }
  951. if (ret < 0)
  952. goto err;
  953. offset += loop_len;
  954. temp += loop_len;
  955. temp_phys += loop_len;
  956. remaining_len -= loop_len;
  957. offset_in_ca = 0;
  958. }
  959. if (tail_len) {
  960. if (offset == end_offset) {
  961. window = list_next_entry(window, list);
  962. end_offset = window->offset +
  963. (window->nr_pages << PAGE_SHIFT);
  964. }
  965. window_virt_addr = ioremap_remote(offset, window, tail_len,
  966. work->remote_dev,
  967. NULL);
  968. if (!window_virt_addr)
  969. return -ENOMEM;
  970. /*
  971. * The CPU copy for the tail bytes must be initiated only once
  972. * previous DMA transfers for this endpoint have completed
  973. * to guarantee ordering.
  974. */
  975. if (work->ordered) {
  976. struct scif_dev *rdev = work->remote_dev;
  977. ret = scif_drain_dma_intr(rdev->sdev, chan);
  978. if (ret)
  979. return ret;
  980. }
  981. if (src_local)
  982. scif_unaligned_cpy_toio(window_virt_addr, temp,
  983. tail_len, work->ordered);
  984. else
  985. scif_unaligned_cpy_fromio(temp, window_virt_addr,
  986. tail_len, work->ordered);
  987. iounmap_remote(window_virt_addr, tail_len, work);
  988. }
  989. tx = dev->device_prep_dma_memcpy(chan, 0, 0, 0, DMA_PREP_INTERRUPT);
  990. if (!tx) {
  991. ret = -ENOMEM;
  992. return ret;
  993. }
  994. tx->callback = &scif_rma_completion_cb;
  995. tx->callback_param = comp_cb;
  996. cookie = tx->tx_submit(tx);
  997. if (dma_submit_error(cookie)) {
  998. ret = -ENOMEM;
  999. return ret;
  1000. }
  1001. dma_async_issue_pending(chan);
  1002. return 0;
  1003. err:
  1004. dev_err(scif_info.mdev.this_device,
  1005. "%s %d Desc Prog Failed ret %d\n",
  1006. __func__, __LINE__, ret);
  1007. return ret;
  1008. }
  1009. /*
  1010. * _scif_rma_list_dma_copy_aligned:
  1011. *
  1012. * Traverse all the windows and perform DMA copy.
  1013. */
  1014. static int _scif_rma_list_dma_copy_aligned(struct scif_copy_work *work,
  1015. struct dma_chan *chan)
  1016. {
  1017. dma_addr_t src_dma_addr, dst_dma_addr;
  1018. size_t loop_len, remaining_len, src_contig_bytes = 0;
  1019. size_t dst_contig_bytes = 0;
  1020. struct scif_window_iter src_win_iter;
  1021. struct scif_window_iter dst_win_iter;
  1022. s64 end_src_offset, end_dst_offset;
  1023. struct scif_window *src_window = work->src_window;
  1024. struct scif_window *dst_window = work->dst_window;
  1025. s64 src_offset = work->src_offset, dst_offset = work->dst_offset;
  1026. int ret = 0;
  1027. struct dma_async_tx_descriptor *tx;
  1028. struct dma_device *dev = chan->device;
  1029. dma_cookie_t cookie;
  1030. remaining_len = work->len;
  1031. scif_init_window_iter(src_window, &src_win_iter);
  1032. scif_init_window_iter(dst_window, &dst_win_iter);
  1033. end_src_offset = src_window->offset +
  1034. (src_window->nr_pages << PAGE_SHIFT);
  1035. end_dst_offset = dst_window->offset +
  1036. (dst_window->nr_pages << PAGE_SHIFT);
  1037. while (remaining_len) {
  1038. if (src_offset == end_src_offset) {
  1039. src_window = list_next_entry(src_window, list);
  1040. end_src_offset = src_window->offset +
  1041. (src_window->nr_pages << PAGE_SHIFT);
  1042. scif_init_window_iter(src_window, &src_win_iter);
  1043. }
  1044. if (dst_offset == end_dst_offset) {
  1045. dst_window = list_next_entry(dst_window, list);
  1046. end_dst_offset = dst_window->offset +
  1047. (dst_window->nr_pages << PAGE_SHIFT);
  1048. scif_init_window_iter(dst_window, &dst_win_iter);
  1049. }
  1050. /* compute dma addresses for transfer */
  1051. src_dma_addr = scif_off_to_dma_addr(src_window, src_offset,
  1052. &src_contig_bytes,
  1053. &src_win_iter);
  1054. dst_dma_addr = scif_off_to_dma_addr(dst_window, dst_offset,
  1055. &dst_contig_bytes,
  1056. &dst_win_iter);
  1057. loop_len = min(src_contig_bytes, dst_contig_bytes);
  1058. loop_len = min(loop_len, remaining_len);
  1059. if (work->ordered && !(remaining_len - loop_len)) {
  1060. /*
  1061. * Break up the last chunk of the transfer into two
  1062. * steps to ensure that the last byte in step 2 is
  1063. * updated last.
  1064. */
  1065. /* Step 1) DMA: Body Length - 1 */
  1066. tx = dev->device_prep_dma_memcpy(chan, dst_dma_addr,
  1067. src_dma_addr,
  1068. loop_len - 1,
  1069. DMA_PREP_FENCE);
  1070. if (!tx) {
  1071. ret = -ENOMEM;
  1072. goto err;
  1073. }
  1074. cookie = tx->tx_submit(tx);
  1075. if (dma_submit_error(cookie)) {
  1076. ret = -ENOMEM;
  1077. goto err;
  1078. }
  1079. src_offset += (loop_len - 1);
  1080. dst_offset += (loop_len - 1);
  1081. src_dma_addr += (loop_len - 1);
  1082. dst_dma_addr += (loop_len - 1);
  1083. remaining_len -= (loop_len - 1);
  1084. loop_len = remaining_len;
  1085. /* Step 2) DMA: 1 BYTES */
  1086. tx = dev->device_prep_dma_memcpy(chan, dst_dma_addr,
  1087. src_dma_addr, loop_len, 0);
  1088. if (!tx) {
  1089. ret = -ENOMEM;
  1090. goto err;
  1091. }
  1092. cookie = tx->tx_submit(tx);
  1093. if (dma_submit_error(cookie)) {
  1094. ret = -ENOMEM;
  1095. goto err;
  1096. }
  1097. dma_async_issue_pending(chan);
  1098. } else {
  1099. tx = dev->device_prep_dma_memcpy(chan, dst_dma_addr,
  1100. src_dma_addr, loop_len, 0);
  1101. if (!tx) {
  1102. ret = -ENOMEM;
  1103. goto err;
  1104. }
  1105. cookie = tx->tx_submit(tx);
  1106. if (dma_submit_error(cookie)) {
  1107. ret = -ENOMEM;
  1108. goto err;
  1109. }
  1110. }
  1111. src_offset += loop_len;
  1112. dst_offset += loop_len;
  1113. remaining_len -= loop_len;
  1114. }
  1115. return ret;
  1116. err:
  1117. dev_err(scif_info.mdev.this_device,
  1118. "%s %d Desc Prog Failed ret %d\n",
  1119. __func__, __LINE__, ret);
  1120. return ret;
  1121. }
  1122. /*
  1123. * scif_rma_list_dma_copy_aligned:
  1124. *
  1125. * Traverse all the windows and perform DMA copy.
  1126. */
  1127. static int scif_rma_list_dma_copy_aligned(struct scif_copy_work *work,
  1128. struct dma_chan *chan)
  1129. {
  1130. dma_addr_t src_dma_addr, dst_dma_addr;
  1131. size_t loop_len, remaining_len, tail_len, src_contig_bytes = 0;
  1132. size_t dst_contig_bytes = 0;
  1133. int src_cache_off;
  1134. s64 end_src_offset, end_dst_offset;
  1135. struct scif_window_iter src_win_iter;
  1136. struct scif_window_iter dst_win_iter;
  1137. void *src_virt, *dst_virt;
  1138. struct scif_window *src_window = work->src_window;
  1139. struct scif_window *dst_window = work->dst_window;
  1140. s64 src_offset = work->src_offset, dst_offset = work->dst_offset;
  1141. int ret = 0;
  1142. struct dma_async_tx_descriptor *tx;
  1143. struct dma_device *dev = chan->device;
  1144. dma_cookie_t cookie;
  1145. remaining_len = work->len;
  1146. scif_init_window_iter(src_window, &src_win_iter);
  1147. scif_init_window_iter(dst_window, &dst_win_iter);
  1148. src_cache_off = src_offset & (L1_CACHE_BYTES - 1);
  1149. if (src_cache_off != 0) {
  1150. /* Head */
  1151. loop_len = L1_CACHE_BYTES - src_cache_off;
  1152. loop_len = min(loop_len, remaining_len);
  1153. src_dma_addr = __scif_off_to_dma_addr(src_window, src_offset);
  1154. dst_dma_addr = __scif_off_to_dma_addr(dst_window, dst_offset);
  1155. if (src_window->type == SCIF_WINDOW_SELF)
  1156. src_virt = _get_local_va(src_offset, src_window,
  1157. loop_len);
  1158. else
  1159. src_virt = ioremap_remote(src_offset, src_window,
  1160. loop_len,
  1161. work->remote_dev, NULL);
  1162. if (!src_virt)
  1163. return -ENOMEM;
  1164. if (dst_window->type == SCIF_WINDOW_SELF)
  1165. dst_virt = _get_local_va(dst_offset, dst_window,
  1166. loop_len);
  1167. else
  1168. dst_virt = ioremap_remote(dst_offset, dst_window,
  1169. loop_len,
  1170. work->remote_dev, NULL);
  1171. if (!dst_virt) {
  1172. if (src_window->type != SCIF_WINDOW_SELF)
  1173. iounmap_remote(src_virt, loop_len, work);
  1174. return -ENOMEM;
  1175. }
  1176. if (src_window->type == SCIF_WINDOW_SELF)
  1177. scif_unaligned_cpy_toio(dst_virt, src_virt, loop_len,
  1178. remaining_len == loop_len ?
  1179. work->ordered : false);
  1180. else
  1181. scif_unaligned_cpy_fromio(dst_virt, src_virt, loop_len,
  1182. remaining_len == loop_len ?
  1183. work->ordered : false);
  1184. if (src_window->type != SCIF_WINDOW_SELF)
  1185. iounmap_remote(src_virt, loop_len, work);
  1186. if (dst_window->type != SCIF_WINDOW_SELF)
  1187. iounmap_remote(dst_virt, loop_len, work);
  1188. src_offset += loop_len;
  1189. dst_offset += loop_len;
  1190. remaining_len -= loop_len;
  1191. }
  1192. end_src_offset = src_window->offset +
  1193. (src_window->nr_pages << PAGE_SHIFT);
  1194. end_dst_offset = dst_window->offset +
  1195. (dst_window->nr_pages << PAGE_SHIFT);
  1196. tail_len = remaining_len & (L1_CACHE_BYTES - 1);
  1197. remaining_len -= tail_len;
  1198. while (remaining_len) {
  1199. if (src_offset == end_src_offset) {
  1200. src_window = list_next_entry(src_window, list);
  1201. end_src_offset = src_window->offset +
  1202. (src_window->nr_pages << PAGE_SHIFT);
  1203. scif_init_window_iter(src_window, &src_win_iter);
  1204. }
  1205. if (dst_offset == end_dst_offset) {
  1206. dst_window = list_next_entry(dst_window, list);
  1207. end_dst_offset = dst_window->offset +
  1208. (dst_window->nr_pages << PAGE_SHIFT);
  1209. scif_init_window_iter(dst_window, &dst_win_iter);
  1210. }
  1211. /* compute dma addresses for transfer */
  1212. src_dma_addr = scif_off_to_dma_addr(src_window, src_offset,
  1213. &src_contig_bytes,
  1214. &src_win_iter);
  1215. dst_dma_addr = scif_off_to_dma_addr(dst_window, dst_offset,
  1216. &dst_contig_bytes,
  1217. &dst_win_iter);
  1218. loop_len = min(src_contig_bytes, dst_contig_bytes);
  1219. loop_len = min(loop_len, remaining_len);
  1220. if (work->ordered && !tail_len &&
  1221. !(remaining_len - loop_len)) {
  1222. /*
  1223. * Break up the last chunk of the transfer into two
  1224. * steps. if there is no tail to gurantee DMA ordering.
  1225. * Passing SCIF_DMA_POLLING inserts a status update
  1226. * descriptor in step 1 which acts as a double sided
  1227. * synchronization fence for the DMA engine to ensure
  1228. * that the last cache line in step 2 is updated last.
  1229. */
  1230. /* Step 1) DMA: Body Length - L1_CACHE_BYTES. */
  1231. tx = dev->device_prep_dma_memcpy(chan, dst_dma_addr,
  1232. src_dma_addr,
  1233. loop_len -
  1234. L1_CACHE_BYTES,
  1235. DMA_PREP_FENCE);
  1236. if (!tx) {
  1237. ret = -ENOMEM;
  1238. goto err;
  1239. }
  1240. cookie = tx->tx_submit(tx);
  1241. if (dma_submit_error(cookie)) {
  1242. ret = -ENOMEM;
  1243. goto err;
  1244. }
  1245. dma_async_issue_pending(chan);
  1246. src_offset += (loop_len - L1_CACHE_BYTES);
  1247. dst_offset += (loop_len - L1_CACHE_BYTES);
  1248. src_dma_addr += (loop_len - L1_CACHE_BYTES);
  1249. dst_dma_addr += (loop_len - L1_CACHE_BYTES);
  1250. remaining_len -= (loop_len - L1_CACHE_BYTES);
  1251. loop_len = remaining_len;
  1252. /* Step 2) DMA: L1_CACHE_BYTES */
  1253. tx = dev->device_prep_dma_memcpy(chan, dst_dma_addr,
  1254. src_dma_addr,
  1255. loop_len, 0);
  1256. if (!tx) {
  1257. ret = -ENOMEM;
  1258. goto err;
  1259. }
  1260. cookie = tx->tx_submit(tx);
  1261. if (dma_submit_error(cookie)) {
  1262. ret = -ENOMEM;
  1263. goto err;
  1264. }
  1265. dma_async_issue_pending(chan);
  1266. } else {
  1267. tx = dev->device_prep_dma_memcpy(chan, dst_dma_addr,
  1268. src_dma_addr,
  1269. loop_len, 0);
  1270. if (!tx) {
  1271. ret = -ENOMEM;
  1272. goto err;
  1273. }
  1274. cookie = tx->tx_submit(tx);
  1275. if (dma_submit_error(cookie)) {
  1276. ret = -ENOMEM;
  1277. goto err;
  1278. }
  1279. dma_async_issue_pending(chan);
  1280. }
  1281. src_offset += loop_len;
  1282. dst_offset += loop_len;
  1283. remaining_len -= loop_len;
  1284. }
  1285. remaining_len = tail_len;
  1286. if (remaining_len) {
  1287. loop_len = remaining_len;
  1288. if (src_offset == end_src_offset)
  1289. src_window = list_next_entry(src_window, list);
  1290. if (dst_offset == end_dst_offset)
  1291. dst_window = list_next_entry(dst_window, list);
  1292. src_dma_addr = __scif_off_to_dma_addr(src_window, src_offset);
  1293. dst_dma_addr = __scif_off_to_dma_addr(dst_window, dst_offset);
  1294. /*
  1295. * The CPU copy for the tail bytes must be initiated only once
  1296. * previous DMA transfers for this endpoint have completed to
  1297. * guarantee ordering.
  1298. */
  1299. if (work->ordered) {
  1300. struct scif_dev *rdev = work->remote_dev;
  1301. ret = scif_drain_dma_poll(rdev->sdev, chan);
  1302. if (ret)
  1303. return ret;
  1304. }
  1305. if (src_window->type == SCIF_WINDOW_SELF)
  1306. src_virt = _get_local_va(src_offset, src_window,
  1307. loop_len);
  1308. else
  1309. src_virt = ioremap_remote(src_offset, src_window,
  1310. loop_len,
  1311. work->remote_dev, NULL);
  1312. if (!src_virt)
  1313. return -ENOMEM;
  1314. if (dst_window->type == SCIF_WINDOW_SELF)
  1315. dst_virt = _get_local_va(dst_offset, dst_window,
  1316. loop_len);
  1317. else
  1318. dst_virt = ioremap_remote(dst_offset, dst_window,
  1319. loop_len,
  1320. work->remote_dev, NULL);
  1321. if (!dst_virt) {
  1322. if (src_window->type != SCIF_WINDOW_SELF)
  1323. iounmap_remote(src_virt, loop_len, work);
  1324. return -ENOMEM;
  1325. }
  1326. if (src_window->type == SCIF_WINDOW_SELF)
  1327. scif_unaligned_cpy_toio(dst_virt, src_virt, loop_len,
  1328. work->ordered);
  1329. else
  1330. scif_unaligned_cpy_fromio(dst_virt, src_virt,
  1331. loop_len, work->ordered);
  1332. if (src_window->type != SCIF_WINDOW_SELF)
  1333. iounmap_remote(src_virt, loop_len, work);
  1334. if (dst_window->type != SCIF_WINDOW_SELF)
  1335. iounmap_remote(dst_virt, loop_len, work);
  1336. remaining_len -= loop_len;
  1337. }
  1338. return ret;
  1339. err:
  1340. dev_err(scif_info.mdev.this_device,
  1341. "%s %d Desc Prog Failed ret %d\n",
  1342. __func__, __LINE__, ret);
  1343. return ret;
  1344. }
  1345. /*
  1346. * scif_rma_list_cpu_copy:
  1347. *
  1348. * Traverse all the windows and perform CPU copy.
  1349. */
  1350. static int scif_rma_list_cpu_copy(struct scif_copy_work *work)
  1351. {
  1352. void *src_virt, *dst_virt;
  1353. size_t loop_len, remaining_len;
  1354. int src_page_off, dst_page_off;
  1355. s64 src_offset = work->src_offset, dst_offset = work->dst_offset;
  1356. struct scif_window *src_window = work->src_window;
  1357. struct scif_window *dst_window = work->dst_window;
  1358. s64 end_src_offset, end_dst_offset;
  1359. int ret = 0;
  1360. struct scif_window_iter src_win_iter;
  1361. struct scif_window_iter dst_win_iter;
  1362. remaining_len = work->len;
  1363. scif_init_window_iter(src_window, &src_win_iter);
  1364. scif_init_window_iter(dst_window, &dst_win_iter);
  1365. while (remaining_len) {
  1366. src_page_off = src_offset & ~PAGE_MASK;
  1367. dst_page_off = dst_offset & ~PAGE_MASK;
  1368. loop_len = min(PAGE_SIZE -
  1369. max(src_page_off, dst_page_off),
  1370. remaining_len);
  1371. if (src_window->type == SCIF_WINDOW_SELF)
  1372. src_virt = _get_local_va(src_offset, src_window,
  1373. loop_len);
  1374. else
  1375. src_virt = ioremap_remote(src_offset, src_window,
  1376. loop_len,
  1377. work->remote_dev,
  1378. &src_win_iter);
  1379. if (!src_virt) {
  1380. ret = -ENOMEM;
  1381. goto error;
  1382. }
  1383. if (dst_window->type == SCIF_WINDOW_SELF)
  1384. dst_virt = _get_local_va(dst_offset, dst_window,
  1385. loop_len);
  1386. else
  1387. dst_virt = ioremap_remote(dst_offset, dst_window,
  1388. loop_len,
  1389. work->remote_dev,
  1390. &dst_win_iter);
  1391. if (!dst_virt) {
  1392. if (src_window->type == SCIF_WINDOW_PEER)
  1393. iounmap_remote(src_virt, loop_len, work);
  1394. ret = -ENOMEM;
  1395. goto error;
  1396. }
  1397. if (work->loopback) {
  1398. memcpy(dst_virt, src_virt, loop_len);
  1399. } else {
  1400. if (src_window->type == SCIF_WINDOW_SELF)
  1401. memcpy_toio((void __iomem __force *)dst_virt,
  1402. src_virt, loop_len);
  1403. else
  1404. memcpy_fromio(dst_virt,
  1405. (void __iomem __force *)src_virt,
  1406. loop_len);
  1407. }
  1408. if (src_window->type == SCIF_WINDOW_PEER)
  1409. iounmap_remote(src_virt, loop_len, work);
  1410. if (dst_window->type == SCIF_WINDOW_PEER)
  1411. iounmap_remote(dst_virt, loop_len, work);
  1412. src_offset += loop_len;
  1413. dst_offset += loop_len;
  1414. remaining_len -= loop_len;
  1415. if (remaining_len) {
  1416. end_src_offset = src_window->offset +
  1417. (src_window->nr_pages << PAGE_SHIFT);
  1418. end_dst_offset = dst_window->offset +
  1419. (dst_window->nr_pages << PAGE_SHIFT);
  1420. if (src_offset == end_src_offset) {
  1421. src_window = list_next_entry(src_window, list);
  1422. scif_init_window_iter(src_window,
  1423. &src_win_iter);
  1424. }
  1425. if (dst_offset == end_dst_offset) {
  1426. dst_window = list_next_entry(dst_window, list);
  1427. scif_init_window_iter(dst_window,
  1428. &dst_win_iter);
  1429. }
  1430. }
  1431. }
  1432. error:
  1433. return ret;
  1434. }
  1435. static int scif_rma_list_dma_copy_wrapper(struct scif_endpt *epd,
  1436. struct scif_copy_work *work,
  1437. struct dma_chan *chan, off_t loffset)
  1438. {
  1439. int src_cache_off, dst_cache_off;
  1440. s64 src_offset = work->src_offset, dst_offset = work->dst_offset;
  1441. u8 *temp = NULL;
  1442. bool src_local = true, dst_local = false;
  1443. struct scif_dma_comp_cb *comp_cb;
  1444. dma_addr_t src_dma_addr, dst_dma_addr;
  1445. int err;
  1446. if (is_dma_copy_aligned(chan->device, 1, 1, 1))
  1447. return _scif_rma_list_dma_copy_aligned(work, chan);
  1448. src_cache_off = src_offset & (L1_CACHE_BYTES - 1);
  1449. dst_cache_off = dst_offset & (L1_CACHE_BYTES - 1);
  1450. if (dst_cache_off == src_cache_off)
  1451. return scif_rma_list_dma_copy_aligned(work, chan);
  1452. if (work->loopback)
  1453. return scif_rma_list_cpu_copy(work);
  1454. src_dma_addr = __scif_off_to_dma_addr(work->src_window, src_offset);
  1455. dst_dma_addr = __scif_off_to_dma_addr(work->dst_window, dst_offset);
  1456. src_local = work->src_window->type == SCIF_WINDOW_SELF;
  1457. dst_local = work->dst_window->type == SCIF_WINDOW_SELF;
  1458. dst_local = dst_local;
  1459. /* Allocate dma_completion cb */
  1460. comp_cb = kzalloc(sizeof(*comp_cb), GFP_KERNEL);
  1461. if (!comp_cb)
  1462. goto error;
  1463. work->comp_cb = comp_cb;
  1464. comp_cb->cb_cookie = comp_cb;
  1465. comp_cb->dma_completion_func = &scif_rma_completion_cb;
  1466. if (work->len + (L1_CACHE_BYTES << 1) < SCIF_KMEM_UNALIGNED_BUF_SIZE) {
  1467. comp_cb->is_cache = false;
  1468. /* Allocate padding bytes to align to a cache line */
  1469. temp = kmalloc(work->len + (L1_CACHE_BYTES << 1),
  1470. GFP_KERNEL);
  1471. if (!temp)
  1472. goto free_comp_cb;
  1473. comp_cb->temp_buf_to_free = temp;
  1474. /* kmalloc(..) does not guarantee cache line alignment */
  1475. if (!IS_ALIGNED((u64)temp, L1_CACHE_BYTES))
  1476. temp = PTR_ALIGN(temp, L1_CACHE_BYTES);
  1477. } else {
  1478. comp_cb->is_cache = true;
  1479. temp = kmem_cache_alloc(unaligned_cache, GFP_KERNEL);
  1480. if (!temp)
  1481. goto free_comp_cb;
  1482. comp_cb->temp_buf_to_free = temp;
  1483. }
  1484. if (src_local) {
  1485. temp += dst_cache_off;
  1486. scif_rma_local_cpu_copy(work->src_offset, work->src_window,
  1487. temp, work->len, true);
  1488. } else {
  1489. comp_cb->dst_window = work->dst_window;
  1490. comp_cb->dst_offset = work->dst_offset;
  1491. work->src_offset = work->src_offset - src_cache_off;
  1492. comp_cb->len = work->len;
  1493. work->len = ALIGN(work->len + src_cache_off, L1_CACHE_BYTES);
  1494. comp_cb->header_padding = src_cache_off;
  1495. }
  1496. comp_cb->temp_buf = temp;
  1497. err = scif_map_single(&comp_cb->temp_phys, temp,
  1498. work->remote_dev, SCIF_KMEM_UNALIGNED_BUF_SIZE);
  1499. if (err)
  1500. goto free_temp_buf;
  1501. comp_cb->sdev = work->remote_dev;
  1502. if (scif_rma_list_dma_copy_unaligned(work, temp, chan, src_local) < 0)
  1503. goto free_temp_buf;
  1504. if (!src_local)
  1505. work->fence_type = SCIF_DMA_INTR;
  1506. return 0;
  1507. free_temp_buf:
  1508. if (comp_cb->is_cache)
  1509. kmem_cache_free(unaligned_cache, comp_cb->temp_buf_to_free);
  1510. else
  1511. kfree(comp_cb->temp_buf_to_free);
  1512. free_comp_cb:
  1513. kfree(comp_cb);
  1514. error:
  1515. return -ENOMEM;
  1516. }
  1517. /**
  1518. * scif_rma_copy:
  1519. * @epd: end point descriptor.
  1520. * @loffset: offset in local registered address space to/from which to copy
  1521. * @addr: user virtual address to/from which to copy
  1522. * @len: length of range to copy
  1523. * @roffset: offset in remote registered address space to/from which to copy
  1524. * @flags: flags
  1525. * @dir: LOCAL->REMOTE or vice versa.
  1526. * @last_chunk: true if this is the last chunk of a larger transfer
  1527. *
  1528. * Validate parameters, check if src/dst registered ranges requested for copy
  1529. * are valid and initiate either CPU or DMA copy.
  1530. */
  1531. static int scif_rma_copy(scif_epd_t epd, off_t loffset, unsigned long addr,
  1532. size_t len, off_t roffset, int flags,
  1533. enum scif_rma_dir dir, bool last_chunk)
  1534. {
  1535. struct scif_endpt *ep = (struct scif_endpt *)epd;
  1536. struct scif_rma_req remote_req;
  1537. struct scif_rma_req req;
  1538. struct scif_window *local_window = NULL;
  1539. struct scif_window *remote_window = NULL;
  1540. struct scif_copy_work copy_work;
  1541. bool loopback;
  1542. int err = 0;
  1543. struct dma_chan *chan;
  1544. struct scif_mmu_notif *mmn = NULL;
  1545. bool cache = false;
  1546. struct device *spdev;
  1547. err = scif_verify_epd(ep);
  1548. if (err)
  1549. return err;
  1550. if (flags && !(flags & (SCIF_RMA_USECPU | SCIF_RMA_USECACHE |
  1551. SCIF_RMA_SYNC | SCIF_RMA_ORDERED)))
  1552. return -EINVAL;
  1553. loopback = scifdev_self(ep->remote_dev) ? true : false;
  1554. copy_work.fence_type = ((flags & SCIF_RMA_SYNC) && last_chunk) ?
  1555. SCIF_DMA_POLL : 0;
  1556. copy_work.ordered = !!((flags & SCIF_RMA_ORDERED) && last_chunk);
  1557. /* Use CPU for Mgmt node <-> Mgmt node copies */
  1558. if (loopback && scif_is_mgmt_node()) {
  1559. flags |= SCIF_RMA_USECPU;
  1560. copy_work.fence_type = 0x0;
  1561. }
  1562. cache = scif_is_set_reg_cache(flags);
  1563. remote_req.out_window = &remote_window;
  1564. remote_req.offset = roffset;
  1565. remote_req.nr_bytes = len;
  1566. /*
  1567. * If transfer is from local to remote then the remote window
  1568. * must be writeable and vice versa.
  1569. */
  1570. remote_req.prot = dir == SCIF_LOCAL_TO_REMOTE ? VM_WRITE : VM_READ;
  1571. remote_req.type = SCIF_WINDOW_PARTIAL;
  1572. remote_req.head = &ep->rma_info.remote_reg_list;
  1573. spdev = scif_get_peer_dev(ep->remote_dev);
  1574. if (IS_ERR(spdev)) {
  1575. err = PTR_ERR(spdev);
  1576. return err;
  1577. }
  1578. if (addr && cache) {
  1579. mutex_lock(&ep->rma_info.mmn_lock);
  1580. mmn = scif_find_mmu_notifier(current->mm, &ep->rma_info);
  1581. if (!mmn)
  1582. mmn = scif_add_mmu_notifier(current->mm, ep);
  1583. mutex_unlock(&ep->rma_info.mmn_lock);
  1584. if (IS_ERR(mmn)) {
  1585. scif_put_peer_dev(spdev);
  1586. return PTR_ERR(mmn);
  1587. }
  1588. cache = cache && !scif_rma_tc_can_cache(ep, len);
  1589. }
  1590. mutex_lock(&ep->rma_info.rma_lock);
  1591. if (addr) {
  1592. req.out_window = &local_window;
  1593. req.nr_bytes = ALIGN(len + (addr & ~PAGE_MASK),
  1594. PAGE_SIZE);
  1595. req.va_for_temp = addr & PAGE_MASK;
  1596. req.prot = (dir == SCIF_LOCAL_TO_REMOTE ?
  1597. VM_READ : VM_WRITE | VM_READ);
  1598. /* Does a valid local window exist? */
  1599. if (mmn) {
  1600. spin_lock(&ep->rma_info.tc_lock);
  1601. req.head = &mmn->tc_reg_list;
  1602. err = scif_query_tcw(ep, &req);
  1603. spin_unlock(&ep->rma_info.tc_lock);
  1604. }
  1605. if (!mmn || err) {
  1606. err = scif_register_temp(epd, req.va_for_temp,
  1607. req.nr_bytes, req.prot,
  1608. &loffset, &local_window);
  1609. if (err) {
  1610. mutex_unlock(&ep->rma_info.rma_lock);
  1611. goto error;
  1612. }
  1613. if (!cache)
  1614. goto skip_cache;
  1615. atomic_inc(&ep->rma_info.tcw_refcount);
  1616. atomic_add_return(local_window->nr_pages,
  1617. &ep->rma_info.tcw_total_pages);
  1618. if (mmn) {
  1619. spin_lock(&ep->rma_info.tc_lock);
  1620. scif_insert_tcw(local_window,
  1621. &mmn->tc_reg_list);
  1622. spin_unlock(&ep->rma_info.tc_lock);
  1623. }
  1624. }
  1625. skip_cache:
  1626. loffset = local_window->offset +
  1627. (addr - local_window->va_for_temp);
  1628. } else {
  1629. req.out_window = &local_window;
  1630. req.offset = loffset;
  1631. /*
  1632. * If transfer is from local to remote then the self window
  1633. * must be readable and vice versa.
  1634. */
  1635. req.prot = dir == SCIF_LOCAL_TO_REMOTE ? VM_READ : VM_WRITE;
  1636. req.nr_bytes = len;
  1637. req.type = SCIF_WINDOW_PARTIAL;
  1638. req.head = &ep->rma_info.reg_list;
  1639. /* Does a valid local window exist? */
  1640. err = scif_query_window(&req);
  1641. if (err) {
  1642. mutex_unlock(&ep->rma_info.rma_lock);
  1643. goto error;
  1644. }
  1645. }
  1646. /* Does a valid remote window exist? */
  1647. err = scif_query_window(&remote_req);
  1648. if (err) {
  1649. mutex_unlock(&ep->rma_info.rma_lock);
  1650. goto error;
  1651. }
  1652. /*
  1653. * Prepare copy_work for submitting work to the DMA kernel thread
  1654. * or CPU copy routine.
  1655. */
  1656. copy_work.len = len;
  1657. copy_work.loopback = loopback;
  1658. copy_work.remote_dev = ep->remote_dev;
  1659. if (dir == SCIF_LOCAL_TO_REMOTE) {
  1660. copy_work.src_offset = loffset;
  1661. copy_work.src_window = local_window;
  1662. copy_work.dst_offset = roffset;
  1663. copy_work.dst_window = remote_window;
  1664. } else {
  1665. copy_work.src_offset = roffset;
  1666. copy_work.src_window = remote_window;
  1667. copy_work.dst_offset = loffset;
  1668. copy_work.dst_window = local_window;
  1669. }
  1670. if (flags & SCIF_RMA_USECPU) {
  1671. scif_rma_list_cpu_copy(&copy_work);
  1672. } else {
  1673. chan = ep->rma_info.dma_chan;
  1674. err = scif_rma_list_dma_copy_wrapper(epd, &copy_work,
  1675. chan, loffset);
  1676. }
  1677. if (addr && !cache)
  1678. atomic_inc(&ep->rma_info.tw_refcount);
  1679. mutex_unlock(&ep->rma_info.rma_lock);
  1680. if (last_chunk) {
  1681. struct scif_dev *rdev = ep->remote_dev;
  1682. if (copy_work.fence_type == SCIF_DMA_POLL)
  1683. err = scif_drain_dma_poll(rdev->sdev,
  1684. ep->rma_info.dma_chan);
  1685. else if (copy_work.fence_type == SCIF_DMA_INTR)
  1686. err = scif_drain_dma_intr(rdev->sdev,
  1687. ep->rma_info.dma_chan);
  1688. }
  1689. if (addr && !cache)
  1690. scif_queue_for_cleanup(local_window, &scif_info.rma);
  1691. scif_put_peer_dev(spdev);
  1692. return err;
  1693. error:
  1694. if (err) {
  1695. if (addr && local_window && !cache)
  1696. scif_destroy_window(ep, local_window);
  1697. dev_err(scif_info.mdev.this_device,
  1698. "%s %d err %d len 0x%lx\n",
  1699. __func__, __LINE__, err, len);
  1700. }
  1701. scif_put_peer_dev(spdev);
  1702. return err;
  1703. }
  1704. int scif_readfrom(scif_epd_t epd, off_t loffset, size_t len,
  1705. off_t roffset, int flags)
  1706. {
  1707. int err;
  1708. dev_dbg(scif_info.mdev.this_device,
  1709. "SCIFAPI readfrom: ep %p loffset 0x%lx len 0x%lx offset 0x%lx flags 0x%x\n",
  1710. epd, loffset, len, roffset, flags);
  1711. if (scif_unaligned(loffset, roffset)) {
  1712. while (len > SCIF_MAX_UNALIGNED_BUF_SIZE) {
  1713. err = scif_rma_copy(epd, loffset, 0x0,
  1714. SCIF_MAX_UNALIGNED_BUF_SIZE,
  1715. roffset, flags,
  1716. SCIF_REMOTE_TO_LOCAL, false);
  1717. if (err)
  1718. goto readfrom_err;
  1719. loffset += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1720. roffset += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1721. len -= SCIF_MAX_UNALIGNED_BUF_SIZE;
  1722. }
  1723. }
  1724. err = scif_rma_copy(epd, loffset, 0x0, len,
  1725. roffset, flags, SCIF_REMOTE_TO_LOCAL, true);
  1726. readfrom_err:
  1727. return err;
  1728. }
  1729. EXPORT_SYMBOL_GPL(scif_readfrom);
  1730. int scif_writeto(scif_epd_t epd, off_t loffset, size_t len,
  1731. off_t roffset, int flags)
  1732. {
  1733. int err;
  1734. dev_dbg(scif_info.mdev.this_device,
  1735. "SCIFAPI writeto: ep %p loffset 0x%lx len 0x%lx roffset 0x%lx flags 0x%x\n",
  1736. epd, loffset, len, roffset, flags);
  1737. if (scif_unaligned(loffset, roffset)) {
  1738. while (len > SCIF_MAX_UNALIGNED_BUF_SIZE) {
  1739. err = scif_rma_copy(epd, loffset, 0x0,
  1740. SCIF_MAX_UNALIGNED_BUF_SIZE,
  1741. roffset, flags,
  1742. SCIF_LOCAL_TO_REMOTE, false);
  1743. if (err)
  1744. goto writeto_err;
  1745. loffset += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1746. roffset += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1747. len -= SCIF_MAX_UNALIGNED_BUF_SIZE;
  1748. }
  1749. }
  1750. err = scif_rma_copy(epd, loffset, 0x0, len,
  1751. roffset, flags, SCIF_LOCAL_TO_REMOTE, true);
  1752. writeto_err:
  1753. return err;
  1754. }
  1755. EXPORT_SYMBOL_GPL(scif_writeto);
  1756. int scif_vreadfrom(scif_epd_t epd, void *addr, size_t len,
  1757. off_t roffset, int flags)
  1758. {
  1759. int err;
  1760. dev_dbg(scif_info.mdev.this_device,
  1761. "SCIFAPI vreadfrom: ep %p addr %p len 0x%lx roffset 0x%lx flags 0x%x\n",
  1762. epd, addr, len, roffset, flags);
  1763. if (scif_unaligned((off_t __force)addr, roffset)) {
  1764. if (len > SCIF_MAX_UNALIGNED_BUF_SIZE)
  1765. flags &= ~SCIF_RMA_USECACHE;
  1766. while (len > SCIF_MAX_UNALIGNED_BUF_SIZE) {
  1767. err = scif_rma_copy(epd, 0, (u64)addr,
  1768. SCIF_MAX_UNALIGNED_BUF_SIZE,
  1769. roffset, flags,
  1770. SCIF_REMOTE_TO_LOCAL, false);
  1771. if (err)
  1772. goto vreadfrom_err;
  1773. addr += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1774. roffset += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1775. len -= SCIF_MAX_UNALIGNED_BUF_SIZE;
  1776. }
  1777. }
  1778. err = scif_rma_copy(epd, 0, (u64)addr, len,
  1779. roffset, flags, SCIF_REMOTE_TO_LOCAL, true);
  1780. vreadfrom_err:
  1781. return err;
  1782. }
  1783. EXPORT_SYMBOL_GPL(scif_vreadfrom);
  1784. int scif_vwriteto(scif_epd_t epd, void *addr, size_t len,
  1785. off_t roffset, int flags)
  1786. {
  1787. int err;
  1788. dev_dbg(scif_info.mdev.this_device,
  1789. "SCIFAPI vwriteto: ep %p addr %p len 0x%lx roffset 0x%lx flags 0x%x\n",
  1790. epd, addr, len, roffset, flags);
  1791. if (scif_unaligned((off_t __force)addr, roffset)) {
  1792. if (len > SCIF_MAX_UNALIGNED_BUF_SIZE)
  1793. flags &= ~SCIF_RMA_USECACHE;
  1794. while (len > SCIF_MAX_UNALIGNED_BUF_SIZE) {
  1795. err = scif_rma_copy(epd, 0, (u64)addr,
  1796. SCIF_MAX_UNALIGNED_BUF_SIZE,
  1797. roffset, flags,
  1798. SCIF_LOCAL_TO_REMOTE, false);
  1799. if (err)
  1800. goto vwriteto_err;
  1801. addr += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1802. roffset += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1803. len -= SCIF_MAX_UNALIGNED_BUF_SIZE;
  1804. }
  1805. }
  1806. err = scif_rma_copy(epd, 0, (u64)addr, len,
  1807. roffset, flags, SCIF_LOCAL_TO_REMOTE, true);
  1808. vwriteto_err:
  1809. return err;
  1810. }
  1811. EXPORT_SYMBOL_GPL(scif_vwriteto);