core.c 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005
  1. /*
  2. * Silicon Labs C2 port core Linux support
  3. *
  4. * Copyright (c) 2007 Rodolfo Giometti <giometti@linux.it>
  5. * Copyright (c) 2007 Eurotech S.p.A. <info@eurotech.it>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation
  10. */
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/device.h>
  14. #include <linux/errno.h>
  15. #include <linux/err.h>
  16. #include <linux/kernel.h>
  17. #include <linux/kmemcheck.h>
  18. #include <linux/ctype.h>
  19. #include <linux/delay.h>
  20. #include <linux/idr.h>
  21. #include <linux/sched.h>
  22. #include <linux/slab.h>
  23. #include <linux/c2port.h>
  24. #define DRIVER_NAME "c2port"
  25. #define DRIVER_VERSION "0.51.0"
  26. static DEFINE_SPINLOCK(c2port_idr_lock);
  27. static DEFINE_IDR(c2port_idr);
  28. /*
  29. * Local variables
  30. */
  31. static struct class *c2port_class;
  32. /*
  33. * C2 registers & commands defines
  34. */
  35. /* C2 registers */
  36. #define C2PORT_DEVICEID 0x00
  37. #define C2PORT_REVID 0x01
  38. #define C2PORT_FPCTL 0x02
  39. #define C2PORT_FPDAT 0xB4
  40. /* C2 interface commands */
  41. #define C2PORT_GET_VERSION 0x01
  42. #define C2PORT_DEVICE_ERASE 0x03
  43. #define C2PORT_BLOCK_READ 0x06
  44. #define C2PORT_BLOCK_WRITE 0x07
  45. #define C2PORT_PAGE_ERASE 0x08
  46. /* C2 status return codes */
  47. #define C2PORT_INVALID_COMMAND 0x00
  48. #define C2PORT_COMMAND_FAILED 0x02
  49. #define C2PORT_COMMAND_OK 0x0d
  50. /*
  51. * C2 port low level signal managements
  52. */
  53. static void c2port_reset(struct c2port_device *dev)
  54. {
  55. struct c2port_ops *ops = dev->ops;
  56. /* To reset the device we have to keep clock line low for at least
  57. * 20us.
  58. */
  59. local_irq_disable();
  60. ops->c2ck_set(dev, 0);
  61. udelay(25);
  62. ops->c2ck_set(dev, 1);
  63. local_irq_enable();
  64. udelay(1);
  65. }
  66. static void c2port_strobe_ck(struct c2port_device *dev)
  67. {
  68. struct c2port_ops *ops = dev->ops;
  69. /* During hi-low-hi transition we disable local IRQs to avoid
  70. * interructions since C2 port specification says that it must be
  71. * shorter than 5us, otherwise the microcontroller may consider
  72. * it as a reset signal!
  73. */
  74. local_irq_disable();
  75. ops->c2ck_set(dev, 0);
  76. udelay(1);
  77. ops->c2ck_set(dev, 1);
  78. local_irq_enable();
  79. udelay(1);
  80. }
  81. /*
  82. * C2 port basic functions
  83. */
  84. static void c2port_write_ar(struct c2port_device *dev, u8 addr)
  85. {
  86. struct c2port_ops *ops = dev->ops;
  87. int i;
  88. /* START field */
  89. c2port_strobe_ck(dev);
  90. /* INS field (11b, LSB first) */
  91. ops->c2d_dir(dev, 0);
  92. ops->c2d_set(dev, 1);
  93. c2port_strobe_ck(dev);
  94. ops->c2d_set(dev, 1);
  95. c2port_strobe_ck(dev);
  96. /* ADDRESS field */
  97. for (i = 0; i < 8; i++) {
  98. ops->c2d_set(dev, addr & 0x01);
  99. c2port_strobe_ck(dev);
  100. addr >>= 1;
  101. }
  102. /* STOP field */
  103. ops->c2d_dir(dev, 1);
  104. c2port_strobe_ck(dev);
  105. }
  106. static int c2port_read_ar(struct c2port_device *dev, u8 *addr)
  107. {
  108. struct c2port_ops *ops = dev->ops;
  109. int i;
  110. /* START field */
  111. c2port_strobe_ck(dev);
  112. /* INS field (10b, LSB first) */
  113. ops->c2d_dir(dev, 0);
  114. ops->c2d_set(dev, 0);
  115. c2port_strobe_ck(dev);
  116. ops->c2d_set(dev, 1);
  117. c2port_strobe_ck(dev);
  118. /* ADDRESS field */
  119. ops->c2d_dir(dev, 1);
  120. *addr = 0;
  121. for (i = 0; i < 8; i++) {
  122. *addr >>= 1; /* shift in 8-bit ADDRESS field LSB first */
  123. c2port_strobe_ck(dev);
  124. if (ops->c2d_get(dev))
  125. *addr |= 0x80;
  126. }
  127. /* STOP field */
  128. c2port_strobe_ck(dev);
  129. return 0;
  130. }
  131. static int c2port_write_dr(struct c2port_device *dev, u8 data)
  132. {
  133. struct c2port_ops *ops = dev->ops;
  134. int timeout, i;
  135. /* START field */
  136. c2port_strobe_ck(dev);
  137. /* INS field (01b, LSB first) */
  138. ops->c2d_dir(dev, 0);
  139. ops->c2d_set(dev, 1);
  140. c2port_strobe_ck(dev);
  141. ops->c2d_set(dev, 0);
  142. c2port_strobe_ck(dev);
  143. /* LENGTH field (00b, LSB first -> 1 byte) */
  144. ops->c2d_set(dev, 0);
  145. c2port_strobe_ck(dev);
  146. ops->c2d_set(dev, 0);
  147. c2port_strobe_ck(dev);
  148. /* DATA field */
  149. for (i = 0; i < 8; i++) {
  150. ops->c2d_set(dev, data & 0x01);
  151. c2port_strobe_ck(dev);
  152. data >>= 1;
  153. }
  154. /* WAIT field */
  155. ops->c2d_dir(dev, 1);
  156. timeout = 20;
  157. do {
  158. c2port_strobe_ck(dev);
  159. if (ops->c2d_get(dev))
  160. break;
  161. udelay(1);
  162. } while (--timeout > 0);
  163. if (timeout == 0)
  164. return -EIO;
  165. /* STOP field */
  166. c2port_strobe_ck(dev);
  167. return 0;
  168. }
  169. static int c2port_read_dr(struct c2port_device *dev, u8 *data)
  170. {
  171. struct c2port_ops *ops = dev->ops;
  172. int timeout, i;
  173. /* START field */
  174. c2port_strobe_ck(dev);
  175. /* INS field (00b, LSB first) */
  176. ops->c2d_dir(dev, 0);
  177. ops->c2d_set(dev, 0);
  178. c2port_strobe_ck(dev);
  179. ops->c2d_set(dev, 0);
  180. c2port_strobe_ck(dev);
  181. /* LENGTH field (00b, LSB first -> 1 byte) */
  182. ops->c2d_set(dev, 0);
  183. c2port_strobe_ck(dev);
  184. ops->c2d_set(dev, 0);
  185. c2port_strobe_ck(dev);
  186. /* WAIT field */
  187. ops->c2d_dir(dev, 1);
  188. timeout = 20;
  189. do {
  190. c2port_strobe_ck(dev);
  191. if (ops->c2d_get(dev))
  192. break;
  193. udelay(1);
  194. } while (--timeout > 0);
  195. if (timeout == 0)
  196. return -EIO;
  197. /* DATA field */
  198. *data = 0;
  199. for (i = 0; i < 8; i++) {
  200. *data >>= 1; /* shift in 8-bit DATA field LSB first */
  201. c2port_strobe_ck(dev);
  202. if (ops->c2d_get(dev))
  203. *data |= 0x80;
  204. }
  205. /* STOP field */
  206. c2port_strobe_ck(dev);
  207. return 0;
  208. }
  209. static int c2port_poll_in_busy(struct c2port_device *dev)
  210. {
  211. u8 addr;
  212. int ret, timeout = 20;
  213. do {
  214. ret = (c2port_read_ar(dev, &addr));
  215. if (ret < 0)
  216. return -EIO;
  217. if (!(addr & 0x02))
  218. break;
  219. udelay(1);
  220. } while (--timeout > 0);
  221. if (timeout == 0)
  222. return -EIO;
  223. return 0;
  224. }
  225. static int c2port_poll_out_ready(struct c2port_device *dev)
  226. {
  227. u8 addr;
  228. int ret, timeout = 10000; /* erase flash needs long time... */
  229. do {
  230. ret = (c2port_read_ar(dev, &addr));
  231. if (ret < 0)
  232. return -EIO;
  233. if (addr & 0x01)
  234. break;
  235. udelay(1);
  236. } while (--timeout > 0);
  237. if (timeout == 0)
  238. return -EIO;
  239. return 0;
  240. }
  241. /*
  242. * sysfs methods
  243. */
  244. static ssize_t c2port_show_name(struct device *dev,
  245. struct device_attribute *attr, char *buf)
  246. {
  247. struct c2port_device *c2dev = dev_get_drvdata(dev);
  248. return sprintf(buf, "%s\n", c2dev->name);
  249. }
  250. static DEVICE_ATTR(name, 0444, c2port_show_name, NULL);
  251. static ssize_t c2port_show_flash_blocks_num(struct device *dev,
  252. struct device_attribute *attr, char *buf)
  253. {
  254. struct c2port_device *c2dev = dev_get_drvdata(dev);
  255. struct c2port_ops *ops = c2dev->ops;
  256. return sprintf(buf, "%d\n", ops->blocks_num);
  257. }
  258. static DEVICE_ATTR(flash_blocks_num, 0444, c2port_show_flash_blocks_num, NULL);
  259. static ssize_t c2port_show_flash_block_size(struct device *dev,
  260. struct device_attribute *attr, char *buf)
  261. {
  262. struct c2port_device *c2dev = dev_get_drvdata(dev);
  263. struct c2port_ops *ops = c2dev->ops;
  264. return sprintf(buf, "%d\n", ops->block_size);
  265. }
  266. static DEVICE_ATTR(flash_block_size, 0444, c2port_show_flash_block_size, NULL);
  267. static ssize_t c2port_show_flash_size(struct device *dev,
  268. struct device_attribute *attr, char *buf)
  269. {
  270. struct c2port_device *c2dev = dev_get_drvdata(dev);
  271. struct c2port_ops *ops = c2dev->ops;
  272. return sprintf(buf, "%d\n", ops->blocks_num * ops->block_size);
  273. }
  274. static DEVICE_ATTR(flash_size, 0444, c2port_show_flash_size, NULL);
  275. static ssize_t access_show(struct device *dev, struct device_attribute *attr,
  276. char *buf)
  277. {
  278. struct c2port_device *c2dev = dev_get_drvdata(dev);
  279. return sprintf(buf, "%d\n", c2dev->access);
  280. }
  281. static ssize_t access_store(struct device *dev, struct device_attribute *attr,
  282. const char *buf, size_t count)
  283. {
  284. struct c2port_device *c2dev = dev_get_drvdata(dev);
  285. struct c2port_ops *ops = c2dev->ops;
  286. int status, ret;
  287. ret = sscanf(buf, "%d", &status);
  288. if (ret != 1)
  289. return -EINVAL;
  290. mutex_lock(&c2dev->mutex);
  291. c2dev->access = !!status;
  292. /* If access is "on" clock should be HIGH _before_ setting the line
  293. * as output and data line should be set as INPUT anyway */
  294. if (c2dev->access)
  295. ops->c2ck_set(c2dev, 1);
  296. ops->access(c2dev, c2dev->access);
  297. if (c2dev->access)
  298. ops->c2d_dir(c2dev, 1);
  299. mutex_unlock(&c2dev->mutex);
  300. return count;
  301. }
  302. static DEVICE_ATTR_RW(access);
  303. static ssize_t c2port_store_reset(struct device *dev,
  304. struct device_attribute *attr,
  305. const char *buf, size_t count)
  306. {
  307. struct c2port_device *c2dev = dev_get_drvdata(dev);
  308. /* Check the device access status */
  309. if (!c2dev->access)
  310. return -EBUSY;
  311. mutex_lock(&c2dev->mutex);
  312. c2port_reset(c2dev);
  313. c2dev->flash_access = 0;
  314. mutex_unlock(&c2dev->mutex);
  315. return count;
  316. }
  317. static DEVICE_ATTR(reset, 0200, NULL, c2port_store_reset);
  318. static ssize_t __c2port_show_dev_id(struct c2port_device *dev, char *buf)
  319. {
  320. u8 data;
  321. int ret;
  322. /* Select DEVICEID register for C2 data register accesses */
  323. c2port_write_ar(dev, C2PORT_DEVICEID);
  324. /* Read and return the device ID register */
  325. ret = c2port_read_dr(dev, &data);
  326. if (ret < 0)
  327. return ret;
  328. return sprintf(buf, "%d\n", data);
  329. }
  330. static ssize_t c2port_show_dev_id(struct device *dev,
  331. struct device_attribute *attr, char *buf)
  332. {
  333. struct c2port_device *c2dev = dev_get_drvdata(dev);
  334. ssize_t ret;
  335. /* Check the device access status */
  336. if (!c2dev->access)
  337. return -EBUSY;
  338. mutex_lock(&c2dev->mutex);
  339. ret = __c2port_show_dev_id(c2dev, buf);
  340. mutex_unlock(&c2dev->mutex);
  341. if (ret < 0)
  342. dev_err(dev, "cannot read from %s\n", c2dev->name);
  343. return ret;
  344. }
  345. static DEVICE_ATTR(dev_id, 0444, c2port_show_dev_id, NULL);
  346. static ssize_t __c2port_show_rev_id(struct c2port_device *dev, char *buf)
  347. {
  348. u8 data;
  349. int ret;
  350. /* Select REVID register for C2 data register accesses */
  351. c2port_write_ar(dev, C2PORT_REVID);
  352. /* Read and return the revision ID register */
  353. ret = c2port_read_dr(dev, &data);
  354. if (ret < 0)
  355. return ret;
  356. return sprintf(buf, "%d\n", data);
  357. }
  358. static ssize_t c2port_show_rev_id(struct device *dev,
  359. struct device_attribute *attr, char *buf)
  360. {
  361. struct c2port_device *c2dev = dev_get_drvdata(dev);
  362. ssize_t ret;
  363. /* Check the device access status */
  364. if (!c2dev->access)
  365. return -EBUSY;
  366. mutex_lock(&c2dev->mutex);
  367. ret = __c2port_show_rev_id(c2dev, buf);
  368. mutex_unlock(&c2dev->mutex);
  369. if (ret < 0)
  370. dev_err(c2dev->dev, "cannot read from %s\n", c2dev->name);
  371. return ret;
  372. }
  373. static DEVICE_ATTR(rev_id, 0444, c2port_show_rev_id, NULL);
  374. static ssize_t c2port_show_flash_access(struct device *dev,
  375. struct device_attribute *attr, char *buf)
  376. {
  377. struct c2port_device *c2dev = dev_get_drvdata(dev);
  378. return sprintf(buf, "%d\n", c2dev->flash_access);
  379. }
  380. static ssize_t __c2port_store_flash_access(struct c2port_device *dev,
  381. int status)
  382. {
  383. int ret;
  384. /* Check the device access status */
  385. if (!dev->access)
  386. return -EBUSY;
  387. dev->flash_access = !!status;
  388. /* If flash_access is off we have nothing to do... */
  389. if (dev->flash_access == 0)
  390. return 0;
  391. /* Target the C2 flash programming control register for C2 data
  392. * register access */
  393. c2port_write_ar(dev, C2PORT_FPCTL);
  394. /* Write the first keycode to enable C2 Flash programming */
  395. ret = c2port_write_dr(dev, 0x02);
  396. if (ret < 0)
  397. return ret;
  398. /* Write the second keycode to enable C2 Flash programming */
  399. ret = c2port_write_dr(dev, 0x01);
  400. if (ret < 0)
  401. return ret;
  402. /* Delay for at least 20ms to ensure the target is ready for
  403. * C2 flash programming */
  404. mdelay(25);
  405. return 0;
  406. }
  407. static ssize_t c2port_store_flash_access(struct device *dev,
  408. struct device_attribute *attr,
  409. const char *buf, size_t count)
  410. {
  411. struct c2port_device *c2dev = dev_get_drvdata(dev);
  412. int status;
  413. ssize_t ret;
  414. ret = sscanf(buf, "%d", &status);
  415. if (ret != 1)
  416. return -EINVAL;
  417. mutex_lock(&c2dev->mutex);
  418. ret = __c2port_store_flash_access(c2dev, status);
  419. mutex_unlock(&c2dev->mutex);
  420. if (ret < 0) {
  421. dev_err(c2dev->dev, "cannot enable %s flash programming\n",
  422. c2dev->name);
  423. return ret;
  424. }
  425. return count;
  426. }
  427. static DEVICE_ATTR(flash_access, 0644, c2port_show_flash_access,
  428. c2port_store_flash_access);
  429. static ssize_t __c2port_write_flash_erase(struct c2port_device *dev)
  430. {
  431. u8 status;
  432. int ret;
  433. /* Target the C2 flash programming data register for C2 data register
  434. * access.
  435. */
  436. c2port_write_ar(dev, C2PORT_FPDAT);
  437. /* Send device erase command */
  438. c2port_write_dr(dev, C2PORT_DEVICE_ERASE);
  439. /* Wait for input acknowledge */
  440. ret = c2port_poll_in_busy(dev);
  441. if (ret < 0)
  442. return ret;
  443. /* Should check status before starting FLASH access sequence */
  444. /* Wait for status information */
  445. ret = c2port_poll_out_ready(dev);
  446. if (ret < 0)
  447. return ret;
  448. /* Read flash programming interface status */
  449. ret = c2port_read_dr(dev, &status);
  450. if (ret < 0)
  451. return ret;
  452. if (status != C2PORT_COMMAND_OK)
  453. return -EBUSY;
  454. /* Send a three-byte arming sequence to enable the device erase.
  455. * If the sequence is not received correctly, the command will be
  456. * ignored.
  457. * Sequence is: 0xde, 0xad, 0xa5.
  458. */
  459. c2port_write_dr(dev, 0xde);
  460. ret = c2port_poll_in_busy(dev);
  461. if (ret < 0)
  462. return ret;
  463. c2port_write_dr(dev, 0xad);
  464. ret = c2port_poll_in_busy(dev);
  465. if (ret < 0)
  466. return ret;
  467. c2port_write_dr(dev, 0xa5);
  468. ret = c2port_poll_in_busy(dev);
  469. if (ret < 0)
  470. return ret;
  471. ret = c2port_poll_out_ready(dev);
  472. if (ret < 0)
  473. return ret;
  474. return 0;
  475. }
  476. static ssize_t c2port_store_flash_erase(struct device *dev,
  477. struct device_attribute *attr,
  478. const char *buf, size_t count)
  479. {
  480. struct c2port_device *c2dev = dev_get_drvdata(dev);
  481. int ret;
  482. /* Check the device and flash access status */
  483. if (!c2dev->access || !c2dev->flash_access)
  484. return -EBUSY;
  485. mutex_lock(&c2dev->mutex);
  486. ret = __c2port_write_flash_erase(c2dev);
  487. mutex_unlock(&c2dev->mutex);
  488. if (ret < 0) {
  489. dev_err(c2dev->dev, "cannot erase %s flash\n", c2dev->name);
  490. return ret;
  491. }
  492. return count;
  493. }
  494. static DEVICE_ATTR(flash_erase, 0200, NULL, c2port_store_flash_erase);
  495. static ssize_t __c2port_read_flash_data(struct c2port_device *dev,
  496. char *buffer, loff_t offset, size_t count)
  497. {
  498. struct c2port_ops *ops = dev->ops;
  499. u8 status, nread = 128;
  500. int i, ret;
  501. /* Check for flash end */
  502. if (offset >= ops->block_size * ops->blocks_num)
  503. return 0;
  504. if (ops->block_size * ops->blocks_num - offset < nread)
  505. nread = ops->block_size * ops->blocks_num - offset;
  506. if (count < nread)
  507. nread = count;
  508. if (nread == 0)
  509. return nread;
  510. /* Target the C2 flash programming data register for C2 data register
  511. * access */
  512. c2port_write_ar(dev, C2PORT_FPDAT);
  513. /* Send flash block read command */
  514. c2port_write_dr(dev, C2PORT_BLOCK_READ);
  515. /* Wait for input acknowledge */
  516. ret = c2port_poll_in_busy(dev);
  517. if (ret < 0)
  518. return ret;
  519. /* Should check status before starting FLASH access sequence */
  520. /* Wait for status information */
  521. ret = c2port_poll_out_ready(dev);
  522. if (ret < 0)
  523. return ret;
  524. /* Read flash programming interface status */
  525. ret = c2port_read_dr(dev, &status);
  526. if (ret < 0)
  527. return ret;
  528. if (status != C2PORT_COMMAND_OK)
  529. return -EBUSY;
  530. /* Send address high byte */
  531. c2port_write_dr(dev, offset >> 8);
  532. ret = c2port_poll_in_busy(dev);
  533. if (ret < 0)
  534. return ret;
  535. /* Send address low byte */
  536. c2port_write_dr(dev, offset & 0x00ff);
  537. ret = c2port_poll_in_busy(dev);
  538. if (ret < 0)
  539. return ret;
  540. /* Send address block size */
  541. c2port_write_dr(dev, nread);
  542. ret = c2port_poll_in_busy(dev);
  543. if (ret < 0)
  544. return ret;
  545. /* Should check status before reading FLASH block */
  546. /* Wait for status information */
  547. ret = c2port_poll_out_ready(dev);
  548. if (ret < 0)
  549. return ret;
  550. /* Read flash programming interface status */
  551. ret = c2port_read_dr(dev, &status);
  552. if (ret < 0)
  553. return ret;
  554. if (status != C2PORT_COMMAND_OK)
  555. return -EBUSY;
  556. /* Read flash block */
  557. for (i = 0; i < nread; i++) {
  558. ret = c2port_poll_out_ready(dev);
  559. if (ret < 0)
  560. return ret;
  561. ret = c2port_read_dr(dev, buffer+i);
  562. if (ret < 0)
  563. return ret;
  564. }
  565. return nread;
  566. }
  567. static ssize_t c2port_read_flash_data(struct file *filp, struct kobject *kobj,
  568. struct bin_attribute *attr,
  569. char *buffer, loff_t offset, size_t count)
  570. {
  571. struct c2port_device *c2dev = dev_get_drvdata(kobj_to_dev(kobj));
  572. ssize_t ret;
  573. /* Check the device and flash access status */
  574. if (!c2dev->access || !c2dev->flash_access)
  575. return -EBUSY;
  576. mutex_lock(&c2dev->mutex);
  577. ret = __c2port_read_flash_data(c2dev, buffer, offset, count);
  578. mutex_unlock(&c2dev->mutex);
  579. if (ret < 0)
  580. dev_err(c2dev->dev, "cannot read %s flash\n", c2dev->name);
  581. return ret;
  582. }
  583. static ssize_t __c2port_write_flash_data(struct c2port_device *dev,
  584. char *buffer, loff_t offset, size_t count)
  585. {
  586. struct c2port_ops *ops = dev->ops;
  587. u8 status, nwrite = 128;
  588. int i, ret;
  589. if (nwrite > count)
  590. nwrite = count;
  591. if (ops->block_size * ops->blocks_num - offset < nwrite)
  592. nwrite = ops->block_size * ops->blocks_num - offset;
  593. /* Check for flash end */
  594. if (offset >= ops->block_size * ops->blocks_num)
  595. return -EINVAL;
  596. /* Target the C2 flash programming data register for C2 data register
  597. * access */
  598. c2port_write_ar(dev, C2PORT_FPDAT);
  599. /* Send flash block write command */
  600. c2port_write_dr(dev, C2PORT_BLOCK_WRITE);
  601. /* Wait for input acknowledge */
  602. ret = c2port_poll_in_busy(dev);
  603. if (ret < 0)
  604. return ret;
  605. /* Should check status before starting FLASH access sequence */
  606. /* Wait for status information */
  607. ret = c2port_poll_out_ready(dev);
  608. if (ret < 0)
  609. return ret;
  610. /* Read flash programming interface status */
  611. ret = c2port_read_dr(dev, &status);
  612. if (ret < 0)
  613. return ret;
  614. if (status != C2PORT_COMMAND_OK)
  615. return -EBUSY;
  616. /* Send address high byte */
  617. c2port_write_dr(dev, offset >> 8);
  618. ret = c2port_poll_in_busy(dev);
  619. if (ret < 0)
  620. return ret;
  621. /* Send address low byte */
  622. c2port_write_dr(dev, offset & 0x00ff);
  623. ret = c2port_poll_in_busy(dev);
  624. if (ret < 0)
  625. return ret;
  626. /* Send address block size */
  627. c2port_write_dr(dev, nwrite);
  628. ret = c2port_poll_in_busy(dev);
  629. if (ret < 0)
  630. return ret;
  631. /* Should check status before writing FLASH block */
  632. /* Wait for status information */
  633. ret = c2port_poll_out_ready(dev);
  634. if (ret < 0)
  635. return ret;
  636. /* Read flash programming interface status */
  637. ret = c2port_read_dr(dev, &status);
  638. if (ret < 0)
  639. return ret;
  640. if (status != C2PORT_COMMAND_OK)
  641. return -EBUSY;
  642. /* Write flash block */
  643. for (i = 0; i < nwrite; i++) {
  644. ret = c2port_write_dr(dev, *(buffer+i));
  645. if (ret < 0)
  646. return ret;
  647. ret = c2port_poll_in_busy(dev);
  648. if (ret < 0)
  649. return ret;
  650. }
  651. /* Wait for last flash write to complete */
  652. ret = c2port_poll_out_ready(dev);
  653. if (ret < 0)
  654. return ret;
  655. return nwrite;
  656. }
  657. static ssize_t c2port_write_flash_data(struct file *filp, struct kobject *kobj,
  658. struct bin_attribute *attr,
  659. char *buffer, loff_t offset, size_t count)
  660. {
  661. struct c2port_device *c2dev = dev_get_drvdata(kobj_to_dev(kobj));
  662. int ret;
  663. /* Check the device access status */
  664. if (!c2dev->access || !c2dev->flash_access)
  665. return -EBUSY;
  666. mutex_lock(&c2dev->mutex);
  667. ret = __c2port_write_flash_data(c2dev, buffer, offset, count);
  668. mutex_unlock(&c2dev->mutex);
  669. if (ret < 0)
  670. dev_err(c2dev->dev, "cannot write %s flash\n", c2dev->name);
  671. return ret;
  672. }
  673. /* size is computed at run-time */
  674. static BIN_ATTR(flash_data, 0644, c2port_read_flash_data,
  675. c2port_write_flash_data, 0);
  676. /*
  677. * Class attributes
  678. */
  679. static struct attribute *c2port_attrs[] = {
  680. &dev_attr_name.attr,
  681. &dev_attr_flash_blocks_num.attr,
  682. &dev_attr_flash_block_size.attr,
  683. &dev_attr_flash_size.attr,
  684. &dev_attr_access.attr,
  685. &dev_attr_reset.attr,
  686. &dev_attr_dev_id.attr,
  687. &dev_attr_rev_id.attr,
  688. &dev_attr_flash_access.attr,
  689. &dev_attr_flash_erase.attr,
  690. NULL,
  691. };
  692. static struct bin_attribute *c2port_bin_attrs[] = {
  693. &bin_attr_flash_data,
  694. NULL,
  695. };
  696. static const struct attribute_group c2port_group = {
  697. .attrs = c2port_attrs,
  698. .bin_attrs = c2port_bin_attrs,
  699. };
  700. static const struct attribute_group *c2port_groups[] = {
  701. &c2port_group,
  702. NULL,
  703. };
  704. /*
  705. * Exported functions
  706. */
  707. struct c2port_device *c2port_device_register(char *name,
  708. struct c2port_ops *ops, void *devdata)
  709. {
  710. struct c2port_device *c2dev;
  711. int ret;
  712. if (unlikely(!ops) || unlikely(!ops->access) || \
  713. unlikely(!ops->c2d_dir) || unlikely(!ops->c2ck_set) || \
  714. unlikely(!ops->c2d_get) || unlikely(!ops->c2d_set))
  715. return ERR_PTR(-EINVAL);
  716. c2dev = kmalloc(sizeof(struct c2port_device), GFP_KERNEL);
  717. kmemcheck_annotate_bitfield(c2dev, flags);
  718. if (unlikely(!c2dev))
  719. return ERR_PTR(-ENOMEM);
  720. idr_preload(GFP_KERNEL);
  721. spin_lock_irq(&c2port_idr_lock);
  722. ret = idr_alloc(&c2port_idr, c2dev, 0, 0, GFP_NOWAIT);
  723. spin_unlock_irq(&c2port_idr_lock);
  724. idr_preload_end();
  725. if (ret < 0)
  726. goto error_idr_alloc;
  727. c2dev->id = ret;
  728. bin_attr_flash_data.size = ops->blocks_num * ops->block_size;
  729. c2dev->dev = device_create(c2port_class, NULL, 0, c2dev,
  730. "c2port%d", c2dev->id);
  731. if (IS_ERR(c2dev->dev)) {
  732. ret = PTR_ERR(c2dev->dev);
  733. goto error_device_create;
  734. }
  735. dev_set_drvdata(c2dev->dev, c2dev);
  736. strncpy(c2dev->name, name, C2PORT_NAME_LEN);
  737. c2dev->ops = ops;
  738. mutex_init(&c2dev->mutex);
  739. /* By default C2 port access is off */
  740. c2dev->access = c2dev->flash_access = 0;
  741. ops->access(c2dev, 0);
  742. dev_info(c2dev->dev, "C2 port %s added\n", name);
  743. dev_info(c2dev->dev, "%s flash has %d blocks x %d bytes "
  744. "(%d bytes total)\n",
  745. name, ops->blocks_num, ops->block_size,
  746. ops->blocks_num * ops->block_size);
  747. return c2dev;
  748. error_device_create:
  749. spin_lock_irq(&c2port_idr_lock);
  750. idr_remove(&c2port_idr, c2dev->id);
  751. spin_unlock_irq(&c2port_idr_lock);
  752. error_idr_alloc:
  753. kfree(c2dev);
  754. return ERR_PTR(ret);
  755. }
  756. EXPORT_SYMBOL(c2port_device_register);
  757. void c2port_device_unregister(struct c2port_device *c2dev)
  758. {
  759. if (!c2dev)
  760. return;
  761. dev_info(c2dev->dev, "C2 port %s removed\n", c2dev->name);
  762. spin_lock_irq(&c2port_idr_lock);
  763. idr_remove(&c2port_idr, c2dev->id);
  764. spin_unlock_irq(&c2port_idr_lock);
  765. device_destroy(c2port_class, c2dev->id);
  766. kfree(c2dev);
  767. }
  768. EXPORT_SYMBOL(c2port_device_unregister);
  769. /*
  770. * Module stuff
  771. */
  772. static int __init c2port_init(void)
  773. {
  774. printk(KERN_INFO "Silicon Labs C2 port support v. " DRIVER_VERSION
  775. " - (C) 2007 Rodolfo Giometti\n");
  776. c2port_class = class_create(THIS_MODULE, "c2port");
  777. if (IS_ERR(c2port_class)) {
  778. printk(KERN_ERR "c2port: failed to allocate class\n");
  779. return PTR_ERR(c2port_class);
  780. }
  781. c2port_class->dev_groups = c2port_groups;
  782. return 0;
  783. }
  784. static void __exit c2port_exit(void)
  785. {
  786. class_destroy(c2port_class);
  787. }
  788. module_init(c2port_init);
  789. module_exit(c2port_exit);
  790. MODULE_AUTHOR("Rodolfo Giometti <giometti@linux.it>");
  791. MODULE_DESCRIPTION("Silicon Labs C2 port support v. " DRIVER_VERSION);
  792. MODULE_LICENSE("GPL");