atmel-isi.c 31 KB

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  1. /*
  2. * Copyright (c) 2011 Atmel Corporation
  3. * Josh Wu, <josh.wu@atmel.com>
  4. *
  5. * Based on previous work by Lars Haring, <lars.haring@atmel.com>
  6. * and Sedji Gaouaou
  7. * Based on the bttv driver for Bt848 with respective copyright holders
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/completion.h>
  15. #include <linux/delay.h>
  16. #include <linux/fs.h>
  17. #include <linux/init.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/pm_runtime.h>
  23. #include <linux/slab.h>
  24. #include <media/soc_camera.h>
  25. #include <media/drv-intf/soc_mediabus.h>
  26. #include <media/v4l2-of.h>
  27. #include <media/videobuf2-dma-contig.h>
  28. #include "atmel-isi.h"
  29. #define MAX_BUFFER_NUM 32
  30. #define MAX_SUPPORT_WIDTH 2048
  31. #define MAX_SUPPORT_HEIGHT 2048
  32. #define VID_LIMIT_BYTES (16 * 1024 * 1024)
  33. #define MIN_FRAME_RATE 15
  34. #define FRAME_INTERVAL_MILLI_SEC (1000 / MIN_FRAME_RATE)
  35. /* Frame buffer descriptor */
  36. struct fbd {
  37. /* Physical address of the frame buffer */
  38. u32 fb_address;
  39. /* DMA Control Register(only in HISI2) */
  40. u32 dma_ctrl;
  41. /* Physical address of the next fbd */
  42. u32 next_fbd_address;
  43. };
  44. static void set_dma_ctrl(struct fbd *fb_desc, u32 ctrl)
  45. {
  46. fb_desc->dma_ctrl = ctrl;
  47. }
  48. struct isi_dma_desc {
  49. struct list_head list;
  50. struct fbd *p_fbd;
  51. dma_addr_t fbd_phys;
  52. };
  53. /* Frame buffer data */
  54. struct frame_buffer {
  55. struct vb2_v4l2_buffer vb;
  56. struct isi_dma_desc *p_dma_desc;
  57. struct list_head list;
  58. };
  59. struct atmel_isi {
  60. /* Protects the access of variables shared with the ISR */
  61. spinlock_t lock;
  62. void __iomem *regs;
  63. int sequence;
  64. /* Allocate descriptors for dma buffer use */
  65. struct fbd *p_fb_descriptors;
  66. dma_addr_t fb_descriptors_phys;
  67. struct list_head dma_desc_head;
  68. struct isi_dma_desc dma_desc[MAX_BUFFER_NUM];
  69. bool enable_preview_path;
  70. struct completion complete;
  71. /* ISI peripherial clock */
  72. struct clk *pclk;
  73. unsigned int irq;
  74. struct isi_platform_data pdata;
  75. u16 width_flags; /* max 12 bits */
  76. struct list_head video_buffer_list;
  77. struct frame_buffer *active;
  78. struct soc_camera_host soc_host;
  79. };
  80. static void isi_writel(struct atmel_isi *isi, u32 reg, u32 val)
  81. {
  82. writel(val, isi->regs + reg);
  83. }
  84. static u32 isi_readl(struct atmel_isi *isi, u32 reg)
  85. {
  86. return readl(isi->regs + reg);
  87. }
  88. static u32 setup_cfg2_yuv_swap(struct atmel_isi *isi,
  89. const struct soc_camera_format_xlate *xlate)
  90. {
  91. if (xlate->host_fmt->fourcc == V4L2_PIX_FMT_YUYV) {
  92. /* all convert to YUYV */
  93. switch (xlate->code) {
  94. case MEDIA_BUS_FMT_VYUY8_2X8:
  95. return ISI_CFG2_YCC_SWAP_MODE_3;
  96. case MEDIA_BUS_FMT_UYVY8_2X8:
  97. return ISI_CFG2_YCC_SWAP_MODE_2;
  98. case MEDIA_BUS_FMT_YVYU8_2X8:
  99. return ISI_CFG2_YCC_SWAP_MODE_1;
  100. }
  101. } else if (xlate->host_fmt->fourcc == V4L2_PIX_FMT_RGB565) {
  102. /*
  103. * Preview path is enabled, it will convert UYVY to RGB format.
  104. * But if sensor output format is not UYVY, we need to set
  105. * YCC_SWAP_MODE to convert it as UYVY.
  106. */
  107. switch (xlate->code) {
  108. case MEDIA_BUS_FMT_VYUY8_2X8:
  109. return ISI_CFG2_YCC_SWAP_MODE_1;
  110. case MEDIA_BUS_FMT_YUYV8_2X8:
  111. return ISI_CFG2_YCC_SWAP_MODE_2;
  112. case MEDIA_BUS_FMT_YVYU8_2X8:
  113. return ISI_CFG2_YCC_SWAP_MODE_3;
  114. }
  115. }
  116. /*
  117. * By default, no swap for the codec path of Atmel ISI. So codec
  118. * output is same as sensor's output.
  119. * For instance, if sensor's output is YUYV, then codec outputs YUYV.
  120. * And if sensor's output is UYVY, then codec outputs UYVY.
  121. */
  122. return ISI_CFG2_YCC_SWAP_DEFAULT;
  123. }
  124. static void configure_geometry(struct atmel_isi *isi, u32 width,
  125. u32 height, const struct soc_camera_format_xlate *xlate)
  126. {
  127. u32 cfg2, psize;
  128. u32 fourcc = xlate->host_fmt->fourcc;
  129. isi->enable_preview_path = fourcc == V4L2_PIX_FMT_RGB565 ||
  130. fourcc == V4L2_PIX_FMT_RGB32;
  131. /* According to sensor's output format to set cfg2 */
  132. switch (xlate->code) {
  133. default:
  134. /* Grey */
  135. case MEDIA_BUS_FMT_Y8_1X8:
  136. cfg2 = ISI_CFG2_GRAYSCALE | ISI_CFG2_COL_SPACE_YCbCr;
  137. break;
  138. /* YUV */
  139. case MEDIA_BUS_FMT_VYUY8_2X8:
  140. case MEDIA_BUS_FMT_UYVY8_2X8:
  141. case MEDIA_BUS_FMT_YVYU8_2X8:
  142. case MEDIA_BUS_FMT_YUYV8_2X8:
  143. cfg2 = ISI_CFG2_COL_SPACE_YCbCr |
  144. setup_cfg2_yuv_swap(isi, xlate);
  145. break;
  146. /* RGB, TODO */
  147. }
  148. isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
  149. /* Set width */
  150. cfg2 |= ((width - 1) << ISI_CFG2_IM_HSIZE_OFFSET) &
  151. ISI_CFG2_IM_HSIZE_MASK;
  152. /* Set height */
  153. cfg2 |= ((height - 1) << ISI_CFG2_IM_VSIZE_OFFSET)
  154. & ISI_CFG2_IM_VSIZE_MASK;
  155. isi_writel(isi, ISI_CFG2, cfg2);
  156. /* No down sampling, preview size equal to sensor output size */
  157. psize = ((width - 1) << ISI_PSIZE_PREV_HSIZE_OFFSET) &
  158. ISI_PSIZE_PREV_HSIZE_MASK;
  159. psize |= ((height - 1) << ISI_PSIZE_PREV_VSIZE_OFFSET) &
  160. ISI_PSIZE_PREV_VSIZE_MASK;
  161. isi_writel(isi, ISI_PSIZE, psize);
  162. isi_writel(isi, ISI_PDECF, ISI_PDECF_NO_SAMPLING);
  163. return;
  164. }
  165. static bool is_supported(struct soc_camera_device *icd,
  166. const u32 pixformat)
  167. {
  168. switch (pixformat) {
  169. /* YUV, including grey */
  170. case V4L2_PIX_FMT_GREY:
  171. case V4L2_PIX_FMT_YUYV:
  172. case V4L2_PIX_FMT_UYVY:
  173. case V4L2_PIX_FMT_YVYU:
  174. case V4L2_PIX_FMT_VYUY:
  175. /* RGB */
  176. case V4L2_PIX_FMT_RGB565:
  177. return true;
  178. default:
  179. return false;
  180. }
  181. }
  182. static irqreturn_t atmel_isi_handle_streaming(struct atmel_isi *isi)
  183. {
  184. if (isi->active) {
  185. struct vb2_v4l2_buffer *vbuf = &isi->active->vb;
  186. struct frame_buffer *buf = isi->active;
  187. list_del_init(&buf->list);
  188. vbuf->vb2_buf.timestamp = ktime_get_ns();
  189. vbuf->sequence = isi->sequence++;
  190. vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_DONE);
  191. }
  192. if (list_empty(&isi->video_buffer_list)) {
  193. isi->active = NULL;
  194. } else {
  195. /* start next dma frame. */
  196. isi->active = list_entry(isi->video_buffer_list.next,
  197. struct frame_buffer, list);
  198. if (!isi->enable_preview_path) {
  199. isi_writel(isi, ISI_DMA_C_DSCR,
  200. (u32)isi->active->p_dma_desc->fbd_phys);
  201. isi_writel(isi, ISI_DMA_C_CTRL,
  202. ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
  203. isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_C_CH);
  204. } else {
  205. isi_writel(isi, ISI_DMA_P_DSCR,
  206. (u32)isi->active->p_dma_desc->fbd_phys);
  207. isi_writel(isi, ISI_DMA_P_CTRL,
  208. ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
  209. isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_P_CH);
  210. }
  211. }
  212. return IRQ_HANDLED;
  213. }
  214. /* ISI interrupt service routine */
  215. static irqreturn_t isi_interrupt(int irq, void *dev_id)
  216. {
  217. struct atmel_isi *isi = dev_id;
  218. u32 status, mask, pending;
  219. irqreturn_t ret = IRQ_NONE;
  220. spin_lock(&isi->lock);
  221. status = isi_readl(isi, ISI_STATUS);
  222. mask = isi_readl(isi, ISI_INTMASK);
  223. pending = status & mask;
  224. if (pending & ISI_CTRL_SRST) {
  225. complete(&isi->complete);
  226. isi_writel(isi, ISI_INTDIS, ISI_CTRL_SRST);
  227. ret = IRQ_HANDLED;
  228. } else if (pending & ISI_CTRL_DIS) {
  229. complete(&isi->complete);
  230. isi_writel(isi, ISI_INTDIS, ISI_CTRL_DIS);
  231. ret = IRQ_HANDLED;
  232. } else {
  233. if (likely(pending & ISI_SR_CXFR_DONE) ||
  234. likely(pending & ISI_SR_PXFR_DONE))
  235. ret = atmel_isi_handle_streaming(isi);
  236. }
  237. spin_unlock(&isi->lock);
  238. return ret;
  239. }
  240. #define WAIT_ISI_RESET 1
  241. #define WAIT_ISI_DISABLE 0
  242. static int atmel_isi_wait_status(struct atmel_isi *isi, int wait_reset)
  243. {
  244. unsigned long timeout;
  245. /*
  246. * The reset or disable will only succeed if we have a
  247. * pixel clock from the camera.
  248. */
  249. init_completion(&isi->complete);
  250. if (wait_reset) {
  251. isi_writel(isi, ISI_INTEN, ISI_CTRL_SRST);
  252. isi_writel(isi, ISI_CTRL, ISI_CTRL_SRST);
  253. } else {
  254. isi_writel(isi, ISI_INTEN, ISI_CTRL_DIS);
  255. isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
  256. }
  257. timeout = wait_for_completion_timeout(&isi->complete,
  258. msecs_to_jiffies(500));
  259. if (timeout == 0)
  260. return -ETIMEDOUT;
  261. return 0;
  262. }
  263. /* ------------------------------------------------------------------
  264. Videobuf operations
  265. ------------------------------------------------------------------*/
  266. static int queue_setup(struct vb2_queue *vq,
  267. unsigned int *nbuffers, unsigned int *nplanes,
  268. unsigned int sizes[], struct device *alloc_devs[])
  269. {
  270. struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
  271. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  272. struct atmel_isi *isi = ici->priv;
  273. unsigned long size;
  274. size = icd->sizeimage;
  275. if (!*nbuffers || *nbuffers > MAX_BUFFER_NUM)
  276. *nbuffers = MAX_BUFFER_NUM;
  277. if (size * *nbuffers > VID_LIMIT_BYTES)
  278. *nbuffers = VID_LIMIT_BYTES / size;
  279. *nplanes = 1;
  280. sizes[0] = size;
  281. isi->sequence = 0;
  282. isi->active = NULL;
  283. dev_dbg(icd->parent, "%s, count=%d, size=%ld\n", __func__,
  284. *nbuffers, size);
  285. return 0;
  286. }
  287. static int buffer_init(struct vb2_buffer *vb)
  288. {
  289. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  290. struct frame_buffer *buf = container_of(vbuf, struct frame_buffer, vb);
  291. buf->p_dma_desc = NULL;
  292. INIT_LIST_HEAD(&buf->list);
  293. return 0;
  294. }
  295. static int buffer_prepare(struct vb2_buffer *vb)
  296. {
  297. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  298. struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
  299. struct frame_buffer *buf = container_of(vbuf, struct frame_buffer, vb);
  300. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  301. struct atmel_isi *isi = ici->priv;
  302. unsigned long size;
  303. struct isi_dma_desc *desc;
  304. size = icd->sizeimage;
  305. if (vb2_plane_size(vb, 0) < size) {
  306. dev_err(icd->parent, "%s data will not fit into plane (%lu < %lu)\n",
  307. __func__, vb2_plane_size(vb, 0), size);
  308. return -EINVAL;
  309. }
  310. vb2_set_plane_payload(vb, 0, size);
  311. if (!buf->p_dma_desc) {
  312. if (list_empty(&isi->dma_desc_head)) {
  313. dev_err(icd->parent, "Not enough dma descriptors.\n");
  314. return -EINVAL;
  315. } else {
  316. /* Get an available descriptor */
  317. desc = list_entry(isi->dma_desc_head.next,
  318. struct isi_dma_desc, list);
  319. /* Delete the descriptor since now it is used */
  320. list_del_init(&desc->list);
  321. /* Initialize the dma descriptor */
  322. desc->p_fbd->fb_address =
  323. vb2_dma_contig_plane_dma_addr(vb, 0);
  324. desc->p_fbd->next_fbd_address = 0;
  325. set_dma_ctrl(desc->p_fbd, ISI_DMA_CTRL_WB);
  326. buf->p_dma_desc = desc;
  327. }
  328. }
  329. return 0;
  330. }
  331. static void buffer_cleanup(struct vb2_buffer *vb)
  332. {
  333. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  334. struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
  335. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  336. struct atmel_isi *isi = ici->priv;
  337. struct frame_buffer *buf = container_of(vbuf, struct frame_buffer, vb);
  338. /* This descriptor is available now and we add to head list */
  339. if (buf->p_dma_desc)
  340. list_add(&buf->p_dma_desc->list, &isi->dma_desc_head);
  341. }
  342. static void start_dma(struct atmel_isi *isi, struct frame_buffer *buffer)
  343. {
  344. u32 ctrl, cfg1;
  345. cfg1 = isi_readl(isi, ISI_CFG1);
  346. /* Enable irq: cxfr for the codec path, pxfr for the preview path */
  347. isi_writel(isi, ISI_INTEN,
  348. ISI_SR_CXFR_DONE | ISI_SR_PXFR_DONE);
  349. /* Check if already in a frame */
  350. if (!isi->enable_preview_path) {
  351. if (isi_readl(isi, ISI_STATUS) & ISI_CTRL_CDC) {
  352. dev_err(isi->soc_host.icd->parent, "Already in frame handling.\n");
  353. return;
  354. }
  355. isi_writel(isi, ISI_DMA_C_DSCR,
  356. (u32)buffer->p_dma_desc->fbd_phys);
  357. isi_writel(isi, ISI_DMA_C_CTRL,
  358. ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
  359. isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_C_CH);
  360. } else {
  361. isi_writel(isi, ISI_DMA_P_DSCR,
  362. (u32)buffer->p_dma_desc->fbd_phys);
  363. isi_writel(isi, ISI_DMA_P_CTRL,
  364. ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
  365. isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_P_CH);
  366. }
  367. cfg1 &= ~ISI_CFG1_FRATE_DIV_MASK;
  368. /* Enable linked list */
  369. cfg1 |= isi->pdata.frate | ISI_CFG1_DISCR;
  370. /* Enable ISI */
  371. ctrl = ISI_CTRL_EN;
  372. if (!isi->enable_preview_path)
  373. ctrl |= ISI_CTRL_CDC;
  374. isi_writel(isi, ISI_CTRL, ctrl);
  375. isi_writel(isi, ISI_CFG1, cfg1);
  376. }
  377. static void buffer_queue(struct vb2_buffer *vb)
  378. {
  379. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  380. struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
  381. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  382. struct atmel_isi *isi = ici->priv;
  383. struct frame_buffer *buf = container_of(vbuf, struct frame_buffer, vb);
  384. unsigned long flags = 0;
  385. spin_lock_irqsave(&isi->lock, flags);
  386. list_add_tail(&buf->list, &isi->video_buffer_list);
  387. if (isi->active == NULL) {
  388. isi->active = buf;
  389. if (vb2_is_streaming(vb->vb2_queue))
  390. start_dma(isi, buf);
  391. }
  392. spin_unlock_irqrestore(&isi->lock, flags);
  393. }
  394. static int start_streaming(struct vb2_queue *vq, unsigned int count)
  395. {
  396. struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
  397. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  398. struct atmel_isi *isi = ici->priv;
  399. int ret;
  400. pm_runtime_get_sync(ici->v4l2_dev.dev);
  401. /* Reset ISI */
  402. ret = atmel_isi_wait_status(isi, WAIT_ISI_RESET);
  403. if (ret < 0) {
  404. dev_err(icd->parent, "Reset ISI timed out\n");
  405. pm_runtime_put(ici->v4l2_dev.dev);
  406. return ret;
  407. }
  408. /* Disable all interrupts */
  409. isi_writel(isi, ISI_INTDIS, (u32)~0UL);
  410. configure_geometry(isi, icd->user_width, icd->user_height,
  411. icd->current_fmt);
  412. spin_lock_irq(&isi->lock);
  413. /* Clear any pending interrupt */
  414. isi_readl(isi, ISI_STATUS);
  415. if (count)
  416. start_dma(isi, isi->active);
  417. spin_unlock_irq(&isi->lock);
  418. return 0;
  419. }
  420. /* abort streaming and wait for last buffer */
  421. static void stop_streaming(struct vb2_queue *vq)
  422. {
  423. struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
  424. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  425. struct atmel_isi *isi = ici->priv;
  426. struct frame_buffer *buf, *node;
  427. int ret = 0;
  428. unsigned long timeout;
  429. spin_lock_irq(&isi->lock);
  430. isi->active = NULL;
  431. /* Release all active buffers */
  432. list_for_each_entry_safe(buf, node, &isi->video_buffer_list, list) {
  433. list_del_init(&buf->list);
  434. vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
  435. }
  436. spin_unlock_irq(&isi->lock);
  437. if (!isi->enable_preview_path) {
  438. timeout = jiffies + FRAME_INTERVAL_MILLI_SEC * HZ;
  439. /* Wait until the end of the current frame. */
  440. while ((isi_readl(isi, ISI_STATUS) & ISI_CTRL_CDC) &&
  441. time_before(jiffies, timeout))
  442. msleep(1);
  443. if (time_after(jiffies, timeout))
  444. dev_err(icd->parent,
  445. "Timeout waiting for finishing codec request\n");
  446. }
  447. /* Disable interrupts */
  448. isi_writel(isi, ISI_INTDIS,
  449. ISI_SR_CXFR_DONE | ISI_SR_PXFR_DONE);
  450. /* Disable ISI and wait for it is done */
  451. ret = atmel_isi_wait_status(isi, WAIT_ISI_DISABLE);
  452. if (ret < 0)
  453. dev_err(icd->parent, "Disable ISI timed out\n");
  454. pm_runtime_put(ici->v4l2_dev.dev);
  455. }
  456. static const struct vb2_ops isi_video_qops = {
  457. .queue_setup = queue_setup,
  458. .buf_init = buffer_init,
  459. .buf_prepare = buffer_prepare,
  460. .buf_cleanup = buffer_cleanup,
  461. .buf_queue = buffer_queue,
  462. .start_streaming = start_streaming,
  463. .stop_streaming = stop_streaming,
  464. .wait_prepare = vb2_ops_wait_prepare,
  465. .wait_finish = vb2_ops_wait_finish,
  466. };
  467. /* ------------------------------------------------------------------
  468. SOC camera operations for the device
  469. ------------------------------------------------------------------*/
  470. static int isi_camera_init_videobuf(struct vb2_queue *q,
  471. struct soc_camera_device *icd)
  472. {
  473. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  474. q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  475. q->io_modes = VB2_MMAP;
  476. q->drv_priv = icd;
  477. q->buf_struct_size = sizeof(struct frame_buffer);
  478. q->ops = &isi_video_qops;
  479. q->mem_ops = &vb2_dma_contig_memops;
  480. q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
  481. q->lock = &ici->host_lock;
  482. q->dev = ici->v4l2_dev.dev;
  483. return vb2_queue_init(q);
  484. }
  485. static int isi_camera_set_fmt(struct soc_camera_device *icd,
  486. struct v4l2_format *f)
  487. {
  488. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  489. const struct soc_camera_format_xlate *xlate;
  490. struct v4l2_pix_format *pix = &f->fmt.pix;
  491. struct v4l2_subdev_format format = {
  492. .which = V4L2_SUBDEV_FORMAT_ACTIVE,
  493. };
  494. struct v4l2_mbus_framefmt *mf = &format.format;
  495. int ret;
  496. /* check with atmel-isi support format, if not support use YUYV */
  497. if (!is_supported(icd, pix->pixelformat))
  498. pix->pixelformat = V4L2_PIX_FMT_YUYV;
  499. xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
  500. if (!xlate) {
  501. dev_warn(icd->parent, "Format %x not found\n",
  502. pix->pixelformat);
  503. return -EINVAL;
  504. }
  505. dev_dbg(icd->parent, "Plan to set format %dx%d\n",
  506. pix->width, pix->height);
  507. mf->width = pix->width;
  508. mf->height = pix->height;
  509. mf->field = pix->field;
  510. mf->colorspace = pix->colorspace;
  511. mf->code = xlate->code;
  512. ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &format);
  513. if (ret < 0)
  514. return ret;
  515. if (mf->code != xlate->code)
  516. return -EINVAL;
  517. pix->width = mf->width;
  518. pix->height = mf->height;
  519. pix->field = mf->field;
  520. pix->colorspace = mf->colorspace;
  521. icd->current_fmt = xlate;
  522. dev_dbg(icd->parent, "Finally set format %dx%d\n",
  523. pix->width, pix->height);
  524. return ret;
  525. }
  526. static int isi_camera_try_fmt(struct soc_camera_device *icd,
  527. struct v4l2_format *f)
  528. {
  529. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  530. const struct soc_camera_format_xlate *xlate;
  531. struct v4l2_pix_format *pix = &f->fmt.pix;
  532. struct v4l2_subdev_pad_config pad_cfg;
  533. struct v4l2_subdev_format format = {
  534. .which = V4L2_SUBDEV_FORMAT_TRY,
  535. };
  536. struct v4l2_mbus_framefmt *mf = &format.format;
  537. u32 pixfmt = pix->pixelformat;
  538. int ret;
  539. /* check with atmel-isi support format, if not support use YUYV */
  540. if (!is_supported(icd, pix->pixelformat))
  541. pix->pixelformat = V4L2_PIX_FMT_YUYV;
  542. xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
  543. if (pixfmt && !xlate) {
  544. dev_warn(icd->parent, "Format %x not found\n", pixfmt);
  545. return -EINVAL;
  546. }
  547. /* limit to Atmel ISI hardware capabilities */
  548. if (pix->height > MAX_SUPPORT_HEIGHT)
  549. pix->height = MAX_SUPPORT_HEIGHT;
  550. if (pix->width > MAX_SUPPORT_WIDTH)
  551. pix->width = MAX_SUPPORT_WIDTH;
  552. /* limit to sensor capabilities */
  553. mf->width = pix->width;
  554. mf->height = pix->height;
  555. mf->field = pix->field;
  556. mf->colorspace = pix->colorspace;
  557. mf->code = xlate->code;
  558. ret = v4l2_subdev_call(sd, pad, set_fmt, &pad_cfg, &format);
  559. if (ret < 0)
  560. return ret;
  561. pix->width = mf->width;
  562. pix->height = mf->height;
  563. pix->colorspace = mf->colorspace;
  564. switch (mf->field) {
  565. case V4L2_FIELD_ANY:
  566. pix->field = V4L2_FIELD_NONE;
  567. break;
  568. case V4L2_FIELD_NONE:
  569. break;
  570. default:
  571. dev_err(icd->parent, "Field type %d unsupported.\n",
  572. mf->field);
  573. ret = -EINVAL;
  574. }
  575. return ret;
  576. }
  577. static const struct soc_mbus_pixelfmt isi_camera_formats[] = {
  578. {
  579. .fourcc = V4L2_PIX_FMT_YUYV,
  580. .name = "Packed YUV422 16 bit",
  581. .bits_per_sample = 8,
  582. .packing = SOC_MBUS_PACKING_2X8_PADHI,
  583. .order = SOC_MBUS_ORDER_LE,
  584. .layout = SOC_MBUS_LAYOUT_PACKED,
  585. },
  586. {
  587. .fourcc = V4L2_PIX_FMT_RGB565,
  588. .name = "RGB565",
  589. .bits_per_sample = 8,
  590. .packing = SOC_MBUS_PACKING_2X8_PADHI,
  591. .order = SOC_MBUS_ORDER_LE,
  592. .layout = SOC_MBUS_LAYOUT_PACKED,
  593. },
  594. };
  595. /* This will be corrected as we get more formats */
  596. static bool isi_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
  597. {
  598. return fmt->packing == SOC_MBUS_PACKING_NONE ||
  599. (fmt->bits_per_sample == 8 &&
  600. fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
  601. (fmt->bits_per_sample > 8 &&
  602. fmt->packing == SOC_MBUS_PACKING_EXTEND16);
  603. }
  604. #define ISI_BUS_PARAM (V4L2_MBUS_MASTER | \
  605. V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
  606. V4L2_MBUS_HSYNC_ACTIVE_LOW | \
  607. V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
  608. V4L2_MBUS_VSYNC_ACTIVE_LOW | \
  609. V4L2_MBUS_PCLK_SAMPLE_RISING | \
  610. V4L2_MBUS_PCLK_SAMPLE_FALLING | \
  611. V4L2_MBUS_DATA_ACTIVE_HIGH)
  612. static int isi_camera_try_bus_param(struct soc_camera_device *icd,
  613. unsigned char buswidth)
  614. {
  615. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  616. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  617. struct atmel_isi *isi = ici->priv;
  618. struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
  619. unsigned long common_flags;
  620. int ret;
  621. ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
  622. if (!ret) {
  623. common_flags = soc_mbus_config_compatible(&cfg,
  624. ISI_BUS_PARAM);
  625. if (!common_flags) {
  626. dev_warn(icd->parent,
  627. "Flags incompatible: camera 0x%x, host 0x%x\n",
  628. cfg.flags, ISI_BUS_PARAM);
  629. return -EINVAL;
  630. }
  631. } else if (ret != -ENOIOCTLCMD) {
  632. return ret;
  633. }
  634. if ((1 << (buswidth - 1)) & isi->width_flags)
  635. return 0;
  636. return -EINVAL;
  637. }
  638. static int isi_camera_get_formats(struct soc_camera_device *icd,
  639. unsigned int idx,
  640. struct soc_camera_format_xlate *xlate)
  641. {
  642. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  643. int formats = 0, ret, i, n;
  644. /* sensor format */
  645. struct v4l2_subdev_mbus_code_enum code = {
  646. .which = V4L2_SUBDEV_FORMAT_ACTIVE,
  647. .index = idx,
  648. };
  649. /* soc camera host format */
  650. const struct soc_mbus_pixelfmt *fmt;
  651. ret = v4l2_subdev_call(sd, pad, enum_mbus_code, NULL, &code);
  652. if (ret < 0)
  653. /* No more formats */
  654. return 0;
  655. fmt = soc_mbus_get_fmtdesc(code.code);
  656. if (!fmt) {
  657. dev_err(icd->parent,
  658. "Invalid format code #%u: %d\n", idx, code.code);
  659. return 0;
  660. }
  661. /* This also checks support for the requested bits-per-sample */
  662. ret = isi_camera_try_bus_param(icd, fmt->bits_per_sample);
  663. if (ret < 0) {
  664. dev_err(icd->parent,
  665. "Fail to try the bus parameters.\n");
  666. return 0;
  667. }
  668. switch (code.code) {
  669. case MEDIA_BUS_FMT_UYVY8_2X8:
  670. case MEDIA_BUS_FMT_VYUY8_2X8:
  671. case MEDIA_BUS_FMT_YUYV8_2X8:
  672. case MEDIA_BUS_FMT_YVYU8_2X8:
  673. n = ARRAY_SIZE(isi_camera_formats);
  674. formats += n;
  675. for (i = 0; xlate && i < n; i++, xlate++) {
  676. xlate->host_fmt = &isi_camera_formats[i];
  677. xlate->code = code.code;
  678. dev_dbg(icd->parent, "Providing format %s using code %d\n",
  679. xlate->host_fmt->name, xlate->code);
  680. }
  681. break;
  682. default:
  683. if (!isi_camera_packing_supported(fmt))
  684. return 0;
  685. if (xlate)
  686. dev_dbg(icd->parent,
  687. "Providing format %s in pass-through mode\n",
  688. fmt->name);
  689. }
  690. /* Generic pass-through */
  691. formats++;
  692. if (xlate) {
  693. xlate->host_fmt = fmt;
  694. xlate->code = code.code;
  695. xlate++;
  696. }
  697. return formats;
  698. }
  699. static int isi_camera_add_device(struct soc_camera_device *icd)
  700. {
  701. dev_dbg(icd->parent, "Atmel ISI Camera driver attached to camera %d\n",
  702. icd->devnum);
  703. return 0;
  704. }
  705. static void isi_camera_remove_device(struct soc_camera_device *icd)
  706. {
  707. dev_dbg(icd->parent, "Atmel ISI Camera driver detached from camera %d\n",
  708. icd->devnum);
  709. }
  710. static unsigned int isi_camera_poll(struct file *file, poll_table *pt)
  711. {
  712. struct soc_camera_device *icd = file->private_data;
  713. return vb2_poll(&icd->vb2_vidq, file, pt);
  714. }
  715. static int isi_camera_querycap(struct soc_camera_host *ici,
  716. struct v4l2_capability *cap)
  717. {
  718. strcpy(cap->driver, "atmel-isi");
  719. strcpy(cap->card, "Atmel Image Sensor Interface");
  720. cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
  721. cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
  722. return 0;
  723. }
  724. static int isi_camera_set_bus_param(struct soc_camera_device *icd)
  725. {
  726. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  727. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  728. struct atmel_isi *isi = ici->priv;
  729. struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
  730. unsigned long common_flags;
  731. int ret;
  732. u32 cfg1 = 0;
  733. ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
  734. if (!ret) {
  735. common_flags = soc_mbus_config_compatible(&cfg,
  736. ISI_BUS_PARAM);
  737. if (!common_flags) {
  738. dev_warn(icd->parent,
  739. "Flags incompatible: camera 0x%x, host 0x%x\n",
  740. cfg.flags, ISI_BUS_PARAM);
  741. return -EINVAL;
  742. }
  743. } else if (ret != -ENOIOCTLCMD) {
  744. return ret;
  745. } else {
  746. common_flags = ISI_BUS_PARAM;
  747. }
  748. dev_dbg(icd->parent, "Flags cam: 0x%x host: 0x%x common: 0x%lx\n",
  749. cfg.flags, ISI_BUS_PARAM, common_flags);
  750. /* Make choises, based on platform preferences */
  751. if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
  752. (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
  753. if (isi->pdata.hsync_act_low)
  754. common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
  755. else
  756. common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
  757. }
  758. if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
  759. (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
  760. if (isi->pdata.vsync_act_low)
  761. common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
  762. else
  763. common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
  764. }
  765. if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
  766. (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
  767. if (isi->pdata.pclk_act_falling)
  768. common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
  769. else
  770. common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
  771. }
  772. cfg.flags = common_flags;
  773. ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
  774. if (ret < 0 && ret != -ENOIOCTLCMD) {
  775. dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
  776. common_flags, ret);
  777. return ret;
  778. }
  779. /* set bus param for ISI */
  780. if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
  781. cfg1 |= ISI_CFG1_HSYNC_POL_ACTIVE_LOW;
  782. if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
  783. cfg1 |= ISI_CFG1_VSYNC_POL_ACTIVE_LOW;
  784. if (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
  785. cfg1 |= ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING;
  786. dev_dbg(icd->parent, "vsync active %s, hsync active %s, sampling on pix clock %s edge\n",
  787. common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW ? "low" : "high",
  788. common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW ? "low" : "high",
  789. common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING ? "falling" : "rising");
  790. if (isi->pdata.has_emb_sync)
  791. cfg1 |= ISI_CFG1_EMB_SYNC;
  792. if (isi->pdata.full_mode)
  793. cfg1 |= ISI_CFG1_FULL_MODE;
  794. cfg1 |= ISI_CFG1_THMASK_BEATS_16;
  795. /* Enable PM and peripheral clock before operate isi registers */
  796. pm_runtime_get_sync(ici->v4l2_dev.dev);
  797. isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
  798. isi_writel(isi, ISI_CFG1, cfg1);
  799. pm_runtime_put(ici->v4l2_dev.dev);
  800. return 0;
  801. }
  802. static struct soc_camera_host_ops isi_soc_camera_host_ops = {
  803. .owner = THIS_MODULE,
  804. .add = isi_camera_add_device,
  805. .remove = isi_camera_remove_device,
  806. .set_fmt = isi_camera_set_fmt,
  807. .try_fmt = isi_camera_try_fmt,
  808. .get_formats = isi_camera_get_formats,
  809. .init_videobuf2 = isi_camera_init_videobuf,
  810. .poll = isi_camera_poll,
  811. .querycap = isi_camera_querycap,
  812. .set_bus_param = isi_camera_set_bus_param,
  813. };
  814. /* -----------------------------------------------------------------------*/
  815. static int atmel_isi_remove(struct platform_device *pdev)
  816. {
  817. struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
  818. struct atmel_isi *isi = container_of(soc_host,
  819. struct atmel_isi, soc_host);
  820. soc_camera_host_unregister(soc_host);
  821. dma_free_coherent(&pdev->dev,
  822. sizeof(struct fbd) * MAX_BUFFER_NUM,
  823. isi->p_fb_descriptors,
  824. isi->fb_descriptors_phys);
  825. pm_runtime_disable(&pdev->dev);
  826. return 0;
  827. }
  828. static int atmel_isi_parse_dt(struct atmel_isi *isi,
  829. struct platform_device *pdev)
  830. {
  831. struct device_node *np= pdev->dev.of_node;
  832. struct v4l2_of_endpoint ep;
  833. int err;
  834. /* Default settings for ISI */
  835. isi->pdata.full_mode = 1;
  836. isi->pdata.frate = ISI_CFG1_FRATE_CAPTURE_ALL;
  837. np = of_graph_get_next_endpoint(np, NULL);
  838. if (!np) {
  839. dev_err(&pdev->dev, "Could not find the endpoint\n");
  840. return -EINVAL;
  841. }
  842. err = v4l2_of_parse_endpoint(np, &ep);
  843. of_node_put(np);
  844. if (err) {
  845. dev_err(&pdev->dev, "Could not parse the endpoint\n");
  846. return err;
  847. }
  848. switch (ep.bus.parallel.bus_width) {
  849. case 8:
  850. isi->pdata.data_width_flags = ISI_DATAWIDTH_8;
  851. break;
  852. case 10:
  853. isi->pdata.data_width_flags =
  854. ISI_DATAWIDTH_8 | ISI_DATAWIDTH_10;
  855. break;
  856. default:
  857. dev_err(&pdev->dev, "Unsupported bus width: %d\n",
  858. ep.bus.parallel.bus_width);
  859. return -EINVAL;
  860. }
  861. if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
  862. isi->pdata.hsync_act_low = true;
  863. if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
  864. isi->pdata.vsync_act_low = true;
  865. if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
  866. isi->pdata.pclk_act_falling = true;
  867. if (ep.bus_type == V4L2_MBUS_BT656)
  868. isi->pdata.has_emb_sync = true;
  869. return 0;
  870. }
  871. static int atmel_isi_probe(struct platform_device *pdev)
  872. {
  873. int irq;
  874. struct atmel_isi *isi;
  875. struct resource *regs;
  876. int ret, i;
  877. struct soc_camera_host *soc_host;
  878. isi = devm_kzalloc(&pdev->dev, sizeof(struct atmel_isi), GFP_KERNEL);
  879. if (!isi) {
  880. dev_err(&pdev->dev, "Can't allocate interface!\n");
  881. return -ENOMEM;
  882. }
  883. isi->pclk = devm_clk_get(&pdev->dev, "isi_clk");
  884. if (IS_ERR(isi->pclk))
  885. return PTR_ERR(isi->pclk);
  886. ret = atmel_isi_parse_dt(isi, pdev);
  887. if (ret)
  888. return ret;
  889. isi->active = NULL;
  890. spin_lock_init(&isi->lock);
  891. INIT_LIST_HEAD(&isi->video_buffer_list);
  892. INIT_LIST_HEAD(&isi->dma_desc_head);
  893. isi->p_fb_descriptors = dma_alloc_coherent(&pdev->dev,
  894. sizeof(struct fbd) * MAX_BUFFER_NUM,
  895. &isi->fb_descriptors_phys,
  896. GFP_KERNEL);
  897. if (!isi->p_fb_descriptors) {
  898. dev_err(&pdev->dev, "Can't allocate descriptors!\n");
  899. return -ENOMEM;
  900. }
  901. for (i = 0; i < MAX_BUFFER_NUM; i++) {
  902. isi->dma_desc[i].p_fbd = isi->p_fb_descriptors + i;
  903. isi->dma_desc[i].fbd_phys = isi->fb_descriptors_phys +
  904. i * sizeof(struct fbd);
  905. list_add(&isi->dma_desc[i].list, &isi->dma_desc_head);
  906. }
  907. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  908. isi->regs = devm_ioremap_resource(&pdev->dev, regs);
  909. if (IS_ERR(isi->regs)) {
  910. ret = PTR_ERR(isi->regs);
  911. goto err_ioremap;
  912. }
  913. if (isi->pdata.data_width_flags & ISI_DATAWIDTH_8)
  914. isi->width_flags = 1 << 7;
  915. if (isi->pdata.data_width_flags & ISI_DATAWIDTH_10)
  916. isi->width_flags |= 1 << 9;
  917. irq = platform_get_irq(pdev, 0);
  918. if (irq < 0) {
  919. ret = irq;
  920. goto err_req_irq;
  921. }
  922. ret = devm_request_irq(&pdev->dev, irq, isi_interrupt, 0, "isi", isi);
  923. if (ret) {
  924. dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
  925. goto err_req_irq;
  926. }
  927. isi->irq = irq;
  928. soc_host = &isi->soc_host;
  929. soc_host->drv_name = "isi-camera";
  930. soc_host->ops = &isi_soc_camera_host_ops;
  931. soc_host->priv = isi;
  932. soc_host->v4l2_dev.dev = &pdev->dev;
  933. soc_host->nr = pdev->id;
  934. pm_suspend_ignore_children(&pdev->dev, true);
  935. pm_runtime_enable(&pdev->dev);
  936. ret = soc_camera_host_register(soc_host);
  937. if (ret) {
  938. dev_err(&pdev->dev, "Unable to register soc camera host\n");
  939. goto err_register_soc_camera_host;
  940. }
  941. return 0;
  942. err_register_soc_camera_host:
  943. pm_runtime_disable(&pdev->dev);
  944. err_req_irq:
  945. err_ioremap:
  946. dma_free_coherent(&pdev->dev,
  947. sizeof(struct fbd) * MAX_BUFFER_NUM,
  948. isi->p_fb_descriptors,
  949. isi->fb_descriptors_phys);
  950. return ret;
  951. }
  952. #ifdef CONFIG_PM
  953. static int atmel_isi_runtime_suspend(struct device *dev)
  954. {
  955. struct soc_camera_host *soc_host = to_soc_camera_host(dev);
  956. struct atmel_isi *isi = container_of(soc_host,
  957. struct atmel_isi, soc_host);
  958. clk_disable_unprepare(isi->pclk);
  959. return 0;
  960. }
  961. static int atmel_isi_runtime_resume(struct device *dev)
  962. {
  963. struct soc_camera_host *soc_host = to_soc_camera_host(dev);
  964. struct atmel_isi *isi = container_of(soc_host,
  965. struct atmel_isi, soc_host);
  966. return clk_prepare_enable(isi->pclk);
  967. }
  968. #endif /* CONFIG_PM */
  969. static const struct dev_pm_ops atmel_isi_dev_pm_ops = {
  970. SET_RUNTIME_PM_OPS(atmel_isi_runtime_suspend,
  971. atmel_isi_runtime_resume, NULL)
  972. };
  973. static const struct of_device_id atmel_isi_of_match[] = {
  974. { .compatible = "atmel,at91sam9g45-isi" },
  975. { }
  976. };
  977. MODULE_DEVICE_TABLE(of, atmel_isi_of_match);
  978. static struct platform_driver atmel_isi_driver = {
  979. .remove = atmel_isi_remove,
  980. .driver = {
  981. .name = "atmel_isi",
  982. .of_match_table = of_match_ptr(atmel_isi_of_match),
  983. .pm = &atmel_isi_dev_pm_ops,
  984. },
  985. };
  986. module_platform_driver_probe(atmel_isi_driver, atmel_isi_probe);
  987. MODULE_AUTHOR("Josh Wu <josh.wu@atmel.com>");
  988. MODULE_DESCRIPTION("The V4L2 driver for Atmel Linux");
  989. MODULE_LICENSE("GPL");
  990. MODULE_SUPPORTED_DEVICE("video");