atmel-isc.c 37 KB

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  1. /*
  2. * Atmel Image Sensor Controller (ISC) driver
  3. *
  4. * Copyright (C) 2016 Atmel
  5. *
  6. * Author: Songjun Wu <songjun.wu@microchip.com>
  7. *
  8. * This program is free software; you may redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * Sensor-->PFE-->WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB-->RLP-->DMA
  13. *
  14. * ISC video pipeline integrates the following submodules:
  15. * PFE: Parallel Front End to sample the camera sensor input stream
  16. * WB: Programmable white balance in the Bayer domain
  17. * CFA: Color filter array interpolation module
  18. * CC: Programmable color correction
  19. * GAM: Gamma correction
  20. * CSC: Programmable color space conversion
  21. * CBC: Contrast and Brightness control
  22. * SUB: This module performs YCbCr444 to YCbCr420 chrominance subsampling
  23. * RLP: This module performs rounding, range limiting
  24. * and packing of the incoming data
  25. */
  26. #include <linux/clk.h>
  27. #include <linux/clkdev.h>
  28. #include <linux/clk-provider.h>
  29. #include <linux/delay.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/module.h>
  32. #include <linux/of.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/pm_runtime.h>
  35. #include <linux/regmap.h>
  36. #include <linux/videodev2.h>
  37. #include <media/v4l2-device.h>
  38. #include <media/v4l2-image-sizes.h>
  39. #include <media/v4l2-ioctl.h>
  40. #include <media/v4l2-of.h>
  41. #include <media/v4l2-subdev.h>
  42. #include <media/videobuf2-dma-contig.h>
  43. #include "atmel-isc-regs.h"
  44. #define ATMEL_ISC_NAME "atmel_isc"
  45. #define ISC_MAX_SUPPORT_WIDTH 2592
  46. #define ISC_MAX_SUPPORT_HEIGHT 1944
  47. #define ISC_CLK_MAX_DIV 255
  48. enum isc_clk_id {
  49. ISC_ISPCK = 0,
  50. ISC_MCK = 1,
  51. };
  52. struct isc_clk {
  53. struct clk_hw hw;
  54. struct clk *clk;
  55. struct regmap *regmap;
  56. u8 id;
  57. u8 parent_id;
  58. u32 div;
  59. struct device *dev;
  60. };
  61. #define to_isc_clk(hw) container_of(hw, struct isc_clk, hw)
  62. struct isc_buffer {
  63. struct vb2_v4l2_buffer vb;
  64. struct list_head list;
  65. };
  66. struct isc_subdev_entity {
  67. struct v4l2_subdev *sd;
  68. struct v4l2_async_subdev *asd;
  69. struct v4l2_async_notifier notifier;
  70. struct v4l2_subdev_pad_config *config;
  71. u32 pfe_cfg0;
  72. struct list_head list;
  73. };
  74. /*
  75. * struct isc_format - ISC media bus format information
  76. * @fourcc: Fourcc code for this format
  77. * @mbus_code: V4L2 media bus format code.
  78. * @bpp: Bytes per pixel (when stored in memory)
  79. * @reg_bps: reg value for bits per sample
  80. * (when transferred over a bus)
  81. * @support: Indicates format supported by subdev
  82. */
  83. struct isc_format {
  84. u32 fourcc;
  85. u32 mbus_code;
  86. u8 bpp;
  87. u32 reg_bps;
  88. u32 reg_rlp_mode;
  89. u32 reg_dcfg_imode;
  90. u32 reg_dctrl_dview;
  91. bool support;
  92. };
  93. #define ISC_PIPE_LINE_NODE_NUM 11
  94. struct isc_device {
  95. struct regmap *regmap;
  96. struct clk *hclock;
  97. struct clk *ispck;
  98. struct isc_clk isc_clks[2];
  99. struct device *dev;
  100. struct v4l2_device v4l2_dev;
  101. struct video_device video_dev;
  102. struct vb2_queue vb2_vidq;
  103. spinlock_t dma_queue_lock;
  104. struct list_head dma_queue;
  105. struct isc_buffer *cur_frm;
  106. unsigned int sequence;
  107. bool stop;
  108. struct completion comp;
  109. struct v4l2_format fmt;
  110. struct isc_format **user_formats;
  111. unsigned int num_user_formats;
  112. const struct isc_format *current_fmt;
  113. struct mutex lock;
  114. struct regmap_field *pipeline[ISC_PIPE_LINE_NODE_NUM];
  115. struct isc_subdev_entity *current_subdev;
  116. struct list_head subdev_entities;
  117. };
  118. static struct isc_format isc_formats[] = {
  119. { V4L2_PIX_FMT_SBGGR8, MEDIA_BUS_FMT_SBGGR8_1X8,
  120. 1, ISC_PFE_CFG0_BPS_EIGHT, ISC_RLP_CFG_MODE_DAT8,
  121. ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, false },
  122. { V4L2_PIX_FMT_SGBRG8, MEDIA_BUS_FMT_SGBRG8_1X8,
  123. 1, ISC_PFE_CFG0_BPS_EIGHT, ISC_RLP_CFG_MODE_DAT8,
  124. ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, false },
  125. { V4L2_PIX_FMT_SGRBG8, MEDIA_BUS_FMT_SGRBG8_1X8,
  126. 1, ISC_PFE_CFG0_BPS_EIGHT, ISC_RLP_CFG_MODE_DAT8,
  127. ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, false },
  128. { V4L2_PIX_FMT_SRGGB8, MEDIA_BUS_FMT_SRGGB8_1X8,
  129. 1, ISC_PFE_CFG0_BPS_EIGHT, ISC_RLP_CFG_MODE_DAT8,
  130. ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, false },
  131. { V4L2_PIX_FMT_SBGGR10, MEDIA_BUS_FMT_SBGGR10_1X10,
  132. 2, ISC_PFG_CFG0_BPS_TEN, ISC_RLP_CFG_MODE_DAT10,
  133. ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, false },
  134. { V4L2_PIX_FMT_SGBRG10, MEDIA_BUS_FMT_SGBRG10_1X10,
  135. 2, ISC_PFG_CFG0_BPS_TEN, ISC_RLP_CFG_MODE_DAT10,
  136. ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, false },
  137. { V4L2_PIX_FMT_SGRBG10, MEDIA_BUS_FMT_SGRBG10_1X10,
  138. 2, ISC_PFG_CFG0_BPS_TEN, ISC_RLP_CFG_MODE_DAT10,
  139. ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, false },
  140. { V4L2_PIX_FMT_SRGGB10, MEDIA_BUS_FMT_SRGGB10_1X10,
  141. 2, ISC_PFG_CFG0_BPS_TEN, ISC_RLP_CFG_MODE_DAT10,
  142. ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, false },
  143. { V4L2_PIX_FMT_SBGGR12, MEDIA_BUS_FMT_SBGGR12_1X12,
  144. 2, ISC_PFG_CFG0_BPS_TWELVE, ISC_RLP_CFG_MODE_DAT12,
  145. ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, false },
  146. { V4L2_PIX_FMT_SGBRG12, MEDIA_BUS_FMT_SGBRG12_1X12,
  147. 2, ISC_PFG_CFG0_BPS_TWELVE, ISC_RLP_CFG_MODE_DAT12,
  148. ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, false },
  149. { V4L2_PIX_FMT_SGRBG12, MEDIA_BUS_FMT_SGRBG12_1X12,
  150. 2, ISC_PFG_CFG0_BPS_TWELVE, ISC_RLP_CFG_MODE_DAT12,
  151. ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, false },
  152. { V4L2_PIX_FMT_SRGGB12, MEDIA_BUS_FMT_SRGGB12_1X12,
  153. 2, ISC_PFG_CFG0_BPS_TWELVE, ISC_RLP_CFG_MODE_DAT12,
  154. ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, false },
  155. { V4L2_PIX_FMT_YUYV, MEDIA_BUS_FMT_YUYV8_2X8,
  156. 2, ISC_PFE_CFG0_BPS_EIGHT, ISC_RLP_CFG_MODE_DAT8,
  157. ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, false },
  158. };
  159. static int isc_clk_enable(struct clk_hw *hw)
  160. {
  161. struct isc_clk *isc_clk = to_isc_clk(hw);
  162. u32 id = isc_clk->id;
  163. struct regmap *regmap = isc_clk->regmap;
  164. dev_dbg(isc_clk->dev, "ISC CLK: %s, div = %d, parent id = %d\n",
  165. __func__, isc_clk->div, isc_clk->parent_id);
  166. regmap_update_bits(regmap, ISC_CLKCFG,
  167. ISC_CLKCFG_DIV_MASK(id) | ISC_CLKCFG_SEL_MASK(id),
  168. (isc_clk->div << ISC_CLKCFG_DIV_SHIFT(id)) |
  169. (isc_clk->parent_id << ISC_CLKCFG_SEL_SHIFT(id)));
  170. regmap_write(regmap, ISC_CLKEN, ISC_CLK(id));
  171. return 0;
  172. }
  173. static void isc_clk_disable(struct clk_hw *hw)
  174. {
  175. struct isc_clk *isc_clk = to_isc_clk(hw);
  176. u32 id = isc_clk->id;
  177. regmap_write(isc_clk->regmap, ISC_CLKDIS, ISC_CLK(id));
  178. }
  179. static int isc_clk_is_enabled(struct clk_hw *hw)
  180. {
  181. struct isc_clk *isc_clk = to_isc_clk(hw);
  182. u32 status;
  183. regmap_read(isc_clk->regmap, ISC_CLKSR, &status);
  184. return status & ISC_CLK(isc_clk->id) ? 1 : 0;
  185. }
  186. static unsigned long
  187. isc_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
  188. {
  189. struct isc_clk *isc_clk = to_isc_clk(hw);
  190. return DIV_ROUND_CLOSEST(parent_rate, isc_clk->div + 1);
  191. }
  192. static int isc_clk_determine_rate(struct clk_hw *hw,
  193. struct clk_rate_request *req)
  194. {
  195. struct isc_clk *isc_clk = to_isc_clk(hw);
  196. long best_rate = -EINVAL;
  197. int best_diff = -1;
  198. unsigned int i, div;
  199. for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
  200. struct clk_hw *parent;
  201. unsigned long parent_rate;
  202. parent = clk_hw_get_parent_by_index(hw, i);
  203. if (!parent)
  204. continue;
  205. parent_rate = clk_hw_get_rate(parent);
  206. if (!parent_rate)
  207. continue;
  208. for (div = 1; div < ISC_CLK_MAX_DIV + 2; div++) {
  209. unsigned long rate;
  210. int diff;
  211. rate = DIV_ROUND_CLOSEST(parent_rate, div);
  212. diff = abs(req->rate - rate);
  213. if (best_diff < 0 || best_diff > diff) {
  214. best_rate = rate;
  215. best_diff = diff;
  216. req->best_parent_rate = parent_rate;
  217. req->best_parent_hw = parent;
  218. }
  219. if (!best_diff || rate < req->rate)
  220. break;
  221. }
  222. if (!best_diff)
  223. break;
  224. }
  225. dev_dbg(isc_clk->dev,
  226. "ISC CLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
  227. __func__, best_rate,
  228. __clk_get_name((req->best_parent_hw)->clk),
  229. req->best_parent_rate);
  230. if (best_rate < 0)
  231. return best_rate;
  232. req->rate = best_rate;
  233. return 0;
  234. }
  235. static int isc_clk_set_parent(struct clk_hw *hw, u8 index)
  236. {
  237. struct isc_clk *isc_clk = to_isc_clk(hw);
  238. if (index >= clk_hw_get_num_parents(hw))
  239. return -EINVAL;
  240. isc_clk->parent_id = index;
  241. return 0;
  242. }
  243. static u8 isc_clk_get_parent(struct clk_hw *hw)
  244. {
  245. struct isc_clk *isc_clk = to_isc_clk(hw);
  246. return isc_clk->parent_id;
  247. }
  248. static int isc_clk_set_rate(struct clk_hw *hw,
  249. unsigned long rate,
  250. unsigned long parent_rate)
  251. {
  252. struct isc_clk *isc_clk = to_isc_clk(hw);
  253. u32 div;
  254. if (!rate)
  255. return -EINVAL;
  256. div = DIV_ROUND_CLOSEST(parent_rate, rate);
  257. if (div > (ISC_CLK_MAX_DIV + 1) || !div)
  258. return -EINVAL;
  259. isc_clk->div = div - 1;
  260. return 0;
  261. }
  262. static const struct clk_ops isc_clk_ops = {
  263. .enable = isc_clk_enable,
  264. .disable = isc_clk_disable,
  265. .is_enabled = isc_clk_is_enabled,
  266. .recalc_rate = isc_clk_recalc_rate,
  267. .determine_rate = isc_clk_determine_rate,
  268. .set_parent = isc_clk_set_parent,
  269. .get_parent = isc_clk_get_parent,
  270. .set_rate = isc_clk_set_rate,
  271. };
  272. static int isc_clk_register(struct isc_device *isc, unsigned int id)
  273. {
  274. struct regmap *regmap = isc->regmap;
  275. struct device_node *np = isc->dev->of_node;
  276. struct isc_clk *isc_clk;
  277. struct clk_init_data init;
  278. const char *clk_name = np->name;
  279. const char *parent_names[3];
  280. int num_parents;
  281. num_parents = of_clk_get_parent_count(np);
  282. if (num_parents < 1 || num_parents > 3)
  283. return -EINVAL;
  284. if (num_parents > 2 && id == ISC_ISPCK)
  285. num_parents = 2;
  286. of_clk_parent_fill(np, parent_names, num_parents);
  287. if (id == ISC_MCK)
  288. of_property_read_string(np, "clock-output-names", &clk_name);
  289. else
  290. clk_name = "isc-ispck";
  291. init.parent_names = parent_names;
  292. init.num_parents = num_parents;
  293. init.name = clk_name;
  294. init.ops = &isc_clk_ops;
  295. init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
  296. isc_clk = &isc->isc_clks[id];
  297. isc_clk->hw.init = &init;
  298. isc_clk->regmap = regmap;
  299. isc_clk->id = id;
  300. isc_clk->dev = isc->dev;
  301. isc_clk->clk = clk_register(isc->dev, &isc_clk->hw);
  302. if (IS_ERR(isc_clk->clk)) {
  303. dev_err(isc->dev, "%s: clock register fail\n", clk_name);
  304. return PTR_ERR(isc_clk->clk);
  305. } else if (id == ISC_MCK)
  306. of_clk_add_provider(np, of_clk_src_simple_get, isc_clk->clk);
  307. return 0;
  308. }
  309. static int isc_clk_init(struct isc_device *isc)
  310. {
  311. unsigned int i;
  312. int ret;
  313. for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++)
  314. isc->isc_clks[i].clk = ERR_PTR(-EINVAL);
  315. for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) {
  316. ret = isc_clk_register(isc, i);
  317. if (ret)
  318. return ret;
  319. }
  320. return 0;
  321. }
  322. static void isc_clk_cleanup(struct isc_device *isc)
  323. {
  324. unsigned int i;
  325. of_clk_del_provider(isc->dev->of_node);
  326. for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) {
  327. struct isc_clk *isc_clk = &isc->isc_clks[i];
  328. if (!IS_ERR(isc_clk->clk))
  329. clk_unregister(isc_clk->clk);
  330. }
  331. }
  332. static int isc_queue_setup(struct vb2_queue *vq,
  333. unsigned int *nbuffers, unsigned int *nplanes,
  334. unsigned int sizes[], struct device *alloc_devs[])
  335. {
  336. struct isc_device *isc = vb2_get_drv_priv(vq);
  337. unsigned int size = isc->fmt.fmt.pix.sizeimage;
  338. if (*nplanes)
  339. return sizes[0] < size ? -EINVAL : 0;
  340. *nplanes = 1;
  341. sizes[0] = size;
  342. return 0;
  343. }
  344. static int isc_buffer_prepare(struct vb2_buffer *vb)
  345. {
  346. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  347. struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
  348. unsigned long size = isc->fmt.fmt.pix.sizeimage;
  349. if (vb2_plane_size(vb, 0) < size) {
  350. v4l2_err(&isc->v4l2_dev, "buffer too small (%lu < %lu)\n",
  351. vb2_plane_size(vb, 0), size);
  352. return -EINVAL;
  353. }
  354. vb2_set_plane_payload(vb, 0, size);
  355. vbuf->field = isc->fmt.fmt.pix.field;
  356. return 0;
  357. }
  358. static inline void isc_start_dma(struct regmap *regmap,
  359. struct isc_buffer *frm, u32 dview)
  360. {
  361. dma_addr_t addr;
  362. addr = vb2_dma_contig_plane_dma_addr(&frm->vb.vb2_buf, 0);
  363. regmap_write(regmap, ISC_DCTRL, dview | ISC_DCTRL_IE_IS);
  364. regmap_write(regmap, ISC_DAD0, addr);
  365. regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE);
  366. }
  367. static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
  368. {
  369. u32 val;
  370. unsigned int i;
  371. for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
  372. val = pipeline & BIT(i) ? 1 : 0;
  373. regmap_field_write(isc->pipeline[i], val);
  374. }
  375. }
  376. static int isc_configure(struct isc_device *isc)
  377. {
  378. struct regmap *regmap = isc->regmap;
  379. const struct isc_format *current_fmt = isc->current_fmt;
  380. struct isc_subdev_entity *subdev = isc->current_subdev;
  381. u32 val, mask;
  382. int counter = 10;
  383. val = current_fmt->reg_bps | subdev->pfe_cfg0 |
  384. ISC_PFE_CFG0_MODE_PROGRESSIVE;
  385. mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
  386. ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW |
  387. ISC_PFE_CFG0_MODE_MASK;
  388. regmap_update_bits(regmap, ISC_PFE_CFG0, mask, val);
  389. regmap_update_bits(regmap, ISC_RLP_CFG, ISC_RLP_CFG_MODE_MASK,
  390. current_fmt->reg_rlp_mode);
  391. regmap_update_bits(regmap, ISC_DCFG, ISC_DCFG_IMODE_MASK,
  392. current_fmt->reg_dcfg_imode);
  393. /* Disable the pipeline */
  394. isc_set_pipeline(isc, 0x0);
  395. /* Update profile */
  396. regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_UPPRO);
  397. regmap_read(regmap, ISC_CTRLSR, &val);
  398. while ((val & ISC_CTRL_UPPRO) && counter--) {
  399. usleep_range(1000, 2000);
  400. regmap_read(regmap, ISC_CTRLSR, &val);
  401. }
  402. if (counter < 0)
  403. return -ETIMEDOUT;
  404. return 0;
  405. }
  406. static int isc_start_streaming(struct vb2_queue *vq, unsigned int count)
  407. {
  408. struct isc_device *isc = vb2_get_drv_priv(vq);
  409. struct regmap *regmap = isc->regmap;
  410. struct isc_buffer *buf;
  411. unsigned long flags;
  412. int ret;
  413. u32 val;
  414. /* Enable stream on the sub device */
  415. ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 1);
  416. if (ret && ret != -ENOIOCTLCMD) {
  417. v4l2_err(&isc->v4l2_dev, "stream on failed in subdev\n");
  418. goto err_start_stream;
  419. }
  420. pm_runtime_get_sync(isc->dev);
  421. /* Disable all the interrupts */
  422. regmap_write(isc->regmap, ISC_INTDIS, (u32)~0UL);
  423. /* Clean the interrupt status register */
  424. regmap_read(regmap, ISC_INTSR, &val);
  425. ret = isc_configure(isc);
  426. if (unlikely(ret))
  427. goto err_configure;
  428. /* Enable DMA interrupt */
  429. regmap_write(regmap, ISC_INTEN, ISC_INT_DDONE);
  430. spin_lock_irqsave(&isc->dma_queue_lock, flags);
  431. isc->sequence = 0;
  432. isc->stop = false;
  433. reinit_completion(&isc->comp);
  434. isc->cur_frm = list_first_entry(&isc->dma_queue,
  435. struct isc_buffer, list);
  436. list_del(&isc->cur_frm->list);
  437. isc_start_dma(regmap, isc->cur_frm, isc->current_fmt->reg_dctrl_dview);
  438. spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
  439. return 0;
  440. err_configure:
  441. pm_runtime_put_sync(isc->dev);
  442. v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
  443. err_start_stream:
  444. spin_lock_irqsave(&isc->dma_queue_lock, flags);
  445. list_for_each_entry(buf, &isc->dma_queue, list)
  446. vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
  447. INIT_LIST_HEAD(&isc->dma_queue);
  448. spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
  449. return ret;
  450. }
  451. static void isc_stop_streaming(struct vb2_queue *vq)
  452. {
  453. struct isc_device *isc = vb2_get_drv_priv(vq);
  454. unsigned long flags;
  455. struct isc_buffer *buf;
  456. int ret;
  457. isc->stop = true;
  458. /* Wait until the end of the current frame */
  459. if (isc->cur_frm && !wait_for_completion_timeout(&isc->comp, 5 * HZ))
  460. v4l2_err(&isc->v4l2_dev,
  461. "Timeout waiting for end of the capture\n");
  462. /* Disable DMA interrupt */
  463. regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE);
  464. pm_runtime_put_sync(isc->dev);
  465. /* Disable stream on the sub device */
  466. ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
  467. if (ret && ret != -ENOIOCTLCMD)
  468. v4l2_err(&isc->v4l2_dev, "stream off failed in subdev\n");
  469. /* Release all active buffers */
  470. spin_lock_irqsave(&isc->dma_queue_lock, flags);
  471. if (unlikely(isc->cur_frm)) {
  472. vb2_buffer_done(&isc->cur_frm->vb.vb2_buf,
  473. VB2_BUF_STATE_ERROR);
  474. isc->cur_frm = NULL;
  475. }
  476. list_for_each_entry(buf, &isc->dma_queue, list)
  477. vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
  478. INIT_LIST_HEAD(&isc->dma_queue);
  479. spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
  480. }
  481. static void isc_buffer_queue(struct vb2_buffer *vb)
  482. {
  483. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  484. struct isc_buffer *buf = container_of(vbuf, struct isc_buffer, vb);
  485. struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
  486. unsigned long flags;
  487. spin_lock_irqsave(&isc->dma_queue_lock, flags);
  488. if (!isc->cur_frm && list_empty(&isc->dma_queue) &&
  489. vb2_is_streaming(vb->vb2_queue)) {
  490. isc->cur_frm = buf;
  491. isc_start_dma(isc->regmap, isc->cur_frm,
  492. isc->current_fmt->reg_dctrl_dview);
  493. } else
  494. list_add_tail(&buf->list, &isc->dma_queue);
  495. spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
  496. }
  497. static struct vb2_ops isc_vb2_ops = {
  498. .queue_setup = isc_queue_setup,
  499. .wait_prepare = vb2_ops_wait_prepare,
  500. .wait_finish = vb2_ops_wait_finish,
  501. .buf_prepare = isc_buffer_prepare,
  502. .start_streaming = isc_start_streaming,
  503. .stop_streaming = isc_stop_streaming,
  504. .buf_queue = isc_buffer_queue,
  505. };
  506. static int isc_querycap(struct file *file, void *priv,
  507. struct v4l2_capability *cap)
  508. {
  509. struct isc_device *isc = video_drvdata(file);
  510. strcpy(cap->driver, ATMEL_ISC_NAME);
  511. strcpy(cap->card, "Atmel Image Sensor Controller");
  512. snprintf(cap->bus_info, sizeof(cap->bus_info),
  513. "platform:%s", isc->v4l2_dev.name);
  514. return 0;
  515. }
  516. static int isc_enum_fmt_vid_cap(struct file *file, void *priv,
  517. struct v4l2_fmtdesc *f)
  518. {
  519. struct isc_device *isc = video_drvdata(file);
  520. u32 index = f->index;
  521. if (index >= isc->num_user_formats)
  522. return -EINVAL;
  523. f->pixelformat = isc->user_formats[index]->fourcc;
  524. return 0;
  525. }
  526. static int isc_g_fmt_vid_cap(struct file *file, void *priv,
  527. struct v4l2_format *fmt)
  528. {
  529. struct isc_device *isc = video_drvdata(file);
  530. *fmt = isc->fmt;
  531. return 0;
  532. }
  533. static struct isc_format *find_format_by_fourcc(struct isc_device *isc,
  534. unsigned int fourcc)
  535. {
  536. unsigned int num_formats = isc->num_user_formats;
  537. struct isc_format *fmt;
  538. unsigned int i;
  539. for (i = 0; i < num_formats; i++) {
  540. fmt = isc->user_formats[i];
  541. if (fmt->fourcc == fourcc)
  542. return fmt;
  543. }
  544. return NULL;
  545. }
  546. static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f,
  547. struct isc_format **current_fmt)
  548. {
  549. struct isc_format *isc_fmt;
  550. struct v4l2_pix_format *pixfmt = &f->fmt.pix;
  551. struct v4l2_subdev_format format = {
  552. .which = V4L2_SUBDEV_FORMAT_TRY,
  553. };
  554. int ret;
  555. if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
  556. return -EINVAL;
  557. isc_fmt = find_format_by_fourcc(isc, pixfmt->pixelformat);
  558. if (!isc_fmt) {
  559. v4l2_warn(&isc->v4l2_dev, "Format 0x%x not found\n",
  560. pixfmt->pixelformat);
  561. isc_fmt = isc->user_formats[isc->num_user_formats - 1];
  562. pixfmt->pixelformat = isc_fmt->fourcc;
  563. }
  564. /* Limit to Atmel ISC hardware capabilities */
  565. if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH)
  566. pixfmt->width = ISC_MAX_SUPPORT_WIDTH;
  567. if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT)
  568. pixfmt->height = ISC_MAX_SUPPORT_HEIGHT;
  569. v4l2_fill_mbus_format(&format.format, pixfmt, isc_fmt->mbus_code);
  570. ret = v4l2_subdev_call(isc->current_subdev->sd, pad, set_fmt,
  571. isc->current_subdev->config, &format);
  572. if (ret < 0)
  573. return ret;
  574. v4l2_fill_pix_format(pixfmt, &format.format);
  575. pixfmt->field = V4L2_FIELD_NONE;
  576. pixfmt->bytesperline = pixfmt->width * isc_fmt->bpp;
  577. pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height;
  578. if (current_fmt)
  579. *current_fmt = isc_fmt;
  580. return 0;
  581. }
  582. static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f)
  583. {
  584. struct v4l2_subdev_format format = {
  585. .which = V4L2_SUBDEV_FORMAT_ACTIVE,
  586. };
  587. struct isc_format *current_fmt;
  588. int ret;
  589. ret = isc_try_fmt(isc, f, &current_fmt);
  590. if (ret)
  591. return ret;
  592. v4l2_fill_mbus_format(&format.format, &f->fmt.pix,
  593. current_fmt->mbus_code);
  594. ret = v4l2_subdev_call(isc->current_subdev->sd, pad,
  595. set_fmt, NULL, &format);
  596. if (ret < 0)
  597. return ret;
  598. isc->fmt = *f;
  599. isc->current_fmt = current_fmt;
  600. return 0;
  601. }
  602. static int isc_s_fmt_vid_cap(struct file *file, void *priv,
  603. struct v4l2_format *f)
  604. {
  605. struct isc_device *isc = video_drvdata(file);
  606. if (vb2_is_streaming(&isc->vb2_vidq))
  607. return -EBUSY;
  608. return isc_set_fmt(isc, f);
  609. }
  610. static int isc_try_fmt_vid_cap(struct file *file, void *priv,
  611. struct v4l2_format *f)
  612. {
  613. struct isc_device *isc = video_drvdata(file);
  614. return isc_try_fmt(isc, f, NULL);
  615. }
  616. static int isc_enum_input(struct file *file, void *priv,
  617. struct v4l2_input *inp)
  618. {
  619. if (inp->index != 0)
  620. return -EINVAL;
  621. inp->type = V4L2_INPUT_TYPE_CAMERA;
  622. inp->std = 0;
  623. strcpy(inp->name, "Camera");
  624. return 0;
  625. }
  626. static int isc_g_input(struct file *file, void *priv, unsigned int *i)
  627. {
  628. *i = 0;
  629. return 0;
  630. }
  631. static int isc_s_input(struct file *file, void *priv, unsigned int i)
  632. {
  633. if (i > 0)
  634. return -EINVAL;
  635. return 0;
  636. }
  637. static int isc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
  638. {
  639. struct isc_device *isc = video_drvdata(file);
  640. if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
  641. return -EINVAL;
  642. return v4l2_subdev_call(isc->current_subdev->sd, video, g_parm, a);
  643. }
  644. static int isc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
  645. {
  646. struct isc_device *isc = video_drvdata(file);
  647. if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
  648. return -EINVAL;
  649. return v4l2_subdev_call(isc->current_subdev->sd, video, s_parm, a);
  650. }
  651. static int isc_enum_framesizes(struct file *file, void *fh,
  652. struct v4l2_frmsizeenum *fsize)
  653. {
  654. struct isc_device *isc = video_drvdata(file);
  655. const struct isc_format *isc_fmt;
  656. struct v4l2_subdev_frame_size_enum fse = {
  657. .index = fsize->index,
  658. .which = V4L2_SUBDEV_FORMAT_ACTIVE,
  659. };
  660. int ret;
  661. isc_fmt = find_format_by_fourcc(isc, fsize->pixel_format);
  662. if (!isc_fmt)
  663. return -EINVAL;
  664. fse.code = isc_fmt->mbus_code;
  665. ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size,
  666. NULL, &fse);
  667. if (ret)
  668. return ret;
  669. fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
  670. fsize->discrete.width = fse.max_width;
  671. fsize->discrete.height = fse.max_height;
  672. return 0;
  673. }
  674. static int isc_enum_frameintervals(struct file *file, void *fh,
  675. struct v4l2_frmivalenum *fival)
  676. {
  677. struct isc_device *isc = video_drvdata(file);
  678. const struct isc_format *isc_fmt;
  679. struct v4l2_subdev_frame_interval_enum fie = {
  680. .index = fival->index,
  681. .width = fival->width,
  682. .height = fival->height,
  683. .which = V4L2_SUBDEV_FORMAT_ACTIVE,
  684. };
  685. int ret;
  686. isc_fmt = find_format_by_fourcc(isc, fival->pixel_format);
  687. if (!isc_fmt)
  688. return -EINVAL;
  689. fie.code = isc_fmt->mbus_code;
  690. ret = v4l2_subdev_call(isc->current_subdev->sd, pad,
  691. enum_frame_interval, NULL, &fie);
  692. if (ret)
  693. return ret;
  694. fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
  695. fival->discrete = fie.interval;
  696. return 0;
  697. }
  698. static const struct v4l2_ioctl_ops isc_ioctl_ops = {
  699. .vidioc_querycap = isc_querycap,
  700. .vidioc_enum_fmt_vid_cap = isc_enum_fmt_vid_cap,
  701. .vidioc_g_fmt_vid_cap = isc_g_fmt_vid_cap,
  702. .vidioc_s_fmt_vid_cap = isc_s_fmt_vid_cap,
  703. .vidioc_try_fmt_vid_cap = isc_try_fmt_vid_cap,
  704. .vidioc_enum_input = isc_enum_input,
  705. .vidioc_g_input = isc_g_input,
  706. .vidioc_s_input = isc_s_input,
  707. .vidioc_reqbufs = vb2_ioctl_reqbufs,
  708. .vidioc_querybuf = vb2_ioctl_querybuf,
  709. .vidioc_qbuf = vb2_ioctl_qbuf,
  710. .vidioc_expbuf = vb2_ioctl_expbuf,
  711. .vidioc_dqbuf = vb2_ioctl_dqbuf,
  712. .vidioc_create_bufs = vb2_ioctl_create_bufs,
  713. .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
  714. .vidioc_streamon = vb2_ioctl_streamon,
  715. .vidioc_streamoff = vb2_ioctl_streamoff,
  716. .vidioc_g_parm = isc_g_parm,
  717. .vidioc_s_parm = isc_s_parm,
  718. .vidioc_enum_framesizes = isc_enum_framesizes,
  719. .vidioc_enum_frameintervals = isc_enum_frameintervals,
  720. };
  721. static int isc_open(struct file *file)
  722. {
  723. struct isc_device *isc = video_drvdata(file);
  724. struct v4l2_subdev *sd = isc->current_subdev->sd;
  725. int ret;
  726. if (mutex_lock_interruptible(&isc->lock))
  727. return -ERESTARTSYS;
  728. ret = v4l2_fh_open(file);
  729. if (ret < 0)
  730. goto unlock;
  731. if (!v4l2_fh_is_singular_file(file))
  732. goto unlock;
  733. ret = v4l2_subdev_call(sd, core, s_power, 1);
  734. if (ret < 0 && ret != -ENOIOCTLCMD) {
  735. v4l2_fh_release(file);
  736. goto unlock;
  737. }
  738. ret = isc_set_fmt(isc, &isc->fmt);
  739. if (ret) {
  740. v4l2_subdev_call(sd, core, s_power, 0);
  741. v4l2_fh_release(file);
  742. }
  743. unlock:
  744. mutex_unlock(&isc->lock);
  745. return ret;
  746. }
  747. static int isc_release(struct file *file)
  748. {
  749. struct isc_device *isc = video_drvdata(file);
  750. struct v4l2_subdev *sd = isc->current_subdev->sd;
  751. bool fh_singular;
  752. int ret;
  753. mutex_lock(&isc->lock);
  754. fh_singular = v4l2_fh_is_singular_file(file);
  755. ret = _vb2_fop_release(file, NULL);
  756. if (fh_singular)
  757. v4l2_subdev_call(sd, core, s_power, 0);
  758. mutex_unlock(&isc->lock);
  759. return ret;
  760. }
  761. static const struct v4l2_file_operations isc_fops = {
  762. .owner = THIS_MODULE,
  763. .open = isc_open,
  764. .release = isc_release,
  765. .unlocked_ioctl = video_ioctl2,
  766. .read = vb2_fop_read,
  767. .mmap = vb2_fop_mmap,
  768. .poll = vb2_fop_poll,
  769. };
  770. static irqreturn_t isc_interrupt(int irq, void *dev_id)
  771. {
  772. struct isc_device *isc = (struct isc_device *)dev_id;
  773. struct regmap *regmap = isc->regmap;
  774. u32 isc_intsr, isc_intmask, pending;
  775. irqreturn_t ret = IRQ_NONE;
  776. spin_lock(&isc->dma_queue_lock);
  777. regmap_read(regmap, ISC_INTSR, &isc_intsr);
  778. regmap_read(regmap, ISC_INTMASK, &isc_intmask);
  779. pending = isc_intsr & isc_intmask;
  780. if (likely(pending & ISC_INT_DDONE)) {
  781. if (isc->cur_frm) {
  782. struct vb2_v4l2_buffer *vbuf = &isc->cur_frm->vb;
  783. struct vb2_buffer *vb = &vbuf->vb2_buf;
  784. vb->timestamp = ktime_get_ns();
  785. vbuf->sequence = isc->sequence++;
  786. vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
  787. isc->cur_frm = NULL;
  788. }
  789. if (!list_empty(&isc->dma_queue) && !isc->stop) {
  790. isc->cur_frm = list_first_entry(&isc->dma_queue,
  791. struct isc_buffer, list);
  792. list_del(&isc->cur_frm->list);
  793. isc_start_dma(regmap, isc->cur_frm,
  794. isc->current_fmt->reg_dctrl_dview);
  795. }
  796. if (isc->stop)
  797. complete(&isc->comp);
  798. ret = IRQ_HANDLED;
  799. }
  800. spin_unlock(&isc->dma_queue_lock);
  801. return ret;
  802. }
  803. static int isc_async_bound(struct v4l2_async_notifier *notifier,
  804. struct v4l2_subdev *subdev,
  805. struct v4l2_async_subdev *asd)
  806. {
  807. struct isc_device *isc = container_of(notifier->v4l2_dev,
  808. struct isc_device, v4l2_dev);
  809. struct isc_subdev_entity *subdev_entity =
  810. container_of(notifier, struct isc_subdev_entity, notifier);
  811. if (video_is_registered(&isc->video_dev)) {
  812. v4l2_err(&isc->v4l2_dev, "only supports one sub-device.\n");
  813. return -EBUSY;
  814. }
  815. subdev_entity->sd = subdev;
  816. return 0;
  817. }
  818. static void isc_async_unbind(struct v4l2_async_notifier *notifier,
  819. struct v4l2_subdev *subdev,
  820. struct v4l2_async_subdev *asd)
  821. {
  822. struct isc_device *isc = container_of(notifier->v4l2_dev,
  823. struct isc_device, v4l2_dev);
  824. video_unregister_device(&isc->video_dev);
  825. if (isc->current_subdev->config)
  826. v4l2_subdev_free_pad_config(isc->current_subdev->config);
  827. }
  828. static struct isc_format *find_format_by_code(unsigned int code, int *index)
  829. {
  830. struct isc_format *fmt = &isc_formats[0];
  831. unsigned int i;
  832. for (i = 0; i < ARRAY_SIZE(isc_formats); i++) {
  833. if (fmt->mbus_code == code) {
  834. *index = i;
  835. return fmt;
  836. }
  837. fmt++;
  838. }
  839. return NULL;
  840. }
  841. static int isc_formats_init(struct isc_device *isc)
  842. {
  843. struct isc_format *fmt;
  844. struct v4l2_subdev *subdev = isc->current_subdev->sd;
  845. int num_fmts = 0, i, j;
  846. struct v4l2_subdev_mbus_code_enum mbus_code = {
  847. .which = V4L2_SUBDEV_FORMAT_ACTIVE,
  848. };
  849. fmt = &isc_formats[0];
  850. for (i = 0; i < ARRAY_SIZE(isc_formats); i++) {
  851. fmt->support = false;
  852. fmt++;
  853. }
  854. while (!v4l2_subdev_call(subdev, pad, enum_mbus_code,
  855. NULL, &mbus_code)) {
  856. mbus_code.index++;
  857. fmt = find_format_by_code(mbus_code.code, &i);
  858. if (!fmt)
  859. continue;
  860. fmt->support = true;
  861. num_fmts++;
  862. }
  863. if (!num_fmts)
  864. return -ENXIO;
  865. isc->num_user_formats = num_fmts;
  866. isc->user_formats = devm_kcalloc(isc->dev,
  867. num_fmts, sizeof(struct isc_format *),
  868. GFP_KERNEL);
  869. if (!isc->user_formats) {
  870. v4l2_err(&isc->v4l2_dev, "could not allocate memory\n");
  871. return -ENOMEM;
  872. }
  873. fmt = &isc_formats[0];
  874. for (i = 0, j = 0; i < ARRAY_SIZE(isc_formats); i++) {
  875. if (fmt->support)
  876. isc->user_formats[j++] = fmt;
  877. fmt++;
  878. }
  879. return 0;
  880. }
  881. static int isc_set_default_fmt(struct isc_device *isc)
  882. {
  883. struct v4l2_format f = {
  884. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  885. .fmt.pix = {
  886. .width = VGA_WIDTH,
  887. .height = VGA_HEIGHT,
  888. .field = V4L2_FIELD_NONE,
  889. .pixelformat = isc->user_formats[0]->fourcc,
  890. },
  891. };
  892. int ret;
  893. ret = isc_try_fmt(isc, &f, NULL);
  894. if (ret)
  895. return ret;
  896. isc->current_fmt = isc->user_formats[0];
  897. isc->fmt = f;
  898. return 0;
  899. }
  900. static int isc_async_complete(struct v4l2_async_notifier *notifier)
  901. {
  902. struct isc_device *isc = container_of(notifier->v4l2_dev,
  903. struct isc_device, v4l2_dev);
  904. struct isc_subdev_entity *sd_entity;
  905. struct video_device *vdev = &isc->video_dev;
  906. struct vb2_queue *q = &isc->vb2_vidq;
  907. int ret;
  908. isc->current_subdev = container_of(notifier,
  909. struct isc_subdev_entity, notifier);
  910. sd_entity = isc->current_subdev;
  911. mutex_init(&isc->lock);
  912. init_completion(&isc->comp);
  913. /* Initialize videobuf2 queue */
  914. q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  915. q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
  916. q->drv_priv = isc;
  917. q->buf_struct_size = sizeof(struct isc_buffer);
  918. q->ops = &isc_vb2_ops;
  919. q->mem_ops = &vb2_dma_contig_memops;
  920. q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
  921. q->lock = &isc->lock;
  922. q->min_buffers_needed = 1;
  923. q->dev = isc->dev;
  924. ret = vb2_queue_init(q);
  925. if (ret < 0) {
  926. v4l2_err(&isc->v4l2_dev,
  927. "vb2_queue_init() failed: %d\n", ret);
  928. return ret;
  929. }
  930. /* Init video dma queues */
  931. INIT_LIST_HEAD(&isc->dma_queue);
  932. spin_lock_init(&isc->dma_queue_lock);
  933. sd_entity->config = v4l2_subdev_alloc_pad_config(sd_entity->sd);
  934. if (sd_entity->config == NULL)
  935. return -ENOMEM;
  936. ret = isc_formats_init(isc);
  937. if (ret < 0) {
  938. v4l2_err(&isc->v4l2_dev,
  939. "Init format failed: %d\n", ret);
  940. return ret;
  941. }
  942. ret = isc_set_default_fmt(isc);
  943. if (ret) {
  944. v4l2_err(&isc->v4l2_dev, "Could not set default format\n");
  945. return ret;
  946. }
  947. /* Register video device */
  948. strlcpy(vdev->name, ATMEL_ISC_NAME, sizeof(vdev->name));
  949. vdev->release = video_device_release_empty;
  950. vdev->fops = &isc_fops;
  951. vdev->ioctl_ops = &isc_ioctl_ops;
  952. vdev->v4l2_dev = &isc->v4l2_dev;
  953. vdev->vfl_dir = VFL_DIR_RX;
  954. vdev->queue = q;
  955. vdev->lock = &isc->lock;
  956. vdev->ctrl_handler = isc->current_subdev->sd->ctrl_handler;
  957. vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE;
  958. video_set_drvdata(vdev, isc);
  959. ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1);
  960. if (ret < 0) {
  961. v4l2_err(&isc->v4l2_dev,
  962. "video_register_device failed: %d\n", ret);
  963. return ret;
  964. }
  965. return 0;
  966. }
  967. static void isc_subdev_cleanup(struct isc_device *isc)
  968. {
  969. struct isc_subdev_entity *subdev_entity;
  970. list_for_each_entry(subdev_entity, &isc->subdev_entities, list)
  971. v4l2_async_notifier_unregister(&subdev_entity->notifier);
  972. INIT_LIST_HEAD(&isc->subdev_entities);
  973. }
  974. static int isc_pipeline_init(struct isc_device *isc)
  975. {
  976. struct device *dev = isc->dev;
  977. struct regmap *regmap = isc->regmap;
  978. struct regmap_field *regs;
  979. unsigned int i;
  980. /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */
  981. const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = {
  982. REG_FIELD(ISC_WB_CTRL, 0, 0),
  983. REG_FIELD(ISC_CFA_CTRL, 0, 0),
  984. REG_FIELD(ISC_CC_CTRL, 0, 0),
  985. REG_FIELD(ISC_GAM_CTRL, 0, 0),
  986. REG_FIELD(ISC_GAM_CTRL, 1, 1),
  987. REG_FIELD(ISC_GAM_CTRL, 2, 2),
  988. REG_FIELD(ISC_GAM_CTRL, 3, 3),
  989. REG_FIELD(ISC_CSC_CTRL, 0, 0),
  990. REG_FIELD(ISC_CBC_CTRL, 0, 0),
  991. REG_FIELD(ISC_SUB422_CTRL, 0, 0),
  992. REG_FIELD(ISC_SUB420_CTRL, 0, 0),
  993. };
  994. for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
  995. regs = devm_regmap_field_alloc(dev, regmap, regfields[i]);
  996. if (IS_ERR(regs))
  997. return PTR_ERR(regs);
  998. isc->pipeline[i] = regs;
  999. }
  1000. return 0;
  1001. }
  1002. static int isc_parse_dt(struct device *dev, struct isc_device *isc)
  1003. {
  1004. struct device_node *np = dev->of_node;
  1005. struct device_node *epn = NULL, *rem;
  1006. struct v4l2_of_endpoint v4l2_epn;
  1007. struct isc_subdev_entity *subdev_entity;
  1008. unsigned int flags;
  1009. int ret;
  1010. INIT_LIST_HEAD(&isc->subdev_entities);
  1011. for (; ;) {
  1012. epn = of_graph_get_next_endpoint(np, epn);
  1013. if (!epn)
  1014. break;
  1015. rem = of_graph_get_remote_port_parent(epn);
  1016. if (!rem) {
  1017. dev_notice(dev, "Remote device at %s not found\n",
  1018. of_node_full_name(epn));
  1019. continue;
  1020. }
  1021. ret = v4l2_of_parse_endpoint(epn, &v4l2_epn);
  1022. if (ret) {
  1023. of_node_put(rem);
  1024. ret = -EINVAL;
  1025. dev_err(dev, "Could not parse the endpoint\n");
  1026. break;
  1027. }
  1028. subdev_entity = devm_kzalloc(dev,
  1029. sizeof(*subdev_entity), GFP_KERNEL);
  1030. if (subdev_entity == NULL) {
  1031. of_node_put(rem);
  1032. ret = -ENOMEM;
  1033. break;
  1034. }
  1035. subdev_entity->asd = devm_kzalloc(dev,
  1036. sizeof(*subdev_entity->asd), GFP_KERNEL);
  1037. if (subdev_entity->asd == NULL) {
  1038. of_node_put(rem);
  1039. ret = -ENOMEM;
  1040. break;
  1041. }
  1042. flags = v4l2_epn.bus.parallel.flags;
  1043. if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
  1044. subdev_entity->pfe_cfg0 = ISC_PFE_CFG0_HPOL_LOW;
  1045. if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
  1046. subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_VPOL_LOW;
  1047. if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
  1048. subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_PPOL_LOW;
  1049. subdev_entity->asd->match_type = V4L2_ASYNC_MATCH_OF;
  1050. subdev_entity->asd->match.of.node = rem;
  1051. list_add_tail(&subdev_entity->list, &isc->subdev_entities);
  1052. }
  1053. of_node_put(epn);
  1054. return ret;
  1055. }
  1056. /* regmap configuration */
  1057. #define ATMEL_ISC_REG_MAX 0xbfc
  1058. static const struct regmap_config isc_regmap_config = {
  1059. .reg_bits = 32,
  1060. .reg_stride = 4,
  1061. .val_bits = 32,
  1062. .max_register = ATMEL_ISC_REG_MAX,
  1063. };
  1064. static int atmel_isc_probe(struct platform_device *pdev)
  1065. {
  1066. struct device *dev = &pdev->dev;
  1067. struct isc_device *isc;
  1068. struct resource *res;
  1069. void __iomem *io_base;
  1070. struct isc_subdev_entity *subdev_entity;
  1071. int irq;
  1072. int ret;
  1073. isc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL);
  1074. if (!isc)
  1075. return -ENOMEM;
  1076. platform_set_drvdata(pdev, isc);
  1077. isc->dev = dev;
  1078. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1079. io_base = devm_ioremap_resource(dev, res);
  1080. if (IS_ERR(io_base))
  1081. return PTR_ERR(io_base);
  1082. isc->regmap = devm_regmap_init_mmio(dev, io_base, &isc_regmap_config);
  1083. if (IS_ERR(isc->regmap)) {
  1084. ret = PTR_ERR(isc->regmap);
  1085. dev_err(dev, "failed to init register map: %d\n", ret);
  1086. return ret;
  1087. }
  1088. irq = platform_get_irq(pdev, 0);
  1089. if (irq < 0) {
  1090. ret = irq;
  1091. dev_err(dev, "failed to get irq: %d\n", ret);
  1092. return ret;
  1093. }
  1094. ret = devm_request_irq(dev, irq, isc_interrupt, 0,
  1095. ATMEL_ISC_NAME, isc);
  1096. if (ret < 0) {
  1097. dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
  1098. irq, ret);
  1099. return ret;
  1100. }
  1101. ret = isc_pipeline_init(isc);
  1102. if (ret)
  1103. return ret;
  1104. isc->hclock = devm_clk_get(dev, "hclock");
  1105. if (IS_ERR(isc->hclock)) {
  1106. ret = PTR_ERR(isc->hclock);
  1107. dev_err(dev, "failed to get hclock: %d\n", ret);
  1108. return ret;
  1109. }
  1110. ret = isc_clk_init(isc);
  1111. if (ret) {
  1112. dev_err(dev, "failed to init isc clock: %d\n", ret);
  1113. goto clean_isc_clk;
  1114. }
  1115. isc->ispck = isc->isc_clks[ISC_ISPCK].clk;
  1116. /* ispck should be greater or equal to hclock */
  1117. ret = clk_set_rate(isc->ispck, clk_get_rate(isc->hclock));
  1118. if (ret) {
  1119. dev_err(dev, "failed to set ispck rate: %d\n", ret);
  1120. goto clean_isc_clk;
  1121. }
  1122. ret = v4l2_device_register(dev, &isc->v4l2_dev);
  1123. if (ret) {
  1124. dev_err(dev, "unable to register v4l2 device.\n");
  1125. goto clean_isc_clk;
  1126. }
  1127. ret = isc_parse_dt(dev, isc);
  1128. if (ret) {
  1129. dev_err(dev, "fail to parse device tree\n");
  1130. goto unregister_v4l2_device;
  1131. }
  1132. if (list_empty(&isc->subdev_entities)) {
  1133. dev_err(dev, "no subdev found\n");
  1134. ret = -ENODEV;
  1135. goto unregister_v4l2_device;
  1136. }
  1137. list_for_each_entry(subdev_entity, &isc->subdev_entities, list) {
  1138. subdev_entity->notifier.subdevs = &subdev_entity->asd;
  1139. subdev_entity->notifier.num_subdevs = 1;
  1140. subdev_entity->notifier.bound = isc_async_bound;
  1141. subdev_entity->notifier.unbind = isc_async_unbind;
  1142. subdev_entity->notifier.complete = isc_async_complete;
  1143. ret = v4l2_async_notifier_register(&isc->v4l2_dev,
  1144. &subdev_entity->notifier);
  1145. if (ret) {
  1146. dev_err(dev, "fail to register async notifier\n");
  1147. goto cleanup_subdev;
  1148. }
  1149. if (video_is_registered(&isc->video_dev))
  1150. break;
  1151. }
  1152. pm_runtime_enable(dev);
  1153. return 0;
  1154. cleanup_subdev:
  1155. isc_subdev_cleanup(isc);
  1156. unregister_v4l2_device:
  1157. v4l2_device_unregister(&isc->v4l2_dev);
  1158. clean_isc_clk:
  1159. isc_clk_cleanup(isc);
  1160. return ret;
  1161. }
  1162. static int atmel_isc_remove(struct platform_device *pdev)
  1163. {
  1164. struct isc_device *isc = platform_get_drvdata(pdev);
  1165. pm_runtime_disable(&pdev->dev);
  1166. isc_subdev_cleanup(isc);
  1167. v4l2_device_unregister(&isc->v4l2_dev);
  1168. isc_clk_cleanup(isc);
  1169. return 0;
  1170. }
  1171. static int __maybe_unused isc_runtime_suspend(struct device *dev)
  1172. {
  1173. struct isc_device *isc = dev_get_drvdata(dev);
  1174. clk_disable_unprepare(isc->ispck);
  1175. clk_disable_unprepare(isc->hclock);
  1176. return 0;
  1177. }
  1178. static int __maybe_unused isc_runtime_resume(struct device *dev)
  1179. {
  1180. struct isc_device *isc = dev_get_drvdata(dev);
  1181. int ret;
  1182. ret = clk_prepare_enable(isc->hclock);
  1183. if (ret)
  1184. return ret;
  1185. return clk_prepare_enable(isc->ispck);
  1186. }
  1187. static const struct dev_pm_ops atmel_isc_dev_pm_ops = {
  1188. SET_RUNTIME_PM_OPS(isc_runtime_suspend, isc_runtime_resume, NULL)
  1189. };
  1190. static const struct of_device_id atmel_isc_of_match[] = {
  1191. { .compatible = "atmel,sama5d2-isc" },
  1192. { }
  1193. };
  1194. MODULE_DEVICE_TABLE(of, atmel_isc_of_match);
  1195. static struct platform_driver atmel_isc_driver = {
  1196. .probe = atmel_isc_probe,
  1197. .remove = atmel_isc_remove,
  1198. .driver = {
  1199. .name = ATMEL_ISC_NAME,
  1200. .pm = &atmel_isc_dev_pm_ops,
  1201. .of_match_table = of_match_ptr(atmel_isc_of_match),
  1202. },
  1203. };
  1204. module_platform_driver(atmel_isc_driver);
  1205. MODULE_AUTHOR("Songjun Wu <songjun.wu@microchip.com>");
  1206. MODULE_DESCRIPTION("The V4L2 driver for Atmel-ISC");
  1207. MODULE_LICENSE("GPL v2");
  1208. MODULE_SUPPORTED_DEVICE("video");