tw5864-video.c 47 KB

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  1. /*
  2. * TW5864 driver - video encoding functions
  3. *
  4. * Copyright (C) 2016 Bluecherry, LLC <maintainers@bluecherrydvr.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/module.h>
  17. #include <media/v4l2-common.h>
  18. #include <media/v4l2-event.h>
  19. #include <media/videobuf2-dma-contig.h>
  20. #include "tw5864.h"
  21. #include "tw5864-reg.h"
  22. #define QUANTIZATION_TABLE_LEN 96
  23. #define VLC_LOOKUP_TABLE_LEN 1024
  24. static const u16 forward_quantization_table[QUANTIZATION_TABLE_LEN] = {
  25. 0x3333, 0x1f82, 0x3333, 0x1f82, 0x1f82, 0x147b, 0x1f82, 0x147b,
  26. 0x3333, 0x1f82, 0x3333, 0x1f82, 0x1f82, 0x147b, 0x1f82, 0x147b,
  27. 0x2e8c, 0x1d42, 0x2e8c, 0x1d42, 0x1d42, 0x1234, 0x1d42, 0x1234,
  28. 0x2e8c, 0x1d42, 0x2e8c, 0x1d42, 0x1d42, 0x1234, 0x1d42, 0x1234,
  29. 0x2762, 0x199a, 0x2762, 0x199a, 0x199a, 0x1062, 0x199a, 0x1062,
  30. 0x2762, 0x199a, 0x2762, 0x199a, 0x199a, 0x1062, 0x199a, 0x1062,
  31. 0x2492, 0x16c1, 0x2492, 0x16c1, 0x16c1, 0x0e3f, 0x16c1, 0x0e3f,
  32. 0x2492, 0x16c1, 0x2492, 0x16c1, 0x16c1, 0x0e3f, 0x16c1, 0x0e3f,
  33. 0x2000, 0x147b, 0x2000, 0x147b, 0x147b, 0x0d1b, 0x147b, 0x0d1b,
  34. 0x2000, 0x147b, 0x2000, 0x147b, 0x147b, 0x0d1b, 0x147b, 0x0d1b,
  35. 0x1c72, 0x11cf, 0x1c72, 0x11cf, 0x11cf, 0x0b4d, 0x11cf, 0x0b4d,
  36. 0x1c72, 0x11cf, 0x1c72, 0x11cf, 0x11cf, 0x0b4d, 0x11cf, 0x0b4d
  37. };
  38. static const u16 inverse_quantization_table[QUANTIZATION_TABLE_LEN] = {
  39. 0x800a, 0x800d, 0x800a, 0x800d, 0x800d, 0x8010, 0x800d, 0x8010,
  40. 0x800a, 0x800d, 0x800a, 0x800d, 0x800d, 0x8010, 0x800d, 0x8010,
  41. 0x800b, 0x800e, 0x800b, 0x800e, 0x800e, 0x8012, 0x800e, 0x8012,
  42. 0x800b, 0x800e, 0x800b, 0x800e, 0x800e, 0x8012, 0x800e, 0x8012,
  43. 0x800d, 0x8010, 0x800d, 0x8010, 0x8010, 0x8014, 0x8010, 0x8014,
  44. 0x800d, 0x8010, 0x800d, 0x8010, 0x8010, 0x8014, 0x8010, 0x8014,
  45. 0x800e, 0x8012, 0x800e, 0x8012, 0x8012, 0x8017, 0x8012, 0x8017,
  46. 0x800e, 0x8012, 0x800e, 0x8012, 0x8012, 0x8017, 0x8012, 0x8017,
  47. 0x8010, 0x8014, 0x8010, 0x8014, 0x8014, 0x8019, 0x8014, 0x8019,
  48. 0x8010, 0x8014, 0x8010, 0x8014, 0x8014, 0x8019, 0x8014, 0x8019,
  49. 0x8012, 0x8017, 0x8012, 0x8017, 0x8017, 0x801d, 0x8017, 0x801d,
  50. 0x8012, 0x8017, 0x8012, 0x8017, 0x8017, 0x801d, 0x8017, 0x801d
  51. };
  52. static const u16 encoder_vlc_lookup_table[VLC_LOOKUP_TABLE_LEN] = {
  53. 0x011, 0x000, 0x000, 0x000, 0x065, 0x021, 0x000, 0x000, 0x087, 0x064,
  54. 0x031, 0x000, 0x097, 0x086, 0x075, 0x053, 0x0a7, 0x096, 0x085, 0x063,
  55. 0x0b7, 0x0a6, 0x095, 0x074, 0x0df, 0x0b6, 0x0a5, 0x084, 0x0db, 0x0de,
  56. 0x0b5, 0x094, 0x0d8, 0x0da, 0x0dd, 0x0a4, 0x0ef, 0x0ee, 0x0d9, 0x0b4,
  57. 0x0eb, 0x0ea, 0x0ed, 0x0dc, 0x0ff, 0x0fe, 0x0e9, 0x0ec, 0x0fb, 0x0fa,
  58. 0x0fd, 0x0e8, 0x10f, 0x0f1, 0x0f9, 0x0fc, 0x10b, 0x10e, 0x10d, 0x0f8,
  59. 0x107, 0x10a, 0x109, 0x10c, 0x104, 0x106, 0x105, 0x108, 0x023, 0x000,
  60. 0x000, 0x000, 0x06b, 0x022, 0x000, 0x000, 0x067, 0x057, 0x033, 0x000,
  61. 0x077, 0x06a, 0x069, 0x045, 0x087, 0x066, 0x065, 0x044, 0x084, 0x076,
  62. 0x075, 0x056, 0x097, 0x086, 0x085, 0x068, 0x0bf, 0x096, 0x095, 0x064,
  63. 0x0bb, 0x0be, 0x0bd, 0x074, 0x0cf, 0x0ba, 0x0b9, 0x094, 0x0cb, 0x0ce,
  64. 0x0cd, 0x0bc, 0x0c8, 0x0ca, 0x0c9, 0x0b8, 0x0df, 0x0de, 0x0dd, 0x0cc,
  65. 0x0db, 0x0da, 0x0d9, 0x0dc, 0x0d7, 0x0eb, 0x0d6, 0x0d8, 0x0e9, 0x0e8,
  66. 0x0ea, 0x0d1, 0x0e7, 0x0e6, 0x0e5, 0x0e4, 0x04f, 0x000, 0x000, 0x000,
  67. 0x06f, 0x04e, 0x000, 0x000, 0x06b, 0x05f, 0x04d, 0x000, 0x068, 0x05c,
  68. 0x05e, 0x04c, 0x07f, 0x05a, 0x05b, 0x04b, 0x07b, 0x058, 0x059, 0x04a,
  69. 0x079, 0x06e, 0x06d, 0x049, 0x078, 0x06a, 0x069, 0x048, 0x08f, 0x07e,
  70. 0x07d, 0x05d, 0x08b, 0x08e, 0x07a, 0x06c, 0x09f, 0x08a, 0x08d, 0x07c,
  71. 0x09b, 0x09e, 0x089, 0x08c, 0x098, 0x09a, 0x09d, 0x088, 0x0ad, 0x097,
  72. 0x099, 0x09c, 0x0a9, 0x0ac, 0x0ab, 0x0aa, 0x0a5, 0x0a8, 0x0a7, 0x0a6,
  73. 0x0a1, 0x0a4, 0x0a3, 0x0a2, 0x021, 0x000, 0x000, 0x000, 0x067, 0x011,
  74. 0x000, 0x000, 0x064, 0x066, 0x031, 0x000, 0x063, 0x073, 0x072, 0x065,
  75. 0x062, 0x083, 0x082, 0x070, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  76. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  77. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  78. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  79. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  80. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  81. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  82. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  83. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  84. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  85. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  86. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  87. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  88. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  89. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  90. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  91. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  92. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  93. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  94. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  95. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  96. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  97. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  98. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  99. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  100. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  101. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  102. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  103. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  104. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  105. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x011, 0x010,
  106. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  107. 0x000, 0x000, 0x000, 0x000, 0x011, 0x021, 0x020, 0x000, 0x000, 0x000,
  108. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  109. 0x023, 0x022, 0x021, 0x020, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  110. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x023, 0x022, 0x021, 0x031,
  111. 0x030, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  112. 0x000, 0x000, 0x023, 0x022, 0x033, 0x032, 0x031, 0x030, 0x000, 0x000,
  113. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x023, 0x030,
  114. 0x031, 0x033, 0x032, 0x035, 0x034, 0x000, 0x000, 0x000, 0x000, 0x000,
  115. 0x000, 0x000, 0x000, 0x000, 0x037, 0x036, 0x035, 0x034, 0x033, 0x032,
  116. 0x031, 0x041, 0x051, 0x061, 0x071, 0x081, 0x091, 0x0a1, 0x0b1, 0x000,
  117. 0x002, 0x000, 0x0e4, 0x011, 0x0f4, 0x002, 0x024, 0x003, 0x005, 0x012,
  118. 0x034, 0x013, 0x065, 0x024, 0x013, 0x063, 0x015, 0x022, 0x075, 0x034,
  119. 0x044, 0x023, 0x023, 0x073, 0x054, 0x033, 0x033, 0x004, 0x043, 0x014,
  120. 0x011, 0x043, 0x014, 0x001, 0x025, 0x015, 0x035, 0x025, 0x064, 0x055,
  121. 0x045, 0x035, 0x074, 0x065, 0x085, 0x0d5, 0x012, 0x095, 0x055, 0x045,
  122. 0x095, 0x0e5, 0x084, 0x075, 0x022, 0x0a5, 0x094, 0x085, 0x032, 0x0b5,
  123. 0x003, 0x0c5, 0x001, 0x044, 0x0a5, 0x032, 0x0b5, 0x094, 0x0c5, 0x0a4,
  124. 0x0a4, 0x054, 0x0d5, 0x0b4, 0x0b4, 0x064, 0x0f5, 0x0f5, 0x053, 0x0d4,
  125. 0x0e5, 0x0c4, 0x105, 0x105, 0x0c4, 0x074, 0x063, 0x0e4, 0x0d4, 0x084,
  126. 0x073, 0x0f4, 0x004, 0x005, 0x000, 0x053, 0x000, 0x000, 0x000, 0x000,
  127. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  128. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  129. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  130. 0x000, 0x000, 0x011, 0x021, 0x031, 0x030, 0x011, 0x021, 0x020, 0x000,
  131. 0x011, 0x010, 0x000, 0x000, 0x011, 0x033, 0x032, 0x043, 0x042, 0x053,
  132. 0x052, 0x063, 0x062, 0x073, 0x072, 0x083, 0x082, 0x093, 0x092, 0x091,
  133. 0x037, 0x036, 0x035, 0x034, 0x033, 0x045, 0x044, 0x043, 0x042, 0x053,
  134. 0x052, 0x063, 0x062, 0x061, 0x060, 0x000, 0x045, 0x037, 0x036, 0x035,
  135. 0x044, 0x043, 0x034, 0x033, 0x042, 0x053, 0x052, 0x061, 0x051, 0x060,
  136. 0x000, 0x000, 0x053, 0x037, 0x045, 0x044, 0x036, 0x035, 0x034, 0x043,
  137. 0x033, 0x042, 0x052, 0x051, 0x050, 0x000, 0x000, 0x000, 0x045, 0x044,
  138. 0x043, 0x037, 0x036, 0x035, 0x034, 0x033, 0x042, 0x051, 0x041, 0x050,
  139. 0x000, 0x000, 0x000, 0x000, 0x061, 0x051, 0x037, 0x036, 0x035, 0x034,
  140. 0x033, 0x032, 0x041, 0x031, 0x060, 0x000, 0x000, 0x000, 0x000, 0x000,
  141. 0x061, 0x051, 0x035, 0x034, 0x033, 0x023, 0x032, 0x041, 0x031, 0x060,
  142. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x061, 0x041, 0x051, 0x033,
  143. 0x023, 0x022, 0x032, 0x031, 0x060, 0x000, 0x000, 0x000, 0x000, 0x000,
  144. 0x000, 0x000, 0x061, 0x060, 0x041, 0x023, 0x022, 0x031, 0x021, 0x051,
  145. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x051, 0x050,
  146. 0x031, 0x023, 0x022, 0x021, 0x041, 0x000, 0x000, 0x000, 0x000, 0x000,
  147. 0x000, 0x000, 0x000, 0x000, 0x040, 0x041, 0x031, 0x032, 0x011, 0x033,
  148. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  149. 0x040, 0x041, 0x021, 0x011, 0x031, 0x000, 0x000, 0x000, 0x000, 0x000,
  150. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x030, 0x031, 0x011, 0x021,
  151. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  152. 0x000, 0x000, 0x020, 0x021, 0x011, 0x000, 0x000, 0x000, 0x000, 0x000,
  153. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x010, 0x011,
  154. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  155. 0x000, 0x000, 0x000, 0x000
  156. };
  157. static const unsigned int lambda_lookup_table[] = {
  158. 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020,
  159. 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020,
  160. 0x0040, 0x0040, 0x0040, 0x0040, 0x0060, 0x0060, 0x0060, 0x0080,
  161. 0x0080, 0x0080, 0x00a0, 0x00c0, 0x00c0, 0x00e0, 0x0100, 0x0120,
  162. 0x0140, 0x0160, 0x01a0, 0x01c0, 0x0200, 0x0240, 0x0280, 0x02e0,
  163. 0x0320, 0x03a0, 0x0400, 0x0480, 0x0500, 0x05a0, 0x0660, 0x0720,
  164. 0x0800, 0x0900, 0x0a20, 0x0b60
  165. };
  166. static const unsigned int intra4x4_lambda3[] = {
  167. 1, 1, 1, 1, 1, 1, 1, 1,
  168. 1, 1, 1, 1, 1, 1, 1, 1,
  169. 2, 2, 2, 2, 3, 3, 3, 4,
  170. 4, 4, 5, 6, 6, 7, 8, 9,
  171. 10, 11, 13, 14, 16, 18, 20, 23,
  172. 25, 29, 32, 36, 40, 45, 51, 57,
  173. 64, 72, 81, 91
  174. };
  175. static v4l2_std_id tw5864_get_v4l2_std(enum tw5864_vid_std std);
  176. static enum tw5864_vid_std tw5864_from_v4l2_std(v4l2_std_id v4l2_std);
  177. static void tw5864_handle_frame_task(unsigned long data);
  178. static void tw5864_handle_frame(struct tw5864_h264_frame *frame);
  179. static void tw5864_frame_interval_set(struct tw5864_input *input);
  180. static int tw5864_queue_setup(struct vb2_queue *q, unsigned int *num_buffers,
  181. unsigned int *num_planes, unsigned int sizes[],
  182. struct device *alloc_ctxs[])
  183. {
  184. if (*num_planes)
  185. return sizes[0] < H264_VLC_BUF_SIZE ? -EINVAL : 0;
  186. sizes[0] = H264_VLC_BUF_SIZE;
  187. *num_planes = 1;
  188. return 0;
  189. }
  190. static void tw5864_buf_queue(struct vb2_buffer *vb)
  191. {
  192. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  193. struct vb2_queue *vq = vb->vb2_queue;
  194. struct tw5864_input *dev = vb2_get_drv_priv(vq);
  195. struct tw5864_buf *buf = container_of(vbuf, struct tw5864_buf, vb);
  196. unsigned long flags;
  197. spin_lock_irqsave(&dev->slock, flags);
  198. list_add_tail(&buf->list, &dev->active);
  199. spin_unlock_irqrestore(&dev->slock, flags);
  200. }
  201. static int tw5864_input_std_get(struct tw5864_input *input,
  202. enum tw5864_vid_std *std)
  203. {
  204. struct tw5864_dev *dev = input->root;
  205. u8 std_reg = tw_indir_readb(TW5864_INDIR_VIN_E(input->nr));
  206. *std = (std_reg & 0x70) >> 4;
  207. if (std_reg & 0x80) {
  208. dev_dbg(&dev->pci->dev,
  209. "Video format detection is in progress, please wait\n");
  210. return -EAGAIN;
  211. }
  212. return 0;
  213. }
  214. static int tw5864_enable_input(struct tw5864_input *input)
  215. {
  216. struct tw5864_dev *dev = input->root;
  217. int nr = input->nr;
  218. unsigned long flags;
  219. int d1_width = 720;
  220. int d1_height;
  221. int frame_width_bus_value = 0;
  222. int frame_height_bus_value = 0;
  223. int reg_frame_bus = 0x1c;
  224. int fmt_reg_value = 0;
  225. int downscale_enabled = 0;
  226. dev_dbg(&dev->pci->dev, "Enabling channel %d\n", nr);
  227. input->frame_seqno = 0;
  228. input->frame_gop_seqno = 0;
  229. input->h264_idr_pic_id = 0;
  230. input->reg_dsp_qp = input->qp;
  231. input->reg_dsp_ref_mvp_lambda = lambda_lookup_table[input->qp];
  232. input->reg_dsp_i4x4_weight = intra4x4_lambda3[input->qp];
  233. input->reg_emu = TW5864_EMU_EN_LPF | TW5864_EMU_EN_BHOST
  234. | TW5864_EMU_EN_SEN | TW5864_EMU_EN_ME | TW5864_EMU_EN_DDR;
  235. input->reg_dsp = nr /* channel id */
  236. | TW5864_DSP_CHROM_SW
  237. | ((0xa << 8) & TW5864_DSP_MB_DELAY)
  238. ;
  239. input->resolution = D1;
  240. d1_height = (input->std == STD_NTSC) ? 480 : 576;
  241. input->width = d1_width;
  242. input->height = d1_height;
  243. input->reg_interlacing = 0x4;
  244. switch (input->resolution) {
  245. case D1:
  246. frame_width_bus_value = 0x2cf;
  247. frame_height_bus_value = input->height - 1;
  248. reg_frame_bus = 0x1c;
  249. fmt_reg_value = 0;
  250. downscale_enabled = 0;
  251. input->reg_dsp_codec |= TW5864_CIF_MAP_MD | TW5864_HD1_MAP_MD;
  252. input->reg_emu |= TW5864_DSP_FRAME_TYPE_D1;
  253. input->reg_interlacing = TW5864_DI_EN | TW5864_DSP_INTER_ST;
  254. tw_setl(TW5864_FULL_HALF_FLAG, 1 << nr);
  255. break;
  256. case HD1:
  257. input->height /= 2;
  258. input->width /= 2;
  259. frame_width_bus_value = 0x2cf;
  260. frame_height_bus_value = input->height * 2 - 1;
  261. reg_frame_bus = 0x1c;
  262. fmt_reg_value = 0;
  263. downscale_enabled = 0;
  264. input->reg_dsp_codec |= TW5864_HD1_MAP_MD;
  265. input->reg_emu |= TW5864_DSP_FRAME_TYPE_D1;
  266. tw_clearl(TW5864_FULL_HALF_FLAG, 1 << nr);
  267. break;
  268. case CIF:
  269. input->height /= 4;
  270. input->width /= 2;
  271. frame_width_bus_value = 0x15f;
  272. frame_height_bus_value = input->height * 2 - 1;
  273. reg_frame_bus = 0x07;
  274. fmt_reg_value = 1;
  275. downscale_enabled = 1;
  276. input->reg_dsp_codec |= TW5864_CIF_MAP_MD;
  277. tw_clearl(TW5864_FULL_HALF_FLAG, 1 << nr);
  278. break;
  279. case QCIF:
  280. input->height /= 4;
  281. input->width /= 4;
  282. frame_width_bus_value = 0x15f;
  283. frame_height_bus_value = input->height * 2 - 1;
  284. reg_frame_bus = 0x07;
  285. fmt_reg_value = 1;
  286. downscale_enabled = 1;
  287. input->reg_dsp_codec |= TW5864_CIF_MAP_MD;
  288. tw_clearl(TW5864_FULL_HALF_FLAG, 1 << nr);
  289. break;
  290. }
  291. /* analog input width / 4 */
  292. tw_indir_writeb(TW5864_INDIR_IN_PIC_WIDTH(nr), d1_width / 4);
  293. tw_indir_writeb(TW5864_INDIR_IN_PIC_HEIGHT(nr), d1_height / 4);
  294. /* output width / 4 */
  295. tw_indir_writeb(TW5864_INDIR_OUT_PIC_WIDTH(nr), input->width / 4);
  296. tw_indir_writeb(TW5864_INDIR_OUT_PIC_HEIGHT(nr), input->height / 4);
  297. /*
  298. * Crop width from 720 to 704.
  299. * Above register settings need value 720 involved.
  300. */
  301. input->width = 704;
  302. tw_indir_writeb(TW5864_INDIR_CROP_ETC,
  303. tw_indir_readb(TW5864_INDIR_CROP_ETC) |
  304. TW5864_INDIR_CROP_ETC_CROP_EN);
  305. tw_writel(TW5864_DSP_PIC_MAX_MB,
  306. ((input->width / 16) << 8) | (input->height / 16));
  307. tw_writel(TW5864_FRAME_WIDTH_BUS_A(nr),
  308. frame_width_bus_value);
  309. tw_writel(TW5864_FRAME_WIDTH_BUS_B(nr),
  310. frame_width_bus_value);
  311. tw_writel(TW5864_FRAME_HEIGHT_BUS_A(nr),
  312. frame_height_bus_value);
  313. tw_writel(TW5864_FRAME_HEIGHT_BUS_B(nr),
  314. (frame_height_bus_value + 1) / 2 - 1);
  315. tw5864_frame_interval_set(input);
  316. if (downscale_enabled)
  317. tw_setl(TW5864_H264EN_CH_DNS, 1 << nr);
  318. tw_mask_shift_writel(TW5864_H264EN_CH_FMT_REG1, 0x3, 2 * nr,
  319. fmt_reg_value);
  320. tw_mask_shift_writel((nr < 2
  321. ? TW5864_H264EN_RATE_MAX_LINE_REG1
  322. : TW5864_H264EN_RATE_MAX_LINE_REG2),
  323. 0x1f, 5 * (nr % 2),
  324. input->std == STD_NTSC ? 29 : 24);
  325. tw_mask_shift_writel((nr < 2) ? TW5864_FRAME_BUS1 :
  326. TW5864_FRAME_BUS2, 0xff, (nr % 2) * 8,
  327. reg_frame_bus);
  328. spin_lock_irqsave(&dev->slock, flags);
  329. input->enabled = 1;
  330. spin_unlock_irqrestore(&dev->slock, flags);
  331. return 0;
  332. }
  333. void tw5864_request_encoded_frame(struct tw5864_input *input)
  334. {
  335. struct tw5864_dev *dev = input->root;
  336. u32 enc_buf_id_new;
  337. tw_setl(TW5864_DSP_CODEC, TW5864_CIF_MAP_MD | TW5864_HD1_MAP_MD);
  338. tw_writel(TW5864_EMU, input->reg_emu);
  339. tw_writel(TW5864_INTERLACING, input->reg_interlacing);
  340. tw_writel(TW5864_DSP, input->reg_dsp);
  341. tw_writel(TW5864_DSP_QP, input->reg_dsp_qp);
  342. tw_writel(TW5864_DSP_REF_MVP_LAMBDA, input->reg_dsp_ref_mvp_lambda);
  343. tw_writel(TW5864_DSP_I4x4_WEIGHT, input->reg_dsp_i4x4_weight);
  344. tw_mask_shift_writel(TW5864_DSP_INTRA_MODE, TW5864_DSP_INTRA_MODE_MASK,
  345. TW5864_DSP_INTRA_MODE_SHIFT,
  346. TW5864_DSP_INTRA_MODE_16x16);
  347. if (input->frame_gop_seqno == 0) {
  348. /* Produce I-frame */
  349. tw_writel(TW5864_MOTION_SEARCH_ETC, TW5864_INTRA_EN);
  350. input->h264_idr_pic_id++;
  351. input->h264_idr_pic_id &= TW5864_DSP_REF_FRM;
  352. } else {
  353. /* Produce P-frame */
  354. tw_writel(TW5864_MOTION_SEARCH_ETC, TW5864_INTRA_EN |
  355. TW5864_ME_EN | BIT(5) /* SRCH_OPT default */);
  356. }
  357. tw5864_prepare_frame_headers(input);
  358. tw_writel(TW5864_VLC,
  359. TW5864_VLC_PCI_SEL |
  360. ((input->tail_nb_bits + 24) << TW5864_VLC_BIT_ALIGN_SHIFT) |
  361. input->reg_dsp_qp);
  362. enc_buf_id_new = tw_mask_shift_readl(TW5864_ENC_BUF_PTR_REC1, 0x3,
  363. 2 * input->nr);
  364. tw_writel(TW5864_DSP_ENC_ORG_PTR_REG,
  365. enc_buf_id_new << TW5864_DSP_ENC_ORG_PTR_SHIFT);
  366. tw_writel(TW5864_DSP_ENC_REC,
  367. enc_buf_id_new << 12 | ((enc_buf_id_new + 3) & 3));
  368. tw_writel(TW5864_SLICE, TW5864_START_NSLICE);
  369. tw_writel(TW5864_SLICE, 0);
  370. }
  371. static int tw5864_disable_input(struct tw5864_input *input)
  372. {
  373. struct tw5864_dev *dev = input->root;
  374. unsigned long flags;
  375. dev_dbg(&dev->pci->dev, "Disabling channel %d\n", input->nr);
  376. spin_lock_irqsave(&dev->slock, flags);
  377. input->enabled = 0;
  378. spin_unlock_irqrestore(&dev->slock, flags);
  379. return 0;
  380. }
  381. static int tw5864_start_streaming(struct vb2_queue *q, unsigned int count)
  382. {
  383. struct tw5864_input *input = vb2_get_drv_priv(q);
  384. int ret;
  385. ret = tw5864_enable_input(input);
  386. if (!ret)
  387. return 0;
  388. while (!list_empty(&input->active)) {
  389. struct tw5864_buf *buf = list_entry(input->active.next,
  390. struct tw5864_buf, list);
  391. list_del(&buf->list);
  392. vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
  393. }
  394. return ret;
  395. }
  396. static void tw5864_stop_streaming(struct vb2_queue *q)
  397. {
  398. unsigned long flags;
  399. struct tw5864_input *input = vb2_get_drv_priv(q);
  400. tw5864_disable_input(input);
  401. spin_lock_irqsave(&input->slock, flags);
  402. if (input->vb) {
  403. vb2_buffer_done(&input->vb->vb.vb2_buf, VB2_BUF_STATE_ERROR);
  404. input->vb = NULL;
  405. }
  406. while (!list_empty(&input->active)) {
  407. struct tw5864_buf *buf = list_entry(input->active.next,
  408. struct tw5864_buf, list);
  409. list_del(&buf->list);
  410. vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
  411. }
  412. spin_unlock_irqrestore(&input->slock, flags);
  413. }
  414. static const struct vb2_ops tw5864_video_qops = {
  415. .queue_setup = tw5864_queue_setup,
  416. .buf_queue = tw5864_buf_queue,
  417. .start_streaming = tw5864_start_streaming,
  418. .stop_streaming = tw5864_stop_streaming,
  419. .wait_prepare = vb2_ops_wait_prepare,
  420. .wait_finish = vb2_ops_wait_finish,
  421. };
  422. static int tw5864_s_ctrl(struct v4l2_ctrl *ctrl)
  423. {
  424. struct tw5864_input *input =
  425. container_of(ctrl->handler, struct tw5864_input, hdl);
  426. struct tw5864_dev *dev = input->root;
  427. unsigned long flags;
  428. switch (ctrl->id) {
  429. case V4L2_CID_BRIGHTNESS:
  430. tw_indir_writeb(TW5864_INDIR_VIN_A_BRIGHT(input->nr),
  431. (u8)ctrl->val);
  432. break;
  433. case V4L2_CID_HUE:
  434. tw_indir_writeb(TW5864_INDIR_VIN_7_HUE(input->nr),
  435. (u8)ctrl->val);
  436. break;
  437. case V4L2_CID_CONTRAST:
  438. tw_indir_writeb(TW5864_INDIR_VIN_9_CNTRST(input->nr),
  439. (u8)ctrl->val);
  440. break;
  441. case V4L2_CID_SATURATION:
  442. tw_indir_writeb(TW5864_INDIR_VIN_B_SAT_U(input->nr),
  443. (u8)ctrl->val);
  444. tw_indir_writeb(TW5864_INDIR_VIN_C_SAT_V(input->nr),
  445. (u8)ctrl->val);
  446. break;
  447. case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
  448. input->gop = ctrl->val;
  449. return 0;
  450. case V4L2_CID_MPEG_VIDEO_H264_MIN_QP:
  451. spin_lock_irqsave(&input->slock, flags);
  452. input->qp = ctrl->val;
  453. input->reg_dsp_qp = input->qp;
  454. input->reg_dsp_ref_mvp_lambda = lambda_lookup_table[input->qp];
  455. input->reg_dsp_i4x4_weight = intra4x4_lambda3[input->qp];
  456. spin_unlock_irqrestore(&input->slock, flags);
  457. return 0;
  458. case V4L2_CID_DETECT_MD_GLOBAL_THRESHOLD:
  459. memset(input->md_threshold_grid_values, ctrl->val,
  460. sizeof(input->md_threshold_grid_values));
  461. return 0;
  462. case V4L2_CID_DETECT_MD_MODE:
  463. return 0;
  464. case V4L2_CID_DETECT_MD_THRESHOLD_GRID:
  465. /* input->md_threshold_grid_ctrl->p_new.p_u16 contains data */
  466. memcpy(input->md_threshold_grid_values,
  467. input->md_threshold_grid_ctrl->p_new.p_u16,
  468. sizeof(input->md_threshold_grid_values));
  469. return 0;
  470. }
  471. return 0;
  472. }
  473. static int tw5864_fmt_vid_cap(struct file *file, void *priv,
  474. struct v4l2_format *f)
  475. {
  476. struct tw5864_input *input = video_drvdata(file);
  477. f->fmt.pix.width = 704;
  478. switch (input->std) {
  479. default:
  480. WARN_ON_ONCE(1);
  481. case STD_NTSC:
  482. f->fmt.pix.height = 480;
  483. break;
  484. case STD_PAL:
  485. case STD_SECAM:
  486. f->fmt.pix.height = 576;
  487. break;
  488. }
  489. f->fmt.pix.field = V4L2_FIELD_INTERLACED;
  490. f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
  491. f->fmt.pix.sizeimage = H264_VLC_BUF_SIZE;
  492. f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
  493. return 0;
  494. }
  495. static int tw5864_enum_input(struct file *file, void *priv,
  496. struct v4l2_input *i)
  497. {
  498. struct tw5864_input *input = video_drvdata(file);
  499. struct tw5864_dev *dev = input->root;
  500. u8 indir_0x000 = tw_indir_readb(TW5864_INDIR_VIN_0(input->nr));
  501. u8 indir_0x00d = tw_indir_readb(TW5864_INDIR_VIN_D(input->nr));
  502. u8 v1 = indir_0x000;
  503. u8 v2 = indir_0x00d;
  504. if (i->index)
  505. return -EINVAL;
  506. i->type = V4L2_INPUT_TYPE_CAMERA;
  507. snprintf(i->name, sizeof(i->name), "Encoder %d", input->nr);
  508. i->std = TW5864_NORMS;
  509. if (v1 & (1 << 7))
  510. i->status |= V4L2_IN_ST_NO_SYNC;
  511. if (!(v1 & (1 << 6)))
  512. i->status |= V4L2_IN_ST_NO_H_LOCK;
  513. if (v1 & (1 << 2))
  514. i->status |= V4L2_IN_ST_NO_SIGNAL;
  515. if (v1 & (1 << 1))
  516. i->status |= V4L2_IN_ST_NO_COLOR;
  517. if (v2 & (1 << 2))
  518. i->status |= V4L2_IN_ST_MACROVISION;
  519. return 0;
  520. }
  521. static int tw5864_g_input(struct file *file, void *priv, unsigned int *i)
  522. {
  523. *i = 0;
  524. return 0;
  525. }
  526. static int tw5864_s_input(struct file *file, void *priv, unsigned int i)
  527. {
  528. if (i)
  529. return -EINVAL;
  530. return 0;
  531. }
  532. static int tw5864_querycap(struct file *file, void *priv,
  533. struct v4l2_capability *cap)
  534. {
  535. struct tw5864_input *input = video_drvdata(file);
  536. strcpy(cap->driver, "tw5864");
  537. snprintf(cap->card, sizeof(cap->card), "TW5864 Encoder %d",
  538. input->nr);
  539. sprintf(cap->bus_info, "PCI:%s", pci_name(input->root->pci));
  540. return 0;
  541. }
  542. static int tw5864_querystd(struct file *file, void *priv, v4l2_std_id *std)
  543. {
  544. struct tw5864_input *input = video_drvdata(file);
  545. enum tw5864_vid_std tw_std;
  546. int ret;
  547. ret = tw5864_input_std_get(input, &tw_std);
  548. if (ret)
  549. return ret;
  550. *std = tw5864_get_v4l2_std(tw_std);
  551. return 0;
  552. }
  553. static int tw5864_g_std(struct file *file, void *priv, v4l2_std_id *std)
  554. {
  555. struct tw5864_input *input = video_drvdata(file);
  556. *std = input->v4l2_std;
  557. return 0;
  558. }
  559. static int tw5864_s_std(struct file *file, void *priv, v4l2_std_id std)
  560. {
  561. struct tw5864_input *input = video_drvdata(file);
  562. struct tw5864_dev *dev = input->root;
  563. input->v4l2_std = std;
  564. input->std = tw5864_from_v4l2_std(std);
  565. tw_indir_writeb(TW5864_INDIR_VIN_E(input->nr), input->std);
  566. return 0;
  567. }
  568. static int tw5864_enum_fmt_vid_cap(struct file *file, void *priv,
  569. struct v4l2_fmtdesc *f)
  570. {
  571. if (f->index)
  572. return -EINVAL;
  573. f->pixelformat = V4L2_PIX_FMT_H264;
  574. return 0;
  575. }
  576. static int tw5864_subscribe_event(struct v4l2_fh *fh,
  577. const struct v4l2_event_subscription *sub)
  578. {
  579. switch (sub->type) {
  580. case V4L2_EVENT_CTRL:
  581. return v4l2_ctrl_subscribe_event(fh, sub);
  582. case V4L2_EVENT_MOTION_DET:
  583. /*
  584. * Allow for up to 30 events (1 second for NTSC) to be stored.
  585. */
  586. return v4l2_event_subscribe(fh, sub, 30, NULL);
  587. }
  588. return -EINVAL;
  589. }
  590. static void tw5864_frame_interval_set(struct tw5864_input *input)
  591. {
  592. /*
  593. * This register value seems to follow such approach: In each second
  594. * interval, when processing Nth frame, it checks Nth bit of register
  595. * value and, if the bit is 1, it processes the frame, otherwise the
  596. * frame is discarded.
  597. * So unary representation would work, but more or less equal gaps
  598. * between the frames should be preserved.
  599. *
  600. * For 1 FPS - 0x00000001
  601. * 00000000 00000000 00000000 00000001
  602. *
  603. * For max FPS - set all 25/30 lower bits:
  604. * 00111111 11111111 11111111 11111111 (NTSC)
  605. * 00000001 11111111 11111111 11111111 (PAL)
  606. *
  607. * For half of max FPS - use such pattern:
  608. * 00010101 01010101 01010101 01010101 (NTSC)
  609. * 00000001 01010101 01010101 01010101 (PAL)
  610. *
  611. * Et cetera.
  612. *
  613. * The value supplied to hardware is capped by mask of 25/30 lower bits.
  614. */
  615. struct tw5864_dev *dev = input->root;
  616. u32 unary_framerate = 0;
  617. int shift = 0;
  618. int std_max_fps = input->std == STD_NTSC ? 30 : 25;
  619. for (shift = 0; shift < std_max_fps; shift += input->frame_interval)
  620. unary_framerate |= 0x00000001 << shift;
  621. tw_writel(TW5864_H264EN_RATE_CNTL_LO_WORD(input->nr, 0),
  622. unary_framerate >> 16);
  623. tw_writel(TW5864_H264EN_RATE_CNTL_HI_WORD(input->nr, 0),
  624. unary_framerate & 0xffff);
  625. }
  626. static int tw5864_frameinterval_get(struct tw5864_input *input,
  627. struct v4l2_fract *frameinterval)
  628. {
  629. switch (input->std) {
  630. case STD_NTSC:
  631. frameinterval->numerator = 1001;
  632. frameinterval->denominator = 30000;
  633. break;
  634. case STD_PAL:
  635. case STD_SECAM:
  636. frameinterval->numerator = 1;
  637. frameinterval->denominator = 25;
  638. break;
  639. default:
  640. WARN(1, "tw5864_frameinterval_get requested for unknown std %d\n",
  641. input->std);
  642. return -EINVAL;
  643. }
  644. return 0;
  645. }
  646. static int tw5864_enum_framesizes(struct file *file, void *priv,
  647. struct v4l2_frmsizeenum *fsize)
  648. {
  649. struct tw5864_input *input = video_drvdata(file);
  650. if (fsize->index > 0)
  651. return -EINVAL;
  652. if (fsize->pixel_format != V4L2_PIX_FMT_H264)
  653. return -EINVAL;
  654. fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
  655. fsize->discrete.width = 704;
  656. fsize->discrete.height = input->std == STD_NTSC ? 480 : 576;
  657. return 0;
  658. }
  659. static int tw5864_enum_frameintervals(struct file *file, void *priv,
  660. struct v4l2_frmivalenum *fintv)
  661. {
  662. struct tw5864_input *input = video_drvdata(file);
  663. struct v4l2_fract frameinterval;
  664. int std_max_fps = input->std == STD_NTSC ? 30 : 25;
  665. struct v4l2_frmsizeenum fsize = { .index = fintv->index,
  666. .pixel_format = fintv->pixel_format };
  667. int ret;
  668. ret = tw5864_enum_framesizes(file, priv, &fsize);
  669. if (ret)
  670. return ret;
  671. if (fintv->width != fsize.discrete.width ||
  672. fintv->height != fsize.discrete.height)
  673. return -EINVAL;
  674. fintv->type = V4L2_FRMIVAL_TYPE_STEPWISE;
  675. ret = tw5864_frameinterval_get(input, &frameinterval);
  676. fintv->stepwise.step = frameinterval;
  677. fintv->stepwise.min = frameinterval;
  678. fintv->stepwise.max = frameinterval;
  679. fintv->stepwise.max.numerator *= std_max_fps;
  680. return ret;
  681. }
  682. static int tw5864_g_parm(struct file *file, void *priv,
  683. struct v4l2_streamparm *sp)
  684. {
  685. struct tw5864_input *input = video_drvdata(file);
  686. struct v4l2_captureparm *cp = &sp->parm.capture;
  687. int ret;
  688. cp->capability = V4L2_CAP_TIMEPERFRAME;
  689. ret = tw5864_frameinterval_get(input, &cp->timeperframe);
  690. cp->timeperframe.numerator *= input->frame_interval;
  691. cp->capturemode = 0;
  692. cp->readbuffers = 2;
  693. return ret;
  694. }
  695. static int tw5864_s_parm(struct file *file, void *priv,
  696. struct v4l2_streamparm *sp)
  697. {
  698. struct tw5864_input *input = video_drvdata(file);
  699. struct v4l2_fract *t = &sp->parm.capture.timeperframe;
  700. struct v4l2_fract time_base;
  701. int ret;
  702. ret = tw5864_frameinterval_get(input, &time_base);
  703. if (ret)
  704. return ret;
  705. if (!t->numerator || !t->denominator) {
  706. t->numerator = time_base.numerator * input->frame_interval;
  707. t->denominator = time_base.denominator;
  708. } else if (t->denominator != time_base.denominator) {
  709. t->numerator = t->numerator * time_base.denominator /
  710. t->denominator;
  711. t->denominator = time_base.denominator;
  712. }
  713. input->frame_interval = t->numerator / time_base.numerator;
  714. if (input->frame_interval < 1)
  715. input->frame_interval = 1;
  716. tw5864_frame_interval_set(input);
  717. return tw5864_g_parm(file, priv, sp);
  718. }
  719. static const struct v4l2_ctrl_ops tw5864_ctrl_ops = {
  720. .s_ctrl = tw5864_s_ctrl,
  721. };
  722. static const struct v4l2_file_operations video_fops = {
  723. .owner = THIS_MODULE,
  724. .open = v4l2_fh_open,
  725. .release = vb2_fop_release,
  726. .read = vb2_fop_read,
  727. .poll = vb2_fop_poll,
  728. .mmap = vb2_fop_mmap,
  729. .unlocked_ioctl = video_ioctl2,
  730. };
  731. #ifdef CONFIG_VIDEO_ADV_DEBUG
  732. #define INDIR_SPACE_MAP_SHIFT 0x100000
  733. static int tw5864_g_reg(struct file *file, void *fh,
  734. struct v4l2_dbg_register *reg)
  735. {
  736. struct tw5864_input *input = video_drvdata(file);
  737. struct tw5864_dev *dev = input->root;
  738. if (reg->reg < INDIR_SPACE_MAP_SHIFT) {
  739. if (reg->reg > 0x87fff)
  740. return -EINVAL;
  741. reg->size = 4;
  742. reg->val = tw_readl(reg->reg);
  743. } else {
  744. __u64 indir_addr = reg->reg - INDIR_SPACE_MAP_SHIFT;
  745. if (indir_addr > 0xefe)
  746. return -EINVAL;
  747. reg->size = 1;
  748. reg->val = tw_indir_readb(reg->reg);
  749. }
  750. return 0;
  751. }
  752. static int tw5864_s_reg(struct file *file, void *fh,
  753. const struct v4l2_dbg_register *reg)
  754. {
  755. struct tw5864_input *input = video_drvdata(file);
  756. struct tw5864_dev *dev = input->root;
  757. if (reg->reg < INDIR_SPACE_MAP_SHIFT) {
  758. if (reg->reg > 0x87fff)
  759. return -EINVAL;
  760. tw_writel(reg->reg, reg->val);
  761. } else {
  762. __u64 indir_addr = reg->reg - INDIR_SPACE_MAP_SHIFT;
  763. if (indir_addr > 0xefe)
  764. return -EINVAL;
  765. tw_indir_writeb(reg->reg, reg->val);
  766. }
  767. return 0;
  768. }
  769. #endif
  770. static const struct v4l2_ioctl_ops video_ioctl_ops = {
  771. .vidioc_querycap = tw5864_querycap,
  772. .vidioc_enum_fmt_vid_cap = tw5864_enum_fmt_vid_cap,
  773. .vidioc_reqbufs = vb2_ioctl_reqbufs,
  774. .vidioc_create_bufs = vb2_ioctl_create_bufs,
  775. .vidioc_querybuf = vb2_ioctl_querybuf,
  776. .vidioc_qbuf = vb2_ioctl_qbuf,
  777. .vidioc_dqbuf = vb2_ioctl_dqbuf,
  778. .vidioc_expbuf = vb2_ioctl_expbuf,
  779. .vidioc_querystd = tw5864_querystd,
  780. .vidioc_s_std = tw5864_s_std,
  781. .vidioc_g_std = tw5864_g_std,
  782. .vidioc_enum_input = tw5864_enum_input,
  783. .vidioc_g_input = tw5864_g_input,
  784. .vidioc_s_input = tw5864_s_input,
  785. .vidioc_streamon = vb2_ioctl_streamon,
  786. .vidioc_streamoff = vb2_ioctl_streamoff,
  787. .vidioc_try_fmt_vid_cap = tw5864_fmt_vid_cap,
  788. .vidioc_s_fmt_vid_cap = tw5864_fmt_vid_cap,
  789. .vidioc_g_fmt_vid_cap = tw5864_fmt_vid_cap,
  790. .vidioc_log_status = v4l2_ctrl_log_status,
  791. .vidioc_subscribe_event = tw5864_subscribe_event,
  792. .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
  793. .vidioc_enum_framesizes = tw5864_enum_framesizes,
  794. .vidioc_enum_frameintervals = tw5864_enum_frameintervals,
  795. .vidioc_s_parm = tw5864_s_parm,
  796. .vidioc_g_parm = tw5864_g_parm,
  797. #ifdef CONFIG_VIDEO_ADV_DEBUG
  798. .vidioc_g_register = tw5864_g_reg,
  799. .vidioc_s_register = tw5864_s_reg,
  800. #endif
  801. };
  802. static const struct video_device tw5864_video_template = {
  803. .name = "tw5864_video",
  804. .fops = &video_fops,
  805. .ioctl_ops = &video_ioctl_ops,
  806. .release = video_device_release_empty,
  807. .tvnorms = TW5864_NORMS,
  808. .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE |
  809. V4L2_CAP_STREAMING,
  810. };
  811. /* Motion Detection Threshold matrix */
  812. static const struct v4l2_ctrl_config tw5864_md_thresholds = {
  813. .ops = &tw5864_ctrl_ops,
  814. .id = V4L2_CID_DETECT_MD_THRESHOLD_GRID,
  815. .dims = {MD_CELLS_HOR, MD_CELLS_VERT},
  816. .def = 14,
  817. /* See tw5864_md_metric_from_mvd() */
  818. .max = 2 * 0x0f,
  819. .step = 1,
  820. };
  821. static int tw5864_video_input_init(struct tw5864_input *dev, int video_nr);
  822. static void tw5864_video_input_fini(struct tw5864_input *dev);
  823. static void tw5864_encoder_tables_upload(struct tw5864_dev *dev);
  824. int tw5864_video_init(struct tw5864_dev *dev, int *video_nr)
  825. {
  826. int i;
  827. int ret;
  828. unsigned long flags;
  829. int last_dma_allocated = -1;
  830. int last_input_nr_registered = -1;
  831. for (i = 0; i < H264_BUF_CNT; i++) {
  832. struct tw5864_h264_frame *frame = &dev->h264_buf[i];
  833. frame->vlc.addr = dma_alloc_coherent(&dev->pci->dev,
  834. H264_VLC_BUF_SIZE,
  835. &frame->vlc.dma_addr,
  836. GFP_KERNEL | GFP_DMA32);
  837. if (!frame->vlc.addr) {
  838. dev_err(&dev->pci->dev, "dma alloc fail\n");
  839. ret = -ENOMEM;
  840. goto free_dma;
  841. }
  842. frame->mv.addr = dma_alloc_coherent(&dev->pci->dev,
  843. H264_MV_BUF_SIZE,
  844. &frame->mv.dma_addr,
  845. GFP_KERNEL | GFP_DMA32);
  846. if (!frame->mv.addr) {
  847. dev_err(&dev->pci->dev, "dma alloc fail\n");
  848. ret = -ENOMEM;
  849. dma_free_coherent(&dev->pci->dev, H264_VLC_BUF_SIZE,
  850. frame->vlc.addr, frame->vlc.dma_addr);
  851. goto free_dma;
  852. }
  853. last_dma_allocated = i;
  854. }
  855. tw5864_encoder_tables_upload(dev);
  856. /* Picture is distorted without this block */
  857. /* use falling edge to sample 54M to 108M */
  858. tw_indir_writeb(TW5864_INDIR_VD_108_POL, TW5864_INDIR_VD_108_POL_BOTH);
  859. tw_indir_writeb(TW5864_INDIR_CLK0_SEL, 0x00);
  860. tw_indir_writeb(TW5864_INDIR_DDRA_DLL_DQS_SEL0, 0x02);
  861. tw_indir_writeb(TW5864_INDIR_DDRA_DLL_DQS_SEL1, 0x02);
  862. tw_indir_writeb(TW5864_INDIR_DDRA_DLL_CLK90_SEL, 0x02);
  863. tw_indir_writeb(TW5864_INDIR_DDRB_DLL_DQS_SEL0, 0x02);
  864. tw_indir_writeb(TW5864_INDIR_DDRB_DLL_DQS_SEL1, 0x02);
  865. tw_indir_writeb(TW5864_INDIR_DDRB_DLL_CLK90_SEL, 0x02);
  866. /* video input reset */
  867. tw_indir_writeb(TW5864_INDIR_RESET, 0);
  868. tw_indir_writeb(TW5864_INDIR_RESET, TW5864_INDIR_RESET_VD |
  869. TW5864_INDIR_RESET_DLL | TW5864_INDIR_RESET_MUX_CORE);
  870. msleep(20);
  871. /*
  872. * Select Part A mode for all channels.
  873. * tw_setl instead of tw_clearl for Part B mode.
  874. *
  875. * I guess "Part B" is primarily for downscaled version of same channel
  876. * which goes in Part A of same bus
  877. */
  878. tw_writel(TW5864_FULL_HALF_MODE_SEL, 0);
  879. tw_indir_writeb(TW5864_INDIR_PV_VD_CK_POL,
  880. TW5864_INDIR_PV_VD_CK_POL_VD(0) |
  881. TW5864_INDIR_PV_VD_CK_POL_VD(1) |
  882. TW5864_INDIR_PV_VD_CK_POL_VD(2) |
  883. TW5864_INDIR_PV_VD_CK_POL_VD(3));
  884. spin_lock_irqsave(&dev->slock, flags);
  885. dev->encoder_busy = 0;
  886. dev->h264_buf_r_index = 0;
  887. dev->h264_buf_w_index = 0;
  888. tw_writel(TW5864_VLC_STREAM_BASE_ADDR,
  889. dev->h264_buf[dev->h264_buf_w_index].vlc.dma_addr);
  890. tw_writel(TW5864_MV_STREAM_BASE_ADDR,
  891. dev->h264_buf[dev->h264_buf_w_index].mv.dma_addr);
  892. spin_unlock_irqrestore(&dev->slock, flags);
  893. tw_writel(TW5864_SEN_EN_CH, 0x000f);
  894. tw_writel(TW5864_H264EN_CH_EN, 0x000f);
  895. tw_writel(TW5864_H264EN_BUS0_MAP, 0x00000000);
  896. tw_writel(TW5864_H264EN_BUS1_MAP, 0x00001111);
  897. tw_writel(TW5864_H264EN_BUS2_MAP, 0x00002222);
  898. tw_writel(TW5864_H264EN_BUS3_MAP, 0x00003333);
  899. /*
  900. * Quote from Intersil (manufacturer):
  901. * 0x0038 is managed by HW, and by default it won't pass the pointer set
  902. * at 0x0010. So if you don't do encoding, 0x0038 should stay at '3'
  903. * (with 4 frames in buffer). If you encode one frame and then move
  904. * 0x0010 to '1' for example, HW will take one more frame and set it to
  905. * buffer #0, and then you should see 0x0038 is set to '0'. There is
  906. * only one HW encoder engine, so 4 channels cannot get encoded
  907. * simultaneously. But each channel does have its own buffer (for
  908. * original frames and reconstructed frames). So there is no problem to
  909. * manage encoding for 4 channels at same time and no need to force
  910. * I-frames in switching channels.
  911. * End of quote.
  912. *
  913. * If we set 0x0010 (TW5864_ENC_BUF_PTR_REC1) to 0 (for any channel), we
  914. * have no "rolling" (until we change this value).
  915. * If we set 0x0010 (TW5864_ENC_BUF_PTR_REC1) to 0x3, it starts to roll
  916. * continuously together with 0x0038.
  917. */
  918. tw_writel(TW5864_ENC_BUF_PTR_REC1, 0x00ff);
  919. tw_writel(TW5864_PCI_INTTM_SCALE, 0);
  920. tw_writel(TW5864_INTERLACING, TW5864_DI_EN);
  921. tw_writel(TW5864_MASTER_ENB_REG, TW5864_PCI_VLC_INTR_ENB);
  922. tw_writel(TW5864_PCI_INTR_CTL,
  923. TW5864_TIMER_INTR_ENB | TW5864_PCI_MAST_ENB |
  924. TW5864_MVD_VLC_MAST_ENB);
  925. dev->irqmask |= TW5864_INTR_VLC_DONE | TW5864_INTR_TIMER;
  926. tw5864_irqmask_apply(dev);
  927. tasklet_init(&dev->tasklet, tw5864_handle_frame_task,
  928. (unsigned long)dev);
  929. for (i = 0; i < TW5864_INPUTS; i++) {
  930. dev->inputs[i].root = dev;
  931. dev->inputs[i].nr = i;
  932. ret = tw5864_video_input_init(&dev->inputs[i], video_nr[i]);
  933. if (ret)
  934. goto fini_video_inputs;
  935. last_input_nr_registered = i;
  936. }
  937. return 0;
  938. fini_video_inputs:
  939. for (i = last_input_nr_registered; i >= 0; i--)
  940. tw5864_video_input_fini(&dev->inputs[i]);
  941. tasklet_kill(&dev->tasklet);
  942. free_dma:
  943. for (i = last_dma_allocated; i >= 0; i--) {
  944. dma_free_coherent(&dev->pci->dev, H264_VLC_BUF_SIZE,
  945. dev->h264_buf[i].vlc.addr,
  946. dev->h264_buf[i].vlc.dma_addr);
  947. dma_free_coherent(&dev->pci->dev, H264_MV_BUF_SIZE,
  948. dev->h264_buf[i].mv.addr,
  949. dev->h264_buf[i].mv.dma_addr);
  950. }
  951. return ret;
  952. }
  953. static int tw5864_video_input_init(struct tw5864_input *input, int video_nr)
  954. {
  955. struct tw5864_dev *dev = input->root;
  956. int ret;
  957. struct v4l2_ctrl_handler *hdl = &input->hdl;
  958. mutex_init(&input->lock);
  959. spin_lock_init(&input->slock);
  960. /* setup video buffers queue */
  961. INIT_LIST_HEAD(&input->active);
  962. input->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  963. input->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
  964. input->vidq.io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF;
  965. input->vidq.ops = &tw5864_video_qops;
  966. input->vidq.mem_ops = &vb2_dma_contig_memops;
  967. input->vidq.drv_priv = input;
  968. input->vidq.gfp_flags = 0;
  969. input->vidq.buf_struct_size = sizeof(struct tw5864_buf);
  970. input->vidq.lock = &input->lock;
  971. input->vidq.min_buffers_needed = 2;
  972. input->vidq.dev = &input->root->pci->dev;
  973. ret = vb2_queue_init(&input->vidq);
  974. if (ret)
  975. goto free_mutex;
  976. input->vdev = tw5864_video_template;
  977. input->vdev.v4l2_dev = &input->root->v4l2_dev;
  978. input->vdev.lock = &input->lock;
  979. input->vdev.queue = &input->vidq;
  980. video_set_drvdata(&input->vdev, input);
  981. /* Initialize the device control structures */
  982. v4l2_ctrl_handler_init(hdl, 6);
  983. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
  984. V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
  985. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
  986. V4L2_CID_CONTRAST, 0, 255, 1, 100);
  987. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
  988. V4L2_CID_SATURATION, 0, 255, 1, 128);
  989. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops, V4L2_CID_HUE, -128, 127, 1, 0);
  990. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops, V4L2_CID_MPEG_VIDEO_GOP_SIZE,
  991. 1, MAX_GOP_SIZE, 1, GOP_SIZE);
  992. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
  993. V4L2_CID_MPEG_VIDEO_H264_MIN_QP, 28, 51, 1, QP_VALUE);
  994. v4l2_ctrl_new_std_menu(hdl, &tw5864_ctrl_ops,
  995. V4L2_CID_DETECT_MD_MODE,
  996. V4L2_DETECT_MD_MODE_THRESHOLD_GRID, 0,
  997. V4L2_DETECT_MD_MODE_DISABLED);
  998. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
  999. V4L2_CID_DETECT_MD_GLOBAL_THRESHOLD,
  1000. tw5864_md_thresholds.min, tw5864_md_thresholds.max,
  1001. tw5864_md_thresholds.step, tw5864_md_thresholds.def);
  1002. input->md_threshold_grid_ctrl =
  1003. v4l2_ctrl_new_custom(hdl, &tw5864_md_thresholds, NULL);
  1004. if (hdl->error) {
  1005. ret = hdl->error;
  1006. goto free_v4l2_hdl;
  1007. }
  1008. input->vdev.ctrl_handler = hdl;
  1009. v4l2_ctrl_handler_setup(hdl);
  1010. input->qp = QP_VALUE;
  1011. input->gop = GOP_SIZE;
  1012. input->frame_interval = 1;
  1013. ret = video_register_device(&input->vdev, VFL_TYPE_GRABBER, video_nr);
  1014. if (ret)
  1015. goto free_v4l2_hdl;
  1016. dev_info(&input->root->pci->dev, "Registered video device %s\n",
  1017. video_device_node_name(&input->vdev));
  1018. /*
  1019. * Set default video standard. Doesn't matter which, the detected value
  1020. * will be found out by VIDIOC_QUERYSTD handler.
  1021. */
  1022. input->v4l2_std = V4L2_STD_NTSC_M;
  1023. input->std = STD_NTSC;
  1024. tw_indir_writeb(TW5864_INDIR_VIN_E(video_nr), 0x07);
  1025. /* to initiate auto format recognition */
  1026. tw_indir_writeb(TW5864_INDIR_VIN_F(video_nr), 0xff);
  1027. return 0;
  1028. free_v4l2_hdl:
  1029. v4l2_ctrl_handler_free(hdl);
  1030. vb2_queue_release(&input->vidq);
  1031. free_mutex:
  1032. mutex_destroy(&input->lock);
  1033. return ret;
  1034. }
  1035. static void tw5864_video_input_fini(struct tw5864_input *dev)
  1036. {
  1037. video_unregister_device(&dev->vdev);
  1038. v4l2_ctrl_handler_free(&dev->hdl);
  1039. vb2_queue_release(&dev->vidq);
  1040. }
  1041. void tw5864_video_fini(struct tw5864_dev *dev)
  1042. {
  1043. int i;
  1044. tasklet_kill(&dev->tasklet);
  1045. for (i = 0; i < TW5864_INPUTS; i++)
  1046. tw5864_video_input_fini(&dev->inputs[i]);
  1047. for (i = 0; i < H264_BUF_CNT; i++) {
  1048. dma_free_coherent(&dev->pci->dev, H264_VLC_BUF_SIZE,
  1049. dev->h264_buf[i].vlc.addr,
  1050. dev->h264_buf[i].vlc.dma_addr);
  1051. dma_free_coherent(&dev->pci->dev, H264_MV_BUF_SIZE,
  1052. dev->h264_buf[i].mv.addr,
  1053. dev->h264_buf[i].mv.dma_addr);
  1054. }
  1055. }
  1056. void tw5864_prepare_frame_headers(struct tw5864_input *input)
  1057. {
  1058. struct tw5864_buf *vb = input->vb;
  1059. u8 *dst;
  1060. size_t dst_space;
  1061. unsigned long flags;
  1062. if (!vb) {
  1063. spin_lock_irqsave(&input->slock, flags);
  1064. if (list_empty(&input->active)) {
  1065. spin_unlock_irqrestore(&input->slock, flags);
  1066. input->vb = NULL;
  1067. return;
  1068. }
  1069. vb = list_first_entry(&input->active, struct tw5864_buf, list);
  1070. list_del(&vb->list);
  1071. spin_unlock_irqrestore(&input->slock, flags);
  1072. }
  1073. dst = vb2_plane_vaddr(&vb->vb.vb2_buf, 0);
  1074. dst_space = vb2_plane_size(&vb->vb.vb2_buf, 0);
  1075. /*
  1076. * Low-level bitstream writing functions don't have a fine way to say
  1077. * correctly that supplied buffer is too small. So we just check there
  1078. * and warn, and don't care at lower level.
  1079. * Currently all headers take below 32 bytes.
  1080. * The buffer is supposed to have plenty of free space at this point,
  1081. * anyway.
  1082. */
  1083. if (WARN_ON_ONCE(dst_space < 128))
  1084. return;
  1085. /*
  1086. * Generate H264 headers:
  1087. * If this is first frame, put SPS and PPS
  1088. */
  1089. if (input->frame_gop_seqno == 0)
  1090. tw5864_h264_put_stream_header(&dst, &dst_space, input->qp,
  1091. input->width, input->height);
  1092. /* Put slice header */
  1093. tw5864_h264_put_slice_header(&dst, &dst_space, input->h264_idr_pic_id,
  1094. input->frame_gop_seqno,
  1095. &input->tail_nb_bits, &input->tail);
  1096. input->vb = vb;
  1097. input->buf_cur_ptr = dst;
  1098. input->buf_cur_space_left = dst_space;
  1099. }
  1100. /*
  1101. * Returns heuristic motion detection metric value from known components of
  1102. * hardware-provided Motion Vector Data.
  1103. */
  1104. static unsigned int tw5864_md_metric_from_mvd(u32 mvd)
  1105. {
  1106. /*
  1107. * Format of motion vector data exposed by tw5864, according to
  1108. * manufacturer:
  1109. * mv_x 10 bits
  1110. * mv_y 10 bits
  1111. * non_zero_members 8 bits
  1112. * mb_type 3 bits
  1113. * reserved 1 bit
  1114. *
  1115. * non_zero_members: number of non-zero residuals in each macro block
  1116. * after quantization
  1117. *
  1118. * unsigned int reserved = mvd >> 31;
  1119. * unsigned int mb_type = (mvd >> 28) & 0x7;
  1120. * unsigned int non_zero_members = (mvd >> 20) & 0xff;
  1121. */
  1122. unsigned int mv_y = (mvd >> 10) & 0x3ff;
  1123. unsigned int mv_x = mvd & 0x3ff;
  1124. /* heuristic: */
  1125. mv_x &= 0x0f;
  1126. mv_y &= 0x0f;
  1127. return mv_y + mv_x;
  1128. }
  1129. static int tw5864_is_motion_triggered(struct tw5864_h264_frame *frame)
  1130. {
  1131. struct tw5864_input *input = frame->input;
  1132. u32 *mv = (u32 *)frame->mv.addr;
  1133. int i;
  1134. int detected = 0;
  1135. for (i = 0; i < MD_CELLS; i++) {
  1136. const u16 thresh = input->md_threshold_grid_values[i];
  1137. const unsigned int metric = tw5864_md_metric_from_mvd(mv[i]);
  1138. if (metric > thresh)
  1139. detected = 1;
  1140. if (detected)
  1141. break;
  1142. }
  1143. return detected;
  1144. }
  1145. static void tw5864_handle_frame_task(unsigned long data)
  1146. {
  1147. struct tw5864_dev *dev = (struct tw5864_dev *)data;
  1148. unsigned long flags;
  1149. int batch_size = H264_BUF_CNT;
  1150. spin_lock_irqsave(&dev->slock, flags);
  1151. while (dev->h264_buf_r_index != dev->h264_buf_w_index && batch_size--) {
  1152. struct tw5864_h264_frame *frame =
  1153. &dev->h264_buf[dev->h264_buf_r_index];
  1154. spin_unlock_irqrestore(&dev->slock, flags);
  1155. dma_sync_single_for_cpu(&dev->pci->dev, frame->vlc.dma_addr,
  1156. H264_VLC_BUF_SIZE, DMA_FROM_DEVICE);
  1157. dma_sync_single_for_cpu(&dev->pci->dev, frame->mv.dma_addr,
  1158. H264_MV_BUF_SIZE, DMA_FROM_DEVICE);
  1159. tw5864_handle_frame(frame);
  1160. dma_sync_single_for_device(&dev->pci->dev, frame->vlc.dma_addr,
  1161. H264_VLC_BUF_SIZE, DMA_FROM_DEVICE);
  1162. dma_sync_single_for_device(&dev->pci->dev, frame->mv.dma_addr,
  1163. H264_MV_BUF_SIZE, DMA_FROM_DEVICE);
  1164. spin_lock_irqsave(&dev->slock, flags);
  1165. dev->h264_buf_r_index++;
  1166. dev->h264_buf_r_index %= H264_BUF_CNT;
  1167. }
  1168. spin_unlock_irqrestore(&dev->slock, flags);
  1169. }
  1170. #ifdef DEBUG
  1171. static u32 tw5864_vlc_checksum(u32 *data, int len)
  1172. {
  1173. u32 val, count_len = len;
  1174. val = *data++;
  1175. while (((count_len >> 2) - 1) > 0) {
  1176. val ^= *data++;
  1177. count_len -= 4;
  1178. }
  1179. val ^= htonl((len >> 2));
  1180. return val;
  1181. }
  1182. #endif
  1183. static void tw5864_handle_frame(struct tw5864_h264_frame *frame)
  1184. {
  1185. #define SKIP_VLCBUF_BYTES 3
  1186. struct tw5864_input *input = frame->input;
  1187. struct tw5864_dev *dev = input->root;
  1188. struct tw5864_buf *vb;
  1189. struct vb2_v4l2_buffer *v4l2_buf;
  1190. int frame_len = frame->vlc_len - SKIP_VLCBUF_BYTES;
  1191. u8 *dst = input->buf_cur_ptr;
  1192. u8 tail_mask, vlc_mask = 0;
  1193. int i;
  1194. u8 vlc_first_byte = ((u8 *)(frame->vlc.addr + SKIP_VLCBUF_BYTES))[0];
  1195. unsigned long flags;
  1196. int zero_run;
  1197. u8 *src;
  1198. u8 *src_end;
  1199. #ifdef DEBUG
  1200. if (frame->checksum !=
  1201. tw5864_vlc_checksum((u32 *)frame->vlc.addr, frame_len))
  1202. dev_err(&dev->pci->dev,
  1203. "Checksum of encoded frame doesn't match!\n");
  1204. #endif
  1205. spin_lock_irqsave(&input->slock, flags);
  1206. vb = input->vb;
  1207. input->vb = NULL;
  1208. spin_unlock_irqrestore(&input->slock, flags);
  1209. v4l2_buf = to_vb2_v4l2_buffer(&vb->vb.vb2_buf);
  1210. if (!vb) { /* Gone because of disabling */
  1211. dev_dbg(&dev->pci->dev, "vb is empty, dropping frame\n");
  1212. return;
  1213. }
  1214. /*
  1215. * Check for space.
  1216. * Mind the overhead of startcode emulation prevention.
  1217. */
  1218. if (input->buf_cur_space_left < frame_len * 5 / 4) {
  1219. dev_err_once(&dev->pci->dev,
  1220. "Left space in vb2 buffer, %d bytes, is less than considered safely enough to put frame of length %d. Dropping this frame.\n",
  1221. input->buf_cur_space_left, frame_len);
  1222. return;
  1223. }
  1224. for (i = 0; i < 8 - input->tail_nb_bits; i++)
  1225. vlc_mask |= 1 << i;
  1226. tail_mask = (~vlc_mask) & 0xff;
  1227. dst[0] = (input->tail & tail_mask) | (vlc_first_byte & vlc_mask);
  1228. frame_len--;
  1229. dst++;
  1230. /* H.264 startcode emulation prevention */
  1231. src = frame->vlc.addr + SKIP_VLCBUF_BYTES + 1;
  1232. src_end = src + frame_len;
  1233. zero_run = 0;
  1234. for (; src < src_end; src++) {
  1235. if (zero_run < 2) {
  1236. if (*src == 0)
  1237. ++zero_run;
  1238. else
  1239. zero_run = 0;
  1240. } else {
  1241. if ((*src & ~0x03) == 0)
  1242. *dst++ = 0x03;
  1243. zero_run = *src == 0;
  1244. }
  1245. *dst++ = *src;
  1246. }
  1247. vb2_set_plane_payload(&vb->vb.vb2_buf, 0,
  1248. dst - (u8 *)vb2_plane_vaddr(&vb->vb.vb2_buf, 0));
  1249. vb->vb.vb2_buf.timestamp = frame->timestamp;
  1250. v4l2_buf->field = V4L2_FIELD_INTERLACED;
  1251. v4l2_buf->sequence = frame->seqno;
  1252. /* Check for motion flags */
  1253. if (frame->gop_seqno /* P-frame */ &&
  1254. tw5864_is_motion_triggered(frame)) {
  1255. struct v4l2_event ev = {
  1256. .type = V4L2_EVENT_MOTION_DET,
  1257. .u.motion_det = {
  1258. .flags = V4L2_EVENT_MD_FL_HAVE_FRAME_SEQ,
  1259. .frame_sequence = v4l2_buf->sequence,
  1260. },
  1261. };
  1262. v4l2_event_queue(&input->vdev, &ev);
  1263. }
  1264. vb2_buffer_done(&vb->vb.vb2_buf, VB2_BUF_STATE_DONE);
  1265. }
  1266. static v4l2_std_id tw5864_get_v4l2_std(enum tw5864_vid_std std)
  1267. {
  1268. switch (std) {
  1269. case STD_NTSC: return V4L2_STD_NTSC_M;
  1270. case STD_PAL: return V4L2_STD_PAL_B;
  1271. case STD_SECAM: return V4L2_STD_SECAM_B;
  1272. case STD_NTSC443: return V4L2_STD_NTSC_443;
  1273. case STD_PAL_M: return V4L2_STD_PAL_M;
  1274. case STD_PAL_CN: return V4L2_STD_PAL_Nc;
  1275. case STD_PAL_60: return V4L2_STD_PAL_60;
  1276. case STD_INVALID: return V4L2_STD_UNKNOWN;
  1277. }
  1278. return 0;
  1279. }
  1280. static enum tw5864_vid_std tw5864_from_v4l2_std(v4l2_std_id v4l2_std)
  1281. {
  1282. if (v4l2_std & V4L2_STD_NTSC_M)
  1283. return STD_NTSC;
  1284. if (v4l2_std & V4L2_STD_PAL_B)
  1285. return STD_PAL;
  1286. if (v4l2_std & V4L2_STD_SECAM_B)
  1287. return STD_SECAM;
  1288. if (v4l2_std & V4L2_STD_NTSC_443)
  1289. return STD_NTSC443;
  1290. if (v4l2_std & V4L2_STD_PAL_M)
  1291. return STD_PAL_M;
  1292. if (v4l2_std & V4L2_STD_PAL_Nc)
  1293. return STD_PAL_CN;
  1294. if (v4l2_std & V4L2_STD_PAL_60)
  1295. return STD_PAL_60;
  1296. return STD_INVALID;
  1297. }
  1298. static void tw5864_encoder_tables_upload(struct tw5864_dev *dev)
  1299. {
  1300. int i;
  1301. tw_writel(TW5864_VLC_RD, 0x1);
  1302. for (i = 0; i < VLC_LOOKUP_TABLE_LEN; i++) {
  1303. tw_writel((TW5864_VLC_STREAM_MEM_START + i * 4),
  1304. encoder_vlc_lookup_table[i]);
  1305. }
  1306. tw_writel(TW5864_VLC_RD, 0x0);
  1307. for (i = 0; i < QUANTIZATION_TABLE_LEN; i++) {
  1308. tw_writel((TW5864_QUAN_TAB + i * 4),
  1309. forward_quantization_table[i]);
  1310. }
  1311. for (i = 0; i < QUANTIZATION_TABLE_LEN; i++) {
  1312. tw_writel((TW5864_QUAN_TAB + i * 4),
  1313. inverse_quantization_table[i]);
  1314. }
  1315. }