pt1.c 25 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226
  1. /*
  2. * driver for Earthsoft PT1/PT2
  3. *
  4. * Copyright (C) 2009 HIRANO Takahito <hiranotaka@zng.info>
  5. *
  6. * based on pt1dvr - http://pt1dvr.sourceforge.jp/
  7. * by Tomoaki Ishikawa <tomy@users.sourceforge.jp>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #include <linux/kernel.h>
  24. #include <linux/module.h>
  25. #include <linux/slab.h>
  26. #include <linux/vmalloc.h>
  27. #include <linux/pci.h>
  28. #include <linux/kthread.h>
  29. #include <linux/freezer.h>
  30. #include <linux/ratelimit.h>
  31. #include "dvbdev.h"
  32. #include "dvb_demux.h"
  33. #include "dmxdev.h"
  34. #include "dvb_net.h"
  35. #include "dvb_frontend.h"
  36. #include "va1j5jf8007t.h"
  37. #include "va1j5jf8007s.h"
  38. #define DRIVER_NAME "earth-pt1"
  39. #define PT1_PAGE_SHIFT 12
  40. #define PT1_PAGE_SIZE (1 << PT1_PAGE_SHIFT)
  41. #define PT1_NR_UPACKETS 1024
  42. #define PT1_NR_BUFS 511
  43. struct pt1_buffer_page {
  44. __le32 upackets[PT1_NR_UPACKETS];
  45. };
  46. struct pt1_table_page {
  47. __le32 next_pfn;
  48. __le32 buf_pfns[PT1_NR_BUFS];
  49. };
  50. struct pt1_buffer {
  51. struct pt1_buffer_page *page;
  52. dma_addr_t addr;
  53. };
  54. struct pt1_table {
  55. struct pt1_table_page *page;
  56. dma_addr_t addr;
  57. struct pt1_buffer bufs[PT1_NR_BUFS];
  58. };
  59. #define PT1_NR_ADAPS 4
  60. struct pt1_adapter;
  61. struct pt1 {
  62. struct pci_dev *pdev;
  63. void __iomem *regs;
  64. struct i2c_adapter i2c_adap;
  65. int i2c_running;
  66. struct pt1_adapter *adaps[PT1_NR_ADAPS];
  67. struct pt1_table *tables;
  68. struct task_struct *kthread;
  69. int table_index;
  70. int buf_index;
  71. struct mutex lock;
  72. int power;
  73. int reset;
  74. };
  75. struct pt1_adapter {
  76. struct pt1 *pt1;
  77. int index;
  78. u8 *buf;
  79. int upacket_count;
  80. int packet_count;
  81. int st_count;
  82. struct dvb_adapter adap;
  83. struct dvb_demux demux;
  84. int users;
  85. struct dmxdev dmxdev;
  86. struct dvb_frontend *fe;
  87. int (*orig_set_voltage)(struct dvb_frontend *fe,
  88. enum fe_sec_voltage voltage);
  89. int (*orig_sleep)(struct dvb_frontend *fe);
  90. int (*orig_init)(struct dvb_frontend *fe);
  91. enum fe_sec_voltage voltage;
  92. int sleep;
  93. };
  94. static void pt1_write_reg(struct pt1 *pt1, int reg, u32 data)
  95. {
  96. writel(data, pt1->regs + reg * 4);
  97. }
  98. static u32 pt1_read_reg(struct pt1 *pt1, int reg)
  99. {
  100. return readl(pt1->regs + reg * 4);
  101. }
  102. static int pt1_nr_tables = 8;
  103. module_param_named(nr_tables, pt1_nr_tables, int, 0);
  104. static void pt1_increment_table_count(struct pt1 *pt1)
  105. {
  106. pt1_write_reg(pt1, 0, 0x00000020);
  107. }
  108. static void pt1_init_table_count(struct pt1 *pt1)
  109. {
  110. pt1_write_reg(pt1, 0, 0x00000010);
  111. }
  112. static void pt1_register_tables(struct pt1 *pt1, u32 first_pfn)
  113. {
  114. pt1_write_reg(pt1, 5, first_pfn);
  115. pt1_write_reg(pt1, 0, 0x0c000040);
  116. }
  117. static void pt1_unregister_tables(struct pt1 *pt1)
  118. {
  119. pt1_write_reg(pt1, 0, 0x08080000);
  120. }
  121. static int pt1_sync(struct pt1 *pt1)
  122. {
  123. int i;
  124. for (i = 0; i < 57; i++) {
  125. if (pt1_read_reg(pt1, 0) & 0x20000000)
  126. return 0;
  127. pt1_write_reg(pt1, 0, 0x00000008);
  128. }
  129. dev_err(&pt1->pdev->dev, "could not sync\n");
  130. return -EIO;
  131. }
  132. static u64 pt1_identify(struct pt1 *pt1)
  133. {
  134. int i;
  135. u64 id;
  136. id = 0;
  137. for (i = 0; i < 57; i++) {
  138. id |= (u64)(pt1_read_reg(pt1, 0) >> 30 & 1) << i;
  139. pt1_write_reg(pt1, 0, 0x00000008);
  140. }
  141. return id;
  142. }
  143. static int pt1_unlock(struct pt1 *pt1)
  144. {
  145. int i;
  146. pt1_write_reg(pt1, 0, 0x00000008);
  147. for (i = 0; i < 3; i++) {
  148. if (pt1_read_reg(pt1, 0) & 0x80000000)
  149. return 0;
  150. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  151. }
  152. dev_err(&pt1->pdev->dev, "could not unlock\n");
  153. return -EIO;
  154. }
  155. static int pt1_reset_pci(struct pt1 *pt1)
  156. {
  157. int i;
  158. pt1_write_reg(pt1, 0, 0x01010000);
  159. pt1_write_reg(pt1, 0, 0x01000000);
  160. for (i = 0; i < 10; i++) {
  161. if (pt1_read_reg(pt1, 0) & 0x00000001)
  162. return 0;
  163. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  164. }
  165. dev_err(&pt1->pdev->dev, "could not reset PCI\n");
  166. return -EIO;
  167. }
  168. static int pt1_reset_ram(struct pt1 *pt1)
  169. {
  170. int i;
  171. pt1_write_reg(pt1, 0, 0x02020000);
  172. pt1_write_reg(pt1, 0, 0x02000000);
  173. for (i = 0; i < 10; i++) {
  174. if (pt1_read_reg(pt1, 0) & 0x00000002)
  175. return 0;
  176. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  177. }
  178. dev_err(&pt1->pdev->dev, "could not reset RAM\n");
  179. return -EIO;
  180. }
  181. static int pt1_do_enable_ram(struct pt1 *pt1)
  182. {
  183. int i, j;
  184. u32 status;
  185. status = pt1_read_reg(pt1, 0) & 0x00000004;
  186. pt1_write_reg(pt1, 0, 0x00000002);
  187. for (i = 0; i < 10; i++) {
  188. for (j = 0; j < 1024; j++) {
  189. if ((pt1_read_reg(pt1, 0) & 0x00000004) != status)
  190. return 0;
  191. }
  192. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  193. }
  194. dev_err(&pt1->pdev->dev, "could not enable RAM\n");
  195. return -EIO;
  196. }
  197. static int pt1_enable_ram(struct pt1 *pt1)
  198. {
  199. int i, ret;
  200. int phase;
  201. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  202. phase = pt1->pdev->device == 0x211a ? 128 : 166;
  203. for (i = 0; i < phase; i++) {
  204. ret = pt1_do_enable_ram(pt1);
  205. if (ret < 0)
  206. return ret;
  207. }
  208. return 0;
  209. }
  210. static void pt1_disable_ram(struct pt1 *pt1)
  211. {
  212. pt1_write_reg(pt1, 0, 0x0b0b0000);
  213. }
  214. static void pt1_set_stream(struct pt1 *pt1, int index, int enabled)
  215. {
  216. pt1_write_reg(pt1, 2, 1 << (index + 8) | enabled << index);
  217. }
  218. static void pt1_init_streams(struct pt1 *pt1)
  219. {
  220. int i;
  221. for (i = 0; i < PT1_NR_ADAPS; i++)
  222. pt1_set_stream(pt1, i, 0);
  223. }
  224. static int pt1_filter(struct pt1 *pt1, struct pt1_buffer_page *page)
  225. {
  226. u32 upacket;
  227. int i;
  228. int index;
  229. struct pt1_adapter *adap;
  230. int offset;
  231. u8 *buf;
  232. int sc;
  233. if (!page->upackets[PT1_NR_UPACKETS - 1])
  234. return 0;
  235. for (i = 0; i < PT1_NR_UPACKETS; i++) {
  236. upacket = le32_to_cpu(page->upackets[i]);
  237. index = (upacket >> 29) - 1;
  238. if (index < 0 || index >= PT1_NR_ADAPS)
  239. continue;
  240. adap = pt1->adaps[index];
  241. if (upacket >> 25 & 1)
  242. adap->upacket_count = 0;
  243. else if (!adap->upacket_count)
  244. continue;
  245. if (upacket >> 24 & 1)
  246. printk_ratelimited(KERN_INFO "earth-pt1: device buffer overflowing. table[%d] buf[%d]\n",
  247. pt1->table_index, pt1->buf_index);
  248. sc = upacket >> 26 & 0x7;
  249. if (adap->st_count != -1 && sc != ((adap->st_count + 1) & 0x7))
  250. printk_ratelimited(KERN_INFO "earth-pt1: data loss in streamID(adapter)[%d]\n",
  251. index);
  252. adap->st_count = sc;
  253. buf = adap->buf;
  254. offset = adap->packet_count * 188 + adap->upacket_count * 3;
  255. buf[offset] = upacket >> 16;
  256. buf[offset + 1] = upacket >> 8;
  257. if (adap->upacket_count != 62)
  258. buf[offset + 2] = upacket;
  259. if (++adap->upacket_count >= 63) {
  260. adap->upacket_count = 0;
  261. if (++adap->packet_count >= 21) {
  262. dvb_dmx_swfilter_packets(&adap->demux, buf, 21);
  263. adap->packet_count = 0;
  264. }
  265. }
  266. }
  267. page->upackets[PT1_NR_UPACKETS - 1] = 0;
  268. return 1;
  269. }
  270. static int pt1_thread(void *data)
  271. {
  272. struct pt1 *pt1;
  273. struct pt1_buffer_page *page;
  274. pt1 = data;
  275. set_freezable();
  276. while (!kthread_should_stop()) {
  277. try_to_freeze();
  278. page = pt1->tables[pt1->table_index].bufs[pt1->buf_index].page;
  279. if (!pt1_filter(pt1, page)) {
  280. schedule_timeout_interruptible((HZ + 999) / 1000);
  281. continue;
  282. }
  283. if (++pt1->buf_index >= PT1_NR_BUFS) {
  284. pt1_increment_table_count(pt1);
  285. pt1->buf_index = 0;
  286. if (++pt1->table_index >= pt1_nr_tables)
  287. pt1->table_index = 0;
  288. }
  289. }
  290. return 0;
  291. }
  292. static void pt1_free_page(struct pt1 *pt1, void *page, dma_addr_t addr)
  293. {
  294. dma_free_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, page, addr);
  295. }
  296. static void *pt1_alloc_page(struct pt1 *pt1, dma_addr_t *addrp, u32 *pfnp)
  297. {
  298. void *page;
  299. dma_addr_t addr;
  300. page = dma_alloc_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, &addr,
  301. GFP_KERNEL);
  302. if (page == NULL)
  303. return NULL;
  304. BUG_ON(addr & (PT1_PAGE_SIZE - 1));
  305. BUG_ON(addr >> PT1_PAGE_SHIFT >> 31 >> 1);
  306. *addrp = addr;
  307. *pfnp = addr >> PT1_PAGE_SHIFT;
  308. return page;
  309. }
  310. static void pt1_cleanup_buffer(struct pt1 *pt1, struct pt1_buffer *buf)
  311. {
  312. pt1_free_page(pt1, buf->page, buf->addr);
  313. }
  314. static int
  315. pt1_init_buffer(struct pt1 *pt1, struct pt1_buffer *buf, u32 *pfnp)
  316. {
  317. struct pt1_buffer_page *page;
  318. dma_addr_t addr;
  319. page = pt1_alloc_page(pt1, &addr, pfnp);
  320. if (page == NULL)
  321. return -ENOMEM;
  322. page->upackets[PT1_NR_UPACKETS - 1] = 0;
  323. buf->page = page;
  324. buf->addr = addr;
  325. return 0;
  326. }
  327. static void pt1_cleanup_table(struct pt1 *pt1, struct pt1_table *table)
  328. {
  329. int i;
  330. for (i = 0; i < PT1_NR_BUFS; i++)
  331. pt1_cleanup_buffer(pt1, &table->bufs[i]);
  332. pt1_free_page(pt1, table->page, table->addr);
  333. }
  334. static int
  335. pt1_init_table(struct pt1 *pt1, struct pt1_table *table, u32 *pfnp)
  336. {
  337. struct pt1_table_page *page;
  338. dma_addr_t addr;
  339. int i, ret;
  340. u32 buf_pfn;
  341. page = pt1_alloc_page(pt1, &addr, pfnp);
  342. if (page == NULL)
  343. return -ENOMEM;
  344. for (i = 0; i < PT1_NR_BUFS; i++) {
  345. ret = pt1_init_buffer(pt1, &table->bufs[i], &buf_pfn);
  346. if (ret < 0)
  347. goto err;
  348. page->buf_pfns[i] = cpu_to_le32(buf_pfn);
  349. }
  350. pt1_increment_table_count(pt1);
  351. table->page = page;
  352. table->addr = addr;
  353. return 0;
  354. err:
  355. while (i--)
  356. pt1_cleanup_buffer(pt1, &table->bufs[i]);
  357. pt1_free_page(pt1, page, addr);
  358. return ret;
  359. }
  360. static void pt1_cleanup_tables(struct pt1 *pt1)
  361. {
  362. struct pt1_table *tables;
  363. int i;
  364. tables = pt1->tables;
  365. pt1_unregister_tables(pt1);
  366. for (i = 0; i < pt1_nr_tables; i++)
  367. pt1_cleanup_table(pt1, &tables[i]);
  368. vfree(tables);
  369. }
  370. static int pt1_init_tables(struct pt1 *pt1)
  371. {
  372. struct pt1_table *tables;
  373. int i, ret;
  374. u32 first_pfn, pfn;
  375. tables = vmalloc(sizeof(struct pt1_table) * pt1_nr_tables);
  376. if (tables == NULL)
  377. return -ENOMEM;
  378. pt1_init_table_count(pt1);
  379. i = 0;
  380. if (pt1_nr_tables) {
  381. ret = pt1_init_table(pt1, &tables[0], &first_pfn);
  382. if (ret)
  383. goto err;
  384. i++;
  385. }
  386. while (i < pt1_nr_tables) {
  387. ret = pt1_init_table(pt1, &tables[i], &pfn);
  388. if (ret)
  389. goto err;
  390. tables[i - 1].page->next_pfn = cpu_to_le32(pfn);
  391. i++;
  392. }
  393. tables[pt1_nr_tables - 1].page->next_pfn = cpu_to_le32(first_pfn);
  394. pt1_register_tables(pt1, first_pfn);
  395. pt1->tables = tables;
  396. return 0;
  397. err:
  398. while (i--)
  399. pt1_cleanup_table(pt1, &tables[i]);
  400. vfree(tables);
  401. return ret;
  402. }
  403. static int pt1_start_polling(struct pt1 *pt1)
  404. {
  405. int ret = 0;
  406. mutex_lock(&pt1->lock);
  407. if (!pt1->kthread) {
  408. pt1->kthread = kthread_run(pt1_thread, pt1, "earth-pt1");
  409. if (IS_ERR(pt1->kthread)) {
  410. ret = PTR_ERR(pt1->kthread);
  411. pt1->kthread = NULL;
  412. }
  413. }
  414. mutex_unlock(&pt1->lock);
  415. return ret;
  416. }
  417. static int pt1_start_feed(struct dvb_demux_feed *feed)
  418. {
  419. struct pt1_adapter *adap;
  420. adap = container_of(feed->demux, struct pt1_adapter, demux);
  421. if (!adap->users++) {
  422. int ret;
  423. ret = pt1_start_polling(adap->pt1);
  424. if (ret)
  425. return ret;
  426. pt1_set_stream(adap->pt1, adap->index, 1);
  427. }
  428. return 0;
  429. }
  430. static void pt1_stop_polling(struct pt1 *pt1)
  431. {
  432. int i, count;
  433. mutex_lock(&pt1->lock);
  434. for (i = 0, count = 0; i < PT1_NR_ADAPS; i++)
  435. count += pt1->adaps[i]->users;
  436. if (count == 0 && pt1->kthread) {
  437. kthread_stop(pt1->kthread);
  438. pt1->kthread = NULL;
  439. }
  440. mutex_unlock(&pt1->lock);
  441. }
  442. static int pt1_stop_feed(struct dvb_demux_feed *feed)
  443. {
  444. struct pt1_adapter *adap;
  445. adap = container_of(feed->demux, struct pt1_adapter, demux);
  446. if (!--adap->users) {
  447. pt1_set_stream(adap->pt1, adap->index, 0);
  448. pt1_stop_polling(adap->pt1);
  449. }
  450. return 0;
  451. }
  452. static void
  453. pt1_update_power(struct pt1 *pt1)
  454. {
  455. int bits;
  456. int i;
  457. struct pt1_adapter *adap;
  458. static const int sleep_bits[] = {
  459. 1 << 4,
  460. 1 << 6 | 1 << 7,
  461. 1 << 5,
  462. 1 << 6 | 1 << 8,
  463. };
  464. bits = pt1->power | !pt1->reset << 3;
  465. mutex_lock(&pt1->lock);
  466. for (i = 0; i < PT1_NR_ADAPS; i++) {
  467. adap = pt1->adaps[i];
  468. switch (adap->voltage) {
  469. case SEC_VOLTAGE_13: /* actually 11V */
  470. bits |= 1 << 1;
  471. break;
  472. case SEC_VOLTAGE_18: /* actually 15V */
  473. bits |= 1 << 1 | 1 << 2;
  474. break;
  475. default:
  476. break;
  477. }
  478. /* XXX: The bits should be changed depending on adap->sleep. */
  479. bits |= sleep_bits[i];
  480. }
  481. pt1_write_reg(pt1, 1, bits);
  482. mutex_unlock(&pt1->lock);
  483. }
  484. static int pt1_set_voltage(struct dvb_frontend *fe, enum fe_sec_voltage voltage)
  485. {
  486. struct pt1_adapter *adap;
  487. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  488. adap->voltage = voltage;
  489. pt1_update_power(adap->pt1);
  490. if (adap->orig_set_voltage)
  491. return adap->orig_set_voltage(fe, voltage);
  492. else
  493. return 0;
  494. }
  495. static int pt1_sleep(struct dvb_frontend *fe)
  496. {
  497. struct pt1_adapter *adap;
  498. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  499. adap->sleep = 1;
  500. pt1_update_power(adap->pt1);
  501. if (adap->orig_sleep)
  502. return adap->orig_sleep(fe);
  503. else
  504. return 0;
  505. }
  506. static int pt1_wakeup(struct dvb_frontend *fe)
  507. {
  508. struct pt1_adapter *adap;
  509. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  510. adap->sleep = 0;
  511. pt1_update_power(adap->pt1);
  512. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  513. if (adap->orig_init)
  514. return adap->orig_init(fe);
  515. else
  516. return 0;
  517. }
  518. static void pt1_free_adapter(struct pt1_adapter *adap)
  519. {
  520. adap->demux.dmx.close(&adap->demux.dmx);
  521. dvb_dmxdev_release(&adap->dmxdev);
  522. dvb_dmx_release(&adap->demux);
  523. dvb_unregister_adapter(&adap->adap);
  524. free_page((unsigned long)adap->buf);
  525. kfree(adap);
  526. }
  527. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  528. static struct pt1_adapter *
  529. pt1_alloc_adapter(struct pt1 *pt1)
  530. {
  531. struct pt1_adapter *adap;
  532. void *buf;
  533. struct dvb_adapter *dvb_adap;
  534. struct dvb_demux *demux;
  535. struct dmxdev *dmxdev;
  536. int ret;
  537. adap = kzalloc(sizeof(struct pt1_adapter), GFP_KERNEL);
  538. if (!adap) {
  539. ret = -ENOMEM;
  540. goto err;
  541. }
  542. adap->pt1 = pt1;
  543. adap->voltage = SEC_VOLTAGE_OFF;
  544. adap->sleep = 1;
  545. buf = (u8 *)__get_free_page(GFP_KERNEL);
  546. if (!buf) {
  547. ret = -ENOMEM;
  548. goto err_kfree;
  549. }
  550. adap->buf = buf;
  551. adap->upacket_count = 0;
  552. adap->packet_count = 0;
  553. adap->st_count = -1;
  554. dvb_adap = &adap->adap;
  555. dvb_adap->priv = adap;
  556. ret = dvb_register_adapter(dvb_adap, DRIVER_NAME, THIS_MODULE,
  557. &pt1->pdev->dev, adapter_nr);
  558. if (ret < 0)
  559. goto err_free_page;
  560. demux = &adap->demux;
  561. demux->dmx.capabilities = DMX_TS_FILTERING | DMX_SECTION_FILTERING;
  562. demux->priv = adap;
  563. demux->feednum = 256;
  564. demux->filternum = 256;
  565. demux->start_feed = pt1_start_feed;
  566. demux->stop_feed = pt1_stop_feed;
  567. demux->write_to_decoder = NULL;
  568. ret = dvb_dmx_init(demux);
  569. if (ret < 0)
  570. goto err_unregister_adapter;
  571. dmxdev = &adap->dmxdev;
  572. dmxdev->filternum = 256;
  573. dmxdev->demux = &demux->dmx;
  574. dmxdev->capabilities = 0;
  575. ret = dvb_dmxdev_init(dmxdev, dvb_adap);
  576. if (ret < 0)
  577. goto err_dmx_release;
  578. return adap;
  579. err_dmx_release:
  580. dvb_dmx_release(demux);
  581. err_unregister_adapter:
  582. dvb_unregister_adapter(dvb_adap);
  583. err_free_page:
  584. free_page((unsigned long)buf);
  585. err_kfree:
  586. kfree(adap);
  587. err:
  588. return ERR_PTR(ret);
  589. }
  590. static void pt1_cleanup_adapters(struct pt1 *pt1)
  591. {
  592. int i;
  593. for (i = 0; i < PT1_NR_ADAPS; i++)
  594. pt1_free_adapter(pt1->adaps[i]);
  595. }
  596. static int pt1_init_adapters(struct pt1 *pt1)
  597. {
  598. int i;
  599. struct pt1_adapter *adap;
  600. int ret;
  601. for (i = 0; i < PT1_NR_ADAPS; i++) {
  602. adap = pt1_alloc_adapter(pt1);
  603. if (IS_ERR(adap)) {
  604. ret = PTR_ERR(adap);
  605. goto err;
  606. }
  607. adap->index = i;
  608. pt1->adaps[i] = adap;
  609. }
  610. return 0;
  611. err:
  612. while (i--)
  613. pt1_free_adapter(pt1->adaps[i]);
  614. return ret;
  615. }
  616. static void pt1_cleanup_frontend(struct pt1_adapter *adap)
  617. {
  618. dvb_unregister_frontend(adap->fe);
  619. }
  620. static int pt1_init_frontend(struct pt1_adapter *adap, struct dvb_frontend *fe)
  621. {
  622. int ret;
  623. adap->orig_set_voltage = fe->ops.set_voltage;
  624. adap->orig_sleep = fe->ops.sleep;
  625. adap->orig_init = fe->ops.init;
  626. fe->ops.set_voltage = pt1_set_voltage;
  627. fe->ops.sleep = pt1_sleep;
  628. fe->ops.init = pt1_wakeup;
  629. ret = dvb_register_frontend(&adap->adap, fe);
  630. if (ret < 0)
  631. return ret;
  632. adap->fe = fe;
  633. return 0;
  634. }
  635. static void pt1_cleanup_frontends(struct pt1 *pt1)
  636. {
  637. int i;
  638. for (i = 0; i < PT1_NR_ADAPS; i++)
  639. pt1_cleanup_frontend(pt1->adaps[i]);
  640. }
  641. struct pt1_config {
  642. struct va1j5jf8007s_config va1j5jf8007s_config;
  643. struct va1j5jf8007t_config va1j5jf8007t_config;
  644. };
  645. static const struct pt1_config pt1_configs[2] = {
  646. {
  647. {
  648. .demod_address = 0x1b,
  649. .frequency = VA1J5JF8007S_20MHZ,
  650. },
  651. {
  652. .demod_address = 0x1a,
  653. .frequency = VA1J5JF8007T_20MHZ,
  654. },
  655. }, {
  656. {
  657. .demod_address = 0x19,
  658. .frequency = VA1J5JF8007S_20MHZ,
  659. },
  660. {
  661. .demod_address = 0x18,
  662. .frequency = VA1J5JF8007T_20MHZ,
  663. },
  664. },
  665. };
  666. static const struct pt1_config pt2_configs[2] = {
  667. {
  668. {
  669. .demod_address = 0x1b,
  670. .frequency = VA1J5JF8007S_25MHZ,
  671. },
  672. {
  673. .demod_address = 0x1a,
  674. .frequency = VA1J5JF8007T_25MHZ,
  675. },
  676. }, {
  677. {
  678. .demod_address = 0x19,
  679. .frequency = VA1J5JF8007S_25MHZ,
  680. },
  681. {
  682. .demod_address = 0x18,
  683. .frequency = VA1J5JF8007T_25MHZ,
  684. },
  685. },
  686. };
  687. static int pt1_init_frontends(struct pt1 *pt1)
  688. {
  689. int i, j;
  690. struct i2c_adapter *i2c_adap;
  691. const struct pt1_config *configs, *config;
  692. struct dvb_frontend *fe[4];
  693. int ret;
  694. i = 0;
  695. j = 0;
  696. i2c_adap = &pt1->i2c_adap;
  697. configs = pt1->pdev->device == 0x211a ? pt1_configs : pt2_configs;
  698. do {
  699. config = &configs[i / 2];
  700. fe[i] = va1j5jf8007s_attach(&config->va1j5jf8007s_config,
  701. i2c_adap);
  702. if (!fe[i]) {
  703. ret = -ENODEV; /* This does not sound nice... */
  704. goto err;
  705. }
  706. i++;
  707. fe[i] = va1j5jf8007t_attach(&config->va1j5jf8007t_config,
  708. i2c_adap);
  709. if (!fe[i]) {
  710. ret = -ENODEV;
  711. goto err;
  712. }
  713. i++;
  714. ret = va1j5jf8007s_prepare(fe[i - 2]);
  715. if (ret < 0)
  716. goto err;
  717. ret = va1j5jf8007t_prepare(fe[i - 1]);
  718. if (ret < 0)
  719. goto err;
  720. } while (i < 4);
  721. do {
  722. ret = pt1_init_frontend(pt1->adaps[j], fe[j]);
  723. if (ret < 0)
  724. goto err;
  725. } while (++j < 4);
  726. return 0;
  727. err:
  728. while (i-- > j)
  729. fe[i]->ops.release(fe[i]);
  730. while (j--)
  731. dvb_unregister_frontend(fe[j]);
  732. return ret;
  733. }
  734. static void pt1_i2c_emit(struct pt1 *pt1, int addr, int busy, int read_enable,
  735. int clock, int data, int next_addr)
  736. {
  737. pt1_write_reg(pt1, 4, addr << 18 | busy << 13 | read_enable << 12 |
  738. !clock << 11 | !data << 10 | next_addr);
  739. }
  740. static void pt1_i2c_write_bit(struct pt1 *pt1, int addr, int *addrp, int data)
  741. {
  742. pt1_i2c_emit(pt1, addr, 1, 0, 0, data, addr + 1);
  743. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, data, addr + 2);
  744. pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, data, addr + 3);
  745. *addrp = addr + 3;
  746. }
  747. static void pt1_i2c_read_bit(struct pt1 *pt1, int addr, int *addrp)
  748. {
  749. pt1_i2c_emit(pt1, addr, 1, 0, 0, 1, addr + 1);
  750. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 1, addr + 2);
  751. pt1_i2c_emit(pt1, addr + 2, 1, 1, 1, 1, addr + 3);
  752. pt1_i2c_emit(pt1, addr + 3, 1, 0, 0, 1, addr + 4);
  753. *addrp = addr + 4;
  754. }
  755. static void pt1_i2c_write_byte(struct pt1 *pt1, int addr, int *addrp, int data)
  756. {
  757. int i;
  758. for (i = 0; i < 8; i++)
  759. pt1_i2c_write_bit(pt1, addr, &addr, data >> (7 - i) & 1);
  760. pt1_i2c_write_bit(pt1, addr, &addr, 1);
  761. *addrp = addr;
  762. }
  763. static void pt1_i2c_read_byte(struct pt1 *pt1, int addr, int *addrp, int last)
  764. {
  765. int i;
  766. for (i = 0; i < 8; i++)
  767. pt1_i2c_read_bit(pt1, addr, &addr);
  768. pt1_i2c_write_bit(pt1, addr, &addr, last);
  769. *addrp = addr;
  770. }
  771. static void pt1_i2c_prepare(struct pt1 *pt1, int addr, int *addrp)
  772. {
  773. pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
  774. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  775. pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, 0, addr + 3);
  776. *addrp = addr + 3;
  777. }
  778. static void
  779. pt1_i2c_write_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
  780. {
  781. int i;
  782. pt1_i2c_prepare(pt1, addr, &addr);
  783. pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1);
  784. for (i = 0; i < msg->len; i++)
  785. pt1_i2c_write_byte(pt1, addr, &addr, msg->buf[i]);
  786. *addrp = addr;
  787. }
  788. static void
  789. pt1_i2c_read_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
  790. {
  791. int i;
  792. pt1_i2c_prepare(pt1, addr, &addr);
  793. pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1 | 1);
  794. for (i = 0; i < msg->len; i++)
  795. pt1_i2c_read_byte(pt1, addr, &addr, i == msg->len - 1);
  796. *addrp = addr;
  797. }
  798. static int pt1_i2c_end(struct pt1 *pt1, int addr)
  799. {
  800. pt1_i2c_emit(pt1, addr, 1, 0, 0, 0, addr + 1);
  801. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  802. pt1_i2c_emit(pt1, addr + 2, 1, 0, 1, 1, 0);
  803. pt1_write_reg(pt1, 0, 0x00000004);
  804. do {
  805. if (signal_pending(current))
  806. return -EINTR;
  807. schedule_timeout_interruptible((HZ + 999) / 1000);
  808. } while (pt1_read_reg(pt1, 0) & 0x00000080);
  809. return 0;
  810. }
  811. static void pt1_i2c_begin(struct pt1 *pt1, int *addrp)
  812. {
  813. int addr;
  814. addr = 0;
  815. pt1_i2c_emit(pt1, addr, 0, 0, 1, 1, addr /* itself */);
  816. addr = addr + 1;
  817. if (!pt1->i2c_running) {
  818. pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
  819. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  820. addr = addr + 2;
  821. pt1->i2c_running = 1;
  822. }
  823. *addrp = addr;
  824. }
  825. static int pt1_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
  826. {
  827. struct pt1 *pt1;
  828. int i;
  829. struct i2c_msg *msg, *next_msg;
  830. int addr, ret;
  831. u16 len;
  832. u32 word;
  833. pt1 = i2c_get_adapdata(adap);
  834. for (i = 0; i < num; i++) {
  835. msg = &msgs[i];
  836. if (msg->flags & I2C_M_RD)
  837. return -ENOTSUPP;
  838. if (i + 1 < num)
  839. next_msg = &msgs[i + 1];
  840. else
  841. next_msg = NULL;
  842. if (next_msg && next_msg->flags & I2C_M_RD) {
  843. i++;
  844. len = next_msg->len;
  845. if (len > 4)
  846. return -ENOTSUPP;
  847. pt1_i2c_begin(pt1, &addr);
  848. pt1_i2c_write_msg(pt1, addr, &addr, msg);
  849. pt1_i2c_read_msg(pt1, addr, &addr, next_msg);
  850. ret = pt1_i2c_end(pt1, addr);
  851. if (ret < 0)
  852. return ret;
  853. word = pt1_read_reg(pt1, 2);
  854. while (len--) {
  855. next_msg->buf[len] = word;
  856. word >>= 8;
  857. }
  858. } else {
  859. pt1_i2c_begin(pt1, &addr);
  860. pt1_i2c_write_msg(pt1, addr, &addr, msg);
  861. ret = pt1_i2c_end(pt1, addr);
  862. if (ret < 0)
  863. return ret;
  864. }
  865. }
  866. return num;
  867. }
  868. static u32 pt1_i2c_func(struct i2c_adapter *adap)
  869. {
  870. return I2C_FUNC_I2C;
  871. }
  872. static const struct i2c_algorithm pt1_i2c_algo = {
  873. .master_xfer = pt1_i2c_xfer,
  874. .functionality = pt1_i2c_func,
  875. };
  876. static void pt1_i2c_wait(struct pt1 *pt1)
  877. {
  878. int i;
  879. for (i = 0; i < 128; i++)
  880. pt1_i2c_emit(pt1, 0, 0, 0, 1, 1, 0);
  881. }
  882. static void pt1_i2c_init(struct pt1 *pt1)
  883. {
  884. int i;
  885. for (i = 0; i < 1024; i++)
  886. pt1_i2c_emit(pt1, i, 0, 0, 1, 1, 0);
  887. }
  888. static void pt1_remove(struct pci_dev *pdev)
  889. {
  890. struct pt1 *pt1;
  891. void __iomem *regs;
  892. pt1 = pci_get_drvdata(pdev);
  893. regs = pt1->regs;
  894. if (pt1->kthread)
  895. kthread_stop(pt1->kthread);
  896. pt1_cleanup_tables(pt1);
  897. pt1_cleanup_frontends(pt1);
  898. pt1_disable_ram(pt1);
  899. pt1->power = 0;
  900. pt1->reset = 1;
  901. pt1_update_power(pt1);
  902. pt1_cleanup_adapters(pt1);
  903. i2c_del_adapter(&pt1->i2c_adap);
  904. kfree(pt1);
  905. pci_iounmap(pdev, regs);
  906. pci_release_regions(pdev);
  907. pci_disable_device(pdev);
  908. }
  909. static int pt1_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  910. {
  911. int ret;
  912. void __iomem *regs;
  913. struct pt1 *pt1;
  914. struct i2c_adapter *i2c_adap;
  915. ret = pci_enable_device(pdev);
  916. if (ret < 0)
  917. goto err;
  918. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  919. if (ret < 0)
  920. goto err_pci_disable_device;
  921. pci_set_master(pdev);
  922. ret = pci_request_regions(pdev, DRIVER_NAME);
  923. if (ret < 0)
  924. goto err_pci_disable_device;
  925. regs = pci_iomap(pdev, 0, 0);
  926. if (!regs) {
  927. ret = -EIO;
  928. goto err_pci_release_regions;
  929. }
  930. pt1 = kzalloc(sizeof(struct pt1), GFP_KERNEL);
  931. if (!pt1) {
  932. ret = -ENOMEM;
  933. goto err_pci_iounmap;
  934. }
  935. mutex_init(&pt1->lock);
  936. pt1->pdev = pdev;
  937. pt1->regs = regs;
  938. pci_set_drvdata(pdev, pt1);
  939. ret = pt1_init_adapters(pt1);
  940. if (ret < 0)
  941. goto err_kfree;
  942. mutex_init(&pt1->lock);
  943. pt1->power = 0;
  944. pt1->reset = 1;
  945. pt1_update_power(pt1);
  946. i2c_adap = &pt1->i2c_adap;
  947. i2c_adap->algo = &pt1_i2c_algo;
  948. i2c_adap->algo_data = NULL;
  949. i2c_adap->dev.parent = &pdev->dev;
  950. strcpy(i2c_adap->name, DRIVER_NAME);
  951. i2c_set_adapdata(i2c_adap, pt1);
  952. ret = i2c_add_adapter(i2c_adap);
  953. if (ret < 0)
  954. goto err_pt1_cleanup_adapters;
  955. pt1_i2c_init(pt1);
  956. pt1_i2c_wait(pt1);
  957. ret = pt1_sync(pt1);
  958. if (ret < 0)
  959. goto err_i2c_del_adapter;
  960. pt1_identify(pt1);
  961. ret = pt1_unlock(pt1);
  962. if (ret < 0)
  963. goto err_i2c_del_adapter;
  964. ret = pt1_reset_pci(pt1);
  965. if (ret < 0)
  966. goto err_i2c_del_adapter;
  967. ret = pt1_reset_ram(pt1);
  968. if (ret < 0)
  969. goto err_i2c_del_adapter;
  970. ret = pt1_enable_ram(pt1);
  971. if (ret < 0)
  972. goto err_i2c_del_adapter;
  973. pt1_init_streams(pt1);
  974. pt1->power = 1;
  975. pt1_update_power(pt1);
  976. schedule_timeout_uninterruptible((HZ + 49) / 50);
  977. pt1->reset = 0;
  978. pt1_update_power(pt1);
  979. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  980. ret = pt1_init_frontends(pt1);
  981. if (ret < 0)
  982. goto err_pt1_disable_ram;
  983. ret = pt1_init_tables(pt1);
  984. if (ret < 0)
  985. goto err_pt1_cleanup_frontends;
  986. return 0;
  987. err_pt1_cleanup_frontends:
  988. pt1_cleanup_frontends(pt1);
  989. err_pt1_disable_ram:
  990. pt1_disable_ram(pt1);
  991. pt1->power = 0;
  992. pt1->reset = 1;
  993. pt1_update_power(pt1);
  994. err_i2c_del_adapter:
  995. i2c_del_adapter(i2c_adap);
  996. err_pt1_cleanup_adapters:
  997. pt1_cleanup_adapters(pt1);
  998. err_kfree:
  999. kfree(pt1);
  1000. err_pci_iounmap:
  1001. pci_iounmap(pdev, regs);
  1002. err_pci_release_regions:
  1003. pci_release_regions(pdev);
  1004. err_pci_disable_device:
  1005. pci_disable_device(pdev);
  1006. err:
  1007. return ret;
  1008. }
  1009. static struct pci_device_id pt1_id_table[] = {
  1010. { PCI_DEVICE(0x10ee, 0x211a) },
  1011. { PCI_DEVICE(0x10ee, 0x222a) },
  1012. { },
  1013. };
  1014. MODULE_DEVICE_TABLE(pci, pt1_id_table);
  1015. static struct pci_driver pt1_driver = {
  1016. .name = DRIVER_NAME,
  1017. .probe = pt1_probe,
  1018. .remove = pt1_remove,
  1019. .id_table = pt1_id_table,
  1020. };
  1021. module_pci_driver(pt1_driver);
  1022. MODULE_AUTHOR("Takahito HIRANO <hiranotaka@zng.info>");
  1023. MODULE_DESCRIPTION("Earthsoft PT1/PT2 Driver");
  1024. MODULE_LICENSE("GPL");