pvrdma_main.c 32 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211
  1. /*
  2. * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of EITHER the GNU General Public License
  6. * version 2 as published by the Free Software Foundation or the BSD
  7. * 2-Clause License. This program is distributed in the hope that it
  8. * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
  9. * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
  10. * See the GNU General Public License version 2 for more details at
  11. * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program available in the file COPYING in the main
  15. * directory of this source tree.
  16. *
  17. * The BSD 2-Clause License
  18. *
  19. * Redistribution and use in source and binary forms, with or
  20. * without modification, are permitted provided that the following
  21. * conditions are met:
  22. *
  23. * - Redistributions of source code must retain the above
  24. * copyright notice, this list of conditions and the following
  25. * disclaimer.
  26. *
  27. * - Redistributions in binary form must reproduce the above
  28. * copyright notice, this list of conditions and the following
  29. * disclaimer in the documentation and/or other materials
  30. * provided with the distribution.
  31. *
  32. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  33. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  34. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  35. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  36. * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  37. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  38. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  39. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  40. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  41. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  42. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  43. * OF THE POSSIBILITY OF SUCH DAMAGE.
  44. */
  45. #include <linux/errno.h>
  46. #include <linux/inetdevice.h>
  47. #include <linux/init.h>
  48. #include <linux/module.h>
  49. #include <linux/slab.h>
  50. #include <rdma/ib_addr.h>
  51. #include <rdma/ib_smi.h>
  52. #include <rdma/ib_user_verbs.h>
  53. #include <net/addrconf.h>
  54. #include "pvrdma.h"
  55. #define DRV_NAME "vmw_pvrdma"
  56. #define DRV_VERSION "1.0.0.0-k"
  57. static DEFINE_MUTEX(pvrdma_device_list_lock);
  58. static LIST_HEAD(pvrdma_device_list);
  59. static struct workqueue_struct *event_wq;
  60. static int pvrdma_add_gid(struct ib_device *ibdev,
  61. u8 port_num,
  62. unsigned int index,
  63. const union ib_gid *gid,
  64. const struct ib_gid_attr *attr,
  65. void **context);
  66. static int pvrdma_del_gid(struct ib_device *ibdev,
  67. u8 port_num,
  68. unsigned int index,
  69. void **context);
  70. static ssize_t show_hca(struct device *device, struct device_attribute *attr,
  71. char *buf)
  72. {
  73. return sprintf(buf, "VMW_PVRDMA-%s\n", DRV_VERSION);
  74. }
  75. static ssize_t show_rev(struct device *device, struct device_attribute *attr,
  76. char *buf)
  77. {
  78. return sprintf(buf, "%d\n", PVRDMA_REV_ID);
  79. }
  80. static ssize_t show_board(struct device *device, struct device_attribute *attr,
  81. char *buf)
  82. {
  83. return sprintf(buf, "%d\n", PVRDMA_BOARD_ID);
  84. }
  85. static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
  86. static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
  87. static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
  88. static struct device_attribute *pvrdma_class_attributes[] = {
  89. &dev_attr_hw_rev,
  90. &dev_attr_hca_type,
  91. &dev_attr_board_id
  92. };
  93. static void pvrdma_get_fw_ver_str(struct ib_device *device, char *str,
  94. size_t str_len)
  95. {
  96. struct pvrdma_dev *dev =
  97. container_of(device, struct pvrdma_dev, ib_dev);
  98. snprintf(str, str_len, "%d.%d.%d\n",
  99. (int) (dev->dsr->caps.fw_ver >> 32),
  100. (int) (dev->dsr->caps.fw_ver >> 16) & 0xffff,
  101. (int) dev->dsr->caps.fw_ver & 0xffff);
  102. }
  103. static int pvrdma_init_device(struct pvrdma_dev *dev)
  104. {
  105. /* Initialize some device related stuff */
  106. spin_lock_init(&dev->cmd_lock);
  107. sema_init(&dev->cmd_sema, 1);
  108. atomic_set(&dev->num_qps, 0);
  109. atomic_set(&dev->num_cqs, 0);
  110. atomic_set(&dev->num_pds, 0);
  111. atomic_set(&dev->num_ahs, 0);
  112. return 0;
  113. }
  114. static int pvrdma_port_immutable(struct ib_device *ibdev, u8 port_num,
  115. struct ib_port_immutable *immutable)
  116. {
  117. struct ib_port_attr attr;
  118. int err;
  119. err = pvrdma_query_port(ibdev, port_num, &attr);
  120. if (err)
  121. return err;
  122. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  123. immutable->gid_tbl_len = attr.gid_tbl_len;
  124. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
  125. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  126. return 0;
  127. }
  128. static struct net_device *pvrdma_get_netdev(struct ib_device *ibdev,
  129. u8 port_num)
  130. {
  131. struct net_device *netdev;
  132. struct pvrdma_dev *dev = to_vdev(ibdev);
  133. if (port_num != 1)
  134. return NULL;
  135. rcu_read_lock();
  136. netdev = dev->netdev;
  137. if (netdev)
  138. dev_hold(netdev);
  139. rcu_read_unlock();
  140. return netdev;
  141. }
  142. static int pvrdma_register_device(struct pvrdma_dev *dev)
  143. {
  144. int ret = -1;
  145. int i = 0;
  146. strlcpy(dev->ib_dev.name, "vmw_pvrdma%d", IB_DEVICE_NAME_MAX);
  147. dev->ib_dev.node_guid = dev->dsr->caps.node_guid;
  148. dev->sys_image_guid = dev->dsr->caps.sys_image_guid;
  149. dev->flags = 0;
  150. dev->ib_dev.owner = THIS_MODULE;
  151. dev->ib_dev.num_comp_vectors = 1;
  152. dev->ib_dev.dma_device = &dev->pdev->dev;
  153. dev->ib_dev.uverbs_abi_ver = PVRDMA_UVERBS_ABI_VERSION;
  154. dev->ib_dev.uverbs_cmd_mask =
  155. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  156. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  157. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  158. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  159. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  160. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  161. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  162. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  163. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  164. (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
  165. (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
  166. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  167. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  168. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  169. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  170. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  171. (1ull << IB_USER_VERBS_CMD_POST_SEND) |
  172. (1ull << IB_USER_VERBS_CMD_POST_RECV) |
  173. (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
  174. (1ull << IB_USER_VERBS_CMD_DESTROY_AH);
  175. dev->ib_dev.node_type = RDMA_NODE_IB_CA;
  176. dev->ib_dev.phys_port_cnt = dev->dsr->caps.phys_port_cnt;
  177. dev->ib_dev.query_device = pvrdma_query_device;
  178. dev->ib_dev.query_port = pvrdma_query_port;
  179. dev->ib_dev.query_gid = pvrdma_query_gid;
  180. dev->ib_dev.query_pkey = pvrdma_query_pkey;
  181. dev->ib_dev.modify_port = pvrdma_modify_port;
  182. dev->ib_dev.alloc_ucontext = pvrdma_alloc_ucontext;
  183. dev->ib_dev.dealloc_ucontext = pvrdma_dealloc_ucontext;
  184. dev->ib_dev.mmap = pvrdma_mmap;
  185. dev->ib_dev.alloc_pd = pvrdma_alloc_pd;
  186. dev->ib_dev.dealloc_pd = pvrdma_dealloc_pd;
  187. dev->ib_dev.create_ah = pvrdma_create_ah;
  188. dev->ib_dev.destroy_ah = pvrdma_destroy_ah;
  189. dev->ib_dev.create_qp = pvrdma_create_qp;
  190. dev->ib_dev.modify_qp = pvrdma_modify_qp;
  191. dev->ib_dev.query_qp = pvrdma_query_qp;
  192. dev->ib_dev.destroy_qp = pvrdma_destroy_qp;
  193. dev->ib_dev.post_send = pvrdma_post_send;
  194. dev->ib_dev.post_recv = pvrdma_post_recv;
  195. dev->ib_dev.create_cq = pvrdma_create_cq;
  196. dev->ib_dev.modify_cq = pvrdma_modify_cq;
  197. dev->ib_dev.resize_cq = pvrdma_resize_cq;
  198. dev->ib_dev.destroy_cq = pvrdma_destroy_cq;
  199. dev->ib_dev.poll_cq = pvrdma_poll_cq;
  200. dev->ib_dev.req_notify_cq = pvrdma_req_notify_cq;
  201. dev->ib_dev.get_dma_mr = pvrdma_get_dma_mr;
  202. dev->ib_dev.reg_user_mr = pvrdma_reg_user_mr;
  203. dev->ib_dev.dereg_mr = pvrdma_dereg_mr;
  204. dev->ib_dev.alloc_mr = pvrdma_alloc_mr;
  205. dev->ib_dev.map_mr_sg = pvrdma_map_mr_sg;
  206. dev->ib_dev.add_gid = pvrdma_add_gid;
  207. dev->ib_dev.del_gid = pvrdma_del_gid;
  208. dev->ib_dev.get_netdev = pvrdma_get_netdev;
  209. dev->ib_dev.get_port_immutable = pvrdma_port_immutable;
  210. dev->ib_dev.get_link_layer = pvrdma_port_link_layer;
  211. dev->ib_dev.get_dev_fw_str = pvrdma_get_fw_ver_str;
  212. mutex_init(&dev->port_mutex);
  213. spin_lock_init(&dev->desc_lock);
  214. dev->cq_tbl = kcalloc(dev->dsr->caps.max_cq, sizeof(void *),
  215. GFP_KERNEL);
  216. if (!dev->cq_tbl)
  217. return ret;
  218. spin_lock_init(&dev->cq_tbl_lock);
  219. dev->qp_tbl = kcalloc(dev->dsr->caps.max_qp, sizeof(void *),
  220. GFP_KERNEL);
  221. if (!dev->qp_tbl)
  222. goto err_cq_free;
  223. spin_lock_init(&dev->qp_tbl_lock);
  224. ret = ib_register_device(&dev->ib_dev, NULL);
  225. if (ret)
  226. goto err_qp_free;
  227. for (i = 0; i < ARRAY_SIZE(pvrdma_class_attributes); ++i) {
  228. ret = device_create_file(&dev->ib_dev.dev,
  229. pvrdma_class_attributes[i]);
  230. if (ret)
  231. goto err_class;
  232. }
  233. dev->ib_active = true;
  234. return 0;
  235. err_class:
  236. ib_unregister_device(&dev->ib_dev);
  237. err_qp_free:
  238. kfree(dev->qp_tbl);
  239. err_cq_free:
  240. kfree(dev->cq_tbl);
  241. return ret;
  242. }
  243. static irqreturn_t pvrdma_intr0_handler(int irq, void *dev_id)
  244. {
  245. u32 icr = PVRDMA_INTR_CAUSE_RESPONSE;
  246. struct pvrdma_dev *dev = dev_id;
  247. dev_dbg(&dev->pdev->dev, "interrupt 0 (response) handler\n");
  248. if (dev->intr.type != PVRDMA_INTR_TYPE_MSIX) {
  249. /* Legacy intr */
  250. icr = pvrdma_read_reg(dev, PVRDMA_REG_ICR);
  251. if (icr == 0)
  252. return IRQ_NONE;
  253. }
  254. if (icr == PVRDMA_INTR_CAUSE_RESPONSE)
  255. complete(&dev->cmd_done);
  256. return IRQ_HANDLED;
  257. }
  258. static void pvrdma_qp_event(struct pvrdma_dev *dev, u32 qpn, int type)
  259. {
  260. struct pvrdma_qp *qp;
  261. unsigned long flags;
  262. spin_lock_irqsave(&dev->qp_tbl_lock, flags);
  263. qp = dev->qp_tbl[qpn % dev->dsr->caps.max_qp];
  264. if (qp)
  265. atomic_inc(&qp->refcnt);
  266. spin_unlock_irqrestore(&dev->qp_tbl_lock, flags);
  267. if (qp && qp->ibqp.event_handler) {
  268. struct ib_qp *ibqp = &qp->ibqp;
  269. struct ib_event e;
  270. e.device = ibqp->device;
  271. e.element.qp = ibqp;
  272. e.event = type; /* 1:1 mapping for now. */
  273. ibqp->event_handler(&e, ibqp->qp_context);
  274. }
  275. if (qp) {
  276. atomic_dec(&qp->refcnt);
  277. if (atomic_read(&qp->refcnt) == 0)
  278. wake_up(&qp->wait);
  279. }
  280. }
  281. static void pvrdma_cq_event(struct pvrdma_dev *dev, u32 cqn, int type)
  282. {
  283. struct pvrdma_cq *cq;
  284. unsigned long flags;
  285. spin_lock_irqsave(&dev->cq_tbl_lock, flags);
  286. cq = dev->cq_tbl[cqn % dev->dsr->caps.max_cq];
  287. if (cq)
  288. atomic_inc(&cq->refcnt);
  289. spin_unlock_irqrestore(&dev->cq_tbl_lock, flags);
  290. if (cq && cq->ibcq.event_handler) {
  291. struct ib_cq *ibcq = &cq->ibcq;
  292. struct ib_event e;
  293. e.device = ibcq->device;
  294. e.element.cq = ibcq;
  295. e.event = type; /* 1:1 mapping for now. */
  296. ibcq->event_handler(&e, ibcq->cq_context);
  297. }
  298. if (cq) {
  299. atomic_dec(&cq->refcnt);
  300. if (atomic_read(&cq->refcnt) == 0)
  301. wake_up(&cq->wait);
  302. }
  303. }
  304. static void pvrdma_dispatch_event(struct pvrdma_dev *dev, int port,
  305. enum ib_event_type event)
  306. {
  307. struct ib_event ib_event;
  308. memset(&ib_event, 0, sizeof(ib_event));
  309. ib_event.device = &dev->ib_dev;
  310. ib_event.element.port_num = port;
  311. ib_event.event = event;
  312. ib_dispatch_event(&ib_event);
  313. }
  314. static void pvrdma_dev_event(struct pvrdma_dev *dev, u8 port, int type)
  315. {
  316. if (port < 1 || port > dev->dsr->caps.phys_port_cnt) {
  317. dev_warn(&dev->pdev->dev, "event on port %d\n", port);
  318. return;
  319. }
  320. pvrdma_dispatch_event(dev, port, type);
  321. }
  322. static inline struct pvrdma_eqe *get_eqe(struct pvrdma_dev *dev, unsigned int i)
  323. {
  324. return (struct pvrdma_eqe *)pvrdma_page_dir_get_ptr(
  325. &dev->async_pdir,
  326. PAGE_SIZE +
  327. sizeof(struct pvrdma_eqe) * i);
  328. }
  329. static irqreturn_t pvrdma_intr1_handler(int irq, void *dev_id)
  330. {
  331. struct pvrdma_dev *dev = dev_id;
  332. struct pvrdma_ring *ring = &dev->async_ring_state->rx;
  333. int ring_slots = (dev->dsr->async_ring_pages.num_pages - 1) *
  334. PAGE_SIZE / sizeof(struct pvrdma_eqe);
  335. unsigned int head;
  336. dev_dbg(&dev->pdev->dev, "interrupt 1 (async event) handler\n");
  337. /*
  338. * Don't process events until the IB device is registered. Otherwise
  339. * we'll try to ib_dispatch_event() on an invalid device.
  340. */
  341. if (!dev->ib_active)
  342. return IRQ_HANDLED;
  343. while (pvrdma_idx_ring_has_data(ring, ring_slots, &head) > 0) {
  344. struct pvrdma_eqe *eqe;
  345. eqe = get_eqe(dev, head);
  346. switch (eqe->type) {
  347. case PVRDMA_EVENT_QP_FATAL:
  348. case PVRDMA_EVENT_QP_REQ_ERR:
  349. case PVRDMA_EVENT_QP_ACCESS_ERR:
  350. case PVRDMA_EVENT_COMM_EST:
  351. case PVRDMA_EVENT_SQ_DRAINED:
  352. case PVRDMA_EVENT_PATH_MIG:
  353. case PVRDMA_EVENT_PATH_MIG_ERR:
  354. case PVRDMA_EVENT_QP_LAST_WQE_REACHED:
  355. pvrdma_qp_event(dev, eqe->info, eqe->type);
  356. break;
  357. case PVRDMA_EVENT_CQ_ERR:
  358. pvrdma_cq_event(dev, eqe->info, eqe->type);
  359. break;
  360. case PVRDMA_EVENT_SRQ_ERR:
  361. case PVRDMA_EVENT_SRQ_LIMIT_REACHED:
  362. break;
  363. case PVRDMA_EVENT_PORT_ACTIVE:
  364. case PVRDMA_EVENT_PORT_ERR:
  365. case PVRDMA_EVENT_LID_CHANGE:
  366. case PVRDMA_EVENT_PKEY_CHANGE:
  367. case PVRDMA_EVENT_SM_CHANGE:
  368. case PVRDMA_EVENT_CLIENT_REREGISTER:
  369. case PVRDMA_EVENT_GID_CHANGE:
  370. pvrdma_dev_event(dev, eqe->info, eqe->type);
  371. break;
  372. case PVRDMA_EVENT_DEVICE_FATAL:
  373. pvrdma_dev_event(dev, 1, eqe->type);
  374. break;
  375. default:
  376. break;
  377. }
  378. pvrdma_idx_ring_inc(&ring->cons_head, ring_slots);
  379. }
  380. return IRQ_HANDLED;
  381. }
  382. static inline struct pvrdma_cqne *get_cqne(struct pvrdma_dev *dev,
  383. unsigned int i)
  384. {
  385. return (struct pvrdma_cqne *)pvrdma_page_dir_get_ptr(
  386. &dev->cq_pdir,
  387. PAGE_SIZE +
  388. sizeof(struct pvrdma_cqne) * i);
  389. }
  390. static irqreturn_t pvrdma_intrx_handler(int irq, void *dev_id)
  391. {
  392. struct pvrdma_dev *dev = dev_id;
  393. struct pvrdma_ring *ring = &dev->cq_ring_state->rx;
  394. int ring_slots = (dev->dsr->cq_ring_pages.num_pages - 1) * PAGE_SIZE /
  395. sizeof(struct pvrdma_cqne);
  396. unsigned int head;
  397. unsigned long flags;
  398. dev_dbg(&dev->pdev->dev, "interrupt x (completion) handler\n");
  399. while (pvrdma_idx_ring_has_data(ring, ring_slots, &head) > 0) {
  400. struct pvrdma_cqne *cqne;
  401. struct pvrdma_cq *cq;
  402. cqne = get_cqne(dev, head);
  403. spin_lock_irqsave(&dev->cq_tbl_lock, flags);
  404. cq = dev->cq_tbl[cqne->info % dev->dsr->caps.max_cq];
  405. if (cq)
  406. atomic_inc(&cq->refcnt);
  407. spin_unlock_irqrestore(&dev->cq_tbl_lock, flags);
  408. if (cq && cq->ibcq.comp_handler)
  409. cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
  410. if (cq) {
  411. atomic_dec(&cq->refcnt);
  412. if (atomic_read(&cq->refcnt))
  413. wake_up(&cq->wait);
  414. }
  415. pvrdma_idx_ring_inc(&ring->cons_head, ring_slots);
  416. }
  417. return IRQ_HANDLED;
  418. }
  419. static void pvrdma_disable_msi_all(struct pvrdma_dev *dev)
  420. {
  421. if (dev->intr.type == PVRDMA_INTR_TYPE_MSIX)
  422. pci_disable_msix(dev->pdev);
  423. else if (dev->intr.type == PVRDMA_INTR_TYPE_MSI)
  424. pci_disable_msi(dev->pdev);
  425. }
  426. static void pvrdma_free_irq(struct pvrdma_dev *dev)
  427. {
  428. int i;
  429. dev_dbg(&dev->pdev->dev, "freeing interrupts\n");
  430. if (dev->intr.type == PVRDMA_INTR_TYPE_MSIX) {
  431. for (i = 0; i < dev->intr.size; i++) {
  432. if (dev->intr.enabled[i]) {
  433. free_irq(dev->intr.msix_entry[i].vector, dev);
  434. dev->intr.enabled[i] = 0;
  435. }
  436. }
  437. } else if (dev->intr.type == PVRDMA_INTR_TYPE_INTX ||
  438. dev->intr.type == PVRDMA_INTR_TYPE_MSI) {
  439. free_irq(dev->pdev->irq, dev);
  440. }
  441. }
  442. static void pvrdma_enable_intrs(struct pvrdma_dev *dev)
  443. {
  444. dev_dbg(&dev->pdev->dev, "enable interrupts\n");
  445. pvrdma_write_reg(dev, PVRDMA_REG_IMR, 0);
  446. }
  447. static void pvrdma_disable_intrs(struct pvrdma_dev *dev)
  448. {
  449. dev_dbg(&dev->pdev->dev, "disable interrupts\n");
  450. pvrdma_write_reg(dev, PVRDMA_REG_IMR, ~0);
  451. }
  452. static int pvrdma_enable_msix(struct pci_dev *pdev, struct pvrdma_dev *dev)
  453. {
  454. int i;
  455. int ret;
  456. for (i = 0; i < PVRDMA_MAX_INTERRUPTS; i++) {
  457. dev->intr.msix_entry[i].entry = i;
  458. dev->intr.msix_entry[i].vector = i;
  459. switch (i) {
  460. case 0:
  461. /* CMD ring handler */
  462. dev->intr.handler[i] = pvrdma_intr0_handler;
  463. break;
  464. case 1:
  465. /* Async event ring handler */
  466. dev->intr.handler[i] = pvrdma_intr1_handler;
  467. break;
  468. default:
  469. /* Completion queue handler */
  470. dev->intr.handler[i] = pvrdma_intrx_handler;
  471. break;
  472. }
  473. }
  474. ret = pci_enable_msix(pdev, dev->intr.msix_entry,
  475. PVRDMA_MAX_INTERRUPTS);
  476. if (!ret) {
  477. dev->intr.type = PVRDMA_INTR_TYPE_MSIX;
  478. dev->intr.size = PVRDMA_MAX_INTERRUPTS;
  479. } else if (ret > 0) {
  480. ret = pci_enable_msix(pdev, dev->intr.msix_entry, ret);
  481. if (!ret) {
  482. dev->intr.type = PVRDMA_INTR_TYPE_MSIX;
  483. dev->intr.size = ret;
  484. } else {
  485. dev->intr.size = 0;
  486. }
  487. }
  488. dev_dbg(&pdev->dev, "using interrupt type %d, size %d\n",
  489. dev->intr.type, dev->intr.size);
  490. return ret;
  491. }
  492. static int pvrdma_alloc_intrs(struct pvrdma_dev *dev)
  493. {
  494. int ret = 0;
  495. int i;
  496. if (pci_find_capability(dev->pdev, PCI_CAP_ID_MSIX) &&
  497. pvrdma_enable_msix(dev->pdev, dev)) {
  498. /* Try MSI */
  499. ret = pci_enable_msi(dev->pdev);
  500. if (!ret) {
  501. dev->intr.type = PVRDMA_INTR_TYPE_MSI;
  502. } else {
  503. /* Legacy INTR */
  504. dev->intr.type = PVRDMA_INTR_TYPE_INTX;
  505. }
  506. }
  507. /* Request First IRQ */
  508. switch (dev->intr.type) {
  509. case PVRDMA_INTR_TYPE_INTX:
  510. case PVRDMA_INTR_TYPE_MSI:
  511. ret = request_irq(dev->pdev->irq, pvrdma_intr0_handler,
  512. IRQF_SHARED, DRV_NAME, dev);
  513. if (ret) {
  514. dev_err(&dev->pdev->dev,
  515. "failed to request interrupt\n");
  516. goto disable_msi;
  517. }
  518. break;
  519. case PVRDMA_INTR_TYPE_MSIX:
  520. ret = request_irq(dev->intr.msix_entry[0].vector,
  521. pvrdma_intr0_handler, 0, DRV_NAME, dev);
  522. if (ret) {
  523. dev_err(&dev->pdev->dev,
  524. "failed to request interrupt 0\n");
  525. goto disable_msi;
  526. }
  527. dev->intr.enabled[0] = 1;
  528. break;
  529. default:
  530. /* Not reached */
  531. break;
  532. }
  533. /* For MSIX: request intr for each vector */
  534. if (dev->intr.size > 1) {
  535. ret = request_irq(dev->intr.msix_entry[1].vector,
  536. pvrdma_intr1_handler, 0, DRV_NAME, dev);
  537. if (ret) {
  538. dev_err(&dev->pdev->dev,
  539. "failed to request interrupt 1\n");
  540. goto free_irq;
  541. }
  542. dev->intr.enabled[1] = 1;
  543. for (i = 2; i < dev->intr.size; i++) {
  544. ret = request_irq(dev->intr.msix_entry[i].vector,
  545. pvrdma_intrx_handler, 0,
  546. DRV_NAME, dev);
  547. if (ret) {
  548. dev_err(&dev->pdev->dev,
  549. "failed to request interrupt %d\n", i);
  550. goto free_irq;
  551. }
  552. dev->intr.enabled[i] = 1;
  553. }
  554. }
  555. return 0;
  556. free_irq:
  557. pvrdma_free_irq(dev);
  558. disable_msi:
  559. pvrdma_disable_msi_all(dev);
  560. return ret;
  561. }
  562. static void pvrdma_free_slots(struct pvrdma_dev *dev)
  563. {
  564. struct pci_dev *pdev = dev->pdev;
  565. if (dev->resp_slot)
  566. dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->resp_slot,
  567. dev->dsr->resp_slot_dma);
  568. if (dev->cmd_slot)
  569. dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->cmd_slot,
  570. dev->dsr->cmd_slot_dma);
  571. }
  572. static int pvrdma_add_gid_at_index(struct pvrdma_dev *dev,
  573. const union ib_gid *gid,
  574. int index)
  575. {
  576. int ret;
  577. union pvrdma_cmd_req req;
  578. struct pvrdma_cmd_create_bind *cmd_bind = &req.create_bind;
  579. if (!dev->sgid_tbl) {
  580. dev_warn(&dev->pdev->dev, "sgid table not initialized\n");
  581. return -EINVAL;
  582. }
  583. memset(cmd_bind, 0, sizeof(*cmd_bind));
  584. cmd_bind->hdr.cmd = PVRDMA_CMD_CREATE_BIND;
  585. memcpy(cmd_bind->new_gid, gid->raw, 16);
  586. cmd_bind->mtu = ib_mtu_enum_to_int(IB_MTU_1024);
  587. cmd_bind->vlan = 0xfff;
  588. cmd_bind->index = index;
  589. cmd_bind->gid_type = PVRDMA_GID_TYPE_FLAG_ROCE_V1;
  590. ret = pvrdma_cmd_post(dev, &req, NULL, 0);
  591. if (ret < 0) {
  592. dev_warn(&dev->pdev->dev,
  593. "could not create binding, error: %d\n", ret);
  594. return -EFAULT;
  595. }
  596. memcpy(&dev->sgid_tbl[index], gid, sizeof(*gid));
  597. return 0;
  598. }
  599. static int pvrdma_add_gid(struct ib_device *ibdev,
  600. u8 port_num,
  601. unsigned int index,
  602. const union ib_gid *gid,
  603. const struct ib_gid_attr *attr,
  604. void **context)
  605. {
  606. struct pvrdma_dev *dev = to_vdev(ibdev);
  607. return pvrdma_add_gid_at_index(dev, gid, index);
  608. }
  609. static int pvrdma_del_gid_at_index(struct pvrdma_dev *dev, int index)
  610. {
  611. int ret;
  612. union pvrdma_cmd_req req;
  613. struct pvrdma_cmd_destroy_bind *cmd_dest = &req.destroy_bind;
  614. /* Update sgid table. */
  615. if (!dev->sgid_tbl) {
  616. dev_warn(&dev->pdev->dev, "sgid table not initialized\n");
  617. return -EINVAL;
  618. }
  619. memset(cmd_dest, 0, sizeof(*cmd_dest));
  620. cmd_dest->hdr.cmd = PVRDMA_CMD_DESTROY_BIND;
  621. memcpy(cmd_dest->dest_gid, &dev->sgid_tbl[index], 16);
  622. cmd_dest->index = index;
  623. ret = pvrdma_cmd_post(dev, &req, NULL, 0);
  624. if (ret < 0) {
  625. dev_warn(&dev->pdev->dev,
  626. "could not destroy binding, error: %d\n", ret);
  627. return ret;
  628. }
  629. memset(&dev->sgid_tbl[index], 0, 16);
  630. return 0;
  631. }
  632. static int pvrdma_del_gid(struct ib_device *ibdev,
  633. u8 port_num,
  634. unsigned int index,
  635. void **context)
  636. {
  637. struct pvrdma_dev *dev = to_vdev(ibdev);
  638. dev_dbg(&dev->pdev->dev, "removing gid at index %u from %s",
  639. index, dev->netdev->name);
  640. return pvrdma_del_gid_at_index(dev, index);
  641. }
  642. static void pvrdma_netdevice_event_handle(struct pvrdma_dev *dev,
  643. unsigned long event)
  644. {
  645. switch (event) {
  646. case NETDEV_REBOOT:
  647. case NETDEV_DOWN:
  648. pvrdma_dispatch_event(dev, 1, IB_EVENT_PORT_ERR);
  649. break;
  650. case NETDEV_UP:
  651. pvrdma_dispatch_event(dev, 1, IB_EVENT_PORT_ACTIVE);
  652. break;
  653. default:
  654. dev_dbg(&dev->pdev->dev, "ignore netdevice event %ld on %s\n",
  655. event, dev->ib_dev.name);
  656. break;
  657. }
  658. }
  659. static void pvrdma_netdevice_event_work(struct work_struct *work)
  660. {
  661. struct pvrdma_netdevice_work *netdev_work;
  662. struct pvrdma_dev *dev;
  663. netdev_work = container_of(work, struct pvrdma_netdevice_work, work);
  664. mutex_lock(&pvrdma_device_list_lock);
  665. list_for_each_entry(dev, &pvrdma_device_list, device_link) {
  666. if (dev->netdev == netdev_work->event_netdev) {
  667. pvrdma_netdevice_event_handle(dev, netdev_work->event);
  668. break;
  669. }
  670. }
  671. mutex_unlock(&pvrdma_device_list_lock);
  672. kfree(netdev_work);
  673. }
  674. static int pvrdma_netdevice_event(struct notifier_block *this,
  675. unsigned long event, void *ptr)
  676. {
  677. struct net_device *event_netdev = netdev_notifier_info_to_dev(ptr);
  678. struct pvrdma_netdevice_work *netdev_work;
  679. netdev_work = kmalloc(sizeof(*netdev_work), GFP_ATOMIC);
  680. if (!netdev_work)
  681. return NOTIFY_BAD;
  682. INIT_WORK(&netdev_work->work, pvrdma_netdevice_event_work);
  683. netdev_work->event_netdev = event_netdev;
  684. netdev_work->event = event;
  685. queue_work(event_wq, &netdev_work->work);
  686. return NOTIFY_DONE;
  687. }
  688. static int pvrdma_pci_probe(struct pci_dev *pdev,
  689. const struct pci_device_id *id)
  690. {
  691. struct pci_dev *pdev_net;
  692. struct pvrdma_dev *dev;
  693. int ret;
  694. unsigned long start;
  695. unsigned long len;
  696. unsigned int version;
  697. dma_addr_t slot_dma = 0;
  698. dev_dbg(&pdev->dev, "initializing driver %s\n", pci_name(pdev));
  699. /* Allocate zero-out device */
  700. dev = (struct pvrdma_dev *)ib_alloc_device(sizeof(*dev));
  701. if (!dev) {
  702. dev_err(&pdev->dev, "failed to allocate IB device\n");
  703. return -ENOMEM;
  704. }
  705. mutex_lock(&pvrdma_device_list_lock);
  706. list_add(&dev->device_link, &pvrdma_device_list);
  707. mutex_unlock(&pvrdma_device_list_lock);
  708. ret = pvrdma_init_device(dev);
  709. if (ret)
  710. goto err_free_device;
  711. dev->pdev = pdev;
  712. pci_set_drvdata(pdev, dev);
  713. ret = pci_enable_device(pdev);
  714. if (ret) {
  715. dev_err(&pdev->dev, "cannot enable PCI device\n");
  716. goto err_free_device;
  717. }
  718. dev_dbg(&pdev->dev, "PCI resource flags BAR0 %#lx\n",
  719. pci_resource_flags(pdev, 0));
  720. dev_dbg(&pdev->dev, "PCI resource len %#llx\n",
  721. (unsigned long long)pci_resource_len(pdev, 0));
  722. dev_dbg(&pdev->dev, "PCI resource start %#llx\n",
  723. (unsigned long long)pci_resource_start(pdev, 0));
  724. dev_dbg(&pdev->dev, "PCI resource flags BAR1 %#lx\n",
  725. pci_resource_flags(pdev, 1));
  726. dev_dbg(&pdev->dev, "PCI resource len %#llx\n",
  727. (unsigned long long)pci_resource_len(pdev, 1));
  728. dev_dbg(&pdev->dev, "PCI resource start %#llx\n",
  729. (unsigned long long)pci_resource_start(pdev, 1));
  730. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  731. !(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
  732. dev_err(&pdev->dev, "PCI BAR region not MMIO\n");
  733. ret = -ENOMEM;
  734. goto err_free_device;
  735. }
  736. ret = pci_request_regions(pdev, DRV_NAME);
  737. if (ret) {
  738. dev_err(&pdev->dev, "cannot request PCI resources\n");
  739. goto err_disable_pdev;
  740. }
  741. /* Enable 64-Bit DMA */
  742. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
  743. ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
  744. if (ret != 0) {
  745. dev_err(&pdev->dev,
  746. "pci_set_consistent_dma_mask failed\n");
  747. goto err_free_resource;
  748. }
  749. } else {
  750. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  751. if (ret != 0) {
  752. dev_err(&pdev->dev,
  753. "pci_set_dma_mask failed\n");
  754. goto err_free_resource;
  755. }
  756. }
  757. pci_set_master(pdev);
  758. /* Map register space */
  759. start = pci_resource_start(dev->pdev, PVRDMA_PCI_RESOURCE_REG);
  760. len = pci_resource_len(dev->pdev, PVRDMA_PCI_RESOURCE_REG);
  761. dev->regs = ioremap(start, len);
  762. if (!dev->regs) {
  763. dev_err(&pdev->dev, "register mapping failed\n");
  764. ret = -ENOMEM;
  765. goto err_free_resource;
  766. }
  767. /* Setup per-device UAR. */
  768. dev->driver_uar.index = 0;
  769. dev->driver_uar.pfn =
  770. pci_resource_start(dev->pdev, PVRDMA_PCI_RESOURCE_UAR) >>
  771. PAGE_SHIFT;
  772. dev->driver_uar.map =
  773. ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  774. if (!dev->driver_uar.map) {
  775. dev_err(&pdev->dev, "failed to remap UAR pages\n");
  776. ret = -ENOMEM;
  777. goto err_unmap_regs;
  778. }
  779. version = pvrdma_read_reg(dev, PVRDMA_REG_VERSION);
  780. dev_info(&pdev->dev, "device version %d, driver version %d\n",
  781. version, PVRDMA_VERSION);
  782. if (version < PVRDMA_VERSION) {
  783. dev_err(&pdev->dev, "incompatible device version\n");
  784. goto err_uar_unmap;
  785. }
  786. dev->dsr = dma_alloc_coherent(&pdev->dev, sizeof(*dev->dsr),
  787. &dev->dsrbase, GFP_KERNEL);
  788. if (!dev->dsr) {
  789. dev_err(&pdev->dev, "failed to allocate shared region\n");
  790. ret = -ENOMEM;
  791. goto err_uar_unmap;
  792. }
  793. /* Setup the shared region */
  794. memset(dev->dsr, 0, sizeof(*dev->dsr));
  795. dev->dsr->driver_version = PVRDMA_VERSION;
  796. dev->dsr->gos_info.gos_bits = sizeof(void *) == 4 ?
  797. PVRDMA_GOS_BITS_32 :
  798. PVRDMA_GOS_BITS_64;
  799. dev->dsr->gos_info.gos_type = PVRDMA_GOS_TYPE_LINUX;
  800. dev->dsr->gos_info.gos_ver = 1;
  801. dev->dsr->uar_pfn = dev->driver_uar.pfn;
  802. /* Command slot. */
  803. dev->cmd_slot = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
  804. &slot_dma, GFP_KERNEL);
  805. if (!dev->cmd_slot) {
  806. ret = -ENOMEM;
  807. goto err_free_dsr;
  808. }
  809. dev->dsr->cmd_slot_dma = (u64)slot_dma;
  810. /* Response slot. */
  811. dev->resp_slot = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
  812. &slot_dma, GFP_KERNEL);
  813. if (!dev->resp_slot) {
  814. ret = -ENOMEM;
  815. goto err_free_slots;
  816. }
  817. dev->dsr->resp_slot_dma = (u64)slot_dma;
  818. /* Async event ring */
  819. dev->dsr->async_ring_pages.num_pages = 4;
  820. ret = pvrdma_page_dir_init(dev, &dev->async_pdir,
  821. dev->dsr->async_ring_pages.num_pages, true);
  822. if (ret)
  823. goto err_free_slots;
  824. dev->async_ring_state = dev->async_pdir.pages[0];
  825. dev->dsr->async_ring_pages.pdir_dma = dev->async_pdir.dir_dma;
  826. /* CQ notification ring */
  827. dev->dsr->cq_ring_pages.num_pages = 4;
  828. ret = pvrdma_page_dir_init(dev, &dev->cq_pdir,
  829. dev->dsr->cq_ring_pages.num_pages, true);
  830. if (ret)
  831. goto err_free_async_ring;
  832. dev->cq_ring_state = dev->cq_pdir.pages[0];
  833. dev->dsr->cq_ring_pages.pdir_dma = dev->cq_pdir.dir_dma;
  834. /*
  835. * Write the PA of the shared region to the device. The writes must be
  836. * ordered such that the high bits are written last. When the writes
  837. * complete, the device will have filled out the capabilities.
  838. */
  839. pvrdma_write_reg(dev, PVRDMA_REG_DSRLOW, (u32)dev->dsrbase);
  840. pvrdma_write_reg(dev, PVRDMA_REG_DSRHIGH,
  841. (u32)((u64)(dev->dsrbase) >> 32));
  842. /* Make sure the write is complete before reading status. */
  843. mb();
  844. /* Currently, the driver only supports RoCE mode. */
  845. if (dev->dsr->caps.mode != PVRDMA_DEVICE_MODE_ROCE) {
  846. dev_err(&pdev->dev, "unsupported transport %d\n",
  847. dev->dsr->caps.mode);
  848. ret = -EFAULT;
  849. goto err_free_cq_ring;
  850. }
  851. /* Currently, the driver only supports RoCE V1. */
  852. if (!(dev->dsr->caps.gid_types & PVRDMA_GID_TYPE_FLAG_ROCE_V1)) {
  853. dev_err(&pdev->dev, "driver needs RoCE v1 support\n");
  854. ret = -EFAULT;
  855. goto err_free_cq_ring;
  856. }
  857. /* Paired vmxnet3 will have same bus, slot. But func will be 0 */
  858. pdev_net = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
  859. if (!pdev_net) {
  860. dev_err(&pdev->dev, "failed to find paired net device\n");
  861. ret = -ENODEV;
  862. goto err_free_cq_ring;
  863. }
  864. if (pdev_net->vendor != PCI_VENDOR_ID_VMWARE ||
  865. pdev_net->device != PCI_DEVICE_ID_VMWARE_VMXNET3) {
  866. dev_err(&pdev->dev, "failed to find paired vmxnet3 device\n");
  867. pci_dev_put(pdev_net);
  868. ret = -ENODEV;
  869. goto err_free_cq_ring;
  870. }
  871. dev->netdev = pci_get_drvdata(pdev_net);
  872. pci_dev_put(pdev_net);
  873. if (!dev->netdev) {
  874. dev_err(&pdev->dev, "failed to get vmxnet3 device\n");
  875. ret = -ENODEV;
  876. goto err_free_cq_ring;
  877. }
  878. dev_info(&pdev->dev, "paired device to %s\n", dev->netdev->name);
  879. /* Interrupt setup */
  880. ret = pvrdma_alloc_intrs(dev);
  881. if (ret) {
  882. dev_err(&pdev->dev, "failed to allocate interrupts\n");
  883. ret = -ENOMEM;
  884. goto err_netdevice;
  885. }
  886. /* Allocate UAR table. */
  887. ret = pvrdma_uar_table_init(dev);
  888. if (ret) {
  889. dev_err(&pdev->dev, "failed to allocate UAR table\n");
  890. ret = -ENOMEM;
  891. goto err_free_intrs;
  892. }
  893. /* Allocate GID table */
  894. dev->sgid_tbl = kcalloc(dev->dsr->caps.gid_tbl_len,
  895. sizeof(union ib_gid), GFP_KERNEL);
  896. if (!dev->sgid_tbl) {
  897. ret = -ENOMEM;
  898. goto err_free_uar_table;
  899. }
  900. dev_dbg(&pdev->dev, "gid table len %d\n", dev->dsr->caps.gid_tbl_len);
  901. pvrdma_enable_intrs(dev);
  902. /* Activate pvrdma device */
  903. pvrdma_write_reg(dev, PVRDMA_REG_CTL, PVRDMA_DEVICE_CTL_ACTIVATE);
  904. /* Make sure the write is complete before reading status. */
  905. mb();
  906. /* Check if device was successfully activated */
  907. ret = pvrdma_read_reg(dev, PVRDMA_REG_ERR);
  908. if (ret != 0) {
  909. dev_err(&pdev->dev, "failed to activate device\n");
  910. ret = -EFAULT;
  911. goto err_disable_intr;
  912. }
  913. /* Register IB device */
  914. ret = pvrdma_register_device(dev);
  915. if (ret) {
  916. dev_err(&pdev->dev, "failed to register IB device\n");
  917. goto err_disable_intr;
  918. }
  919. dev->nb_netdev.notifier_call = pvrdma_netdevice_event;
  920. ret = register_netdevice_notifier(&dev->nb_netdev);
  921. if (ret) {
  922. dev_err(&pdev->dev, "failed to register netdevice events\n");
  923. goto err_unreg_ibdev;
  924. }
  925. dev_info(&pdev->dev, "attached to device\n");
  926. return 0;
  927. err_unreg_ibdev:
  928. ib_unregister_device(&dev->ib_dev);
  929. err_disable_intr:
  930. pvrdma_disable_intrs(dev);
  931. kfree(dev->sgid_tbl);
  932. err_free_uar_table:
  933. pvrdma_uar_table_cleanup(dev);
  934. err_free_intrs:
  935. pvrdma_free_irq(dev);
  936. pvrdma_disable_msi_all(dev);
  937. err_netdevice:
  938. unregister_netdevice_notifier(&dev->nb_netdev);
  939. err_free_cq_ring:
  940. pvrdma_page_dir_cleanup(dev, &dev->cq_pdir);
  941. err_free_async_ring:
  942. pvrdma_page_dir_cleanup(dev, &dev->async_pdir);
  943. err_free_slots:
  944. pvrdma_free_slots(dev);
  945. err_free_dsr:
  946. dma_free_coherent(&pdev->dev, sizeof(*dev->dsr), dev->dsr,
  947. dev->dsrbase);
  948. err_uar_unmap:
  949. iounmap(dev->driver_uar.map);
  950. err_unmap_regs:
  951. iounmap(dev->regs);
  952. err_free_resource:
  953. pci_release_regions(pdev);
  954. err_disable_pdev:
  955. pci_disable_device(pdev);
  956. pci_set_drvdata(pdev, NULL);
  957. err_free_device:
  958. mutex_lock(&pvrdma_device_list_lock);
  959. list_del(&dev->device_link);
  960. mutex_unlock(&pvrdma_device_list_lock);
  961. ib_dealloc_device(&dev->ib_dev);
  962. return ret;
  963. }
  964. static void pvrdma_pci_remove(struct pci_dev *pdev)
  965. {
  966. struct pvrdma_dev *dev = pci_get_drvdata(pdev);
  967. if (!dev)
  968. return;
  969. dev_info(&pdev->dev, "detaching from device\n");
  970. unregister_netdevice_notifier(&dev->nb_netdev);
  971. dev->nb_netdev.notifier_call = NULL;
  972. flush_workqueue(event_wq);
  973. /* Unregister ib device */
  974. ib_unregister_device(&dev->ib_dev);
  975. mutex_lock(&pvrdma_device_list_lock);
  976. list_del(&dev->device_link);
  977. mutex_unlock(&pvrdma_device_list_lock);
  978. pvrdma_disable_intrs(dev);
  979. pvrdma_free_irq(dev);
  980. pvrdma_disable_msi_all(dev);
  981. /* Deactivate pvrdma device */
  982. pvrdma_write_reg(dev, PVRDMA_REG_CTL, PVRDMA_DEVICE_CTL_RESET);
  983. pvrdma_page_dir_cleanup(dev, &dev->cq_pdir);
  984. pvrdma_page_dir_cleanup(dev, &dev->async_pdir);
  985. pvrdma_free_slots(dev);
  986. iounmap(dev->regs);
  987. kfree(dev->sgid_tbl);
  988. kfree(dev->cq_tbl);
  989. kfree(dev->qp_tbl);
  990. pvrdma_uar_table_cleanup(dev);
  991. iounmap(dev->driver_uar.map);
  992. ib_dealloc_device(&dev->ib_dev);
  993. /* Free pci resources */
  994. pci_release_regions(pdev);
  995. pci_disable_device(pdev);
  996. pci_set_drvdata(pdev, NULL);
  997. }
  998. static struct pci_device_id pvrdma_pci_table[] = {
  999. { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, PCI_DEVICE_ID_VMWARE_PVRDMA), },
  1000. { 0 },
  1001. };
  1002. MODULE_DEVICE_TABLE(pci, pvrdma_pci_table);
  1003. static struct pci_driver pvrdma_driver = {
  1004. .name = DRV_NAME,
  1005. .id_table = pvrdma_pci_table,
  1006. .probe = pvrdma_pci_probe,
  1007. .remove = pvrdma_pci_remove,
  1008. };
  1009. static int __init pvrdma_init(void)
  1010. {
  1011. int err;
  1012. event_wq = alloc_ordered_workqueue("pvrdma_event_wq", WQ_MEM_RECLAIM);
  1013. if (!event_wq)
  1014. return -ENOMEM;
  1015. err = pci_register_driver(&pvrdma_driver);
  1016. if (err)
  1017. destroy_workqueue(event_wq);
  1018. return err;
  1019. }
  1020. static void __exit pvrdma_cleanup(void)
  1021. {
  1022. pci_unregister_driver(&pvrdma_driver);
  1023. destroy_workqueue(event_wq);
  1024. }
  1025. module_init(pvrdma_init);
  1026. module_exit(pvrdma_cleanup);
  1027. MODULE_AUTHOR("VMware, Inc");
  1028. MODULE_DESCRIPTION("VMware Paravirtual RDMA driver");
  1029. MODULE_VERSION(DRV_VERSION);
  1030. MODULE_LICENSE("Dual BSD/GPL");