i40iw_verbs.c 78 KB

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  1. /*******************************************************************************
  2. *
  3. * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenFabrics.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. *
  33. *******************************************************************************/
  34. #include <linux/module.h>
  35. #include <linux/moduleparam.h>
  36. #include <linux/random.h>
  37. #include <linux/highmem.h>
  38. #include <linux/time.h>
  39. #include <linux/hugetlb.h>
  40. #include <asm/byteorder.h>
  41. #include <net/ip.h>
  42. #include <rdma/ib_verbs.h>
  43. #include <rdma/iw_cm.h>
  44. #include <rdma/ib_user_verbs.h>
  45. #include <rdma/ib_umem.h>
  46. #include "i40iw.h"
  47. /**
  48. * i40iw_query_device - get device attributes
  49. * @ibdev: device pointer from stack
  50. * @props: returning device attributes
  51. * @udata: user data
  52. */
  53. static int i40iw_query_device(struct ib_device *ibdev,
  54. struct ib_device_attr *props,
  55. struct ib_udata *udata)
  56. {
  57. struct i40iw_device *iwdev = to_iwdev(ibdev);
  58. if (udata->inlen || udata->outlen)
  59. return -EINVAL;
  60. memset(props, 0, sizeof(*props));
  61. ether_addr_copy((u8 *)&props->sys_image_guid, iwdev->netdev->dev_addr);
  62. props->fw_ver = I40IW_FW_VERSION;
  63. props->device_cap_flags = iwdev->device_cap_flags;
  64. props->vendor_id = iwdev->ldev->pcidev->vendor;
  65. props->vendor_part_id = iwdev->ldev->pcidev->device;
  66. props->hw_ver = (u32)iwdev->sc_dev.hw_rev;
  67. props->max_mr_size = I40IW_MAX_OUTBOUND_MESSAGE_SIZE;
  68. props->max_qp = iwdev->max_qp - iwdev->used_qps;
  69. props->max_qp_wr = (I40IW_MAX_WQ_ENTRIES >> 2) - 1;
  70. props->max_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
  71. props->max_cq = iwdev->max_cq - iwdev->used_cqs;
  72. props->max_cqe = iwdev->max_cqe;
  73. props->max_mr = iwdev->max_mr - iwdev->used_mrs;
  74. props->max_pd = iwdev->max_pd - iwdev->used_pds;
  75. props->max_sge_rd = I40IW_MAX_SGE_RD;
  76. props->max_qp_rd_atom = I40IW_MAX_IRD_SIZE;
  77. props->max_qp_init_rd_atom = props->max_qp_rd_atom;
  78. props->atomic_cap = IB_ATOMIC_NONE;
  79. props->max_map_per_fmr = 1;
  80. props->max_fast_reg_page_list_len = I40IW_MAX_PAGES_PER_FMR;
  81. return 0;
  82. }
  83. /**
  84. * i40iw_query_port - get port attrubutes
  85. * @ibdev: device pointer from stack
  86. * @port: port number for query
  87. * @props: returning device attributes
  88. */
  89. static int i40iw_query_port(struct ib_device *ibdev,
  90. u8 port,
  91. struct ib_port_attr *props)
  92. {
  93. struct i40iw_device *iwdev = to_iwdev(ibdev);
  94. struct net_device *netdev = iwdev->netdev;
  95. memset(props, 0, sizeof(*props));
  96. props->max_mtu = IB_MTU_4096;
  97. if (netdev->mtu >= 4096)
  98. props->active_mtu = IB_MTU_4096;
  99. else if (netdev->mtu >= 2048)
  100. props->active_mtu = IB_MTU_2048;
  101. else if (netdev->mtu >= 1024)
  102. props->active_mtu = IB_MTU_1024;
  103. else if (netdev->mtu >= 512)
  104. props->active_mtu = IB_MTU_512;
  105. else
  106. props->active_mtu = IB_MTU_256;
  107. props->lid = 1;
  108. if (netif_carrier_ok(iwdev->netdev))
  109. props->state = IB_PORT_ACTIVE;
  110. else
  111. props->state = IB_PORT_DOWN;
  112. props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
  113. IB_PORT_VENDOR_CLASS_SUP | IB_PORT_BOOT_MGMT_SUP;
  114. props->gid_tbl_len = 1;
  115. props->pkey_tbl_len = 1;
  116. props->active_width = IB_WIDTH_4X;
  117. props->active_speed = 1;
  118. props->max_msg_sz = I40IW_MAX_OUTBOUND_MESSAGE_SIZE;
  119. return 0;
  120. }
  121. /**
  122. * i40iw_alloc_ucontext - Allocate the user context data structure
  123. * @ibdev: device pointer from stack
  124. * @udata: user data
  125. *
  126. * This keeps track of all objects associated with a particular
  127. * user-mode client.
  128. */
  129. static struct ib_ucontext *i40iw_alloc_ucontext(struct ib_device *ibdev,
  130. struct ib_udata *udata)
  131. {
  132. struct i40iw_device *iwdev = to_iwdev(ibdev);
  133. struct i40iw_alloc_ucontext_req req;
  134. struct i40iw_alloc_ucontext_resp uresp;
  135. struct i40iw_ucontext *ucontext;
  136. if (ib_copy_from_udata(&req, udata, sizeof(req)))
  137. return ERR_PTR(-EINVAL);
  138. if (req.userspace_ver < 4 || req.userspace_ver > I40IW_ABI_VER) {
  139. i40iw_pr_err("Unsupported provider library version %u.\n", req.userspace_ver);
  140. return ERR_PTR(-EINVAL);
  141. }
  142. memset(&uresp, 0, sizeof(uresp));
  143. uresp.max_qps = iwdev->max_qp;
  144. uresp.max_pds = iwdev->max_pd;
  145. uresp.wq_size = iwdev->max_qp_wr * 2;
  146. uresp.kernel_ver = req.userspace_ver;
  147. ucontext = kzalloc(sizeof(*ucontext), GFP_KERNEL);
  148. if (!ucontext)
  149. return ERR_PTR(-ENOMEM);
  150. ucontext->iwdev = iwdev;
  151. ucontext->abi_ver = req.userspace_ver;
  152. if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) {
  153. kfree(ucontext);
  154. return ERR_PTR(-EFAULT);
  155. }
  156. INIT_LIST_HEAD(&ucontext->cq_reg_mem_list);
  157. spin_lock_init(&ucontext->cq_reg_mem_list_lock);
  158. INIT_LIST_HEAD(&ucontext->qp_reg_mem_list);
  159. spin_lock_init(&ucontext->qp_reg_mem_list_lock);
  160. return &ucontext->ibucontext;
  161. }
  162. /**
  163. * i40iw_dealloc_ucontext - deallocate the user context data structure
  164. * @context: user context created during alloc
  165. */
  166. static int i40iw_dealloc_ucontext(struct ib_ucontext *context)
  167. {
  168. struct i40iw_ucontext *ucontext = to_ucontext(context);
  169. unsigned long flags;
  170. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  171. if (!list_empty(&ucontext->cq_reg_mem_list)) {
  172. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  173. return -EBUSY;
  174. }
  175. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  176. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  177. if (!list_empty(&ucontext->qp_reg_mem_list)) {
  178. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  179. return -EBUSY;
  180. }
  181. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  182. kfree(ucontext);
  183. return 0;
  184. }
  185. /**
  186. * i40iw_mmap - user memory map
  187. * @context: context created during alloc
  188. * @vma: kernel info for user memory map
  189. */
  190. static int i40iw_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  191. {
  192. struct i40iw_ucontext *ucontext;
  193. u64 db_addr_offset;
  194. u64 push_offset;
  195. ucontext = to_ucontext(context);
  196. if (ucontext->iwdev->sc_dev.is_pf) {
  197. db_addr_offset = I40IW_DB_ADDR_OFFSET;
  198. push_offset = I40IW_PUSH_OFFSET;
  199. if (vma->vm_pgoff)
  200. vma->vm_pgoff += I40IW_PF_FIRST_PUSH_PAGE_INDEX - 1;
  201. } else {
  202. db_addr_offset = I40IW_VF_DB_ADDR_OFFSET;
  203. push_offset = I40IW_VF_PUSH_OFFSET;
  204. if (vma->vm_pgoff)
  205. vma->vm_pgoff += I40IW_VF_FIRST_PUSH_PAGE_INDEX - 1;
  206. }
  207. vma->vm_pgoff += db_addr_offset >> PAGE_SHIFT;
  208. if (vma->vm_pgoff == (db_addr_offset >> PAGE_SHIFT)) {
  209. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  210. vma->vm_private_data = ucontext;
  211. } else {
  212. if ((vma->vm_pgoff - (push_offset >> PAGE_SHIFT)) % 2)
  213. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  214. else
  215. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  216. }
  217. if (io_remap_pfn_range(vma, vma->vm_start,
  218. vma->vm_pgoff + (pci_resource_start(ucontext->iwdev->ldev->pcidev, 0) >> PAGE_SHIFT),
  219. PAGE_SIZE, vma->vm_page_prot))
  220. return -EAGAIN;
  221. return 0;
  222. }
  223. /**
  224. * i40iw_alloc_push_page - allocate a push page for qp
  225. * @iwdev: iwarp device
  226. * @qp: hardware control qp
  227. */
  228. static void i40iw_alloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp *qp)
  229. {
  230. struct i40iw_cqp_request *cqp_request;
  231. struct cqp_commands_info *cqp_info;
  232. enum i40iw_status_code status;
  233. if (qp->push_idx != I40IW_INVALID_PUSH_PAGE_INDEX)
  234. return;
  235. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  236. if (!cqp_request)
  237. return;
  238. atomic_inc(&cqp_request->refcount);
  239. cqp_info = &cqp_request->info;
  240. cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE;
  241. cqp_info->post_sq = 1;
  242. cqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle;
  243. cqp_info->in.u.manage_push_page.info.free_page = 0;
  244. cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp;
  245. cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
  246. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  247. if (!status)
  248. qp->push_idx = cqp_request->compl_info.op_ret_val;
  249. else
  250. i40iw_pr_err("CQP-OP Push page fail");
  251. i40iw_put_cqp_request(&iwdev->cqp, cqp_request);
  252. }
  253. /**
  254. * i40iw_dealloc_push_page - free a push page for qp
  255. * @iwdev: iwarp device
  256. * @qp: hardware control qp
  257. */
  258. static void i40iw_dealloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp *qp)
  259. {
  260. struct i40iw_cqp_request *cqp_request;
  261. struct cqp_commands_info *cqp_info;
  262. enum i40iw_status_code status;
  263. if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX)
  264. return;
  265. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, false);
  266. if (!cqp_request)
  267. return;
  268. cqp_info = &cqp_request->info;
  269. cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE;
  270. cqp_info->post_sq = 1;
  271. cqp_info->in.u.manage_push_page.info.push_idx = qp->push_idx;
  272. cqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle;
  273. cqp_info->in.u.manage_push_page.info.free_page = 1;
  274. cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp;
  275. cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
  276. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  277. if (!status)
  278. qp->push_idx = I40IW_INVALID_PUSH_PAGE_INDEX;
  279. else
  280. i40iw_pr_err("CQP-OP Push page fail");
  281. }
  282. /**
  283. * i40iw_alloc_pd - allocate protection domain
  284. * @ibdev: device pointer from stack
  285. * @context: user context created during alloc
  286. * @udata: user data
  287. */
  288. static struct ib_pd *i40iw_alloc_pd(struct ib_device *ibdev,
  289. struct ib_ucontext *context,
  290. struct ib_udata *udata)
  291. {
  292. struct i40iw_pd *iwpd;
  293. struct i40iw_device *iwdev = to_iwdev(ibdev);
  294. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  295. struct i40iw_alloc_pd_resp uresp;
  296. struct i40iw_sc_pd *sc_pd;
  297. struct i40iw_ucontext *ucontext;
  298. u32 pd_id = 0;
  299. int err;
  300. if (iwdev->closing)
  301. return ERR_PTR(-ENODEV);
  302. err = i40iw_alloc_resource(iwdev, iwdev->allocated_pds,
  303. iwdev->max_pd, &pd_id, &iwdev->next_pd);
  304. if (err) {
  305. i40iw_pr_err("alloc resource failed\n");
  306. return ERR_PTR(err);
  307. }
  308. iwpd = kzalloc(sizeof(*iwpd), GFP_KERNEL);
  309. if (!iwpd) {
  310. err = -ENOMEM;
  311. goto free_res;
  312. }
  313. sc_pd = &iwpd->sc_pd;
  314. if (context) {
  315. ucontext = to_ucontext(context);
  316. dev->iw_pd_ops->pd_init(dev, sc_pd, pd_id, ucontext->abi_ver);
  317. memset(&uresp, 0, sizeof(uresp));
  318. uresp.pd_id = pd_id;
  319. if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) {
  320. err = -EFAULT;
  321. goto error;
  322. }
  323. } else {
  324. dev->iw_pd_ops->pd_init(dev, sc_pd, pd_id, -1);
  325. }
  326. i40iw_add_pdusecount(iwpd);
  327. return &iwpd->ibpd;
  328. error:
  329. kfree(iwpd);
  330. free_res:
  331. i40iw_free_resource(iwdev, iwdev->allocated_pds, pd_id);
  332. return ERR_PTR(err);
  333. }
  334. /**
  335. * i40iw_dealloc_pd - deallocate pd
  336. * @ibpd: ptr of pd to be deallocated
  337. */
  338. static int i40iw_dealloc_pd(struct ib_pd *ibpd)
  339. {
  340. struct i40iw_pd *iwpd = to_iwpd(ibpd);
  341. struct i40iw_device *iwdev = to_iwdev(ibpd->device);
  342. i40iw_rem_pdusecount(iwpd, iwdev);
  343. return 0;
  344. }
  345. /**
  346. * i40iw_qp_roundup - return round up qp ring size
  347. * @wr_ring_size: ring size to round up
  348. */
  349. static int i40iw_qp_roundup(u32 wr_ring_size)
  350. {
  351. int scount = 1;
  352. if (wr_ring_size < I40IWQP_SW_MIN_WQSIZE)
  353. wr_ring_size = I40IWQP_SW_MIN_WQSIZE;
  354. for (wr_ring_size--; scount <= 16; scount *= 2)
  355. wr_ring_size |= wr_ring_size >> scount;
  356. return ++wr_ring_size;
  357. }
  358. /**
  359. * i40iw_get_pbl - Retrieve pbl from a list given a virtual
  360. * address
  361. * @va: user virtual address
  362. * @pbl_list: pbl list to search in (QP's or CQ's)
  363. */
  364. static struct i40iw_pbl *i40iw_get_pbl(unsigned long va,
  365. struct list_head *pbl_list)
  366. {
  367. struct i40iw_pbl *iwpbl;
  368. list_for_each_entry(iwpbl, pbl_list, list) {
  369. if (iwpbl->user_base == va) {
  370. list_del(&iwpbl->list);
  371. return iwpbl;
  372. }
  373. }
  374. return NULL;
  375. }
  376. /**
  377. * i40iw_free_qp_resources - free up memory resources for qp
  378. * @iwdev: iwarp device
  379. * @iwqp: qp ptr (user or kernel)
  380. * @qp_num: qp number assigned
  381. */
  382. void i40iw_free_qp_resources(struct i40iw_device *iwdev,
  383. struct i40iw_qp *iwqp,
  384. u32 qp_num)
  385. {
  386. i40iw_dealloc_push_page(iwdev, &iwqp->sc_qp);
  387. if (qp_num)
  388. i40iw_free_resource(iwdev, iwdev->allocated_qps, qp_num);
  389. i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->q2_ctx_mem);
  390. i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->kqp.dma_mem);
  391. kfree(iwqp->kqp.wrid_mem);
  392. iwqp->kqp.wrid_mem = NULL;
  393. kfree(iwqp->allocated_buffer);
  394. }
  395. /**
  396. * i40iw_clean_cqes - clean cq entries for qp
  397. * @iwqp: qp ptr (user or kernel)
  398. * @iwcq: cq ptr
  399. */
  400. static void i40iw_clean_cqes(struct i40iw_qp *iwqp, struct i40iw_cq *iwcq)
  401. {
  402. struct i40iw_cq_uk *ukcq = &iwcq->sc_cq.cq_uk;
  403. ukcq->ops.iw_cq_clean(&iwqp->sc_qp.qp_uk, ukcq);
  404. }
  405. /**
  406. * i40iw_destroy_qp - destroy qp
  407. * @ibqp: qp's ib pointer also to get to device's qp address
  408. */
  409. static int i40iw_destroy_qp(struct ib_qp *ibqp)
  410. {
  411. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  412. iwqp->destroyed = 1;
  413. if (iwqp->ibqp_state >= IB_QPS_INIT && iwqp->ibqp_state < IB_QPS_RTS)
  414. i40iw_next_iw_state(iwqp, I40IW_QP_STATE_ERROR, 0, 0, 0);
  415. if (!iwqp->user_mode) {
  416. if (iwqp->iwscq) {
  417. i40iw_clean_cqes(iwqp, iwqp->iwscq);
  418. if (iwqp->iwrcq != iwqp->iwscq)
  419. i40iw_clean_cqes(iwqp, iwqp->iwrcq);
  420. }
  421. }
  422. i40iw_rem_ref(&iwqp->ibqp);
  423. return 0;
  424. }
  425. /**
  426. * i40iw_setup_virt_qp - setup for allocation of virtual qp
  427. * @dev: iwarp device
  428. * @qp: qp ptr
  429. * @init_info: initialize info to return
  430. */
  431. static int i40iw_setup_virt_qp(struct i40iw_device *iwdev,
  432. struct i40iw_qp *iwqp,
  433. struct i40iw_qp_init_info *init_info)
  434. {
  435. struct i40iw_pbl *iwpbl = iwqp->iwpbl;
  436. struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr;
  437. iwqp->page = qpmr->sq_page;
  438. init_info->shadow_area_pa = cpu_to_le64(qpmr->shadow);
  439. if (iwpbl->pbl_allocated) {
  440. init_info->virtual_map = true;
  441. init_info->sq_pa = qpmr->sq_pbl.idx;
  442. init_info->rq_pa = qpmr->rq_pbl.idx;
  443. } else {
  444. init_info->sq_pa = qpmr->sq_pbl.addr;
  445. init_info->rq_pa = qpmr->rq_pbl.addr;
  446. }
  447. return 0;
  448. }
  449. /**
  450. * i40iw_setup_kmode_qp - setup initialization for kernel mode qp
  451. * @iwdev: iwarp device
  452. * @iwqp: qp ptr (user or kernel)
  453. * @info: initialize info to return
  454. */
  455. static int i40iw_setup_kmode_qp(struct i40iw_device *iwdev,
  456. struct i40iw_qp *iwqp,
  457. struct i40iw_qp_init_info *info)
  458. {
  459. struct i40iw_dma_mem *mem = &iwqp->kqp.dma_mem;
  460. u32 sqdepth, rqdepth;
  461. u32 sq_size, rq_size;
  462. u8 sqshift;
  463. u32 size;
  464. enum i40iw_status_code status;
  465. struct i40iw_qp_uk_init_info *ukinfo = &info->qp_uk_init_info;
  466. sq_size = i40iw_qp_roundup(ukinfo->sq_size + 1);
  467. rq_size = i40iw_qp_roundup(ukinfo->rq_size + 1);
  468. status = i40iw_get_wqe_shift(sq_size, ukinfo->max_sq_frag_cnt, ukinfo->max_inline_data, &sqshift);
  469. if (status)
  470. return -ENOMEM;
  471. sqdepth = sq_size << sqshift;
  472. rqdepth = rq_size << I40IW_MAX_RQ_WQE_SHIFT;
  473. size = sqdepth * sizeof(struct i40iw_sq_uk_wr_trk_info) + (rqdepth << 3);
  474. iwqp->kqp.wrid_mem = kzalloc(size, GFP_KERNEL);
  475. ukinfo->sq_wrtrk_array = (struct i40iw_sq_uk_wr_trk_info *)iwqp->kqp.wrid_mem;
  476. if (!ukinfo->sq_wrtrk_array)
  477. return -ENOMEM;
  478. ukinfo->rq_wrid_array = (u64 *)&ukinfo->sq_wrtrk_array[sqdepth];
  479. size = (sqdepth + rqdepth) * I40IW_QP_WQE_MIN_SIZE;
  480. size += (I40IW_SHADOW_AREA_SIZE << 3);
  481. status = i40iw_allocate_dma_mem(iwdev->sc_dev.hw, mem, size, 256);
  482. if (status) {
  483. kfree(ukinfo->sq_wrtrk_array);
  484. ukinfo->sq_wrtrk_array = NULL;
  485. return -ENOMEM;
  486. }
  487. ukinfo->sq = mem->va;
  488. info->sq_pa = mem->pa;
  489. ukinfo->rq = &ukinfo->sq[sqdepth];
  490. info->rq_pa = info->sq_pa + (sqdepth * I40IW_QP_WQE_MIN_SIZE);
  491. ukinfo->shadow_area = ukinfo->rq[rqdepth].elem;
  492. info->shadow_area_pa = info->rq_pa + (rqdepth * I40IW_QP_WQE_MIN_SIZE);
  493. ukinfo->sq_size = sq_size;
  494. ukinfo->rq_size = rq_size;
  495. ukinfo->qp_id = iwqp->ibqp.qp_num;
  496. return 0;
  497. }
  498. /**
  499. * i40iw_create_qp - create qp
  500. * @ibpd: ptr of pd
  501. * @init_attr: attributes for qp
  502. * @udata: user data for create qp
  503. */
  504. static struct ib_qp *i40iw_create_qp(struct ib_pd *ibpd,
  505. struct ib_qp_init_attr *init_attr,
  506. struct ib_udata *udata)
  507. {
  508. struct i40iw_pd *iwpd = to_iwpd(ibpd);
  509. struct i40iw_device *iwdev = to_iwdev(ibpd->device);
  510. struct i40iw_cqp *iwcqp = &iwdev->cqp;
  511. struct i40iw_qp *iwqp;
  512. struct i40iw_ucontext *ucontext;
  513. struct i40iw_create_qp_req req;
  514. struct i40iw_create_qp_resp uresp;
  515. u32 qp_num = 0;
  516. void *mem;
  517. enum i40iw_status_code ret;
  518. int err_code;
  519. int sq_size;
  520. int rq_size;
  521. struct i40iw_sc_qp *qp;
  522. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  523. struct i40iw_qp_init_info init_info;
  524. struct i40iw_create_qp_info *qp_info;
  525. struct i40iw_cqp_request *cqp_request;
  526. struct cqp_commands_info *cqp_info;
  527. struct i40iw_qp_host_ctx_info *ctx_info;
  528. struct i40iwarp_offload_info *iwarp_info;
  529. unsigned long flags;
  530. if (iwdev->closing)
  531. return ERR_PTR(-ENODEV);
  532. if (init_attr->create_flags)
  533. return ERR_PTR(-EINVAL);
  534. if (init_attr->cap.max_inline_data > I40IW_MAX_INLINE_DATA_SIZE)
  535. init_attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
  536. if (init_attr->cap.max_send_sge > I40IW_MAX_WQ_FRAGMENT_COUNT)
  537. init_attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
  538. if (init_attr->cap.max_recv_sge > I40IW_MAX_WQ_FRAGMENT_COUNT)
  539. init_attr->cap.max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
  540. memset(&init_info, 0, sizeof(init_info));
  541. sq_size = init_attr->cap.max_send_wr;
  542. rq_size = init_attr->cap.max_recv_wr;
  543. init_info.vsi = &iwdev->vsi;
  544. init_info.qp_uk_init_info.sq_size = sq_size;
  545. init_info.qp_uk_init_info.rq_size = rq_size;
  546. init_info.qp_uk_init_info.max_sq_frag_cnt = init_attr->cap.max_send_sge;
  547. init_info.qp_uk_init_info.max_rq_frag_cnt = init_attr->cap.max_recv_sge;
  548. init_info.qp_uk_init_info.max_inline_data = init_attr->cap.max_inline_data;
  549. mem = kzalloc(sizeof(*iwqp), GFP_KERNEL);
  550. if (!mem)
  551. return ERR_PTR(-ENOMEM);
  552. iwqp = (struct i40iw_qp *)mem;
  553. qp = &iwqp->sc_qp;
  554. qp->back_qp = (void *)iwqp;
  555. qp->push_idx = I40IW_INVALID_PUSH_PAGE_INDEX;
  556. iwqp->ctx_info.iwarp_info = &iwqp->iwarp_info;
  557. if (i40iw_allocate_dma_mem(dev->hw,
  558. &iwqp->q2_ctx_mem,
  559. I40IW_Q2_BUFFER_SIZE + I40IW_QP_CTX_SIZE,
  560. 256)) {
  561. i40iw_pr_err("dma_mem failed\n");
  562. err_code = -ENOMEM;
  563. goto error;
  564. }
  565. init_info.q2 = iwqp->q2_ctx_mem.va;
  566. init_info.q2_pa = iwqp->q2_ctx_mem.pa;
  567. init_info.host_ctx = (void *)init_info.q2 + I40IW_Q2_BUFFER_SIZE;
  568. init_info.host_ctx_pa = init_info.q2_pa + I40IW_Q2_BUFFER_SIZE;
  569. err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_qps, iwdev->max_qp,
  570. &qp_num, &iwdev->next_qp);
  571. if (err_code) {
  572. i40iw_pr_err("qp resource\n");
  573. goto error;
  574. }
  575. iwqp->allocated_buffer = mem;
  576. iwqp->iwdev = iwdev;
  577. iwqp->iwpd = iwpd;
  578. iwqp->ibqp.qp_num = qp_num;
  579. qp = &iwqp->sc_qp;
  580. iwqp->iwscq = to_iwcq(init_attr->send_cq);
  581. iwqp->iwrcq = to_iwcq(init_attr->recv_cq);
  582. iwqp->host_ctx.va = init_info.host_ctx;
  583. iwqp->host_ctx.pa = init_info.host_ctx_pa;
  584. iwqp->host_ctx.size = I40IW_QP_CTX_SIZE;
  585. init_info.pd = &iwpd->sc_pd;
  586. init_info.qp_uk_init_info.qp_id = iwqp->ibqp.qp_num;
  587. iwqp->ctx_info.qp_compl_ctx = (uintptr_t)qp;
  588. if (init_attr->qp_type != IB_QPT_RC) {
  589. err_code = -EINVAL;
  590. goto error;
  591. }
  592. if (iwdev->push_mode)
  593. i40iw_alloc_push_page(iwdev, qp);
  594. if (udata) {
  595. err_code = ib_copy_from_udata(&req, udata, sizeof(req));
  596. if (err_code) {
  597. i40iw_pr_err("ib_copy_from_data\n");
  598. goto error;
  599. }
  600. iwqp->ctx_info.qp_compl_ctx = req.user_compl_ctx;
  601. if (ibpd->uobject && ibpd->uobject->context) {
  602. iwqp->user_mode = 1;
  603. ucontext = to_ucontext(ibpd->uobject->context);
  604. if (req.user_wqe_buffers) {
  605. spin_lock_irqsave(
  606. &ucontext->qp_reg_mem_list_lock, flags);
  607. iwqp->iwpbl = i40iw_get_pbl(
  608. (unsigned long)req.user_wqe_buffers,
  609. &ucontext->qp_reg_mem_list);
  610. spin_unlock_irqrestore(
  611. &ucontext->qp_reg_mem_list_lock, flags);
  612. if (!iwqp->iwpbl) {
  613. err_code = -ENODATA;
  614. i40iw_pr_err("no pbl info\n");
  615. goto error;
  616. }
  617. }
  618. }
  619. err_code = i40iw_setup_virt_qp(iwdev, iwqp, &init_info);
  620. } else {
  621. err_code = i40iw_setup_kmode_qp(iwdev, iwqp, &init_info);
  622. }
  623. if (err_code) {
  624. i40iw_pr_err("setup qp failed\n");
  625. goto error;
  626. }
  627. init_info.type = I40IW_QP_TYPE_IWARP;
  628. ret = dev->iw_priv_qp_ops->qp_init(qp, &init_info);
  629. if (ret) {
  630. err_code = -EPROTO;
  631. i40iw_pr_err("qp_init fail\n");
  632. goto error;
  633. }
  634. ctx_info = &iwqp->ctx_info;
  635. iwarp_info = &iwqp->iwarp_info;
  636. iwarp_info->rd_enable = true;
  637. iwarp_info->wr_rdresp_en = true;
  638. if (!iwqp->user_mode) {
  639. iwarp_info->fast_reg_en = true;
  640. iwarp_info->priv_mode_en = true;
  641. }
  642. iwarp_info->ddp_ver = 1;
  643. iwarp_info->rdmap_ver = 1;
  644. ctx_info->iwarp_info_valid = true;
  645. ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
  646. ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
  647. if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX) {
  648. ctx_info->push_mode_en = false;
  649. } else {
  650. ctx_info->push_mode_en = true;
  651. ctx_info->push_idx = qp->push_idx;
  652. }
  653. ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
  654. (u64 *)iwqp->host_ctx.va,
  655. ctx_info);
  656. ctx_info->iwarp_info_valid = false;
  657. cqp_request = i40iw_get_cqp_request(iwcqp, true);
  658. if (!cqp_request) {
  659. err_code = -ENOMEM;
  660. goto error;
  661. }
  662. cqp_info = &cqp_request->info;
  663. qp_info = &cqp_request->info.in.u.qp_create.info;
  664. memset(qp_info, 0, sizeof(*qp_info));
  665. qp_info->cq_num_valid = true;
  666. qp_info->next_iwarp_state = I40IW_QP_STATE_IDLE;
  667. cqp_info->cqp_cmd = OP_QP_CREATE;
  668. cqp_info->post_sq = 1;
  669. cqp_info->in.u.qp_create.qp = qp;
  670. cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request;
  671. ret = i40iw_handle_cqp_op(iwdev, cqp_request);
  672. if (ret) {
  673. i40iw_pr_err("CQP-OP QP create fail");
  674. err_code = -EACCES;
  675. goto error;
  676. }
  677. i40iw_add_ref(&iwqp->ibqp);
  678. spin_lock_init(&iwqp->lock);
  679. iwqp->sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1 : 0;
  680. iwdev->qp_table[qp_num] = iwqp;
  681. i40iw_add_pdusecount(iwqp->iwpd);
  682. i40iw_add_devusecount(iwdev);
  683. if (ibpd->uobject && udata) {
  684. memset(&uresp, 0, sizeof(uresp));
  685. uresp.actual_sq_size = sq_size;
  686. uresp.actual_rq_size = rq_size;
  687. uresp.qp_id = qp_num;
  688. uresp.push_idx = qp->push_idx;
  689. err_code = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  690. if (err_code) {
  691. i40iw_pr_err("copy_to_udata failed\n");
  692. i40iw_destroy_qp(&iwqp->ibqp);
  693. /* let the completion of the qp destroy free the qp */
  694. return ERR_PTR(err_code);
  695. }
  696. }
  697. init_completion(&iwqp->sq_drained);
  698. init_completion(&iwqp->rq_drained);
  699. return &iwqp->ibqp;
  700. error:
  701. i40iw_free_qp_resources(iwdev, iwqp, qp_num);
  702. return ERR_PTR(err_code);
  703. }
  704. /**
  705. * i40iw_query - query qp attributes
  706. * @ibqp: qp pointer
  707. * @attr: attributes pointer
  708. * @attr_mask: Not used
  709. * @init_attr: qp attributes to return
  710. */
  711. static int i40iw_query_qp(struct ib_qp *ibqp,
  712. struct ib_qp_attr *attr,
  713. int attr_mask,
  714. struct ib_qp_init_attr *init_attr)
  715. {
  716. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  717. struct i40iw_sc_qp *qp = &iwqp->sc_qp;
  718. attr->qp_access_flags = 0;
  719. attr->cap.max_send_wr = qp->qp_uk.sq_size;
  720. attr->cap.max_recv_wr = qp->qp_uk.rq_size;
  721. attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
  722. attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
  723. attr->cap.max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
  724. init_attr->event_handler = iwqp->ibqp.event_handler;
  725. init_attr->qp_context = iwqp->ibqp.qp_context;
  726. init_attr->send_cq = iwqp->ibqp.send_cq;
  727. init_attr->recv_cq = iwqp->ibqp.recv_cq;
  728. init_attr->srq = iwqp->ibqp.srq;
  729. init_attr->cap = attr->cap;
  730. return 0;
  731. }
  732. /**
  733. * i40iw_hw_modify_qp - setup cqp for modify qp
  734. * @iwdev: iwarp device
  735. * @iwqp: qp ptr (user or kernel)
  736. * @info: info for modify qp
  737. * @wait: flag to wait or not for modify qp completion
  738. */
  739. void i40iw_hw_modify_qp(struct i40iw_device *iwdev, struct i40iw_qp *iwqp,
  740. struct i40iw_modify_qp_info *info, bool wait)
  741. {
  742. enum i40iw_status_code status;
  743. struct i40iw_cqp_request *cqp_request;
  744. struct cqp_commands_info *cqp_info;
  745. struct i40iw_modify_qp_info *m_info;
  746. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait);
  747. if (!cqp_request)
  748. return;
  749. cqp_info = &cqp_request->info;
  750. m_info = &cqp_info->in.u.qp_modify.info;
  751. memcpy(m_info, info, sizeof(*m_info));
  752. cqp_info->cqp_cmd = OP_QP_MODIFY;
  753. cqp_info->post_sq = 1;
  754. cqp_info->in.u.qp_modify.qp = &iwqp->sc_qp;
  755. cqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request;
  756. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  757. if (status)
  758. i40iw_pr_err("CQP-OP Modify QP fail");
  759. }
  760. /**
  761. * i40iw_modify_qp - modify qp request
  762. * @ibqp: qp's pointer for modify
  763. * @attr: access attributes
  764. * @attr_mask: state mask
  765. * @udata: user data
  766. */
  767. int i40iw_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  768. int attr_mask, struct ib_udata *udata)
  769. {
  770. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  771. struct i40iw_device *iwdev = iwqp->iwdev;
  772. struct i40iw_qp_host_ctx_info *ctx_info;
  773. struct i40iwarp_offload_info *iwarp_info;
  774. struct i40iw_modify_qp_info info;
  775. u8 issue_modify_qp = 0;
  776. u8 dont_wait = 0;
  777. u32 err;
  778. unsigned long flags;
  779. memset(&info, 0, sizeof(info));
  780. ctx_info = &iwqp->ctx_info;
  781. iwarp_info = &iwqp->iwarp_info;
  782. spin_lock_irqsave(&iwqp->lock, flags);
  783. if (attr_mask & IB_QP_STATE) {
  784. if (iwdev->closing && attr->qp_state != IB_QPS_ERR) {
  785. err = -EINVAL;
  786. goto exit;
  787. }
  788. switch (attr->qp_state) {
  789. case IB_QPS_INIT:
  790. case IB_QPS_RTR:
  791. if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_IDLE) {
  792. err = -EINVAL;
  793. goto exit;
  794. }
  795. if (iwqp->iwarp_state == I40IW_QP_STATE_INVALID) {
  796. info.next_iwarp_state = I40IW_QP_STATE_IDLE;
  797. issue_modify_qp = 1;
  798. }
  799. break;
  800. case IB_QPS_RTS:
  801. if ((iwqp->iwarp_state > (u32)I40IW_QP_STATE_RTS) ||
  802. (!iwqp->cm_id)) {
  803. err = -EINVAL;
  804. goto exit;
  805. }
  806. issue_modify_qp = 1;
  807. iwqp->hw_tcp_state = I40IW_TCP_STATE_ESTABLISHED;
  808. iwqp->hte_added = 1;
  809. info.next_iwarp_state = I40IW_QP_STATE_RTS;
  810. info.tcp_ctx_valid = true;
  811. info.ord_valid = true;
  812. info.arp_cache_idx_valid = true;
  813. info.cq_num_valid = true;
  814. break;
  815. case IB_QPS_SQD:
  816. if (iwqp->hw_iwarp_state > (u32)I40IW_QP_STATE_RTS) {
  817. err = 0;
  818. goto exit;
  819. }
  820. if ((iwqp->iwarp_state == (u32)I40IW_QP_STATE_CLOSING) ||
  821. (iwqp->iwarp_state < (u32)I40IW_QP_STATE_RTS)) {
  822. err = 0;
  823. goto exit;
  824. }
  825. if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_CLOSING) {
  826. err = -EINVAL;
  827. goto exit;
  828. }
  829. info.next_iwarp_state = I40IW_QP_STATE_CLOSING;
  830. issue_modify_qp = 1;
  831. break;
  832. case IB_QPS_SQE:
  833. if (iwqp->iwarp_state >= (u32)I40IW_QP_STATE_TERMINATE) {
  834. err = -EINVAL;
  835. goto exit;
  836. }
  837. info.next_iwarp_state = I40IW_QP_STATE_TERMINATE;
  838. issue_modify_qp = 1;
  839. break;
  840. case IB_QPS_ERR:
  841. case IB_QPS_RESET:
  842. if (iwqp->iwarp_state == (u32)I40IW_QP_STATE_ERROR) {
  843. err = -EINVAL;
  844. goto exit;
  845. }
  846. if (iwqp->sc_qp.term_flags)
  847. i40iw_terminate_del_timer(&iwqp->sc_qp);
  848. info.next_iwarp_state = I40IW_QP_STATE_ERROR;
  849. if ((iwqp->hw_tcp_state > I40IW_TCP_STATE_CLOSED) &&
  850. iwdev->iw_status &&
  851. (iwqp->hw_tcp_state != I40IW_TCP_STATE_TIME_WAIT))
  852. info.reset_tcp_conn = true;
  853. else
  854. dont_wait = 1;
  855. issue_modify_qp = 1;
  856. info.next_iwarp_state = I40IW_QP_STATE_ERROR;
  857. break;
  858. default:
  859. err = -EINVAL;
  860. goto exit;
  861. }
  862. iwqp->ibqp_state = attr->qp_state;
  863. if (issue_modify_qp)
  864. iwqp->iwarp_state = info.next_iwarp_state;
  865. else
  866. info.next_iwarp_state = iwqp->iwarp_state;
  867. }
  868. if (attr_mask & IB_QP_ACCESS_FLAGS) {
  869. ctx_info->iwarp_info_valid = true;
  870. if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE)
  871. iwarp_info->wr_rdresp_en = true;
  872. if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
  873. iwarp_info->wr_rdresp_en = true;
  874. if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
  875. iwarp_info->rd_enable = true;
  876. if (attr->qp_access_flags & IB_ACCESS_MW_BIND)
  877. iwarp_info->bind_en = true;
  878. if (iwqp->user_mode) {
  879. iwarp_info->rd_enable = true;
  880. iwarp_info->wr_rdresp_en = true;
  881. iwarp_info->priv_mode_en = false;
  882. }
  883. }
  884. if (ctx_info->iwarp_info_valid) {
  885. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  886. int ret;
  887. ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
  888. ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
  889. ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
  890. (u64 *)iwqp->host_ctx.va,
  891. ctx_info);
  892. if (ret) {
  893. i40iw_pr_err("setting QP context\n");
  894. err = -EINVAL;
  895. goto exit;
  896. }
  897. }
  898. spin_unlock_irqrestore(&iwqp->lock, flags);
  899. if (issue_modify_qp)
  900. i40iw_hw_modify_qp(iwdev, iwqp, &info, true);
  901. if (issue_modify_qp && (iwqp->ibqp_state > IB_QPS_RTS)) {
  902. if (dont_wait) {
  903. if (iwqp->cm_id && iwqp->hw_tcp_state) {
  904. spin_lock_irqsave(&iwqp->lock, flags);
  905. iwqp->hw_tcp_state = I40IW_TCP_STATE_CLOSED;
  906. iwqp->last_aeq = I40IW_AE_RESET_SENT;
  907. spin_unlock_irqrestore(&iwqp->lock, flags);
  908. }
  909. }
  910. }
  911. return 0;
  912. exit:
  913. spin_unlock_irqrestore(&iwqp->lock, flags);
  914. return err;
  915. }
  916. /**
  917. * cq_free_resources - free up recources for cq
  918. * @iwdev: iwarp device
  919. * @iwcq: cq ptr
  920. */
  921. static void cq_free_resources(struct i40iw_device *iwdev, struct i40iw_cq *iwcq)
  922. {
  923. struct i40iw_sc_cq *cq = &iwcq->sc_cq;
  924. if (!iwcq->user_mode)
  925. i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwcq->kmem);
  926. i40iw_free_resource(iwdev, iwdev->allocated_cqs, cq->cq_uk.cq_id);
  927. }
  928. /**
  929. * i40iw_cq_wq_destroy - send cq destroy cqp
  930. * @iwdev: iwarp device
  931. * @cq: hardware control cq
  932. */
  933. void i40iw_cq_wq_destroy(struct i40iw_device *iwdev, struct i40iw_sc_cq *cq)
  934. {
  935. enum i40iw_status_code status;
  936. struct i40iw_cqp_request *cqp_request;
  937. struct cqp_commands_info *cqp_info;
  938. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  939. if (!cqp_request)
  940. return;
  941. cqp_info = &cqp_request->info;
  942. cqp_info->cqp_cmd = OP_CQ_DESTROY;
  943. cqp_info->post_sq = 1;
  944. cqp_info->in.u.cq_destroy.cq = cq;
  945. cqp_info->in.u.cq_destroy.scratch = (uintptr_t)cqp_request;
  946. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  947. if (status)
  948. i40iw_pr_err("CQP-OP Destroy QP fail");
  949. }
  950. /**
  951. * i40iw_destroy_cq - destroy cq
  952. * @ib_cq: cq pointer
  953. */
  954. static int i40iw_destroy_cq(struct ib_cq *ib_cq)
  955. {
  956. struct i40iw_cq *iwcq;
  957. struct i40iw_device *iwdev;
  958. struct i40iw_sc_cq *cq;
  959. if (!ib_cq) {
  960. i40iw_pr_err("ib_cq == NULL\n");
  961. return 0;
  962. }
  963. iwcq = to_iwcq(ib_cq);
  964. iwdev = to_iwdev(ib_cq->device);
  965. cq = &iwcq->sc_cq;
  966. i40iw_cq_wq_destroy(iwdev, cq);
  967. cq_free_resources(iwdev, iwcq);
  968. kfree(iwcq);
  969. i40iw_rem_devusecount(iwdev);
  970. return 0;
  971. }
  972. /**
  973. * i40iw_create_cq - create cq
  974. * @ibdev: device pointer from stack
  975. * @attr: attributes for cq
  976. * @context: user context created during alloc
  977. * @udata: user data
  978. */
  979. static struct ib_cq *i40iw_create_cq(struct ib_device *ibdev,
  980. const struct ib_cq_init_attr *attr,
  981. struct ib_ucontext *context,
  982. struct ib_udata *udata)
  983. {
  984. struct i40iw_device *iwdev = to_iwdev(ibdev);
  985. struct i40iw_cq *iwcq;
  986. struct i40iw_pbl *iwpbl;
  987. u32 cq_num = 0;
  988. struct i40iw_sc_cq *cq;
  989. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  990. struct i40iw_cq_init_info info;
  991. enum i40iw_status_code status;
  992. struct i40iw_cqp_request *cqp_request;
  993. struct cqp_commands_info *cqp_info;
  994. struct i40iw_cq_uk_init_info *ukinfo = &info.cq_uk_init_info;
  995. unsigned long flags;
  996. int err_code;
  997. int entries = attr->cqe;
  998. if (iwdev->closing)
  999. return ERR_PTR(-ENODEV);
  1000. if (entries > iwdev->max_cqe)
  1001. return ERR_PTR(-EINVAL);
  1002. iwcq = kzalloc(sizeof(*iwcq), GFP_KERNEL);
  1003. if (!iwcq)
  1004. return ERR_PTR(-ENOMEM);
  1005. memset(&info, 0, sizeof(info));
  1006. err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_cqs,
  1007. iwdev->max_cq, &cq_num,
  1008. &iwdev->next_cq);
  1009. if (err_code)
  1010. goto error;
  1011. cq = &iwcq->sc_cq;
  1012. cq->back_cq = (void *)iwcq;
  1013. spin_lock_init(&iwcq->lock);
  1014. info.dev = dev;
  1015. ukinfo->cq_size = max(entries, 4);
  1016. ukinfo->cq_id = cq_num;
  1017. iwcq->ibcq.cqe = info.cq_uk_init_info.cq_size;
  1018. info.ceqe_mask = 0;
  1019. if (attr->comp_vector < iwdev->ceqs_count)
  1020. info.ceq_id = attr->comp_vector;
  1021. info.ceq_id_valid = true;
  1022. info.ceqe_mask = 1;
  1023. info.type = I40IW_CQ_TYPE_IWARP;
  1024. if (context) {
  1025. struct i40iw_ucontext *ucontext;
  1026. struct i40iw_create_cq_req req;
  1027. struct i40iw_cq_mr *cqmr;
  1028. memset(&req, 0, sizeof(req));
  1029. iwcq->user_mode = true;
  1030. ucontext = to_ucontext(context);
  1031. if (ib_copy_from_udata(&req, udata, sizeof(struct i40iw_create_cq_req)))
  1032. goto cq_free_resources;
  1033. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1034. iwpbl = i40iw_get_pbl((unsigned long)req.user_cq_buffer,
  1035. &ucontext->cq_reg_mem_list);
  1036. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1037. if (!iwpbl) {
  1038. err_code = -EPROTO;
  1039. goto cq_free_resources;
  1040. }
  1041. iwcq->iwpbl = iwpbl;
  1042. iwcq->cq_mem_size = 0;
  1043. cqmr = &iwpbl->cq_mr;
  1044. info.shadow_area_pa = cpu_to_le64(cqmr->shadow);
  1045. if (iwpbl->pbl_allocated) {
  1046. info.virtual_map = true;
  1047. info.pbl_chunk_size = 1;
  1048. info.first_pm_pbl_idx = cqmr->cq_pbl.idx;
  1049. } else {
  1050. info.cq_base_pa = cqmr->cq_pbl.addr;
  1051. }
  1052. } else {
  1053. /* Kmode allocations */
  1054. int rsize;
  1055. int shadow;
  1056. rsize = info.cq_uk_init_info.cq_size * sizeof(struct i40iw_cqe);
  1057. rsize = round_up(rsize, 256);
  1058. shadow = I40IW_SHADOW_AREA_SIZE << 3;
  1059. status = i40iw_allocate_dma_mem(dev->hw, &iwcq->kmem,
  1060. rsize + shadow, 256);
  1061. if (status) {
  1062. err_code = -ENOMEM;
  1063. goto cq_free_resources;
  1064. }
  1065. ukinfo->cq_base = iwcq->kmem.va;
  1066. info.cq_base_pa = iwcq->kmem.pa;
  1067. info.shadow_area_pa = info.cq_base_pa + rsize;
  1068. ukinfo->shadow_area = iwcq->kmem.va + rsize;
  1069. }
  1070. if (dev->iw_priv_cq_ops->cq_init(cq, &info)) {
  1071. i40iw_pr_err("init cq fail\n");
  1072. err_code = -EPROTO;
  1073. goto cq_free_resources;
  1074. }
  1075. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  1076. if (!cqp_request) {
  1077. err_code = -ENOMEM;
  1078. goto cq_free_resources;
  1079. }
  1080. cqp_info = &cqp_request->info;
  1081. cqp_info->cqp_cmd = OP_CQ_CREATE;
  1082. cqp_info->post_sq = 1;
  1083. cqp_info->in.u.cq_create.cq = cq;
  1084. cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;
  1085. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  1086. if (status) {
  1087. i40iw_pr_err("CQP-OP Create QP fail");
  1088. err_code = -EPROTO;
  1089. goto cq_free_resources;
  1090. }
  1091. if (context) {
  1092. struct i40iw_create_cq_resp resp;
  1093. memset(&resp, 0, sizeof(resp));
  1094. resp.cq_id = info.cq_uk_init_info.cq_id;
  1095. resp.cq_size = info.cq_uk_init_info.cq_size;
  1096. if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
  1097. i40iw_pr_err("copy to user data\n");
  1098. err_code = -EPROTO;
  1099. goto cq_destroy;
  1100. }
  1101. }
  1102. i40iw_add_devusecount(iwdev);
  1103. return (struct ib_cq *)iwcq;
  1104. cq_destroy:
  1105. i40iw_cq_wq_destroy(iwdev, cq);
  1106. cq_free_resources:
  1107. cq_free_resources(iwdev, iwcq);
  1108. error:
  1109. kfree(iwcq);
  1110. return ERR_PTR(err_code);
  1111. }
  1112. /**
  1113. * i40iw_get_user_access - get hw access from IB access
  1114. * @acc: IB access to return hw access
  1115. */
  1116. static inline u16 i40iw_get_user_access(int acc)
  1117. {
  1118. u16 access = 0;
  1119. access |= (acc & IB_ACCESS_LOCAL_WRITE) ? I40IW_ACCESS_FLAGS_LOCALWRITE : 0;
  1120. access |= (acc & IB_ACCESS_REMOTE_WRITE) ? I40IW_ACCESS_FLAGS_REMOTEWRITE : 0;
  1121. access |= (acc & IB_ACCESS_REMOTE_READ) ? I40IW_ACCESS_FLAGS_REMOTEREAD : 0;
  1122. access |= (acc & IB_ACCESS_MW_BIND) ? I40IW_ACCESS_FLAGS_BIND_WINDOW : 0;
  1123. return access;
  1124. }
  1125. /**
  1126. * i40iw_free_stag - free stag resource
  1127. * @iwdev: iwarp device
  1128. * @stag: stag to free
  1129. */
  1130. static void i40iw_free_stag(struct i40iw_device *iwdev, u32 stag)
  1131. {
  1132. u32 stag_idx;
  1133. stag_idx = (stag & iwdev->mr_stagmask) >> I40IW_CQPSQ_STAG_IDX_SHIFT;
  1134. i40iw_free_resource(iwdev, iwdev->allocated_mrs, stag_idx);
  1135. i40iw_rem_devusecount(iwdev);
  1136. }
  1137. /**
  1138. * i40iw_create_stag - create random stag
  1139. * @iwdev: iwarp device
  1140. */
  1141. static u32 i40iw_create_stag(struct i40iw_device *iwdev)
  1142. {
  1143. u32 stag = 0;
  1144. u32 stag_index = 0;
  1145. u32 next_stag_index;
  1146. u32 driver_key;
  1147. u32 random;
  1148. u8 consumer_key;
  1149. int ret;
  1150. get_random_bytes(&random, sizeof(random));
  1151. consumer_key = (u8)random;
  1152. driver_key = random & ~iwdev->mr_stagmask;
  1153. next_stag_index = (random & iwdev->mr_stagmask) >> 8;
  1154. next_stag_index %= iwdev->max_mr;
  1155. ret = i40iw_alloc_resource(iwdev,
  1156. iwdev->allocated_mrs, iwdev->max_mr,
  1157. &stag_index, &next_stag_index);
  1158. if (!ret) {
  1159. stag = stag_index << I40IW_CQPSQ_STAG_IDX_SHIFT;
  1160. stag |= driver_key;
  1161. stag += (u32)consumer_key;
  1162. i40iw_add_devusecount(iwdev);
  1163. }
  1164. return stag;
  1165. }
  1166. /**
  1167. * i40iw_next_pbl_addr - Get next pbl address
  1168. * @pbl: pointer to a pble
  1169. * @pinfo: info pointer
  1170. * @idx: index
  1171. */
  1172. static inline u64 *i40iw_next_pbl_addr(u64 *pbl,
  1173. struct i40iw_pble_info **pinfo,
  1174. u32 *idx)
  1175. {
  1176. *idx += 1;
  1177. if ((!(*pinfo)) || (*idx != (*pinfo)->cnt))
  1178. return ++pbl;
  1179. *idx = 0;
  1180. (*pinfo)++;
  1181. return (u64 *)(*pinfo)->addr;
  1182. }
  1183. /**
  1184. * i40iw_copy_user_pgaddrs - copy user page address to pble's os locally
  1185. * @iwmr: iwmr for IB's user page addresses
  1186. * @pbl: ple pointer to save 1 level or 0 level pble
  1187. * @level: indicated level 0, 1 or 2
  1188. */
  1189. static void i40iw_copy_user_pgaddrs(struct i40iw_mr *iwmr,
  1190. u64 *pbl,
  1191. enum i40iw_pble_level level)
  1192. {
  1193. struct ib_umem *region = iwmr->region;
  1194. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1195. int chunk_pages, entry, pg_shift, i;
  1196. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1197. struct i40iw_pble_info *pinfo;
  1198. struct scatterlist *sg;
  1199. u64 pg_addr = 0;
  1200. u32 idx = 0;
  1201. pinfo = (level == I40IW_LEVEL_1) ? NULL : palloc->level2.leaf;
  1202. pg_shift = ffs(region->page_size) - 1;
  1203. for_each_sg(region->sg_head.sgl, sg, region->nmap, entry) {
  1204. chunk_pages = sg_dma_len(sg) >> pg_shift;
  1205. if ((iwmr->type == IW_MEMREG_TYPE_QP) &&
  1206. !iwpbl->qp_mr.sq_page)
  1207. iwpbl->qp_mr.sq_page = sg_page(sg);
  1208. for (i = 0; i < chunk_pages; i++) {
  1209. pg_addr = sg_dma_address(sg) + region->page_size * i;
  1210. if ((entry + i) == 0)
  1211. *pbl = cpu_to_le64(pg_addr & iwmr->page_msk);
  1212. else if (!(pg_addr & ~iwmr->page_msk))
  1213. *pbl = cpu_to_le64(pg_addr);
  1214. else
  1215. continue;
  1216. pbl = i40iw_next_pbl_addr(pbl, &pinfo, &idx);
  1217. }
  1218. }
  1219. }
  1220. /**
  1221. * i40iw_set_hugetlb_params - set MR pg size and mask to huge pg values.
  1222. * @addr: virtual address
  1223. * @iwmr: mr pointer for this memory registration
  1224. */
  1225. static void i40iw_set_hugetlb_values(u64 addr, struct i40iw_mr *iwmr)
  1226. {
  1227. struct vm_area_struct *vma;
  1228. struct hstate *h;
  1229. vma = find_vma(current->mm, addr);
  1230. if (vma && is_vm_hugetlb_page(vma)) {
  1231. h = hstate_vma(vma);
  1232. if (huge_page_size(h) == 0x200000) {
  1233. iwmr->page_size = huge_page_size(h);
  1234. iwmr->page_msk = huge_page_mask(h);
  1235. }
  1236. }
  1237. }
  1238. /**
  1239. * i40iw_check_mem_contiguous - check if pbls stored in arr are contiguous
  1240. * @arr: lvl1 pbl array
  1241. * @npages: page count
  1242. * pg_size: page size
  1243. *
  1244. */
  1245. static bool i40iw_check_mem_contiguous(u64 *arr, u32 npages, u32 pg_size)
  1246. {
  1247. u32 pg_idx;
  1248. for (pg_idx = 0; pg_idx < npages; pg_idx++) {
  1249. if ((*arr + (pg_size * pg_idx)) != arr[pg_idx])
  1250. return false;
  1251. }
  1252. return true;
  1253. }
  1254. /**
  1255. * i40iw_check_mr_contiguous - check if MR is physically contiguous
  1256. * @palloc: pbl allocation struct
  1257. * pg_size: page size
  1258. */
  1259. static bool i40iw_check_mr_contiguous(struct i40iw_pble_alloc *palloc, u32 pg_size)
  1260. {
  1261. struct i40iw_pble_level2 *lvl2 = &palloc->level2;
  1262. struct i40iw_pble_info *leaf = lvl2->leaf;
  1263. u64 *arr = NULL;
  1264. u64 *start_addr = NULL;
  1265. int i;
  1266. bool ret;
  1267. if (palloc->level == I40IW_LEVEL_1) {
  1268. arr = (u64 *)palloc->level1.addr;
  1269. ret = i40iw_check_mem_contiguous(arr, palloc->total_cnt, pg_size);
  1270. return ret;
  1271. }
  1272. start_addr = (u64 *)leaf->addr;
  1273. for (i = 0; i < lvl2->leaf_cnt; i++, leaf++) {
  1274. arr = (u64 *)leaf->addr;
  1275. if ((*start_addr + (i * pg_size * PBLE_PER_PAGE)) != *arr)
  1276. return false;
  1277. ret = i40iw_check_mem_contiguous(arr, leaf->cnt, pg_size);
  1278. if (!ret)
  1279. return false;
  1280. }
  1281. return true;
  1282. }
  1283. /**
  1284. * i40iw_setup_pbles - copy user pg address to pble's
  1285. * @iwdev: iwarp device
  1286. * @iwmr: mr pointer for this memory registration
  1287. * @use_pbles: flag if to use pble's
  1288. */
  1289. static int i40iw_setup_pbles(struct i40iw_device *iwdev,
  1290. struct i40iw_mr *iwmr,
  1291. bool use_pbles)
  1292. {
  1293. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1294. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1295. struct i40iw_pble_info *pinfo;
  1296. u64 *pbl;
  1297. enum i40iw_status_code status;
  1298. enum i40iw_pble_level level = I40IW_LEVEL_1;
  1299. if (use_pbles) {
  1300. mutex_lock(&iwdev->pbl_mutex);
  1301. status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt);
  1302. mutex_unlock(&iwdev->pbl_mutex);
  1303. if (status)
  1304. return -ENOMEM;
  1305. iwpbl->pbl_allocated = true;
  1306. level = palloc->level;
  1307. pinfo = (level == I40IW_LEVEL_1) ? &palloc->level1 : palloc->level2.leaf;
  1308. pbl = (u64 *)pinfo->addr;
  1309. } else {
  1310. pbl = iwmr->pgaddrmem;
  1311. }
  1312. i40iw_copy_user_pgaddrs(iwmr, pbl, level);
  1313. if (use_pbles)
  1314. iwmr->pgaddrmem[0] = *pbl;
  1315. return 0;
  1316. }
  1317. /**
  1318. * i40iw_handle_q_mem - handle memory for qp and cq
  1319. * @iwdev: iwarp device
  1320. * @req: information for q memory management
  1321. * @iwpbl: pble struct
  1322. * @use_pbles: flag to use pble
  1323. */
  1324. static int i40iw_handle_q_mem(struct i40iw_device *iwdev,
  1325. struct i40iw_mem_reg_req *req,
  1326. struct i40iw_pbl *iwpbl,
  1327. bool use_pbles)
  1328. {
  1329. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1330. struct i40iw_mr *iwmr = iwpbl->iwmr;
  1331. struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr;
  1332. struct i40iw_cq_mr *cqmr = &iwpbl->cq_mr;
  1333. struct i40iw_hmc_pble *hmc_p;
  1334. u64 *arr = iwmr->pgaddrmem;
  1335. u32 pg_size;
  1336. int err;
  1337. int total;
  1338. bool ret = true;
  1339. total = req->sq_pages + req->rq_pages + req->cq_pages;
  1340. pg_size = iwmr->page_size;
  1341. err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
  1342. if (err)
  1343. return err;
  1344. if (use_pbles && (palloc->level != I40IW_LEVEL_1)) {
  1345. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1346. iwpbl->pbl_allocated = false;
  1347. return -ENOMEM;
  1348. }
  1349. if (use_pbles)
  1350. arr = (u64 *)palloc->level1.addr;
  1351. if (iwmr->type == IW_MEMREG_TYPE_QP) {
  1352. hmc_p = &qpmr->sq_pbl;
  1353. qpmr->shadow = (dma_addr_t)arr[total];
  1354. if (use_pbles) {
  1355. ret = i40iw_check_mem_contiguous(arr, req->sq_pages, pg_size);
  1356. if (ret)
  1357. ret = i40iw_check_mem_contiguous(&arr[req->sq_pages], req->rq_pages, pg_size);
  1358. }
  1359. if (!ret) {
  1360. hmc_p->idx = palloc->level1.idx;
  1361. hmc_p = &qpmr->rq_pbl;
  1362. hmc_p->idx = palloc->level1.idx + req->sq_pages;
  1363. } else {
  1364. hmc_p->addr = arr[0];
  1365. hmc_p = &qpmr->rq_pbl;
  1366. hmc_p->addr = arr[req->sq_pages];
  1367. }
  1368. } else { /* CQ */
  1369. hmc_p = &cqmr->cq_pbl;
  1370. cqmr->shadow = (dma_addr_t)arr[total];
  1371. if (use_pbles)
  1372. ret = i40iw_check_mem_contiguous(arr, req->cq_pages, pg_size);
  1373. if (!ret)
  1374. hmc_p->idx = palloc->level1.idx;
  1375. else
  1376. hmc_p->addr = arr[0];
  1377. }
  1378. if (use_pbles && ret) {
  1379. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1380. iwpbl->pbl_allocated = false;
  1381. }
  1382. return err;
  1383. }
  1384. /**
  1385. * i40iw_hw_alloc_stag - cqp command to allocate stag
  1386. * @iwdev: iwarp device
  1387. * @iwmr: iwarp mr pointer
  1388. */
  1389. static int i40iw_hw_alloc_stag(struct i40iw_device *iwdev, struct i40iw_mr *iwmr)
  1390. {
  1391. struct i40iw_allocate_stag_info *info;
  1392. struct i40iw_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
  1393. enum i40iw_status_code status;
  1394. int err = 0;
  1395. struct i40iw_cqp_request *cqp_request;
  1396. struct cqp_commands_info *cqp_info;
  1397. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  1398. if (!cqp_request)
  1399. return -ENOMEM;
  1400. cqp_info = &cqp_request->info;
  1401. info = &cqp_info->in.u.alloc_stag.info;
  1402. memset(info, 0, sizeof(*info));
  1403. info->page_size = PAGE_SIZE;
  1404. info->stag_idx = iwmr->stag >> I40IW_CQPSQ_STAG_IDX_SHIFT;
  1405. info->pd_id = iwpd->sc_pd.pd_id;
  1406. info->total_len = iwmr->length;
  1407. info->remote_access = true;
  1408. cqp_info->cqp_cmd = OP_ALLOC_STAG;
  1409. cqp_info->post_sq = 1;
  1410. cqp_info->in.u.alloc_stag.dev = &iwdev->sc_dev;
  1411. cqp_info->in.u.alloc_stag.scratch = (uintptr_t)cqp_request;
  1412. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  1413. if (status) {
  1414. err = -ENOMEM;
  1415. i40iw_pr_err("CQP-OP MR Reg fail");
  1416. }
  1417. return err;
  1418. }
  1419. /**
  1420. * i40iw_alloc_mr - register stag for fast memory registration
  1421. * @pd: ibpd pointer
  1422. * @mr_type: memory for stag registrion
  1423. * @max_num_sg: man number of pages
  1424. */
  1425. static struct ib_mr *i40iw_alloc_mr(struct ib_pd *pd,
  1426. enum ib_mr_type mr_type,
  1427. u32 max_num_sg)
  1428. {
  1429. struct i40iw_pd *iwpd = to_iwpd(pd);
  1430. struct i40iw_device *iwdev = to_iwdev(pd->device);
  1431. struct i40iw_pble_alloc *palloc;
  1432. struct i40iw_pbl *iwpbl;
  1433. struct i40iw_mr *iwmr;
  1434. enum i40iw_status_code status;
  1435. u32 stag;
  1436. int err_code = -ENOMEM;
  1437. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  1438. if (!iwmr)
  1439. return ERR_PTR(-ENOMEM);
  1440. stag = i40iw_create_stag(iwdev);
  1441. if (!stag) {
  1442. err_code = -EOVERFLOW;
  1443. goto err;
  1444. }
  1445. iwmr->stag = stag;
  1446. iwmr->ibmr.rkey = stag;
  1447. iwmr->ibmr.lkey = stag;
  1448. iwmr->ibmr.pd = pd;
  1449. iwmr->ibmr.device = pd->device;
  1450. iwpbl = &iwmr->iwpbl;
  1451. iwpbl->iwmr = iwmr;
  1452. iwmr->type = IW_MEMREG_TYPE_MEM;
  1453. palloc = &iwpbl->pble_alloc;
  1454. iwmr->page_cnt = max_num_sg;
  1455. mutex_lock(&iwdev->pbl_mutex);
  1456. status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt);
  1457. mutex_unlock(&iwdev->pbl_mutex);
  1458. if (status)
  1459. goto err1;
  1460. if (palloc->level != I40IW_LEVEL_1)
  1461. goto err2;
  1462. err_code = i40iw_hw_alloc_stag(iwdev, iwmr);
  1463. if (err_code)
  1464. goto err2;
  1465. iwpbl->pbl_allocated = true;
  1466. i40iw_add_pdusecount(iwpd);
  1467. return &iwmr->ibmr;
  1468. err2:
  1469. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1470. err1:
  1471. i40iw_free_stag(iwdev, stag);
  1472. err:
  1473. kfree(iwmr);
  1474. return ERR_PTR(err_code);
  1475. }
  1476. /**
  1477. * i40iw_set_page - populate pbl list for fmr
  1478. * @ibmr: ib mem to access iwarp mr pointer
  1479. * @addr: page dma address fro pbl list
  1480. */
  1481. static int i40iw_set_page(struct ib_mr *ibmr, u64 addr)
  1482. {
  1483. struct i40iw_mr *iwmr = to_iwmr(ibmr);
  1484. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1485. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1486. u64 *pbl;
  1487. if (unlikely(iwmr->npages == iwmr->page_cnt))
  1488. return -ENOMEM;
  1489. pbl = (u64 *)palloc->level1.addr;
  1490. pbl[iwmr->npages++] = cpu_to_le64(addr);
  1491. return 0;
  1492. }
  1493. /**
  1494. * i40iw_map_mr_sg - map of sg list for fmr
  1495. * @ibmr: ib mem to access iwarp mr pointer
  1496. * @sg: scatter gather list for fmr
  1497. * @sg_nents: number of sg pages
  1498. */
  1499. static int i40iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
  1500. int sg_nents, unsigned int *sg_offset)
  1501. {
  1502. struct i40iw_mr *iwmr = to_iwmr(ibmr);
  1503. iwmr->npages = 0;
  1504. return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, i40iw_set_page);
  1505. }
  1506. /**
  1507. * i40iw_drain_sq - drain the send queue
  1508. * @ibqp: ib qp pointer
  1509. */
  1510. static void i40iw_drain_sq(struct ib_qp *ibqp)
  1511. {
  1512. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  1513. struct i40iw_sc_qp *qp = &iwqp->sc_qp;
  1514. if (I40IW_RING_MORE_WORK(qp->qp_uk.sq_ring))
  1515. wait_for_completion(&iwqp->sq_drained);
  1516. }
  1517. /**
  1518. * i40iw_drain_rq - drain the receive queue
  1519. * @ibqp: ib qp pointer
  1520. */
  1521. static void i40iw_drain_rq(struct ib_qp *ibqp)
  1522. {
  1523. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  1524. struct i40iw_sc_qp *qp = &iwqp->sc_qp;
  1525. if (I40IW_RING_MORE_WORK(qp->qp_uk.rq_ring))
  1526. wait_for_completion(&iwqp->rq_drained);
  1527. }
  1528. /**
  1529. * i40iw_hwreg_mr - send cqp command for memory registration
  1530. * @iwdev: iwarp device
  1531. * @iwmr: iwarp mr pointer
  1532. * @access: access for MR
  1533. */
  1534. static int i40iw_hwreg_mr(struct i40iw_device *iwdev,
  1535. struct i40iw_mr *iwmr,
  1536. u16 access)
  1537. {
  1538. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1539. struct i40iw_reg_ns_stag_info *stag_info;
  1540. struct i40iw_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
  1541. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1542. enum i40iw_status_code status;
  1543. int err = 0;
  1544. struct i40iw_cqp_request *cqp_request;
  1545. struct cqp_commands_info *cqp_info;
  1546. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  1547. if (!cqp_request)
  1548. return -ENOMEM;
  1549. cqp_info = &cqp_request->info;
  1550. stag_info = &cqp_info->in.u.mr_reg_non_shared.info;
  1551. memset(stag_info, 0, sizeof(*stag_info));
  1552. stag_info->va = (void *)(unsigned long)iwpbl->user_base;
  1553. stag_info->stag_idx = iwmr->stag >> I40IW_CQPSQ_STAG_IDX_SHIFT;
  1554. stag_info->stag_key = (u8)iwmr->stag;
  1555. stag_info->total_len = iwmr->length;
  1556. stag_info->access_rights = access;
  1557. stag_info->pd_id = iwpd->sc_pd.pd_id;
  1558. stag_info->addr_type = I40IW_ADDR_TYPE_VA_BASED;
  1559. stag_info->page_size = iwmr->page_size;
  1560. if (iwpbl->pbl_allocated) {
  1561. if (palloc->level == I40IW_LEVEL_1) {
  1562. stag_info->first_pm_pbl_index = palloc->level1.idx;
  1563. stag_info->chunk_size = 1;
  1564. } else {
  1565. stag_info->first_pm_pbl_index = palloc->level2.root.idx;
  1566. stag_info->chunk_size = 3;
  1567. }
  1568. } else {
  1569. stag_info->reg_addr_pa = iwmr->pgaddrmem[0];
  1570. }
  1571. cqp_info->cqp_cmd = OP_MR_REG_NON_SHARED;
  1572. cqp_info->post_sq = 1;
  1573. cqp_info->in.u.mr_reg_non_shared.dev = &iwdev->sc_dev;
  1574. cqp_info->in.u.mr_reg_non_shared.scratch = (uintptr_t)cqp_request;
  1575. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  1576. if (status) {
  1577. err = -ENOMEM;
  1578. i40iw_pr_err("CQP-OP MR Reg fail");
  1579. }
  1580. return err;
  1581. }
  1582. /**
  1583. * i40iw_reg_user_mr - Register a user memory region
  1584. * @pd: ptr of pd
  1585. * @start: virtual start address
  1586. * @length: length of mr
  1587. * @virt: virtual address
  1588. * @acc: access of mr
  1589. * @udata: user data
  1590. */
  1591. static struct ib_mr *i40iw_reg_user_mr(struct ib_pd *pd,
  1592. u64 start,
  1593. u64 length,
  1594. u64 virt,
  1595. int acc,
  1596. struct ib_udata *udata)
  1597. {
  1598. struct i40iw_pd *iwpd = to_iwpd(pd);
  1599. struct i40iw_device *iwdev = to_iwdev(pd->device);
  1600. struct i40iw_ucontext *ucontext;
  1601. struct i40iw_pble_alloc *palloc;
  1602. struct i40iw_pbl *iwpbl;
  1603. struct i40iw_mr *iwmr;
  1604. struct ib_umem *region;
  1605. struct i40iw_mem_reg_req req;
  1606. u64 pbl_depth = 0;
  1607. u32 stag = 0;
  1608. u16 access;
  1609. u64 region_length;
  1610. bool use_pbles = false;
  1611. unsigned long flags;
  1612. int err = -ENOSYS;
  1613. int ret;
  1614. int pg_shift;
  1615. if (iwdev->closing)
  1616. return ERR_PTR(-ENODEV);
  1617. if (length > I40IW_MAX_MR_SIZE)
  1618. return ERR_PTR(-EINVAL);
  1619. region = ib_umem_get(pd->uobject->context, start, length, acc, 0);
  1620. if (IS_ERR(region))
  1621. return (struct ib_mr *)region;
  1622. if (ib_copy_from_udata(&req, udata, sizeof(req))) {
  1623. ib_umem_release(region);
  1624. return ERR_PTR(-EFAULT);
  1625. }
  1626. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  1627. if (!iwmr) {
  1628. ib_umem_release(region);
  1629. return ERR_PTR(-ENOMEM);
  1630. }
  1631. iwpbl = &iwmr->iwpbl;
  1632. iwpbl->iwmr = iwmr;
  1633. iwmr->region = region;
  1634. iwmr->ibmr.pd = pd;
  1635. iwmr->ibmr.device = pd->device;
  1636. ucontext = to_ucontext(pd->uobject->context);
  1637. iwmr->page_size = region->page_size;
  1638. iwmr->page_msk = PAGE_MASK;
  1639. if (region->hugetlb && (req.reg_type == IW_MEMREG_TYPE_MEM))
  1640. i40iw_set_hugetlb_values(start, iwmr);
  1641. region_length = region->length + (start & (iwmr->page_size - 1));
  1642. pg_shift = ffs(iwmr->page_size) - 1;
  1643. pbl_depth = region_length >> pg_shift;
  1644. pbl_depth += (region_length & (iwmr->page_size - 1)) ? 1 : 0;
  1645. iwmr->length = region->length;
  1646. iwpbl->user_base = virt;
  1647. palloc = &iwpbl->pble_alloc;
  1648. iwmr->type = req.reg_type;
  1649. iwmr->page_cnt = (u32)pbl_depth;
  1650. switch (req.reg_type) {
  1651. case IW_MEMREG_TYPE_QP:
  1652. use_pbles = ((req.sq_pages + req.rq_pages) > 2);
  1653. err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
  1654. if (err)
  1655. goto error;
  1656. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  1657. list_add_tail(&iwpbl->list, &ucontext->qp_reg_mem_list);
  1658. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  1659. break;
  1660. case IW_MEMREG_TYPE_CQ:
  1661. use_pbles = (req.cq_pages > 1);
  1662. err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
  1663. if (err)
  1664. goto error;
  1665. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1666. list_add_tail(&iwpbl->list, &ucontext->cq_reg_mem_list);
  1667. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1668. break;
  1669. case IW_MEMREG_TYPE_MEM:
  1670. use_pbles = (iwmr->page_cnt != 1);
  1671. access = I40IW_ACCESS_FLAGS_LOCALREAD;
  1672. err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
  1673. if (err)
  1674. goto error;
  1675. if (use_pbles) {
  1676. ret = i40iw_check_mr_contiguous(palloc, iwmr->page_size);
  1677. if (ret) {
  1678. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1679. iwpbl->pbl_allocated = false;
  1680. }
  1681. }
  1682. access |= i40iw_get_user_access(acc);
  1683. stag = i40iw_create_stag(iwdev);
  1684. if (!stag) {
  1685. err = -ENOMEM;
  1686. goto error;
  1687. }
  1688. iwmr->stag = stag;
  1689. iwmr->ibmr.rkey = stag;
  1690. iwmr->ibmr.lkey = stag;
  1691. err = i40iw_hwreg_mr(iwdev, iwmr, access);
  1692. if (err) {
  1693. i40iw_free_stag(iwdev, stag);
  1694. goto error;
  1695. }
  1696. break;
  1697. default:
  1698. goto error;
  1699. }
  1700. iwmr->type = req.reg_type;
  1701. if (req.reg_type == IW_MEMREG_TYPE_MEM)
  1702. i40iw_add_pdusecount(iwpd);
  1703. return &iwmr->ibmr;
  1704. error:
  1705. if (palloc->level != I40IW_LEVEL_0 && iwpbl->pbl_allocated)
  1706. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1707. ib_umem_release(region);
  1708. kfree(iwmr);
  1709. return ERR_PTR(err);
  1710. }
  1711. /**
  1712. * i40iw_reg_phys_mr - register kernel physical memory
  1713. * @pd: ibpd pointer
  1714. * @addr: physical address of memory to register
  1715. * @size: size of memory to register
  1716. * @acc: Access rights
  1717. * @iova_start: start of virtual address for physical buffers
  1718. */
  1719. struct ib_mr *i40iw_reg_phys_mr(struct ib_pd *pd,
  1720. u64 addr,
  1721. u64 size,
  1722. int acc,
  1723. u64 *iova_start)
  1724. {
  1725. struct i40iw_pd *iwpd = to_iwpd(pd);
  1726. struct i40iw_device *iwdev = to_iwdev(pd->device);
  1727. struct i40iw_pbl *iwpbl;
  1728. struct i40iw_mr *iwmr;
  1729. enum i40iw_status_code status;
  1730. u32 stag;
  1731. u16 access = I40IW_ACCESS_FLAGS_LOCALREAD;
  1732. int ret;
  1733. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  1734. if (!iwmr)
  1735. return ERR_PTR(-ENOMEM);
  1736. iwmr->ibmr.pd = pd;
  1737. iwmr->ibmr.device = pd->device;
  1738. iwpbl = &iwmr->iwpbl;
  1739. iwpbl->iwmr = iwmr;
  1740. iwmr->type = IW_MEMREG_TYPE_MEM;
  1741. iwpbl->user_base = *iova_start;
  1742. stag = i40iw_create_stag(iwdev);
  1743. if (!stag) {
  1744. ret = -EOVERFLOW;
  1745. goto err;
  1746. }
  1747. access |= i40iw_get_user_access(acc);
  1748. iwmr->stag = stag;
  1749. iwmr->ibmr.rkey = stag;
  1750. iwmr->ibmr.lkey = stag;
  1751. iwmr->page_cnt = 1;
  1752. iwmr->pgaddrmem[0] = addr;
  1753. iwmr->length = size;
  1754. status = i40iw_hwreg_mr(iwdev, iwmr, access);
  1755. if (status) {
  1756. i40iw_free_stag(iwdev, stag);
  1757. ret = -ENOMEM;
  1758. goto err;
  1759. }
  1760. i40iw_add_pdusecount(iwpd);
  1761. return &iwmr->ibmr;
  1762. err:
  1763. kfree(iwmr);
  1764. return ERR_PTR(ret);
  1765. }
  1766. /**
  1767. * i40iw_get_dma_mr - register physical mem
  1768. * @pd: ptr of pd
  1769. * @acc: access for memory
  1770. */
  1771. static struct ib_mr *i40iw_get_dma_mr(struct ib_pd *pd, int acc)
  1772. {
  1773. u64 kva = 0;
  1774. return i40iw_reg_phys_mr(pd, 0, 0, acc, &kva);
  1775. }
  1776. /**
  1777. * i40iw_del_mem_list - Deleting pbl list entries for CQ/QP
  1778. * @iwmr: iwmr for IB's user page addresses
  1779. * @ucontext: ptr to user context
  1780. */
  1781. static void i40iw_del_memlist(struct i40iw_mr *iwmr,
  1782. struct i40iw_ucontext *ucontext)
  1783. {
  1784. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1785. unsigned long flags;
  1786. switch (iwmr->type) {
  1787. case IW_MEMREG_TYPE_CQ:
  1788. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1789. if (!list_empty(&ucontext->cq_reg_mem_list))
  1790. list_del(&iwpbl->list);
  1791. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1792. break;
  1793. case IW_MEMREG_TYPE_QP:
  1794. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  1795. if (!list_empty(&ucontext->qp_reg_mem_list))
  1796. list_del(&iwpbl->list);
  1797. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  1798. break;
  1799. default:
  1800. break;
  1801. }
  1802. }
  1803. /**
  1804. * i40iw_dereg_mr - deregister mr
  1805. * @ib_mr: mr ptr for dereg
  1806. */
  1807. static int i40iw_dereg_mr(struct ib_mr *ib_mr)
  1808. {
  1809. struct ib_pd *ibpd = ib_mr->pd;
  1810. struct i40iw_pd *iwpd = to_iwpd(ibpd);
  1811. struct i40iw_mr *iwmr = to_iwmr(ib_mr);
  1812. struct i40iw_device *iwdev = to_iwdev(ib_mr->device);
  1813. enum i40iw_status_code status;
  1814. struct i40iw_dealloc_stag_info *info;
  1815. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1816. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1817. struct i40iw_cqp_request *cqp_request;
  1818. struct cqp_commands_info *cqp_info;
  1819. u32 stag_idx;
  1820. if (iwmr->region)
  1821. ib_umem_release(iwmr->region);
  1822. if (iwmr->type != IW_MEMREG_TYPE_MEM) {
  1823. if (ibpd->uobject) {
  1824. struct i40iw_ucontext *ucontext;
  1825. ucontext = to_ucontext(ibpd->uobject->context);
  1826. i40iw_del_memlist(iwmr, ucontext);
  1827. }
  1828. if (iwpbl->pbl_allocated)
  1829. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1830. kfree(iwmr);
  1831. return 0;
  1832. }
  1833. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  1834. if (!cqp_request)
  1835. return -ENOMEM;
  1836. cqp_info = &cqp_request->info;
  1837. info = &cqp_info->in.u.dealloc_stag.info;
  1838. memset(info, 0, sizeof(*info));
  1839. info->pd_id = cpu_to_le32(iwpd->sc_pd.pd_id & 0x00007fff);
  1840. info->stag_idx = RS_64_1(ib_mr->rkey, I40IW_CQPSQ_STAG_IDX_SHIFT);
  1841. stag_idx = info->stag_idx;
  1842. info->mr = true;
  1843. if (iwpbl->pbl_allocated)
  1844. info->dealloc_pbl = true;
  1845. cqp_info->cqp_cmd = OP_DEALLOC_STAG;
  1846. cqp_info->post_sq = 1;
  1847. cqp_info->in.u.dealloc_stag.dev = &iwdev->sc_dev;
  1848. cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request;
  1849. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  1850. if (status)
  1851. i40iw_pr_err("CQP-OP dealloc failed for stag_idx = 0x%x\n", stag_idx);
  1852. i40iw_rem_pdusecount(iwpd, iwdev);
  1853. i40iw_free_stag(iwdev, iwmr->stag);
  1854. if (iwpbl->pbl_allocated)
  1855. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1856. kfree(iwmr);
  1857. return 0;
  1858. }
  1859. /**
  1860. * i40iw_show_rev
  1861. */
  1862. static ssize_t i40iw_show_rev(struct device *dev,
  1863. struct device_attribute *attr, char *buf)
  1864. {
  1865. struct i40iw_ib_device *iwibdev = container_of(dev,
  1866. struct i40iw_ib_device,
  1867. ibdev.dev);
  1868. u32 hw_rev = iwibdev->iwdev->sc_dev.hw_rev;
  1869. return sprintf(buf, "%x\n", hw_rev);
  1870. }
  1871. /**
  1872. * i40iw_show_hca
  1873. */
  1874. static ssize_t i40iw_show_hca(struct device *dev,
  1875. struct device_attribute *attr, char *buf)
  1876. {
  1877. return sprintf(buf, "I40IW\n");
  1878. }
  1879. /**
  1880. * i40iw_show_board
  1881. */
  1882. static ssize_t i40iw_show_board(struct device *dev,
  1883. struct device_attribute *attr,
  1884. char *buf)
  1885. {
  1886. return sprintf(buf, "%.*s\n", 32, "I40IW Board ID");
  1887. }
  1888. static DEVICE_ATTR(hw_rev, S_IRUGO, i40iw_show_rev, NULL);
  1889. static DEVICE_ATTR(hca_type, S_IRUGO, i40iw_show_hca, NULL);
  1890. static DEVICE_ATTR(board_id, S_IRUGO, i40iw_show_board, NULL);
  1891. static struct device_attribute *i40iw_dev_attributes[] = {
  1892. &dev_attr_hw_rev,
  1893. &dev_attr_hca_type,
  1894. &dev_attr_board_id
  1895. };
  1896. /**
  1897. * i40iw_copy_sg_list - copy sg list for qp
  1898. * @sg_list: copied into sg_list
  1899. * @sgl: copy from sgl
  1900. * @num_sges: count of sg entries
  1901. */
  1902. static void i40iw_copy_sg_list(struct i40iw_sge *sg_list, struct ib_sge *sgl, int num_sges)
  1903. {
  1904. unsigned int i;
  1905. for (i = 0; (i < num_sges) && (i < I40IW_MAX_WQ_FRAGMENT_COUNT); i++) {
  1906. sg_list[i].tag_off = sgl[i].addr;
  1907. sg_list[i].len = sgl[i].length;
  1908. sg_list[i].stag = sgl[i].lkey;
  1909. }
  1910. }
  1911. /**
  1912. * i40iw_post_send - kernel application wr
  1913. * @ibqp: qp ptr for wr
  1914. * @ib_wr: work request ptr
  1915. * @bad_wr: return of bad wr if err
  1916. */
  1917. static int i40iw_post_send(struct ib_qp *ibqp,
  1918. struct ib_send_wr *ib_wr,
  1919. struct ib_send_wr **bad_wr)
  1920. {
  1921. struct i40iw_qp *iwqp;
  1922. struct i40iw_qp_uk *ukqp;
  1923. struct i40iw_post_sq_info info;
  1924. enum i40iw_status_code ret;
  1925. int err = 0;
  1926. unsigned long flags;
  1927. bool inv_stag;
  1928. iwqp = (struct i40iw_qp *)ibqp;
  1929. ukqp = &iwqp->sc_qp.qp_uk;
  1930. spin_lock_irqsave(&iwqp->lock, flags);
  1931. while (ib_wr) {
  1932. inv_stag = false;
  1933. memset(&info, 0, sizeof(info));
  1934. info.wr_id = (u64)(ib_wr->wr_id);
  1935. if ((ib_wr->send_flags & IB_SEND_SIGNALED) || iwqp->sig_all)
  1936. info.signaled = true;
  1937. if (ib_wr->send_flags & IB_SEND_FENCE)
  1938. info.read_fence = true;
  1939. switch (ib_wr->opcode) {
  1940. case IB_WR_SEND:
  1941. /* fall-through */
  1942. case IB_WR_SEND_WITH_INV:
  1943. if (ib_wr->opcode == IB_WR_SEND) {
  1944. if (ib_wr->send_flags & IB_SEND_SOLICITED)
  1945. info.op_type = I40IW_OP_TYPE_SEND_SOL;
  1946. else
  1947. info.op_type = I40IW_OP_TYPE_SEND;
  1948. } else {
  1949. if (ib_wr->send_flags & IB_SEND_SOLICITED)
  1950. info.op_type = I40IW_OP_TYPE_SEND_SOL_INV;
  1951. else
  1952. info.op_type = I40IW_OP_TYPE_SEND_INV;
  1953. }
  1954. if (ib_wr->send_flags & IB_SEND_INLINE) {
  1955. info.op.inline_send.data = (void *)(unsigned long)ib_wr->sg_list[0].addr;
  1956. info.op.inline_send.len = ib_wr->sg_list[0].length;
  1957. ret = ukqp->ops.iw_inline_send(ukqp, &info, ib_wr->ex.invalidate_rkey, false);
  1958. } else {
  1959. info.op.send.num_sges = ib_wr->num_sge;
  1960. info.op.send.sg_list = (struct i40iw_sge *)ib_wr->sg_list;
  1961. ret = ukqp->ops.iw_send(ukqp, &info, ib_wr->ex.invalidate_rkey, false);
  1962. }
  1963. if (ret) {
  1964. if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
  1965. err = -ENOMEM;
  1966. else
  1967. err = -EINVAL;
  1968. }
  1969. break;
  1970. case IB_WR_RDMA_WRITE:
  1971. info.op_type = I40IW_OP_TYPE_RDMA_WRITE;
  1972. if (ib_wr->send_flags & IB_SEND_INLINE) {
  1973. info.op.inline_rdma_write.data = (void *)(unsigned long)ib_wr->sg_list[0].addr;
  1974. info.op.inline_rdma_write.len = ib_wr->sg_list[0].length;
  1975. info.op.inline_rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
  1976. info.op.inline_rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey;
  1977. info.op.inline_rdma_write.rem_addr.len = ib_wr->sg_list->length;
  1978. ret = ukqp->ops.iw_inline_rdma_write(ukqp, &info, false);
  1979. } else {
  1980. info.op.rdma_write.lo_sg_list = (void *)ib_wr->sg_list;
  1981. info.op.rdma_write.num_lo_sges = ib_wr->num_sge;
  1982. info.op.rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
  1983. info.op.rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey;
  1984. info.op.rdma_write.rem_addr.len = ib_wr->sg_list->length;
  1985. ret = ukqp->ops.iw_rdma_write(ukqp, &info, false);
  1986. }
  1987. if (ret) {
  1988. if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
  1989. err = -ENOMEM;
  1990. else
  1991. err = -EINVAL;
  1992. }
  1993. break;
  1994. case IB_WR_RDMA_READ_WITH_INV:
  1995. inv_stag = true;
  1996. /* fall-through*/
  1997. case IB_WR_RDMA_READ:
  1998. if (ib_wr->num_sge > I40IW_MAX_SGE_RD) {
  1999. err = -EINVAL;
  2000. break;
  2001. }
  2002. info.op_type = I40IW_OP_TYPE_RDMA_READ;
  2003. info.op.rdma_read.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
  2004. info.op.rdma_read.rem_addr.stag = rdma_wr(ib_wr)->rkey;
  2005. info.op.rdma_read.rem_addr.len = ib_wr->sg_list->length;
  2006. info.op.rdma_read.lo_addr.tag_off = ib_wr->sg_list->addr;
  2007. info.op.rdma_read.lo_addr.stag = ib_wr->sg_list->lkey;
  2008. info.op.rdma_read.lo_addr.len = ib_wr->sg_list->length;
  2009. ret = ukqp->ops.iw_rdma_read(ukqp, &info, inv_stag, false);
  2010. if (ret) {
  2011. if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
  2012. err = -ENOMEM;
  2013. else
  2014. err = -EINVAL;
  2015. }
  2016. break;
  2017. case IB_WR_LOCAL_INV:
  2018. info.op_type = I40IW_OP_TYPE_INV_STAG;
  2019. info.op.inv_local_stag.target_stag = ib_wr->ex.invalidate_rkey;
  2020. ret = ukqp->ops.iw_stag_local_invalidate(ukqp, &info, true);
  2021. if (ret)
  2022. err = -ENOMEM;
  2023. break;
  2024. case IB_WR_REG_MR:
  2025. {
  2026. struct i40iw_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr);
  2027. int flags = reg_wr(ib_wr)->access;
  2028. struct i40iw_pble_alloc *palloc = &iwmr->iwpbl.pble_alloc;
  2029. struct i40iw_sc_dev *dev = &iwqp->iwdev->sc_dev;
  2030. struct i40iw_fast_reg_stag_info info;
  2031. memset(&info, 0, sizeof(info));
  2032. info.access_rights = I40IW_ACCESS_FLAGS_LOCALREAD;
  2033. info.access_rights |= i40iw_get_user_access(flags);
  2034. info.stag_key = reg_wr(ib_wr)->key & 0xff;
  2035. info.stag_idx = reg_wr(ib_wr)->key >> 8;
  2036. info.page_size = reg_wr(ib_wr)->mr->page_size;
  2037. info.wr_id = ib_wr->wr_id;
  2038. info.addr_type = I40IW_ADDR_TYPE_VA_BASED;
  2039. info.va = (void *)(uintptr_t)iwmr->ibmr.iova;
  2040. info.total_len = iwmr->ibmr.length;
  2041. info.reg_addr_pa = *(u64 *)palloc->level1.addr;
  2042. info.first_pm_pbl_index = palloc->level1.idx;
  2043. info.local_fence = ib_wr->send_flags & IB_SEND_FENCE;
  2044. info.signaled = ib_wr->send_flags & IB_SEND_SIGNALED;
  2045. if (iwmr->npages > I40IW_MIN_PAGES_PER_FMR)
  2046. info.chunk_size = 1;
  2047. ret = dev->iw_priv_qp_ops->iw_mr_fast_register(&iwqp->sc_qp, &info, true);
  2048. if (ret)
  2049. err = -ENOMEM;
  2050. break;
  2051. }
  2052. default:
  2053. err = -EINVAL;
  2054. i40iw_pr_err(" upost_send bad opcode = 0x%x\n",
  2055. ib_wr->opcode);
  2056. break;
  2057. }
  2058. if (err)
  2059. break;
  2060. ib_wr = ib_wr->next;
  2061. }
  2062. if (err)
  2063. *bad_wr = ib_wr;
  2064. else
  2065. ukqp->ops.iw_qp_post_wr(ukqp);
  2066. spin_unlock_irqrestore(&iwqp->lock, flags);
  2067. return err;
  2068. }
  2069. /**
  2070. * i40iw_post_recv - post receive wr for kernel application
  2071. * @ibqp: ib qp pointer
  2072. * @ib_wr: work request for receive
  2073. * @bad_wr: bad wr caused an error
  2074. */
  2075. static int i40iw_post_recv(struct ib_qp *ibqp,
  2076. struct ib_recv_wr *ib_wr,
  2077. struct ib_recv_wr **bad_wr)
  2078. {
  2079. struct i40iw_qp *iwqp;
  2080. struct i40iw_qp_uk *ukqp;
  2081. struct i40iw_post_rq_info post_recv;
  2082. struct i40iw_sge sg_list[I40IW_MAX_WQ_FRAGMENT_COUNT];
  2083. enum i40iw_status_code ret = 0;
  2084. unsigned long flags;
  2085. int err = 0;
  2086. iwqp = (struct i40iw_qp *)ibqp;
  2087. ukqp = &iwqp->sc_qp.qp_uk;
  2088. memset(&post_recv, 0, sizeof(post_recv));
  2089. spin_lock_irqsave(&iwqp->lock, flags);
  2090. while (ib_wr) {
  2091. post_recv.num_sges = ib_wr->num_sge;
  2092. post_recv.wr_id = ib_wr->wr_id;
  2093. i40iw_copy_sg_list(sg_list, ib_wr->sg_list, ib_wr->num_sge);
  2094. post_recv.sg_list = sg_list;
  2095. ret = ukqp->ops.iw_post_receive(ukqp, &post_recv);
  2096. if (ret) {
  2097. i40iw_pr_err(" post_recv err %d\n", ret);
  2098. if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
  2099. err = -ENOMEM;
  2100. else
  2101. err = -EINVAL;
  2102. *bad_wr = ib_wr;
  2103. goto out;
  2104. }
  2105. ib_wr = ib_wr->next;
  2106. }
  2107. out:
  2108. spin_unlock_irqrestore(&iwqp->lock, flags);
  2109. return err;
  2110. }
  2111. /**
  2112. * i40iw_poll_cq - poll cq for completion (kernel apps)
  2113. * @ibcq: cq to poll
  2114. * @num_entries: number of entries to poll
  2115. * @entry: wr of entry completed
  2116. */
  2117. static int i40iw_poll_cq(struct ib_cq *ibcq,
  2118. int num_entries,
  2119. struct ib_wc *entry)
  2120. {
  2121. struct i40iw_cq *iwcq;
  2122. int cqe_count = 0;
  2123. struct i40iw_cq_poll_info cq_poll_info;
  2124. enum i40iw_status_code ret;
  2125. struct i40iw_cq_uk *ukcq;
  2126. struct i40iw_sc_qp *qp;
  2127. struct i40iw_qp *iwqp;
  2128. unsigned long flags;
  2129. iwcq = (struct i40iw_cq *)ibcq;
  2130. ukcq = &iwcq->sc_cq.cq_uk;
  2131. spin_lock_irqsave(&iwcq->lock, flags);
  2132. while (cqe_count < num_entries) {
  2133. ret = ukcq->ops.iw_cq_poll_completion(ukcq, &cq_poll_info);
  2134. if (ret == I40IW_ERR_QUEUE_EMPTY) {
  2135. break;
  2136. } else if (ret == I40IW_ERR_QUEUE_DESTROYED) {
  2137. continue;
  2138. } else if (ret) {
  2139. if (!cqe_count)
  2140. cqe_count = -1;
  2141. break;
  2142. }
  2143. entry->wc_flags = 0;
  2144. entry->wr_id = cq_poll_info.wr_id;
  2145. if (cq_poll_info.error) {
  2146. entry->status = IB_WC_WR_FLUSH_ERR;
  2147. entry->vendor_err = cq_poll_info.major_err << 16 | cq_poll_info.minor_err;
  2148. } else {
  2149. entry->status = IB_WC_SUCCESS;
  2150. }
  2151. switch (cq_poll_info.op_type) {
  2152. case I40IW_OP_TYPE_RDMA_WRITE:
  2153. entry->opcode = IB_WC_RDMA_WRITE;
  2154. break;
  2155. case I40IW_OP_TYPE_RDMA_READ_INV_STAG:
  2156. case I40IW_OP_TYPE_RDMA_READ:
  2157. entry->opcode = IB_WC_RDMA_READ;
  2158. break;
  2159. case I40IW_OP_TYPE_SEND_SOL:
  2160. case I40IW_OP_TYPE_SEND_SOL_INV:
  2161. case I40IW_OP_TYPE_SEND_INV:
  2162. case I40IW_OP_TYPE_SEND:
  2163. entry->opcode = IB_WC_SEND;
  2164. break;
  2165. case I40IW_OP_TYPE_REC:
  2166. entry->opcode = IB_WC_RECV;
  2167. break;
  2168. default:
  2169. entry->opcode = IB_WC_RECV;
  2170. break;
  2171. }
  2172. entry->ex.imm_data = 0;
  2173. qp = (struct i40iw_sc_qp *)cq_poll_info.qp_handle;
  2174. entry->qp = (struct ib_qp *)qp->back_qp;
  2175. entry->src_qp = cq_poll_info.qp_id;
  2176. iwqp = (struct i40iw_qp *)qp->back_qp;
  2177. if (iwqp->iwarp_state > I40IW_QP_STATE_RTS) {
  2178. if (!I40IW_RING_MORE_WORK(qp->qp_uk.sq_ring))
  2179. complete(&iwqp->sq_drained);
  2180. if (!I40IW_RING_MORE_WORK(qp->qp_uk.rq_ring))
  2181. complete(&iwqp->rq_drained);
  2182. }
  2183. entry->byte_len = cq_poll_info.bytes_xfered;
  2184. entry++;
  2185. cqe_count++;
  2186. }
  2187. spin_unlock_irqrestore(&iwcq->lock, flags);
  2188. return cqe_count;
  2189. }
  2190. /**
  2191. * i40iw_req_notify_cq - arm cq kernel application
  2192. * @ibcq: cq to arm
  2193. * @notify_flags: notofication flags
  2194. */
  2195. static int i40iw_req_notify_cq(struct ib_cq *ibcq,
  2196. enum ib_cq_notify_flags notify_flags)
  2197. {
  2198. struct i40iw_cq *iwcq;
  2199. struct i40iw_cq_uk *ukcq;
  2200. unsigned long flags;
  2201. enum i40iw_completion_notify cq_notify = IW_CQ_COMPL_EVENT;
  2202. iwcq = (struct i40iw_cq *)ibcq;
  2203. ukcq = &iwcq->sc_cq.cq_uk;
  2204. if (notify_flags == IB_CQ_SOLICITED)
  2205. cq_notify = IW_CQ_COMPL_SOLICITED;
  2206. spin_lock_irqsave(&iwcq->lock, flags);
  2207. ukcq->ops.iw_cq_request_notification(ukcq, cq_notify);
  2208. spin_unlock_irqrestore(&iwcq->lock, flags);
  2209. return 0;
  2210. }
  2211. /**
  2212. * i40iw_port_immutable - return port's immutable data
  2213. * @ibdev: ib dev struct
  2214. * @port_num: port number
  2215. * @immutable: immutable data for the port return
  2216. */
  2217. static int i40iw_port_immutable(struct ib_device *ibdev, u8 port_num,
  2218. struct ib_port_immutable *immutable)
  2219. {
  2220. struct ib_port_attr attr;
  2221. int err;
  2222. err = i40iw_query_port(ibdev, port_num, &attr);
  2223. if (err)
  2224. return err;
  2225. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  2226. immutable->gid_tbl_len = attr.gid_tbl_len;
  2227. immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
  2228. return 0;
  2229. }
  2230. static const char * const i40iw_hw_stat_names[] = {
  2231. // 32bit names
  2232. [I40IW_HW_STAT_INDEX_IP4RXDISCARD] = "ip4InDiscards",
  2233. [I40IW_HW_STAT_INDEX_IP4RXTRUNC] = "ip4InTruncatedPkts",
  2234. [I40IW_HW_STAT_INDEX_IP4TXNOROUTE] = "ip4OutNoRoutes",
  2235. [I40IW_HW_STAT_INDEX_IP6RXDISCARD] = "ip6InDiscards",
  2236. [I40IW_HW_STAT_INDEX_IP6RXTRUNC] = "ip6InTruncatedPkts",
  2237. [I40IW_HW_STAT_INDEX_IP6TXNOROUTE] = "ip6OutNoRoutes",
  2238. [I40IW_HW_STAT_INDEX_TCPRTXSEG] = "tcpRetransSegs",
  2239. [I40IW_HW_STAT_INDEX_TCPRXOPTERR] = "tcpInOptErrors",
  2240. [I40IW_HW_STAT_INDEX_TCPRXPROTOERR] = "tcpInProtoErrors",
  2241. // 64bit names
  2242. [I40IW_HW_STAT_INDEX_IP4RXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2243. "ip4InOctets",
  2244. [I40IW_HW_STAT_INDEX_IP4RXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2245. "ip4InPkts",
  2246. [I40IW_HW_STAT_INDEX_IP4RXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2247. "ip4InReasmRqd",
  2248. [I40IW_HW_STAT_INDEX_IP4RXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2249. "ip4InMcastPkts",
  2250. [I40IW_HW_STAT_INDEX_IP4TXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2251. "ip4OutOctets",
  2252. [I40IW_HW_STAT_INDEX_IP4TXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2253. "ip4OutPkts",
  2254. [I40IW_HW_STAT_INDEX_IP4TXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2255. "ip4OutSegRqd",
  2256. [I40IW_HW_STAT_INDEX_IP4TXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2257. "ip4OutMcastPkts",
  2258. [I40IW_HW_STAT_INDEX_IP6RXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2259. "ip6InOctets",
  2260. [I40IW_HW_STAT_INDEX_IP6RXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2261. "ip6InPkts",
  2262. [I40IW_HW_STAT_INDEX_IP6RXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2263. "ip6InReasmRqd",
  2264. [I40IW_HW_STAT_INDEX_IP6RXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2265. "ip6InMcastPkts",
  2266. [I40IW_HW_STAT_INDEX_IP6TXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2267. "ip6OutOctets",
  2268. [I40IW_HW_STAT_INDEX_IP6TXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2269. "ip6OutPkts",
  2270. [I40IW_HW_STAT_INDEX_IP6TXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2271. "ip6OutSegRqd",
  2272. [I40IW_HW_STAT_INDEX_IP6TXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2273. "ip6OutMcastPkts",
  2274. [I40IW_HW_STAT_INDEX_TCPRXSEGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2275. "tcpInSegs",
  2276. [I40IW_HW_STAT_INDEX_TCPTXSEG + I40IW_HW_STAT_INDEX_MAX_32] =
  2277. "tcpOutSegs",
  2278. [I40IW_HW_STAT_INDEX_RDMARXRDS + I40IW_HW_STAT_INDEX_MAX_32] =
  2279. "iwInRdmaReads",
  2280. [I40IW_HW_STAT_INDEX_RDMARXSNDS + I40IW_HW_STAT_INDEX_MAX_32] =
  2281. "iwInRdmaSends",
  2282. [I40IW_HW_STAT_INDEX_RDMARXWRS + I40IW_HW_STAT_INDEX_MAX_32] =
  2283. "iwInRdmaWrites",
  2284. [I40IW_HW_STAT_INDEX_RDMATXRDS + I40IW_HW_STAT_INDEX_MAX_32] =
  2285. "iwOutRdmaReads",
  2286. [I40IW_HW_STAT_INDEX_RDMATXSNDS + I40IW_HW_STAT_INDEX_MAX_32] =
  2287. "iwOutRdmaSends",
  2288. [I40IW_HW_STAT_INDEX_RDMATXWRS + I40IW_HW_STAT_INDEX_MAX_32] =
  2289. "iwOutRdmaWrites",
  2290. [I40IW_HW_STAT_INDEX_RDMAVBND + I40IW_HW_STAT_INDEX_MAX_32] =
  2291. "iwRdmaBnd",
  2292. [I40IW_HW_STAT_INDEX_RDMAVINV + I40IW_HW_STAT_INDEX_MAX_32] =
  2293. "iwRdmaInv"
  2294. };
  2295. static void i40iw_get_dev_fw_str(struct ib_device *dev, char *str,
  2296. size_t str_len)
  2297. {
  2298. u32 firmware_version = I40IW_FW_VERSION;
  2299. snprintf(str, str_len, "%u.%u", firmware_version,
  2300. (firmware_version & 0x000000ff));
  2301. }
  2302. /**
  2303. * i40iw_alloc_hw_stats - Allocate a hw stats structure
  2304. * @ibdev: device pointer from stack
  2305. * @port_num: port number
  2306. */
  2307. static struct rdma_hw_stats *i40iw_alloc_hw_stats(struct ib_device *ibdev,
  2308. u8 port_num)
  2309. {
  2310. struct i40iw_device *iwdev = to_iwdev(ibdev);
  2311. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  2312. int num_counters = I40IW_HW_STAT_INDEX_MAX_32 +
  2313. I40IW_HW_STAT_INDEX_MAX_64;
  2314. unsigned long lifespan = RDMA_HW_STATS_DEFAULT_LIFESPAN;
  2315. BUILD_BUG_ON(ARRAY_SIZE(i40iw_hw_stat_names) !=
  2316. (I40IW_HW_STAT_INDEX_MAX_32 +
  2317. I40IW_HW_STAT_INDEX_MAX_64));
  2318. /*
  2319. * PFs get the default update lifespan, but VFs only update once
  2320. * per second
  2321. */
  2322. if (!dev->is_pf)
  2323. lifespan = 1000;
  2324. return rdma_alloc_hw_stats_struct(i40iw_hw_stat_names, num_counters,
  2325. lifespan);
  2326. }
  2327. /**
  2328. * i40iw_get_hw_stats - Populates the rdma_hw_stats structure
  2329. * @ibdev: device pointer from stack
  2330. * @stats: stats pointer from stack
  2331. * @port_num: port number
  2332. * @index: which hw counter the stack is requesting we update
  2333. */
  2334. static int i40iw_get_hw_stats(struct ib_device *ibdev,
  2335. struct rdma_hw_stats *stats,
  2336. u8 port_num, int index)
  2337. {
  2338. struct i40iw_device *iwdev = to_iwdev(ibdev);
  2339. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  2340. struct i40iw_vsi_pestat *devstat = iwdev->vsi.pestat;
  2341. struct i40iw_dev_hw_stats *hw_stats = &devstat->hw_stats;
  2342. if (dev->is_pf) {
  2343. i40iw_hw_stats_read_all(devstat, &devstat->hw_stats);
  2344. } else {
  2345. if (i40iw_vchnl_vf_get_pe_stats(dev, &devstat->hw_stats))
  2346. return -ENOSYS;
  2347. }
  2348. memcpy(&stats->value[0], hw_stats, sizeof(*hw_stats));
  2349. return stats->num_counters;
  2350. }
  2351. /**
  2352. * i40iw_query_gid - Query port GID
  2353. * @ibdev: device pointer from stack
  2354. * @port: port number
  2355. * @index: Entry index
  2356. * @gid: Global ID
  2357. */
  2358. static int i40iw_query_gid(struct ib_device *ibdev,
  2359. u8 port,
  2360. int index,
  2361. union ib_gid *gid)
  2362. {
  2363. struct i40iw_device *iwdev = to_iwdev(ibdev);
  2364. memset(gid->raw, 0, sizeof(gid->raw));
  2365. ether_addr_copy(gid->raw, iwdev->netdev->dev_addr);
  2366. return 0;
  2367. }
  2368. /**
  2369. * i40iw_modify_port Modify port properties
  2370. * @ibdev: device pointer from stack
  2371. * @port: port number
  2372. * @port_modify_mask: mask for port modifications
  2373. * @props: port properties
  2374. */
  2375. static int i40iw_modify_port(struct ib_device *ibdev,
  2376. u8 port,
  2377. int port_modify_mask,
  2378. struct ib_port_modify *props)
  2379. {
  2380. return -ENOSYS;
  2381. }
  2382. /**
  2383. * i40iw_query_pkey - Query partition key
  2384. * @ibdev: device pointer from stack
  2385. * @port: port number
  2386. * @index: index of pkey
  2387. * @pkey: pointer to store the pkey
  2388. */
  2389. static int i40iw_query_pkey(struct ib_device *ibdev,
  2390. u8 port,
  2391. u16 index,
  2392. u16 *pkey)
  2393. {
  2394. *pkey = 0;
  2395. return 0;
  2396. }
  2397. /**
  2398. * i40iw_create_ah - create address handle
  2399. * @ibpd: ptr of pd
  2400. * @ah_attr: address handle attributes
  2401. */
  2402. static struct ib_ah *i40iw_create_ah(struct ib_pd *ibpd,
  2403. struct ib_ah_attr *attr,
  2404. struct ib_udata *udata)
  2405. {
  2406. return ERR_PTR(-ENOSYS);
  2407. }
  2408. /**
  2409. * i40iw_destroy_ah - Destroy address handle
  2410. * @ah: pointer to address handle
  2411. */
  2412. static int i40iw_destroy_ah(struct ib_ah *ah)
  2413. {
  2414. return -ENOSYS;
  2415. }
  2416. /**
  2417. * i40iw_init_rdma_device - initialization of iwarp device
  2418. * @iwdev: iwarp device
  2419. */
  2420. static struct i40iw_ib_device *i40iw_init_rdma_device(struct i40iw_device *iwdev)
  2421. {
  2422. struct i40iw_ib_device *iwibdev;
  2423. struct net_device *netdev = iwdev->netdev;
  2424. struct pci_dev *pcidev = (struct pci_dev *)iwdev->hw.dev_context;
  2425. iwibdev = (struct i40iw_ib_device *)ib_alloc_device(sizeof(*iwibdev));
  2426. if (!iwibdev) {
  2427. i40iw_pr_err("iwdev == NULL\n");
  2428. return NULL;
  2429. }
  2430. strlcpy(iwibdev->ibdev.name, "i40iw%d", IB_DEVICE_NAME_MAX);
  2431. iwibdev->ibdev.owner = THIS_MODULE;
  2432. iwdev->iwibdev = iwibdev;
  2433. iwibdev->iwdev = iwdev;
  2434. iwibdev->ibdev.node_type = RDMA_NODE_RNIC;
  2435. ether_addr_copy((u8 *)&iwibdev->ibdev.node_guid, netdev->dev_addr);
  2436. iwibdev->ibdev.uverbs_cmd_mask =
  2437. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  2438. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  2439. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  2440. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  2441. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  2442. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  2443. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  2444. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  2445. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  2446. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  2447. (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
  2448. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  2449. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  2450. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  2451. (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
  2452. (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
  2453. (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
  2454. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  2455. (1ull << IB_USER_VERBS_CMD_POST_RECV) |
  2456. (1ull << IB_USER_VERBS_CMD_POST_SEND);
  2457. iwibdev->ibdev.phys_port_cnt = 1;
  2458. iwibdev->ibdev.num_comp_vectors = iwdev->ceqs_count;
  2459. iwibdev->ibdev.dma_device = &pcidev->dev;
  2460. iwibdev->ibdev.dev.parent = &pcidev->dev;
  2461. iwibdev->ibdev.query_port = i40iw_query_port;
  2462. iwibdev->ibdev.modify_port = i40iw_modify_port;
  2463. iwibdev->ibdev.query_pkey = i40iw_query_pkey;
  2464. iwibdev->ibdev.query_gid = i40iw_query_gid;
  2465. iwibdev->ibdev.alloc_ucontext = i40iw_alloc_ucontext;
  2466. iwibdev->ibdev.dealloc_ucontext = i40iw_dealloc_ucontext;
  2467. iwibdev->ibdev.mmap = i40iw_mmap;
  2468. iwibdev->ibdev.alloc_pd = i40iw_alloc_pd;
  2469. iwibdev->ibdev.dealloc_pd = i40iw_dealloc_pd;
  2470. iwibdev->ibdev.create_qp = i40iw_create_qp;
  2471. iwibdev->ibdev.modify_qp = i40iw_modify_qp;
  2472. iwibdev->ibdev.query_qp = i40iw_query_qp;
  2473. iwibdev->ibdev.destroy_qp = i40iw_destroy_qp;
  2474. iwibdev->ibdev.create_cq = i40iw_create_cq;
  2475. iwibdev->ibdev.destroy_cq = i40iw_destroy_cq;
  2476. iwibdev->ibdev.get_dma_mr = i40iw_get_dma_mr;
  2477. iwibdev->ibdev.reg_user_mr = i40iw_reg_user_mr;
  2478. iwibdev->ibdev.dereg_mr = i40iw_dereg_mr;
  2479. iwibdev->ibdev.alloc_hw_stats = i40iw_alloc_hw_stats;
  2480. iwibdev->ibdev.get_hw_stats = i40iw_get_hw_stats;
  2481. iwibdev->ibdev.query_device = i40iw_query_device;
  2482. iwibdev->ibdev.create_ah = i40iw_create_ah;
  2483. iwibdev->ibdev.destroy_ah = i40iw_destroy_ah;
  2484. iwibdev->ibdev.drain_sq = i40iw_drain_sq;
  2485. iwibdev->ibdev.drain_rq = i40iw_drain_rq;
  2486. iwibdev->ibdev.alloc_mr = i40iw_alloc_mr;
  2487. iwibdev->ibdev.map_mr_sg = i40iw_map_mr_sg;
  2488. iwibdev->ibdev.iwcm = kzalloc(sizeof(*iwibdev->ibdev.iwcm), GFP_KERNEL);
  2489. if (!iwibdev->ibdev.iwcm) {
  2490. ib_dealloc_device(&iwibdev->ibdev);
  2491. return NULL;
  2492. }
  2493. iwibdev->ibdev.iwcm->add_ref = i40iw_add_ref;
  2494. iwibdev->ibdev.iwcm->rem_ref = i40iw_rem_ref;
  2495. iwibdev->ibdev.iwcm->get_qp = i40iw_get_qp;
  2496. iwibdev->ibdev.iwcm->connect = i40iw_connect;
  2497. iwibdev->ibdev.iwcm->accept = i40iw_accept;
  2498. iwibdev->ibdev.iwcm->reject = i40iw_reject;
  2499. iwibdev->ibdev.iwcm->create_listen = i40iw_create_listen;
  2500. iwibdev->ibdev.iwcm->destroy_listen = i40iw_destroy_listen;
  2501. memcpy(iwibdev->ibdev.iwcm->ifname, netdev->name,
  2502. sizeof(iwibdev->ibdev.iwcm->ifname));
  2503. iwibdev->ibdev.get_port_immutable = i40iw_port_immutable;
  2504. iwibdev->ibdev.get_dev_fw_str = i40iw_get_dev_fw_str;
  2505. iwibdev->ibdev.poll_cq = i40iw_poll_cq;
  2506. iwibdev->ibdev.req_notify_cq = i40iw_req_notify_cq;
  2507. iwibdev->ibdev.post_send = i40iw_post_send;
  2508. iwibdev->ibdev.post_recv = i40iw_post_recv;
  2509. return iwibdev;
  2510. }
  2511. /**
  2512. * i40iw_port_ibevent - indicate port event
  2513. * @iwdev: iwarp device
  2514. */
  2515. void i40iw_port_ibevent(struct i40iw_device *iwdev)
  2516. {
  2517. struct i40iw_ib_device *iwibdev = iwdev->iwibdev;
  2518. struct ib_event event;
  2519. event.device = &iwibdev->ibdev;
  2520. event.element.port_num = 1;
  2521. event.event = iwdev->iw_status ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
  2522. ib_dispatch_event(&event);
  2523. }
  2524. /**
  2525. * i40iw_unregister_rdma_device - unregister of iwarp from IB
  2526. * @iwibdev: rdma device ptr
  2527. */
  2528. static void i40iw_unregister_rdma_device(struct i40iw_ib_device *iwibdev)
  2529. {
  2530. int i;
  2531. for (i = 0; i < ARRAY_SIZE(i40iw_dev_attributes); ++i)
  2532. device_remove_file(&iwibdev->ibdev.dev,
  2533. i40iw_dev_attributes[i]);
  2534. ib_unregister_device(&iwibdev->ibdev);
  2535. }
  2536. /**
  2537. * i40iw_destroy_rdma_device - destroy rdma device and free resources
  2538. * @iwibdev: IB device ptr
  2539. */
  2540. void i40iw_destroy_rdma_device(struct i40iw_ib_device *iwibdev)
  2541. {
  2542. if (!iwibdev)
  2543. return;
  2544. i40iw_unregister_rdma_device(iwibdev);
  2545. kfree(iwibdev->ibdev.iwcm);
  2546. iwibdev->ibdev.iwcm = NULL;
  2547. wait_event_timeout(iwibdev->iwdev->close_wq,
  2548. !atomic64_read(&iwibdev->iwdev->use_count),
  2549. I40IW_EVENT_TIMEOUT);
  2550. ib_dealloc_device(&iwibdev->ibdev);
  2551. }
  2552. /**
  2553. * i40iw_register_rdma_device - register iwarp device to IB
  2554. * @iwdev: iwarp device
  2555. */
  2556. int i40iw_register_rdma_device(struct i40iw_device *iwdev)
  2557. {
  2558. int i, ret;
  2559. struct i40iw_ib_device *iwibdev;
  2560. iwdev->iwibdev = i40iw_init_rdma_device(iwdev);
  2561. if (!iwdev->iwibdev)
  2562. return -ENOMEM;
  2563. iwibdev = iwdev->iwibdev;
  2564. ret = ib_register_device(&iwibdev->ibdev, NULL);
  2565. if (ret)
  2566. goto error;
  2567. for (i = 0; i < ARRAY_SIZE(i40iw_dev_attributes); ++i) {
  2568. ret =
  2569. device_create_file(&iwibdev->ibdev.dev,
  2570. i40iw_dev_attributes[i]);
  2571. if (ret) {
  2572. while (i > 0) {
  2573. i--;
  2574. device_remove_file(&iwibdev->ibdev.dev, i40iw_dev_attributes[i]);
  2575. }
  2576. ib_unregister_device(&iwibdev->ibdev);
  2577. goto error;
  2578. }
  2579. }
  2580. return 0;
  2581. error:
  2582. kfree(iwdev->iwibdev->ibdev.iwcm);
  2583. iwdev->iwibdev->ibdev.iwcm = NULL;
  2584. ib_dealloc_device(&iwdev->iwibdev->ibdev);
  2585. return ret;
  2586. }