hns_roce_main.c 25 KB

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  1. /*
  2. * Copyright (c) 2016 Hisilicon Limited.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/acpi.h>
  34. #include <linux/of_platform.h>
  35. #include <rdma/ib_addr.h>
  36. #include <rdma/ib_smi.h>
  37. #include <rdma/ib_user_verbs.h>
  38. #include <rdma/ib_cache.h>
  39. #include "hns_roce_common.h"
  40. #include "hns_roce_device.h"
  41. #include <rdma/hns-abi.h>
  42. #include "hns_roce_hem.h"
  43. /**
  44. * hns_get_gid_index - Get gid index.
  45. * @hr_dev: pointer to structure hns_roce_dev.
  46. * @port: port, value range: 0 ~ MAX
  47. * @gid_index: gid_index, value range: 0 ~ MAX
  48. * Description:
  49. * N ports shared gids, allocation method as follow:
  50. * GID[0][0], GID[1][0],.....GID[N - 1][0],
  51. * GID[0][0], GID[1][0],.....GID[N - 1][0],
  52. * And so on
  53. */
  54. int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
  55. {
  56. return gid_index * hr_dev->caps.num_ports + port;
  57. }
  58. static void hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
  59. {
  60. u8 phy_port;
  61. u32 i = 0;
  62. if (!memcmp(hr_dev->dev_addr[port], addr, MAC_ADDR_OCTET_NUM))
  63. return;
  64. for (i = 0; i < MAC_ADDR_OCTET_NUM; i++)
  65. hr_dev->dev_addr[port][i] = addr[i];
  66. phy_port = hr_dev->iboe.phy_port[port];
  67. hr_dev->hw->set_mac(hr_dev, phy_port, addr);
  68. }
  69. static int hns_roce_add_gid(struct ib_device *device, u8 port_num,
  70. unsigned int index, const union ib_gid *gid,
  71. const struct ib_gid_attr *attr, void **context)
  72. {
  73. struct hns_roce_dev *hr_dev = to_hr_dev(device);
  74. u8 port = port_num - 1;
  75. unsigned long flags;
  76. if (port >= hr_dev->caps.num_ports)
  77. return -EINVAL;
  78. spin_lock_irqsave(&hr_dev->iboe.lock, flags);
  79. hr_dev->hw->set_gid(hr_dev, port, index, (union ib_gid *)gid);
  80. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  81. return 0;
  82. }
  83. static int hns_roce_del_gid(struct ib_device *device, u8 port_num,
  84. unsigned int index, void **context)
  85. {
  86. struct hns_roce_dev *hr_dev = to_hr_dev(device);
  87. union ib_gid zgid = { {0} };
  88. u8 port = port_num - 1;
  89. unsigned long flags;
  90. if (port >= hr_dev->caps.num_ports)
  91. return -EINVAL;
  92. spin_lock_irqsave(&hr_dev->iboe.lock, flags);
  93. hr_dev->hw->set_gid(hr_dev, port, index, &zgid);
  94. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  95. return 0;
  96. }
  97. static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
  98. unsigned long event)
  99. {
  100. struct device *dev = &hr_dev->pdev->dev;
  101. struct net_device *netdev;
  102. netdev = hr_dev->iboe.netdevs[port];
  103. if (!netdev) {
  104. dev_err(dev, "port(%d) can't find netdev\n", port);
  105. return -ENODEV;
  106. }
  107. spin_lock_bh(&hr_dev->iboe.lock);
  108. switch (event) {
  109. case NETDEV_UP:
  110. case NETDEV_CHANGE:
  111. case NETDEV_REGISTER:
  112. case NETDEV_CHANGEADDR:
  113. hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
  114. break;
  115. case NETDEV_DOWN:
  116. /*
  117. * In v1 engine, only support all ports closed together.
  118. */
  119. break;
  120. default:
  121. dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
  122. break;
  123. }
  124. spin_unlock_bh(&hr_dev->iboe.lock);
  125. return 0;
  126. }
  127. static int hns_roce_netdev_event(struct notifier_block *self,
  128. unsigned long event, void *ptr)
  129. {
  130. struct net_device *dev = netdev_notifier_info_to_dev(ptr);
  131. struct hns_roce_ib_iboe *iboe = NULL;
  132. struct hns_roce_dev *hr_dev = NULL;
  133. u8 port = 0;
  134. int ret = 0;
  135. hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
  136. iboe = &hr_dev->iboe;
  137. for (port = 0; port < hr_dev->caps.num_ports; port++) {
  138. if (dev == iboe->netdevs[port]) {
  139. ret = handle_en_event(hr_dev, port, event);
  140. if (ret)
  141. return NOTIFY_DONE;
  142. break;
  143. }
  144. }
  145. return NOTIFY_DONE;
  146. }
  147. static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
  148. {
  149. u8 i;
  150. for (i = 0; i < hr_dev->caps.num_ports; i++) {
  151. hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i],
  152. hr_dev->caps.max_mtu);
  153. hns_roce_set_mac(hr_dev, i, hr_dev->iboe.netdevs[i]->dev_addr);
  154. }
  155. return 0;
  156. }
  157. static int hns_roce_query_device(struct ib_device *ib_dev,
  158. struct ib_device_attr *props,
  159. struct ib_udata *uhw)
  160. {
  161. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  162. memset(props, 0, sizeof(*props));
  163. props->sys_image_guid = hr_dev->sys_image_guid;
  164. props->max_mr_size = (u64)(~(0ULL));
  165. props->page_size_cap = hr_dev->caps.page_size_cap;
  166. props->vendor_id = hr_dev->vendor_id;
  167. props->vendor_part_id = hr_dev->vendor_part_id;
  168. props->hw_ver = hr_dev->hw_rev;
  169. props->max_qp = hr_dev->caps.num_qps;
  170. props->max_qp_wr = hr_dev->caps.max_wqes;
  171. props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
  172. IB_DEVICE_RC_RNR_NAK_GEN;
  173. props->max_sge = hr_dev->caps.max_sq_sg;
  174. props->max_sge_rd = 1;
  175. props->max_cq = hr_dev->caps.num_cqs;
  176. props->max_cqe = hr_dev->caps.max_cqes;
  177. props->max_mr = hr_dev->caps.num_mtpts;
  178. props->max_pd = hr_dev->caps.num_pds;
  179. props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
  180. props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
  181. props->atomic_cap = IB_ATOMIC_NONE;
  182. props->max_pkeys = 1;
  183. props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
  184. return 0;
  185. }
  186. static struct net_device *hns_roce_get_netdev(struct ib_device *ib_dev,
  187. u8 port_num)
  188. {
  189. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  190. struct net_device *ndev;
  191. if (port_num < 1 || port_num > hr_dev->caps.num_ports)
  192. return NULL;
  193. rcu_read_lock();
  194. ndev = hr_dev->iboe.netdevs[port_num - 1];
  195. if (ndev)
  196. dev_hold(ndev);
  197. rcu_read_unlock();
  198. return ndev;
  199. }
  200. static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num,
  201. struct ib_port_attr *props)
  202. {
  203. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  204. struct device *dev = &hr_dev->pdev->dev;
  205. struct net_device *net_dev;
  206. unsigned long flags;
  207. enum ib_mtu mtu;
  208. u8 port;
  209. assert(port_num > 0);
  210. port = port_num - 1;
  211. memset(props, 0, sizeof(*props));
  212. props->max_mtu = hr_dev->caps.max_mtu;
  213. props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
  214. props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
  215. IB_PORT_VENDOR_CLASS_SUP |
  216. IB_PORT_BOOT_MGMT_SUP;
  217. props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
  218. props->pkey_tbl_len = 1;
  219. props->active_width = IB_WIDTH_4X;
  220. props->active_speed = 1;
  221. spin_lock_irqsave(&hr_dev->iboe.lock, flags);
  222. net_dev = hr_dev->iboe.netdevs[port];
  223. if (!net_dev) {
  224. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  225. dev_err(dev, "find netdev %d failed!\r\n", port);
  226. return -EINVAL;
  227. }
  228. mtu = iboe_get_mtu(net_dev->mtu);
  229. props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
  230. props->state = (netif_running(net_dev) && netif_carrier_ok(net_dev)) ?
  231. IB_PORT_ACTIVE : IB_PORT_DOWN;
  232. props->phys_state = (props->state == IB_PORT_ACTIVE) ? 5 : 3;
  233. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  234. return 0;
  235. }
  236. static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
  237. u8 port_num)
  238. {
  239. return IB_LINK_LAYER_ETHERNET;
  240. }
  241. static int hns_roce_query_gid(struct ib_device *ib_dev, u8 port_num, int index,
  242. union ib_gid *gid)
  243. {
  244. return 0;
  245. }
  246. static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index,
  247. u16 *pkey)
  248. {
  249. *pkey = PKEY_ID;
  250. return 0;
  251. }
  252. static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
  253. struct ib_device_modify *props)
  254. {
  255. unsigned long flags;
  256. if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
  257. return -EOPNOTSUPP;
  258. if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
  259. spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
  260. memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
  261. spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
  262. }
  263. return 0;
  264. }
  265. static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask,
  266. struct ib_port_modify *props)
  267. {
  268. return 0;
  269. }
  270. static struct ib_ucontext *hns_roce_alloc_ucontext(struct ib_device *ib_dev,
  271. struct ib_udata *udata)
  272. {
  273. int ret = 0;
  274. struct hns_roce_ucontext *context;
  275. struct hns_roce_ib_alloc_ucontext_resp resp;
  276. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  277. resp.qp_tab_size = hr_dev->caps.num_qps;
  278. context = kmalloc(sizeof(*context), GFP_KERNEL);
  279. if (!context)
  280. return ERR_PTR(-ENOMEM);
  281. ret = hns_roce_uar_alloc(hr_dev, &context->uar);
  282. if (ret)
  283. goto error_fail_uar_alloc;
  284. ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
  285. if (ret)
  286. goto error_fail_copy_to_udata;
  287. return &context->ibucontext;
  288. error_fail_copy_to_udata:
  289. hns_roce_uar_free(hr_dev, &context->uar);
  290. error_fail_uar_alloc:
  291. kfree(context);
  292. return ERR_PTR(ret);
  293. }
  294. static int hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
  295. {
  296. struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
  297. hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar);
  298. kfree(context);
  299. return 0;
  300. }
  301. static int hns_roce_mmap(struct ib_ucontext *context,
  302. struct vm_area_struct *vma)
  303. {
  304. struct hns_roce_dev *hr_dev = to_hr_dev(context->device);
  305. if (((vma->vm_end - vma->vm_start) % PAGE_SIZE) != 0)
  306. return -EINVAL;
  307. if (vma->vm_pgoff == 0) {
  308. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  309. if (io_remap_pfn_range(vma, vma->vm_start,
  310. to_hr_ucontext(context)->uar.pfn,
  311. PAGE_SIZE, vma->vm_page_prot))
  312. return -EAGAIN;
  313. } else if (vma->vm_pgoff == 1 && hr_dev->hw_rev == HNS_ROCE_HW_VER1) {
  314. /* vm_pgoff: 1 -- TPTR */
  315. if (io_remap_pfn_range(vma, vma->vm_start,
  316. hr_dev->tptr_dma_addr >> PAGE_SHIFT,
  317. hr_dev->tptr_size,
  318. vma->vm_page_prot))
  319. return -EAGAIN;
  320. } else
  321. return -EINVAL;
  322. return 0;
  323. }
  324. static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num,
  325. struct ib_port_immutable *immutable)
  326. {
  327. struct ib_port_attr attr;
  328. int ret;
  329. ret = hns_roce_query_port(ib_dev, port_num, &attr);
  330. if (ret)
  331. return ret;
  332. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  333. immutable->gid_tbl_len = attr.gid_tbl_len;
  334. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
  335. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  336. return 0;
  337. }
  338. static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
  339. {
  340. struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
  341. unregister_inetaddr_notifier(&iboe->nb_inet);
  342. unregister_netdevice_notifier(&iboe->nb);
  343. ib_unregister_device(&hr_dev->ib_dev);
  344. }
  345. static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
  346. {
  347. int ret;
  348. struct hns_roce_ib_iboe *iboe = NULL;
  349. struct ib_device *ib_dev = NULL;
  350. struct device *dev = &hr_dev->pdev->dev;
  351. iboe = &hr_dev->iboe;
  352. spin_lock_init(&iboe->lock);
  353. ib_dev = &hr_dev->ib_dev;
  354. strlcpy(ib_dev->name, "hns_%d", IB_DEVICE_NAME_MAX);
  355. ib_dev->owner = THIS_MODULE;
  356. ib_dev->node_type = RDMA_NODE_IB_CA;
  357. ib_dev->dma_device = dev;
  358. ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
  359. ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
  360. ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
  361. ib_dev->uverbs_abi_ver = 1;
  362. ib_dev->uverbs_cmd_mask =
  363. (1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) |
  364. (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  365. (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) |
  366. (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) |
  367. (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) |
  368. (1ULL << IB_USER_VERBS_CMD_REG_MR) |
  369. (1ULL << IB_USER_VERBS_CMD_DEREG_MR) |
  370. (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  371. (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) |
  372. (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) |
  373. (1ULL << IB_USER_VERBS_CMD_CREATE_QP) |
  374. (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) |
  375. (1ULL << IB_USER_VERBS_CMD_QUERY_QP) |
  376. (1ULL << IB_USER_VERBS_CMD_DESTROY_QP);
  377. /* HCA||device||port */
  378. ib_dev->modify_device = hns_roce_modify_device;
  379. ib_dev->query_device = hns_roce_query_device;
  380. ib_dev->query_port = hns_roce_query_port;
  381. ib_dev->modify_port = hns_roce_modify_port;
  382. ib_dev->get_link_layer = hns_roce_get_link_layer;
  383. ib_dev->get_netdev = hns_roce_get_netdev;
  384. ib_dev->query_gid = hns_roce_query_gid;
  385. ib_dev->add_gid = hns_roce_add_gid;
  386. ib_dev->del_gid = hns_roce_del_gid;
  387. ib_dev->query_pkey = hns_roce_query_pkey;
  388. ib_dev->alloc_ucontext = hns_roce_alloc_ucontext;
  389. ib_dev->dealloc_ucontext = hns_roce_dealloc_ucontext;
  390. ib_dev->mmap = hns_roce_mmap;
  391. /* PD */
  392. ib_dev->alloc_pd = hns_roce_alloc_pd;
  393. ib_dev->dealloc_pd = hns_roce_dealloc_pd;
  394. /* AH */
  395. ib_dev->create_ah = hns_roce_create_ah;
  396. ib_dev->query_ah = hns_roce_query_ah;
  397. ib_dev->destroy_ah = hns_roce_destroy_ah;
  398. /* QP */
  399. ib_dev->create_qp = hns_roce_create_qp;
  400. ib_dev->modify_qp = hns_roce_modify_qp;
  401. ib_dev->query_qp = hr_dev->hw->query_qp;
  402. ib_dev->destroy_qp = hr_dev->hw->destroy_qp;
  403. ib_dev->post_send = hr_dev->hw->post_send;
  404. ib_dev->post_recv = hr_dev->hw->post_recv;
  405. /* CQ */
  406. ib_dev->create_cq = hns_roce_ib_create_cq;
  407. ib_dev->destroy_cq = hns_roce_ib_destroy_cq;
  408. ib_dev->req_notify_cq = hr_dev->hw->req_notify_cq;
  409. ib_dev->poll_cq = hr_dev->hw->poll_cq;
  410. /* MR */
  411. ib_dev->get_dma_mr = hns_roce_get_dma_mr;
  412. ib_dev->reg_user_mr = hns_roce_reg_user_mr;
  413. ib_dev->dereg_mr = hns_roce_dereg_mr;
  414. /* OTHERS */
  415. ib_dev->get_port_immutable = hns_roce_port_immutable;
  416. ret = ib_register_device(ib_dev, NULL);
  417. if (ret) {
  418. dev_err(dev, "ib_register_device failed!\n");
  419. return ret;
  420. }
  421. ret = hns_roce_setup_mtu_mac(hr_dev);
  422. if (ret) {
  423. dev_err(dev, "setup_mtu_mac failed!\n");
  424. goto error_failed_setup_mtu_mac;
  425. }
  426. iboe->nb.notifier_call = hns_roce_netdev_event;
  427. ret = register_netdevice_notifier(&iboe->nb);
  428. if (ret) {
  429. dev_err(dev, "register_netdevice_notifier failed!\n");
  430. goto error_failed_setup_mtu_mac;
  431. }
  432. return 0;
  433. error_failed_setup_mtu_mac:
  434. ib_unregister_device(ib_dev);
  435. return ret;
  436. }
  437. static const struct of_device_id hns_roce_of_match[] = {
  438. { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
  439. {},
  440. };
  441. MODULE_DEVICE_TABLE(of, hns_roce_of_match);
  442. static const struct acpi_device_id hns_roce_acpi_match[] = {
  443. { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
  444. {},
  445. };
  446. MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
  447. static int hns_roce_node_match(struct device *dev, void *fwnode)
  448. {
  449. return dev->fwnode == fwnode;
  450. }
  451. static struct
  452. platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
  453. {
  454. struct device *dev;
  455. /* get the 'device'corresponding to matching 'fwnode' */
  456. dev = bus_find_device(&platform_bus_type, NULL,
  457. fwnode, hns_roce_node_match);
  458. /* get the platform device */
  459. return dev ? to_platform_device(dev) : NULL;
  460. }
  461. static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
  462. {
  463. int i;
  464. int ret;
  465. u8 phy_port;
  466. int port_cnt = 0;
  467. struct device *dev = &hr_dev->pdev->dev;
  468. struct device_node *net_node;
  469. struct net_device *netdev = NULL;
  470. struct platform_device *pdev = NULL;
  471. struct resource *res;
  472. /* check if we are compatible with the underlying SoC */
  473. if (dev_of_node(dev)) {
  474. const struct of_device_id *of_id;
  475. of_id = of_match_node(hns_roce_of_match, dev->of_node);
  476. if (!of_id) {
  477. dev_err(dev, "device is not compatible!\n");
  478. return -ENXIO;
  479. }
  480. hr_dev->hw = (struct hns_roce_hw *)of_id->data;
  481. if (!hr_dev->hw) {
  482. dev_err(dev, "couldn't get H/W specific DT data!\n");
  483. return -ENXIO;
  484. }
  485. } else if (is_acpi_device_node(dev->fwnode)) {
  486. const struct acpi_device_id *acpi_id;
  487. acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
  488. if (!acpi_id) {
  489. dev_err(dev, "device is not compatible!\n");
  490. return -ENXIO;
  491. }
  492. hr_dev->hw = (struct hns_roce_hw *) acpi_id->driver_data;
  493. if (!hr_dev->hw) {
  494. dev_err(dev, "couldn't get H/W specific ACPI data!\n");
  495. return -ENXIO;
  496. }
  497. } else {
  498. dev_err(dev, "can't read compatibility data from DT or ACPI\n");
  499. return -ENXIO;
  500. }
  501. /* get the mapped register base address */
  502. res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0);
  503. if (!res) {
  504. dev_err(dev, "memory resource not found!\n");
  505. return -EINVAL;
  506. }
  507. hr_dev->reg_base = devm_ioremap_resource(dev, res);
  508. if (IS_ERR(hr_dev->reg_base))
  509. return PTR_ERR(hr_dev->reg_base);
  510. /* read the node_guid of IB device from the DT or ACPI */
  511. ret = device_property_read_u8_array(dev, "node-guid",
  512. (u8 *)&hr_dev->ib_dev.node_guid,
  513. GUID_LEN);
  514. if (ret) {
  515. dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
  516. return ret;
  517. }
  518. /* get the RoCE associated ethernet ports or netdevices */
  519. for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
  520. if (dev_of_node(dev)) {
  521. net_node = of_parse_phandle(dev->of_node, "eth-handle",
  522. i);
  523. if (!net_node)
  524. continue;
  525. pdev = of_find_device_by_node(net_node);
  526. } else if (is_acpi_device_node(dev->fwnode)) {
  527. struct acpi_reference_args args;
  528. struct fwnode_handle *fwnode;
  529. ret = acpi_node_get_property_reference(dev->fwnode,
  530. "eth-handle",
  531. i, &args);
  532. if (ret)
  533. continue;
  534. fwnode = acpi_fwnode_handle(args.adev);
  535. pdev = hns_roce_find_pdev(fwnode);
  536. } else {
  537. dev_err(dev, "cannot read data from DT or ACPI\n");
  538. return -ENXIO;
  539. }
  540. if (pdev) {
  541. netdev = platform_get_drvdata(pdev);
  542. phy_port = (u8)i;
  543. if (netdev) {
  544. hr_dev->iboe.netdevs[port_cnt] = netdev;
  545. hr_dev->iboe.phy_port[port_cnt] = phy_port;
  546. } else {
  547. dev_err(dev, "no netdev found with pdev %s\n",
  548. pdev->name);
  549. return -ENODEV;
  550. }
  551. port_cnt++;
  552. }
  553. }
  554. if (port_cnt == 0) {
  555. dev_err(dev, "unable to get eth-handle for available ports!\n");
  556. return -EINVAL;
  557. }
  558. hr_dev->caps.num_ports = port_cnt;
  559. /* cmd issue mode: 0 is poll, 1 is event */
  560. hr_dev->cmd_mod = 1;
  561. hr_dev->loop_idc = 0;
  562. /* read the interrupt names from the DT or ACPI */
  563. ret = device_property_read_string_array(dev, "interrupt-names",
  564. hr_dev->irq_names,
  565. HNS_ROCE_MAX_IRQ_NUM);
  566. if (ret < 0) {
  567. dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
  568. return ret;
  569. }
  570. /* fetch the interrupt numbers */
  571. for (i = 0; i < HNS_ROCE_MAX_IRQ_NUM; i++) {
  572. hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
  573. if (hr_dev->irq[i] <= 0) {
  574. dev_err(dev, "platform get of irq[=%d] failed!\n", i);
  575. return -EINVAL;
  576. }
  577. }
  578. return 0;
  579. }
  580. static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
  581. {
  582. int ret;
  583. struct device *dev = &hr_dev->pdev->dev;
  584. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table,
  585. HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz,
  586. hr_dev->caps.num_mtt_segs, 1);
  587. if (ret) {
  588. dev_err(dev, "Failed to init MTT context memory, aborting.\n");
  589. return ret;
  590. }
  591. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
  592. HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
  593. hr_dev->caps.num_mtpts, 1);
  594. if (ret) {
  595. dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
  596. goto err_unmap_mtt;
  597. }
  598. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
  599. HEM_TYPE_QPC, hr_dev->caps.qpc_entry_sz,
  600. hr_dev->caps.num_qps, 1);
  601. if (ret) {
  602. dev_err(dev, "Failed to init QP context memory, aborting.\n");
  603. goto err_unmap_dmpt;
  604. }
  605. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
  606. HEM_TYPE_IRRL,
  607. hr_dev->caps.irrl_entry_sz *
  608. hr_dev->caps.max_qp_init_rdma,
  609. hr_dev->caps.num_qps, 1);
  610. if (ret) {
  611. dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
  612. goto err_unmap_qp;
  613. }
  614. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
  615. HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
  616. hr_dev->caps.num_cqs, 1);
  617. if (ret) {
  618. dev_err(dev, "Failed to init CQ context memory, aborting.\n");
  619. goto err_unmap_irrl;
  620. }
  621. return 0;
  622. err_unmap_irrl:
  623. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
  624. err_unmap_qp:
  625. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
  626. err_unmap_dmpt:
  627. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
  628. err_unmap_mtt:
  629. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);
  630. return ret;
  631. }
  632. /**
  633. * hns_roce_setup_hca - setup host channel adapter
  634. * @hr_dev: pointer to hns roce device
  635. * Return : int
  636. */
  637. static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
  638. {
  639. int ret;
  640. struct device *dev = &hr_dev->pdev->dev;
  641. spin_lock_init(&hr_dev->sm_lock);
  642. spin_lock_init(&hr_dev->bt_cmd_lock);
  643. ret = hns_roce_init_uar_table(hr_dev);
  644. if (ret) {
  645. dev_err(dev, "Failed to initialize uar table. aborting\n");
  646. return ret;
  647. }
  648. ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
  649. if (ret) {
  650. dev_err(dev, "Failed to allocate priv_uar.\n");
  651. goto err_uar_table_free;
  652. }
  653. ret = hns_roce_init_pd_table(hr_dev);
  654. if (ret) {
  655. dev_err(dev, "Failed to init protected domain table.\n");
  656. goto err_uar_alloc_free;
  657. }
  658. ret = hns_roce_init_mr_table(hr_dev);
  659. if (ret) {
  660. dev_err(dev, "Failed to init memory region table.\n");
  661. goto err_pd_table_free;
  662. }
  663. ret = hns_roce_init_cq_table(hr_dev);
  664. if (ret) {
  665. dev_err(dev, "Failed to init completion queue table.\n");
  666. goto err_mr_table_free;
  667. }
  668. ret = hns_roce_init_qp_table(hr_dev);
  669. if (ret) {
  670. dev_err(dev, "Failed to init queue pair table.\n");
  671. goto err_cq_table_free;
  672. }
  673. return 0;
  674. err_cq_table_free:
  675. hns_roce_cleanup_cq_table(hr_dev);
  676. err_mr_table_free:
  677. hns_roce_cleanup_mr_table(hr_dev);
  678. err_pd_table_free:
  679. hns_roce_cleanup_pd_table(hr_dev);
  680. err_uar_alloc_free:
  681. hns_roce_uar_free(hr_dev, &hr_dev->priv_uar);
  682. err_uar_table_free:
  683. hns_roce_cleanup_uar_table(hr_dev);
  684. return ret;
  685. }
  686. /**
  687. * hns_roce_probe - RoCE driver entrance
  688. * @pdev: pointer to platform device
  689. * Return : int
  690. *
  691. */
  692. static int hns_roce_probe(struct platform_device *pdev)
  693. {
  694. int ret;
  695. struct hns_roce_dev *hr_dev;
  696. struct device *dev = &pdev->dev;
  697. hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev));
  698. if (!hr_dev)
  699. return -ENOMEM;
  700. hr_dev->pdev = pdev;
  701. platform_set_drvdata(pdev, hr_dev);
  702. if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
  703. dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
  704. dev_err(dev, "Not usable DMA addressing mode\n");
  705. ret = -EIO;
  706. goto error_failed_get_cfg;
  707. }
  708. ret = hns_roce_get_cfg(hr_dev);
  709. if (ret) {
  710. dev_err(dev, "Get Configuration failed!\n");
  711. goto error_failed_get_cfg;
  712. }
  713. ret = hr_dev->hw->reset(hr_dev, true);
  714. if (ret) {
  715. dev_err(dev, "Reset RoCE engine failed!\n");
  716. goto error_failed_get_cfg;
  717. }
  718. hr_dev->hw->hw_profile(hr_dev);
  719. ret = hns_roce_cmd_init(hr_dev);
  720. if (ret) {
  721. dev_err(dev, "cmd init failed!\n");
  722. goto error_failed_cmd_init;
  723. }
  724. ret = hns_roce_init_eq_table(hr_dev);
  725. if (ret) {
  726. dev_err(dev, "eq init failed!\n");
  727. goto error_failed_eq_table;
  728. }
  729. if (hr_dev->cmd_mod) {
  730. ret = hns_roce_cmd_use_events(hr_dev);
  731. if (ret) {
  732. dev_err(dev, "Switch to event-driven cmd failed!\n");
  733. goto error_failed_use_event;
  734. }
  735. }
  736. ret = hns_roce_init_hem(hr_dev);
  737. if (ret) {
  738. dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
  739. goto error_failed_init_hem;
  740. }
  741. ret = hns_roce_setup_hca(hr_dev);
  742. if (ret) {
  743. dev_err(dev, "setup hca failed!\n");
  744. goto error_failed_setup_hca;
  745. }
  746. ret = hr_dev->hw->hw_init(hr_dev);
  747. if (ret) {
  748. dev_err(dev, "hw_init failed!\n");
  749. goto error_failed_engine_init;
  750. }
  751. ret = hns_roce_register_device(hr_dev);
  752. if (ret)
  753. goto error_failed_register_device;
  754. return 0;
  755. error_failed_register_device:
  756. hr_dev->hw->hw_exit(hr_dev);
  757. error_failed_engine_init:
  758. hns_roce_cleanup_bitmap(hr_dev);
  759. error_failed_setup_hca:
  760. hns_roce_cleanup_hem(hr_dev);
  761. error_failed_init_hem:
  762. if (hr_dev->cmd_mod)
  763. hns_roce_cmd_use_polling(hr_dev);
  764. error_failed_use_event:
  765. hns_roce_cleanup_eq_table(hr_dev);
  766. error_failed_eq_table:
  767. hns_roce_cmd_cleanup(hr_dev);
  768. error_failed_cmd_init:
  769. ret = hr_dev->hw->reset(hr_dev, false);
  770. if (ret)
  771. dev_err(&hr_dev->pdev->dev, "roce_engine reset fail\n");
  772. error_failed_get_cfg:
  773. ib_dealloc_device(&hr_dev->ib_dev);
  774. return ret;
  775. }
  776. /**
  777. * hns_roce_remove - remove RoCE device
  778. * @pdev: pointer to platform device
  779. */
  780. static int hns_roce_remove(struct platform_device *pdev)
  781. {
  782. struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
  783. hns_roce_unregister_device(hr_dev);
  784. hr_dev->hw->hw_exit(hr_dev);
  785. hns_roce_cleanup_bitmap(hr_dev);
  786. hns_roce_cleanup_hem(hr_dev);
  787. if (hr_dev->cmd_mod)
  788. hns_roce_cmd_use_polling(hr_dev);
  789. hns_roce_cleanup_eq_table(hr_dev);
  790. hns_roce_cmd_cleanup(hr_dev);
  791. hr_dev->hw->reset(hr_dev, false);
  792. ib_dealloc_device(&hr_dev->ib_dev);
  793. return 0;
  794. }
  795. static struct platform_driver hns_roce_driver = {
  796. .probe = hns_roce_probe,
  797. .remove = hns_roce_remove,
  798. .driver = {
  799. .name = DRV_NAME,
  800. .of_match_table = hns_roce_of_match,
  801. .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
  802. },
  803. };
  804. module_platform_driver(hns_roce_driver);
  805. MODULE_LICENSE("Dual BSD/GPL");
  806. MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
  807. MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
  808. MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
  809. MODULE_DESCRIPTION("HNS RoCE Driver");