device.c 42 KB

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  1. /*
  2. * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/module.h>
  33. #include <linux/moduleparam.h>
  34. #include <linux/debugfs.h>
  35. #include <linux/vmalloc.h>
  36. #include <linux/math64.h>
  37. #include <rdma/ib_verbs.h>
  38. #include "iw_cxgb4.h"
  39. #define DRV_VERSION "0.1"
  40. MODULE_AUTHOR("Steve Wise");
  41. MODULE_DESCRIPTION("Chelsio T4/T5 RDMA Driver");
  42. MODULE_LICENSE("Dual BSD/GPL");
  43. MODULE_VERSION(DRV_VERSION);
  44. static int allow_db_fc_on_t5;
  45. module_param(allow_db_fc_on_t5, int, 0644);
  46. MODULE_PARM_DESC(allow_db_fc_on_t5,
  47. "Allow DB Flow Control on T5 (default = 0)");
  48. static int allow_db_coalescing_on_t5;
  49. module_param(allow_db_coalescing_on_t5, int, 0644);
  50. MODULE_PARM_DESC(allow_db_coalescing_on_t5,
  51. "Allow DB Coalescing on T5 (default = 0)");
  52. int c4iw_wr_log = 0;
  53. module_param(c4iw_wr_log, int, 0444);
  54. MODULE_PARM_DESC(c4iw_wr_log, "Enables logging of work request timing data.");
  55. static int c4iw_wr_log_size_order = 12;
  56. module_param(c4iw_wr_log_size_order, int, 0444);
  57. MODULE_PARM_DESC(c4iw_wr_log_size_order,
  58. "Number of entries (log2) in the work request timing log.");
  59. struct uld_ctx {
  60. struct list_head entry;
  61. struct cxgb4_lld_info lldi;
  62. struct c4iw_dev *dev;
  63. };
  64. static LIST_HEAD(uld_ctx_list);
  65. static DEFINE_MUTEX(dev_mutex);
  66. #define DB_FC_RESUME_SIZE 64
  67. #define DB_FC_RESUME_DELAY 1
  68. #define DB_FC_DRAIN_THRESH 0
  69. static struct dentry *c4iw_debugfs_root;
  70. struct c4iw_debugfs_data {
  71. struct c4iw_dev *devp;
  72. char *buf;
  73. int bufsize;
  74. int pos;
  75. };
  76. static int count_idrs(int id, void *p, void *data)
  77. {
  78. int *countp = data;
  79. *countp = *countp + 1;
  80. return 0;
  81. }
  82. static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count,
  83. loff_t *ppos)
  84. {
  85. struct c4iw_debugfs_data *d = file->private_data;
  86. return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos);
  87. }
  88. void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe)
  89. {
  90. struct wr_log_entry le;
  91. int idx;
  92. if (!wq->rdev->wr_log)
  93. return;
  94. idx = (atomic_inc_return(&wq->rdev->wr_log_idx) - 1) &
  95. (wq->rdev->wr_log_size - 1);
  96. le.poll_sge_ts = cxgb4_read_sge_timestamp(wq->rdev->lldi.ports[0]);
  97. getnstimeofday(&le.poll_host_ts);
  98. le.valid = 1;
  99. le.cqe_sge_ts = CQE_TS(cqe);
  100. if (SQ_TYPE(cqe)) {
  101. le.qid = wq->sq.qid;
  102. le.opcode = CQE_OPCODE(cqe);
  103. le.post_host_ts = wq->sq.sw_sq[wq->sq.cidx].host_ts;
  104. le.post_sge_ts = wq->sq.sw_sq[wq->sq.cidx].sge_ts;
  105. le.wr_id = CQE_WRID_SQ_IDX(cqe);
  106. } else {
  107. le.qid = wq->rq.qid;
  108. le.opcode = FW_RI_RECEIVE;
  109. le.post_host_ts = wq->rq.sw_rq[wq->rq.cidx].host_ts;
  110. le.post_sge_ts = wq->rq.sw_rq[wq->rq.cidx].sge_ts;
  111. le.wr_id = CQE_WRID_MSN(cqe);
  112. }
  113. wq->rdev->wr_log[idx] = le;
  114. }
  115. static int wr_log_show(struct seq_file *seq, void *v)
  116. {
  117. struct c4iw_dev *dev = seq->private;
  118. struct timespec prev_ts = {0, 0};
  119. struct wr_log_entry *lep;
  120. int prev_ts_set = 0;
  121. int idx, end;
  122. #define ts2ns(ts) div64_u64((ts) * dev->rdev.lldi.cclk_ps, 1000)
  123. idx = atomic_read(&dev->rdev.wr_log_idx) &
  124. (dev->rdev.wr_log_size - 1);
  125. end = idx - 1;
  126. if (end < 0)
  127. end = dev->rdev.wr_log_size - 1;
  128. lep = &dev->rdev.wr_log[idx];
  129. while (idx != end) {
  130. if (lep->valid) {
  131. if (!prev_ts_set) {
  132. prev_ts_set = 1;
  133. prev_ts = lep->poll_host_ts;
  134. }
  135. seq_printf(seq, "%04u: sec %lu nsec %lu qid %u opcode "
  136. "%u %s 0x%x host_wr_delta sec %lu nsec %lu "
  137. "post_sge_ts 0x%llx cqe_sge_ts 0x%llx "
  138. "poll_sge_ts 0x%llx post_poll_delta_ns %llu "
  139. "cqe_poll_delta_ns %llu\n",
  140. idx,
  141. timespec_sub(lep->poll_host_ts,
  142. prev_ts).tv_sec,
  143. timespec_sub(lep->poll_host_ts,
  144. prev_ts).tv_nsec,
  145. lep->qid, lep->opcode,
  146. lep->opcode == FW_RI_RECEIVE ?
  147. "msn" : "wrid",
  148. lep->wr_id,
  149. timespec_sub(lep->poll_host_ts,
  150. lep->post_host_ts).tv_sec,
  151. timespec_sub(lep->poll_host_ts,
  152. lep->post_host_ts).tv_nsec,
  153. lep->post_sge_ts, lep->cqe_sge_ts,
  154. lep->poll_sge_ts,
  155. ts2ns(lep->poll_sge_ts - lep->post_sge_ts),
  156. ts2ns(lep->poll_sge_ts - lep->cqe_sge_ts));
  157. prev_ts = lep->poll_host_ts;
  158. }
  159. idx++;
  160. if (idx > (dev->rdev.wr_log_size - 1))
  161. idx = 0;
  162. lep = &dev->rdev.wr_log[idx];
  163. }
  164. #undef ts2ns
  165. return 0;
  166. }
  167. static int wr_log_open(struct inode *inode, struct file *file)
  168. {
  169. return single_open(file, wr_log_show, inode->i_private);
  170. }
  171. static ssize_t wr_log_clear(struct file *file, const char __user *buf,
  172. size_t count, loff_t *pos)
  173. {
  174. struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
  175. int i;
  176. if (dev->rdev.wr_log)
  177. for (i = 0; i < dev->rdev.wr_log_size; i++)
  178. dev->rdev.wr_log[i].valid = 0;
  179. return count;
  180. }
  181. static const struct file_operations wr_log_debugfs_fops = {
  182. .owner = THIS_MODULE,
  183. .open = wr_log_open,
  184. .release = single_release,
  185. .read = seq_read,
  186. .llseek = seq_lseek,
  187. .write = wr_log_clear,
  188. };
  189. static int dump_qp(int id, void *p, void *data)
  190. {
  191. struct c4iw_qp *qp = p;
  192. struct c4iw_debugfs_data *qpd = data;
  193. int space;
  194. int cc;
  195. if (id != qp->wq.sq.qid)
  196. return 0;
  197. space = qpd->bufsize - qpd->pos - 1;
  198. if (space == 0)
  199. return 1;
  200. if (qp->ep) {
  201. if (qp->ep->com.local_addr.ss_family == AF_INET) {
  202. struct sockaddr_in *lsin = (struct sockaddr_in *)
  203. &qp->ep->com.cm_id->local_addr;
  204. struct sockaddr_in *rsin = (struct sockaddr_in *)
  205. &qp->ep->com.cm_id->remote_addr;
  206. struct sockaddr_in *mapped_lsin = (struct sockaddr_in *)
  207. &qp->ep->com.cm_id->m_local_addr;
  208. struct sockaddr_in *mapped_rsin = (struct sockaddr_in *)
  209. &qp->ep->com.cm_id->m_remote_addr;
  210. cc = snprintf(qpd->buf + qpd->pos, space,
  211. "rc qp sq id %u rq id %u state %u "
  212. "onchip %u ep tid %u state %u "
  213. "%pI4:%u/%u->%pI4:%u/%u\n",
  214. qp->wq.sq.qid, qp->wq.rq.qid,
  215. (int)qp->attr.state,
  216. qp->wq.sq.flags & T4_SQ_ONCHIP,
  217. qp->ep->hwtid, (int)qp->ep->com.state,
  218. &lsin->sin_addr, ntohs(lsin->sin_port),
  219. ntohs(mapped_lsin->sin_port),
  220. &rsin->sin_addr, ntohs(rsin->sin_port),
  221. ntohs(mapped_rsin->sin_port));
  222. } else {
  223. struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
  224. &qp->ep->com.cm_id->local_addr;
  225. struct sockaddr_in6 *rsin6 = (struct sockaddr_in6 *)
  226. &qp->ep->com.cm_id->remote_addr;
  227. struct sockaddr_in6 *mapped_lsin6 =
  228. (struct sockaddr_in6 *)
  229. &qp->ep->com.cm_id->m_local_addr;
  230. struct sockaddr_in6 *mapped_rsin6 =
  231. (struct sockaddr_in6 *)
  232. &qp->ep->com.cm_id->m_remote_addr;
  233. cc = snprintf(qpd->buf + qpd->pos, space,
  234. "rc qp sq id %u rq id %u state %u "
  235. "onchip %u ep tid %u state %u "
  236. "%pI6:%u/%u->%pI6:%u/%u\n",
  237. qp->wq.sq.qid, qp->wq.rq.qid,
  238. (int)qp->attr.state,
  239. qp->wq.sq.flags & T4_SQ_ONCHIP,
  240. qp->ep->hwtid, (int)qp->ep->com.state,
  241. &lsin6->sin6_addr,
  242. ntohs(lsin6->sin6_port),
  243. ntohs(mapped_lsin6->sin6_port),
  244. &rsin6->sin6_addr,
  245. ntohs(rsin6->sin6_port),
  246. ntohs(mapped_rsin6->sin6_port));
  247. }
  248. } else
  249. cc = snprintf(qpd->buf + qpd->pos, space,
  250. "qp sq id %u rq id %u state %u onchip %u\n",
  251. qp->wq.sq.qid, qp->wq.rq.qid,
  252. (int)qp->attr.state,
  253. qp->wq.sq.flags & T4_SQ_ONCHIP);
  254. if (cc < space)
  255. qpd->pos += cc;
  256. return 0;
  257. }
  258. static int qp_release(struct inode *inode, struct file *file)
  259. {
  260. struct c4iw_debugfs_data *qpd = file->private_data;
  261. if (!qpd) {
  262. printk(KERN_INFO "%s null qpd?\n", __func__);
  263. return 0;
  264. }
  265. vfree(qpd->buf);
  266. kfree(qpd);
  267. return 0;
  268. }
  269. static int qp_open(struct inode *inode, struct file *file)
  270. {
  271. struct c4iw_debugfs_data *qpd;
  272. int count = 1;
  273. qpd = kmalloc(sizeof *qpd, GFP_KERNEL);
  274. if (!qpd)
  275. return -ENOMEM;
  276. qpd->devp = inode->i_private;
  277. qpd->pos = 0;
  278. spin_lock_irq(&qpd->devp->lock);
  279. idr_for_each(&qpd->devp->qpidr, count_idrs, &count);
  280. spin_unlock_irq(&qpd->devp->lock);
  281. qpd->bufsize = count * 180;
  282. qpd->buf = vmalloc(qpd->bufsize);
  283. if (!qpd->buf) {
  284. kfree(qpd);
  285. return -ENOMEM;
  286. }
  287. spin_lock_irq(&qpd->devp->lock);
  288. idr_for_each(&qpd->devp->qpidr, dump_qp, qpd);
  289. spin_unlock_irq(&qpd->devp->lock);
  290. qpd->buf[qpd->pos++] = 0;
  291. file->private_data = qpd;
  292. return 0;
  293. }
  294. static const struct file_operations qp_debugfs_fops = {
  295. .owner = THIS_MODULE,
  296. .open = qp_open,
  297. .release = qp_release,
  298. .read = debugfs_read,
  299. .llseek = default_llseek,
  300. };
  301. static int dump_stag(int id, void *p, void *data)
  302. {
  303. struct c4iw_debugfs_data *stagd = data;
  304. int space;
  305. int cc;
  306. struct fw_ri_tpte tpte;
  307. int ret;
  308. space = stagd->bufsize - stagd->pos - 1;
  309. if (space == 0)
  310. return 1;
  311. ret = cxgb4_read_tpte(stagd->devp->rdev.lldi.ports[0], (u32)id<<8,
  312. (__be32 *)&tpte);
  313. if (ret) {
  314. dev_err(&stagd->devp->rdev.lldi.pdev->dev,
  315. "%s cxgb4_read_tpte err %d\n", __func__, ret);
  316. return ret;
  317. }
  318. cc = snprintf(stagd->buf + stagd->pos, space,
  319. "stag: idx 0x%x valid %d key 0x%x state %d pdid %d "
  320. "perm 0x%x ps %d len 0x%llx va 0x%llx\n",
  321. (u32)id<<8,
  322. FW_RI_TPTE_VALID_G(ntohl(tpte.valid_to_pdid)),
  323. FW_RI_TPTE_STAGKEY_G(ntohl(tpte.valid_to_pdid)),
  324. FW_RI_TPTE_STAGSTATE_G(ntohl(tpte.valid_to_pdid)),
  325. FW_RI_TPTE_PDID_G(ntohl(tpte.valid_to_pdid)),
  326. FW_RI_TPTE_PERM_G(ntohl(tpte.locread_to_qpid)),
  327. FW_RI_TPTE_PS_G(ntohl(tpte.locread_to_qpid)),
  328. ((u64)ntohl(tpte.len_hi) << 32) | ntohl(tpte.len_lo),
  329. ((u64)ntohl(tpte.va_hi) << 32) | ntohl(tpte.va_lo_fbo));
  330. if (cc < space)
  331. stagd->pos += cc;
  332. return 0;
  333. }
  334. static int stag_release(struct inode *inode, struct file *file)
  335. {
  336. struct c4iw_debugfs_data *stagd = file->private_data;
  337. if (!stagd) {
  338. printk(KERN_INFO "%s null stagd?\n", __func__);
  339. return 0;
  340. }
  341. vfree(stagd->buf);
  342. kfree(stagd);
  343. return 0;
  344. }
  345. static int stag_open(struct inode *inode, struct file *file)
  346. {
  347. struct c4iw_debugfs_data *stagd;
  348. int ret = 0;
  349. int count = 1;
  350. stagd = kmalloc(sizeof *stagd, GFP_KERNEL);
  351. if (!stagd) {
  352. ret = -ENOMEM;
  353. goto out;
  354. }
  355. stagd->devp = inode->i_private;
  356. stagd->pos = 0;
  357. spin_lock_irq(&stagd->devp->lock);
  358. idr_for_each(&stagd->devp->mmidr, count_idrs, &count);
  359. spin_unlock_irq(&stagd->devp->lock);
  360. stagd->bufsize = count * 256;
  361. stagd->buf = vmalloc(stagd->bufsize);
  362. if (!stagd->buf) {
  363. ret = -ENOMEM;
  364. goto err1;
  365. }
  366. spin_lock_irq(&stagd->devp->lock);
  367. idr_for_each(&stagd->devp->mmidr, dump_stag, stagd);
  368. spin_unlock_irq(&stagd->devp->lock);
  369. stagd->buf[stagd->pos++] = 0;
  370. file->private_data = stagd;
  371. goto out;
  372. err1:
  373. kfree(stagd);
  374. out:
  375. return ret;
  376. }
  377. static const struct file_operations stag_debugfs_fops = {
  378. .owner = THIS_MODULE,
  379. .open = stag_open,
  380. .release = stag_release,
  381. .read = debugfs_read,
  382. .llseek = default_llseek,
  383. };
  384. static char *db_state_str[] = {"NORMAL", "FLOW_CONTROL", "RECOVERY", "STOPPED"};
  385. static int stats_show(struct seq_file *seq, void *v)
  386. {
  387. struct c4iw_dev *dev = seq->private;
  388. seq_printf(seq, " Object: %10s %10s %10s %10s\n", "Total", "Current",
  389. "Max", "Fail");
  390. seq_printf(seq, " PDID: %10llu %10llu %10llu %10llu\n",
  391. dev->rdev.stats.pd.total, dev->rdev.stats.pd.cur,
  392. dev->rdev.stats.pd.max, dev->rdev.stats.pd.fail);
  393. seq_printf(seq, " QID: %10llu %10llu %10llu %10llu\n",
  394. dev->rdev.stats.qid.total, dev->rdev.stats.qid.cur,
  395. dev->rdev.stats.qid.max, dev->rdev.stats.qid.fail);
  396. seq_printf(seq, " TPTMEM: %10llu %10llu %10llu %10llu\n",
  397. dev->rdev.stats.stag.total, dev->rdev.stats.stag.cur,
  398. dev->rdev.stats.stag.max, dev->rdev.stats.stag.fail);
  399. seq_printf(seq, " PBLMEM: %10llu %10llu %10llu %10llu\n",
  400. dev->rdev.stats.pbl.total, dev->rdev.stats.pbl.cur,
  401. dev->rdev.stats.pbl.max, dev->rdev.stats.pbl.fail);
  402. seq_printf(seq, " RQTMEM: %10llu %10llu %10llu %10llu\n",
  403. dev->rdev.stats.rqt.total, dev->rdev.stats.rqt.cur,
  404. dev->rdev.stats.rqt.max, dev->rdev.stats.rqt.fail);
  405. seq_printf(seq, " OCQPMEM: %10llu %10llu %10llu %10llu\n",
  406. dev->rdev.stats.ocqp.total, dev->rdev.stats.ocqp.cur,
  407. dev->rdev.stats.ocqp.max, dev->rdev.stats.ocqp.fail);
  408. seq_printf(seq, " DB FULL: %10llu\n", dev->rdev.stats.db_full);
  409. seq_printf(seq, " DB EMPTY: %10llu\n", dev->rdev.stats.db_empty);
  410. seq_printf(seq, " DB DROP: %10llu\n", dev->rdev.stats.db_drop);
  411. seq_printf(seq, " DB State: %s Transitions %llu FC Interruptions %llu\n",
  412. db_state_str[dev->db_state],
  413. dev->rdev.stats.db_state_transitions,
  414. dev->rdev.stats.db_fc_interruptions);
  415. seq_printf(seq, "TCAM_FULL: %10llu\n", dev->rdev.stats.tcam_full);
  416. seq_printf(seq, "ACT_OFLD_CONN_FAILS: %10llu\n",
  417. dev->rdev.stats.act_ofld_conn_fails);
  418. seq_printf(seq, "PAS_OFLD_CONN_FAILS: %10llu\n",
  419. dev->rdev.stats.pas_ofld_conn_fails);
  420. seq_printf(seq, "NEG_ADV_RCVD: %10llu\n", dev->rdev.stats.neg_adv);
  421. seq_printf(seq, "AVAILABLE IRD: %10u\n", dev->avail_ird);
  422. return 0;
  423. }
  424. static int stats_open(struct inode *inode, struct file *file)
  425. {
  426. return single_open(file, stats_show, inode->i_private);
  427. }
  428. static ssize_t stats_clear(struct file *file, const char __user *buf,
  429. size_t count, loff_t *pos)
  430. {
  431. struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
  432. mutex_lock(&dev->rdev.stats.lock);
  433. dev->rdev.stats.pd.max = 0;
  434. dev->rdev.stats.pd.fail = 0;
  435. dev->rdev.stats.qid.max = 0;
  436. dev->rdev.stats.qid.fail = 0;
  437. dev->rdev.stats.stag.max = 0;
  438. dev->rdev.stats.stag.fail = 0;
  439. dev->rdev.stats.pbl.max = 0;
  440. dev->rdev.stats.pbl.fail = 0;
  441. dev->rdev.stats.rqt.max = 0;
  442. dev->rdev.stats.rqt.fail = 0;
  443. dev->rdev.stats.ocqp.max = 0;
  444. dev->rdev.stats.ocqp.fail = 0;
  445. dev->rdev.stats.db_full = 0;
  446. dev->rdev.stats.db_empty = 0;
  447. dev->rdev.stats.db_drop = 0;
  448. dev->rdev.stats.db_state_transitions = 0;
  449. dev->rdev.stats.tcam_full = 0;
  450. dev->rdev.stats.act_ofld_conn_fails = 0;
  451. dev->rdev.stats.pas_ofld_conn_fails = 0;
  452. mutex_unlock(&dev->rdev.stats.lock);
  453. return count;
  454. }
  455. static const struct file_operations stats_debugfs_fops = {
  456. .owner = THIS_MODULE,
  457. .open = stats_open,
  458. .release = single_release,
  459. .read = seq_read,
  460. .llseek = seq_lseek,
  461. .write = stats_clear,
  462. };
  463. static int dump_ep(int id, void *p, void *data)
  464. {
  465. struct c4iw_ep *ep = p;
  466. struct c4iw_debugfs_data *epd = data;
  467. int space;
  468. int cc;
  469. space = epd->bufsize - epd->pos - 1;
  470. if (space == 0)
  471. return 1;
  472. if (ep->com.local_addr.ss_family == AF_INET) {
  473. struct sockaddr_in *lsin = (struct sockaddr_in *)
  474. &ep->com.cm_id->local_addr;
  475. struct sockaddr_in *rsin = (struct sockaddr_in *)
  476. &ep->com.cm_id->remote_addr;
  477. struct sockaddr_in *mapped_lsin = (struct sockaddr_in *)
  478. &ep->com.cm_id->m_local_addr;
  479. struct sockaddr_in *mapped_rsin = (struct sockaddr_in *)
  480. &ep->com.cm_id->m_remote_addr;
  481. cc = snprintf(epd->buf + epd->pos, space,
  482. "ep %p cm_id %p qp %p state %d flags 0x%lx "
  483. "history 0x%lx hwtid %d atid %d "
  484. "conn_na %u abort_na %u "
  485. "%pI4:%d/%d <-> %pI4:%d/%d\n",
  486. ep, ep->com.cm_id, ep->com.qp,
  487. (int)ep->com.state, ep->com.flags,
  488. ep->com.history, ep->hwtid, ep->atid,
  489. ep->stats.connect_neg_adv,
  490. ep->stats.abort_neg_adv,
  491. &lsin->sin_addr, ntohs(lsin->sin_port),
  492. ntohs(mapped_lsin->sin_port),
  493. &rsin->sin_addr, ntohs(rsin->sin_port),
  494. ntohs(mapped_rsin->sin_port));
  495. } else {
  496. struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
  497. &ep->com.cm_id->local_addr;
  498. struct sockaddr_in6 *rsin6 = (struct sockaddr_in6 *)
  499. &ep->com.cm_id->remote_addr;
  500. struct sockaddr_in6 *mapped_lsin6 = (struct sockaddr_in6 *)
  501. &ep->com.cm_id->m_local_addr;
  502. struct sockaddr_in6 *mapped_rsin6 = (struct sockaddr_in6 *)
  503. &ep->com.cm_id->m_remote_addr;
  504. cc = snprintf(epd->buf + epd->pos, space,
  505. "ep %p cm_id %p qp %p state %d flags 0x%lx "
  506. "history 0x%lx hwtid %d atid %d "
  507. "conn_na %u abort_na %u "
  508. "%pI6:%d/%d <-> %pI6:%d/%d\n",
  509. ep, ep->com.cm_id, ep->com.qp,
  510. (int)ep->com.state, ep->com.flags,
  511. ep->com.history, ep->hwtid, ep->atid,
  512. ep->stats.connect_neg_adv,
  513. ep->stats.abort_neg_adv,
  514. &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
  515. ntohs(mapped_lsin6->sin6_port),
  516. &rsin6->sin6_addr, ntohs(rsin6->sin6_port),
  517. ntohs(mapped_rsin6->sin6_port));
  518. }
  519. if (cc < space)
  520. epd->pos += cc;
  521. return 0;
  522. }
  523. static int dump_listen_ep(int id, void *p, void *data)
  524. {
  525. struct c4iw_listen_ep *ep = p;
  526. struct c4iw_debugfs_data *epd = data;
  527. int space;
  528. int cc;
  529. space = epd->bufsize - epd->pos - 1;
  530. if (space == 0)
  531. return 1;
  532. if (ep->com.local_addr.ss_family == AF_INET) {
  533. struct sockaddr_in *lsin = (struct sockaddr_in *)
  534. &ep->com.cm_id->local_addr;
  535. struct sockaddr_in *mapped_lsin = (struct sockaddr_in *)
  536. &ep->com.cm_id->m_local_addr;
  537. cc = snprintf(epd->buf + epd->pos, space,
  538. "ep %p cm_id %p state %d flags 0x%lx stid %d "
  539. "backlog %d %pI4:%d/%d\n",
  540. ep, ep->com.cm_id, (int)ep->com.state,
  541. ep->com.flags, ep->stid, ep->backlog,
  542. &lsin->sin_addr, ntohs(lsin->sin_port),
  543. ntohs(mapped_lsin->sin_port));
  544. } else {
  545. struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
  546. &ep->com.cm_id->local_addr;
  547. struct sockaddr_in6 *mapped_lsin6 = (struct sockaddr_in6 *)
  548. &ep->com.cm_id->m_local_addr;
  549. cc = snprintf(epd->buf + epd->pos, space,
  550. "ep %p cm_id %p state %d flags 0x%lx stid %d "
  551. "backlog %d %pI6:%d/%d\n",
  552. ep, ep->com.cm_id, (int)ep->com.state,
  553. ep->com.flags, ep->stid, ep->backlog,
  554. &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
  555. ntohs(mapped_lsin6->sin6_port));
  556. }
  557. if (cc < space)
  558. epd->pos += cc;
  559. return 0;
  560. }
  561. static int ep_release(struct inode *inode, struct file *file)
  562. {
  563. struct c4iw_debugfs_data *epd = file->private_data;
  564. if (!epd) {
  565. pr_info("%s null qpd?\n", __func__);
  566. return 0;
  567. }
  568. vfree(epd->buf);
  569. kfree(epd);
  570. return 0;
  571. }
  572. static int ep_open(struct inode *inode, struct file *file)
  573. {
  574. struct c4iw_debugfs_data *epd;
  575. int ret = 0;
  576. int count = 1;
  577. epd = kmalloc(sizeof(*epd), GFP_KERNEL);
  578. if (!epd) {
  579. ret = -ENOMEM;
  580. goto out;
  581. }
  582. epd->devp = inode->i_private;
  583. epd->pos = 0;
  584. spin_lock_irq(&epd->devp->lock);
  585. idr_for_each(&epd->devp->hwtid_idr, count_idrs, &count);
  586. idr_for_each(&epd->devp->atid_idr, count_idrs, &count);
  587. idr_for_each(&epd->devp->stid_idr, count_idrs, &count);
  588. spin_unlock_irq(&epd->devp->lock);
  589. epd->bufsize = count * 240;
  590. epd->buf = vmalloc(epd->bufsize);
  591. if (!epd->buf) {
  592. ret = -ENOMEM;
  593. goto err1;
  594. }
  595. spin_lock_irq(&epd->devp->lock);
  596. idr_for_each(&epd->devp->hwtid_idr, dump_ep, epd);
  597. idr_for_each(&epd->devp->atid_idr, dump_ep, epd);
  598. idr_for_each(&epd->devp->stid_idr, dump_listen_ep, epd);
  599. spin_unlock_irq(&epd->devp->lock);
  600. file->private_data = epd;
  601. goto out;
  602. err1:
  603. kfree(epd);
  604. out:
  605. return ret;
  606. }
  607. static const struct file_operations ep_debugfs_fops = {
  608. .owner = THIS_MODULE,
  609. .open = ep_open,
  610. .release = ep_release,
  611. .read = debugfs_read,
  612. };
  613. static int setup_debugfs(struct c4iw_dev *devp)
  614. {
  615. if (!devp->debugfs_root)
  616. return -1;
  617. debugfs_create_file_size("qps", S_IWUSR, devp->debugfs_root,
  618. (void *)devp, &qp_debugfs_fops, 4096);
  619. debugfs_create_file_size("stags", S_IWUSR, devp->debugfs_root,
  620. (void *)devp, &stag_debugfs_fops, 4096);
  621. debugfs_create_file_size("stats", S_IWUSR, devp->debugfs_root,
  622. (void *)devp, &stats_debugfs_fops, 4096);
  623. debugfs_create_file_size("eps", S_IWUSR, devp->debugfs_root,
  624. (void *)devp, &ep_debugfs_fops, 4096);
  625. if (c4iw_wr_log)
  626. debugfs_create_file_size("wr_log", S_IWUSR, devp->debugfs_root,
  627. (void *)devp, &wr_log_debugfs_fops, 4096);
  628. return 0;
  629. }
  630. void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
  631. struct c4iw_dev_ucontext *uctx)
  632. {
  633. struct list_head *pos, *nxt;
  634. struct c4iw_qid_list *entry;
  635. mutex_lock(&uctx->lock);
  636. list_for_each_safe(pos, nxt, &uctx->qpids) {
  637. entry = list_entry(pos, struct c4iw_qid_list, entry);
  638. list_del_init(&entry->entry);
  639. if (!(entry->qid & rdev->qpmask)) {
  640. c4iw_put_resource(&rdev->resource.qid_table,
  641. entry->qid);
  642. mutex_lock(&rdev->stats.lock);
  643. rdev->stats.qid.cur -= rdev->qpmask + 1;
  644. mutex_unlock(&rdev->stats.lock);
  645. }
  646. kfree(entry);
  647. }
  648. list_for_each_safe(pos, nxt, &uctx->qpids) {
  649. entry = list_entry(pos, struct c4iw_qid_list, entry);
  650. list_del_init(&entry->entry);
  651. kfree(entry);
  652. }
  653. mutex_unlock(&uctx->lock);
  654. }
  655. void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
  656. struct c4iw_dev_ucontext *uctx)
  657. {
  658. INIT_LIST_HEAD(&uctx->qpids);
  659. INIT_LIST_HEAD(&uctx->cqids);
  660. mutex_init(&uctx->lock);
  661. }
  662. /* Caller takes care of locking if needed */
  663. static int c4iw_rdev_open(struct c4iw_rdev *rdev)
  664. {
  665. int err;
  666. c4iw_init_dev_ucontext(rdev, &rdev->uctx);
  667. /*
  668. * This implementation assumes udb_density == ucq_density! Eventually
  669. * we might need to support this but for now fail the open. Also the
  670. * cqid and qpid range must match for now.
  671. */
  672. if (rdev->lldi.udb_density != rdev->lldi.ucq_density) {
  673. pr_err(MOD "%s: unsupported udb/ucq densities %u/%u\n",
  674. pci_name(rdev->lldi.pdev), rdev->lldi.udb_density,
  675. rdev->lldi.ucq_density);
  676. return -EINVAL;
  677. }
  678. if (rdev->lldi.vr->qp.start != rdev->lldi.vr->cq.start ||
  679. rdev->lldi.vr->qp.size != rdev->lldi.vr->cq.size) {
  680. pr_err(MOD "%s: unsupported qp and cq id ranges "
  681. "qp start %u size %u cq start %u size %u\n",
  682. pci_name(rdev->lldi.pdev), rdev->lldi.vr->qp.start,
  683. rdev->lldi.vr->qp.size, rdev->lldi.vr->cq.size,
  684. rdev->lldi.vr->cq.size);
  685. return -EINVAL;
  686. }
  687. rdev->qpmask = rdev->lldi.udb_density - 1;
  688. rdev->cqmask = rdev->lldi.ucq_density - 1;
  689. PDBG("%s dev %s stag start 0x%0x size 0x%0x num stags %d "
  690. "pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x "
  691. "qp qid start %u size %u cq qid start %u size %u\n",
  692. __func__, pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start,
  693. rdev->lldi.vr->stag.size, c4iw_num_stags(rdev),
  694. rdev->lldi.vr->pbl.start,
  695. rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start,
  696. rdev->lldi.vr->rq.size,
  697. rdev->lldi.vr->qp.start,
  698. rdev->lldi.vr->qp.size,
  699. rdev->lldi.vr->cq.start,
  700. rdev->lldi.vr->cq.size);
  701. PDBG("udb %pR db_reg %p gts_reg %p "
  702. "qpmask 0x%x cqmask 0x%x\n",
  703. &rdev->lldi.pdev->resource[2],
  704. rdev->lldi.db_reg, rdev->lldi.gts_reg,
  705. rdev->qpmask, rdev->cqmask);
  706. if (c4iw_num_stags(rdev) == 0)
  707. return -EINVAL;
  708. rdev->stats.pd.total = T4_MAX_NUM_PD;
  709. rdev->stats.stag.total = rdev->lldi.vr->stag.size;
  710. rdev->stats.pbl.total = rdev->lldi.vr->pbl.size;
  711. rdev->stats.rqt.total = rdev->lldi.vr->rq.size;
  712. rdev->stats.ocqp.total = rdev->lldi.vr->ocq.size;
  713. rdev->stats.qid.total = rdev->lldi.vr->qp.size;
  714. err = c4iw_init_resource(rdev, c4iw_num_stags(rdev), T4_MAX_NUM_PD);
  715. if (err) {
  716. printk(KERN_ERR MOD "error %d initializing resources\n", err);
  717. return err;
  718. }
  719. err = c4iw_pblpool_create(rdev);
  720. if (err) {
  721. printk(KERN_ERR MOD "error %d initializing pbl pool\n", err);
  722. goto destroy_resource;
  723. }
  724. err = c4iw_rqtpool_create(rdev);
  725. if (err) {
  726. printk(KERN_ERR MOD "error %d initializing rqt pool\n", err);
  727. goto destroy_pblpool;
  728. }
  729. err = c4iw_ocqp_pool_create(rdev);
  730. if (err) {
  731. printk(KERN_ERR MOD "error %d initializing ocqp pool\n", err);
  732. goto destroy_rqtpool;
  733. }
  734. rdev->status_page = (struct t4_dev_status_page *)
  735. __get_free_page(GFP_KERNEL);
  736. if (!rdev->status_page) {
  737. err = -ENOMEM;
  738. goto destroy_ocqp_pool;
  739. }
  740. rdev->status_page->qp_start = rdev->lldi.vr->qp.start;
  741. rdev->status_page->qp_size = rdev->lldi.vr->qp.size;
  742. rdev->status_page->cq_start = rdev->lldi.vr->cq.start;
  743. rdev->status_page->cq_size = rdev->lldi.vr->cq.size;
  744. if (c4iw_wr_log) {
  745. rdev->wr_log = kzalloc((1 << c4iw_wr_log_size_order) *
  746. sizeof(*rdev->wr_log), GFP_KERNEL);
  747. if (rdev->wr_log) {
  748. rdev->wr_log_size = 1 << c4iw_wr_log_size_order;
  749. atomic_set(&rdev->wr_log_idx, 0);
  750. }
  751. }
  752. rdev->status_page->db_off = 0;
  753. return 0;
  754. destroy_ocqp_pool:
  755. c4iw_ocqp_pool_destroy(rdev);
  756. destroy_rqtpool:
  757. c4iw_rqtpool_destroy(rdev);
  758. destroy_pblpool:
  759. c4iw_pblpool_destroy(rdev);
  760. destroy_resource:
  761. c4iw_destroy_resource(&rdev->resource);
  762. return err;
  763. }
  764. static void c4iw_rdev_close(struct c4iw_rdev *rdev)
  765. {
  766. kfree(rdev->wr_log);
  767. free_page((unsigned long)rdev->status_page);
  768. c4iw_pblpool_destroy(rdev);
  769. c4iw_rqtpool_destroy(rdev);
  770. c4iw_destroy_resource(&rdev->resource);
  771. }
  772. static void c4iw_dealloc(struct uld_ctx *ctx)
  773. {
  774. c4iw_rdev_close(&ctx->dev->rdev);
  775. WARN_ON_ONCE(!idr_is_empty(&ctx->dev->cqidr));
  776. idr_destroy(&ctx->dev->cqidr);
  777. WARN_ON_ONCE(!idr_is_empty(&ctx->dev->qpidr));
  778. idr_destroy(&ctx->dev->qpidr);
  779. WARN_ON_ONCE(!idr_is_empty(&ctx->dev->mmidr));
  780. idr_destroy(&ctx->dev->mmidr);
  781. wait_event(ctx->dev->wait, idr_is_empty(&ctx->dev->hwtid_idr));
  782. idr_destroy(&ctx->dev->hwtid_idr);
  783. idr_destroy(&ctx->dev->stid_idr);
  784. idr_destroy(&ctx->dev->atid_idr);
  785. if (ctx->dev->rdev.bar2_kva)
  786. iounmap(ctx->dev->rdev.bar2_kva);
  787. if (ctx->dev->rdev.oc_mw_kva)
  788. iounmap(ctx->dev->rdev.oc_mw_kva);
  789. ib_dealloc_device(&ctx->dev->ibdev);
  790. ctx->dev = NULL;
  791. }
  792. static void c4iw_remove(struct uld_ctx *ctx)
  793. {
  794. PDBG("%s c4iw_dev %p\n", __func__, ctx->dev);
  795. c4iw_unregister_device(ctx->dev);
  796. c4iw_dealloc(ctx);
  797. }
  798. static int rdma_supported(const struct cxgb4_lld_info *infop)
  799. {
  800. return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 &&
  801. infop->vr->rq.size > 0 && infop->vr->qp.size > 0 &&
  802. infop->vr->cq.size > 0;
  803. }
  804. static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop)
  805. {
  806. struct c4iw_dev *devp;
  807. int ret;
  808. if (!rdma_supported(infop)) {
  809. printk(KERN_INFO MOD "%s: RDMA not supported on this device.\n",
  810. pci_name(infop->pdev));
  811. return ERR_PTR(-ENOSYS);
  812. }
  813. if (!ocqp_supported(infop))
  814. pr_info("%s: On-Chip Queues not supported on this device.\n",
  815. pci_name(infop->pdev));
  816. devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp));
  817. if (!devp) {
  818. printk(KERN_ERR MOD "Cannot allocate ib device\n");
  819. return ERR_PTR(-ENOMEM);
  820. }
  821. devp->rdev.lldi = *infop;
  822. /* init various hw-queue params based on lld info */
  823. PDBG("%s: Ing. padding boundary is %d, egrsstatuspagesize = %d\n",
  824. __func__, devp->rdev.lldi.sge_ingpadboundary,
  825. devp->rdev.lldi.sge_egrstatuspagesize);
  826. devp->rdev.hw_queue.t4_eq_status_entries =
  827. devp->rdev.lldi.sge_ingpadboundary > 64 ? 2 : 1;
  828. devp->rdev.hw_queue.t4_max_eq_size = 65520;
  829. devp->rdev.hw_queue.t4_max_iq_size = 65520;
  830. devp->rdev.hw_queue.t4_max_rq_size = 8192 -
  831. devp->rdev.hw_queue.t4_eq_status_entries - 1;
  832. devp->rdev.hw_queue.t4_max_sq_size =
  833. devp->rdev.hw_queue.t4_max_eq_size -
  834. devp->rdev.hw_queue.t4_eq_status_entries - 1;
  835. devp->rdev.hw_queue.t4_max_qp_depth =
  836. devp->rdev.hw_queue.t4_max_rq_size;
  837. devp->rdev.hw_queue.t4_max_cq_depth =
  838. devp->rdev.hw_queue.t4_max_iq_size - 2;
  839. devp->rdev.hw_queue.t4_stat_len =
  840. devp->rdev.lldi.sge_egrstatuspagesize;
  841. /*
  842. * For T5/T6 devices, we map all of BAR2 with WC.
  843. * For T4 devices with onchip qp mem, we map only that part
  844. * of BAR2 with WC.
  845. */
  846. devp->rdev.bar2_pa = pci_resource_start(devp->rdev.lldi.pdev, 2);
  847. if (!is_t4(devp->rdev.lldi.adapter_type)) {
  848. devp->rdev.bar2_kva = ioremap_wc(devp->rdev.bar2_pa,
  849. pci_resource_len(devp->rdev.lldi.pdev, 2));
  850. if (!devp->rdev.bar2_kva) {
  851. pr_err(MOD "Unable to ioremap BAR2\n");
  852. ib_dealloc_device(&devp->ibdev);
  853. return ERR_PTR(-EINVAL);
  854. }
  855. } else if (ocqp_supported(infop)) {
  856. devp->rdev.oc_mw_pa =
  857. pci_resource_start(devp->rdev.lldi.pdev, 2) +
  858. pci_resource_len(devp->rdev.lldi.pdev, 2) -
  859. roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size);
  860. devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa,
  861. devp->rdev.lldi.vr->ocq.size);
  862. if (!devp->rdev.oc_mw_kva) {
  863. pr_err(MOD "Unable to ioremap onchip mem\n");
  864. ib_dealloc_device(&devp->ibdev);
  865. return ERR_PTR(-EINVAL);
  866. }
  867. }
  868. PDBG(KERN_INFO MOD "ocq memory: "
  869. "hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n",
  870. devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size,
  871. devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva);
  872. ret = c4iw_rdev_open(&devp->rdev);
  873. if (ret) {
  874. printk(KERN_ERR MOD "Unable to open CXIO rdev err %d\n", ret);
  875. ib_dealloc_device(&devp->ibdev);
  876. return ERR_PTR(ret);
  877. }
  878. idr_init(&devp->cqidr);
  879. idr_init(&devp->qpidr);
  880. idr_init(&devp->mmidr);
  881. idr_init(&devp->hwtid_idr);
  882. idr_init(&devp->stid_idr);
  883. idr_init(&devp->atid_idr);
  884. spin_lock_init(&devp->lock);
  885. mutex_init(&devp->rdev.stats.lock);
  886. mutex_init(&devp->db_mutex);
  887. INIT_LIST_HEAD(&devp->db_fc_list);
  888. init_waitqueue_head(&devp->wait);
  889. devp->avail_ird = devp->rdev.lldi.max_ird_adapter;
  890. if (c4iw_debugfs_root) {
  891. devp->debugfs_root = debugfs_create_dir(
  892. pci_name(devp->rdev.lldi.pdev),
  893. c4iw_debugfs_root);
  894. setup_debugfs(devp);
  895. }
  896. return devp;
  897. }
  898. static void *c4iw_uld_add(const struct cxgb4_lld_info *infop)
  899. {
  900. struct uld_ctx *ctx;
  901. static int vers_printed;
  902. int i;
  903. if (!vers_printed++)
  904. pr_info("Chelsio T4/T5 RDMA Driver - version %s\n",
  905. DRV_VERSION);
  906. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  907. if (!ctx) {
  908. ctx = ERR_PTR(-ENOMEM);
  909. goto out;
  910. }
  911. ctx->lldi = *infop;
  912. PDBG("%s found device %s nchan %u nrxq %u ntxq %u nports %u\n",
  913. __func__, pci_name(ctx->lldi.pdev),
  914. ctx->lldi.nchan, ctx->lldi.nrxq,
  915. ctx->lldi.ntxq, ctx->lldi.nports);
  916. mutex_lock(&dev_mutex);
  917. list_add_tail(&ctx->entry, &uld_ctx_list);
  918. mutex_unlock(&dev_mutex);
  919. for (i = 0; i < ctx->lldi.nrxq; i++)
  920. PDBG("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]);
  921. out:
  922. return ctx;
  923. }
  924. static inline struct sk_buff *copy_gl_to_skb_pkt(const struct pkt_gl *gl,
  925. const __be64 *rsp,
  926. u32 pktshift)
  927. {
  928. struct sk_buff *skb;
  929. /*
  930. * Allocate space for cpl_pass_accept_req which will be synthesized by
  931. * driver. Once the driver synthesizes the request the skb will go
  932. * through the regular cpl_pass_accept_req processing.
  933. * The math here assumes sizeof cpl_pass_accept_req >= sizeof
  934. * cpl_rx_pkt.
  935. */
  936. skb = alloc_skb(gl->tot_len + sizeof(struct cpl_pass_accept_req) +
  937. sizeof(struct rss_header) - pktshift, GFP_ATOMIC);
  938. if (unlikely(!skb))
  939. return NULL;
  940. __skb_put(skb, gl->tot_len + sizeof(struct cpl_pass_accept_req) +
  941. sizeof(struct rss_header) - pktshift);
  942. /*
  943. * This skb will contain:
  944. * rss_header from the rspq descriptor (1 flit)
  945. * cpl_rx_pkt struct from the rspq descriptor (2 flits)
  946. * space for the difference between the size of an
  947. * rx_pkt and pass_accept_req cpl (1 flit)
  948. * the packet data from the gl
  949. */
  950. skb_copy_to_linear_data(skb, rsp, sizeof(struct cpl_pass_accept_req) +
  951. sizeof(struct rss_header));
  952. skb_copy_to_linear_data_offset(skb, sizeof(struct rss_header) +
  953. sizeof(struct cpl_pass_accept_req),
  954. gl->va + pktshift,
  955. gl->tot_len - pktshift);
  956. return skb;
  957. }
  958. static inline int recv_rx_pkt(struct c4iw_dev *dev, const struct pkt_gl *gl,
  959. const __be64 *rsp)
  960. {
  961. unsigned int opcode = *(u8 *)rsp;
  962. struct sk_buff *skb;
  963. if (opcode != CPL_RX_PKT)
  964. goto out;
  965. skb = copy_gl_to_skb_pkt(gl , rsp, dev->rdev.lldi.sge_pktshift);
  966. if (skb == NULL)
  967. goto out;
  968. if (c4iw_handlers[opcode] == NULL) {
  969. pr_info("%s no handler opcode 0x%x...\n", __func__,
  970. opcode);
  971. kfree_skb(skb);
  972. goto out;
  973. }
  974. c4iw_handlers[opcode](dev, skb);
  975. return 1;
  976. out:
  977. return 0;
  978. }
  979. static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp,
  980. const struct pkt_gl *gl)
  981. {
  982. struct uld_ctx *ctx = handle;
  983. struct c4iw_dev *dev = ctx->dev;
  984. struct sk_buff *skb;
  985. u8 opcode;
  986. if (gl == NULL) {
  987. /* omit RSS and rsp_ctrl at end of descriptor */
  988. unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8;
  989. skb = alloc_skb(256, GFP_ATOMIC);
  990. if (!skb)
  991. goto nomem;
  992. __skb_put(skb, len);
  993. skb_copy_to_linear_data(skb, &rsp[1], len);
  994. } else if (gl == CXGB4_MSG_AN) {
  995. const struct rsp_ctrl *rc = (void *)rsp;
  996. u32 qid = be32_to_cpu(rc->pldbuflen_qid);
  997. c4iw_ev_handler(dev, qid);
  998. return 0;
  999. } else if (unlikely(*(u8 *)rsp != *(u8 *)gl->va)) {
  1000. if (recv_rx_pkt(dev, gl, rsp))
  1001. return 0;
  1002. pr_info("%s: unexpected FL contents at %p, " \
  1003. "RSS %#llx, FL %#llx, len %u\n",
  1004. pci_name(ctx->lldi.pdev), gl->va,
  1005. (unsigned long long)be64_to_cpu(*rsp),
  1006. (unsigned long long)be64_to_cpu(
  1007. *(__force __be64 *)gl->va),
  1008. gl->tot_len);
  1009. return 0;
  1010. } else {
  1011. skb = cxgb4_pktgl_to_skb(gl, 128, 128);
  1012. if (unlikely(!skb))
  1013. goto nomem;
  1014. }
  1015. opcode = *(u8 *)rsp;
  1016. if (c4iw_handlers[opcode]) {
  1017. c4iw_handlers[opcode](dev, skb);
  1018. } else {
  1019. pr_info("%s no handler opcode 0x%x...\n", __func__,
  1020. opcode);
  1021. kfree_skb(skb);
  1022. }
  1023. return 0;
  1024. nomem:
  1025. return -1;
  1026. }
  1027. static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state)
  1028. {
  1029. struct uld_ctx *ctx = handle;
  1030. PDBG("%s new_state %u\n", __func__, new_state);
  1031. switch (new_state) {
  1032. case CXGB4_STATE_UP:
  1033. printk(KERN_INFO MOD "%s: Up\n", pci_name(ctx->lldi.pdev));
  1034. if (!ctx->dev) {
  1035. int ret;
  1036. ctx->dev = c4iw_alloc(&ctx->lldi);
  1037. if (IS_ERR(ctx->dev)) {
  1038. printk(KERN_ERR MOD
  1039. "%s: initialization failed: %ld\n",
  1040. pci_name(ctx->lldi.pdev),
  1041. PTR_ERR(ctx->dev));
  1042. ctx->dev = NULL;
  1043. break;
  1044. }
  1045. ret = c4iw_register_device(ctx->dev);
  1046. if (ret) {
  1047. printk(KERN_ERR MOD
  1048. "%s: RDMA registration failed: %d\n",
  1049. pci_name(ctx->lldi.pdev), ret);
  1050. c4iw_dealloc(ctx);
  1051. }
  1052. }
  1053. break;
  1054. case CXGB4_STATE_DOWN:
  1055. printk(KERN_INFO MOD "%s: Down\n",
  1056. pci_name(ctx->lldi.pdev));
  1057. if (ctx->dev)
  1058. c4iw_remove(ctx);
  1059. break;
  1060. case CXGB4_STATE_START_RECOVERY:
  1061. printk(KERN_INFO MOD "%s: Fatal Error\n",
  1062. pci_name(ctx->lldi.pdev));
  1063. if (ctx->dev) {
  1064. struct ib_event event;
  1065. ctx->dev->rdev.flags |= T4_FATAL_ERROR;
  1066. memset(&event, 0, sizeof event);
  1067. event.event = IB_EVENT_DEVICE_FATAL;
  1068. event.device = &ctx->dev->ibdev;
  1069. ib_dispatch_event(&event);
  1070. c4iw_remove(ctx);
  1071. }
  1072. break;
  1073. case CXGB4_STATE_DETACH:
  1074. printk(KERN_INFO MOD "%s: Detach\n",
  1075. pci_name(ctx->lldi.pdev));
  1076. if (ctx->dev)
  1077. c4iw_remove(ctx);
  1078. break;
  1079. }
  1080. return 0;
  1081. }
  1082. static int disable_qp_db(int id, void *p, void *data)
  1083. {
  1084. struct c4iw_qp *qp = p;
  1085. t4_disable_wq_db(&qp->wq);
  1086. return 0;
  1087. }
  1088. static void stop_queues(struct uld_ctx *ctx)
  1089. {
  1090. unsigned long flags;
  1091. spin_lock_irqsave(&ctx->dev->lock, flags);
  1092. ctx->dev->rdev.stats.db_state_transitions++;
  1093. ctx->dev->db_state = STOPPED;
  1094. if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED)
  1095. idr_for_each(&ctx->dev->qpidr, disable_qp_db, NULL);
  1096. else
  1097. ctx->dev->rdev.status_page->db_off = 1;
  1098. spin_unlock_irqrestore(&ctx->dev->lock, flags);
  1099. }
  1100. static int enable_qp_db(int id, void *p, void *data)
  1101. {
  1102. struct c4iw_qp *qp = p;
  1103. t4_enable_wq_db(&qp->wq);
  1104. return 0;
  1105. }
  1106. static void resume_rc_qp(struct c4iw_qp *qp)
  1107. {
  1108. spin_lock(&qp->lock);
  1109. t4_ring_sq_db(&qp->wq, qp->wq.sq.wq_pidx_inc, NULL);
  1110. qp->wq.sq.wq_pidx_inc = 0;
  1111. t4_ring_rq_db(&qp->wq, qp->wq.rq.wq_pidx_inc, NULL);
  1112. qp->wq.rq.wq_pidx_inc = 0;
  1113. spin_unlock(&qp->lock);
  1114. }
  1115. static void resume_a_chunk(struct uld_ctx *ctx)
  1116. {
  1117. int i;
  1118. struct c4iw_qp *qp;
  1119. for (i = 0; i < DB_FC_RESUME_SIZE; i++) {
  1120. qp = list_first_entry(&ctx->dev->db_fc_list, struct c4iw_qp,
  1121. db_fc_entry);
  1122. list_del_init(&qp->db_fc_entry);
  1123. resume_rc_qp(qp);
  1124. if (list_empty(&ctx->dev->db_fc_list))
  1125. break;
  1126. }
  1127. }
  1128. static void resume_queues(struct uld_ctx *ctx)
  1129. {
  1130. spin_lock_irq(&ctx->dev->lock);
  1131. if (ctx->dev->db_state != STOPPED)
  1132. goto out;
  1133. ctx->dev->db_state = FLOW_CONTROL;
  1134. while (1) {
  1135. if (list_empty(&ctx->dev->db_fc_list)) {
  1136. WARN_ON(ctx->dev->db_state != FLOW_CONTROL);
  1137. ctx->dev->db_state = NORMAL;
  1138. ctx->dev->rdev.stats.db_state_transitions++;
  1139. if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED) {
  1140. idr_for_each(&ctx->dev->qpidr, enable_qp_db,
  1141. NULL);
  1142. } else {
  1143. ctx->dev->rdev.status_page->db_off = 0;
  1144. }
  1145. break;
  1146. } else {
  1147. if (cxgb4_dbfifo_count(ctx->dev->rdev.lldi.ports[0], 1)
  1148. < (ctx->dev->rdev.lldi.dbfifo_int_thresh <<
  1149. DB_FC_DRAIN_THRESH)) {
  1150. resume_a_chunk(ctx);
  1151. }
  1152. if (!list_empty(&ctx->dev->db_fc_list)) {
  1153. spin_unlock_irq(&ctx->dev->lock);
  1154. if (DB_FC_RESUME_DELAY) {
  1155. set_current_state(TASK_UNINTERRUPTIBLE);
  1156. schedule_timeout(DB_FC_RESUME_DELAY);
  1157. }
  1158. spin_lock_irq(&ctx->dev->lock);
  1159. if (ctx->dev->db_state != FLOW_CONTROL)
  1160. break;
  1161. }
  1162. }
  1163. }
  1164. out:
  1165. if (ctx->dev->db_state != NORMAL)
  1166. ctx->dev->rdev.stats.db_fc_interruptions++;
  1167. spin_unlock_irq(&ctx->dev->lock);
  1168. }
  1169. struct qp_list {
  1170. unsigned idx;
  1171. struct c4iw_qp **qps;
  1172. };
  1173. static int add_and_ref_qp(int id, void *p, void *data)
  1174. {
  1175. struct qp_list *qp_listp = data;
  1176. struct c4iw_qp *qp = p;
  1177. c4iw_qp_add_ref(&qp->ibqp);
  1178. qp_listp->qps[qp_listp->idx++] = qp;
  1179. return 0;
  1180. }
  1181. static int count_qps(int id, void *p, void *data)
  1182. {
  1183. unsigned *countp = data;
  1184. (*countp)++;
  1185. return 0;
  1186. }
  1187. static void deref_qps(struct qp_list *qp_list)
  1188. {
  1189. int idx;
  1190. for (idx = 0; idx < qp_list->idx; idx++)
  1191. c4iw_qp_rem_ref(&qp_list->qps[idx]->ibqp);
  1192. }
  1193. static void recover_lost_dbs(struct uld_ctx *ctx, struct qp_list *qp_list)
  1194. {
  1195. int idx;
  1196. int ret;
  1197. for (idx = 0; idx < qp_list->idx; idx++) {
  1198. struct c4iw_qp *qp = qp_list->qps[idx];
  1199. spin_lock_irq(&qp->rhp->lock);
  1200. spin_lock(&qp->lock);
  1201. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  1202. qp->wq.sq.qid,
  1203. t4_sq_host_wq_pidx(&qp->wq),
  1204. t4_sq_wq_size(&qp->wq));
  1205. if (ret) {
  1206. pr_err(MOD "%s: Fatal error - "
  1207. "DB overflow recovery failed - "
  1208. "error syncing SQ qid %u\n",
  1209. pci_name(ctx->lldi.pdev), qp->wq.sq.qid);
  1210. spin_unlock(&qp->lock);
  1211. spin_unlock_irq(&qp->rhp->lock);
  1212. return;
  1213. }
  1214. qp->wq.sq.wq_pidx_inc = 0;
  1215. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  1216. qp->wq.rq.qid,
  1217. t4_rq_host_wq_pidx(&qp->wq),
  1218. t4_rq_wq_size(&qp->wq));
  1219. if (ret) {
  1220. pr_err(MOD "%s: Fatal error - "
  1221. "DB overflow recovery failed - "
  1222. "error syncing RQ qid %u\n",
  1223. pci_name(ctx->lldi.pdev), qp->wq.rq.qid);
  1224. spin_unlock(&qp->lock);
  1225. spin_unlock_irq(&qp->rhp->lock);
  1226. return;
  1227. }
  1228. qp->wq.rq.wq_pidx_inc = 0;
  1229. spin_unlock(&qp->lock);
  1230. spin_unlock_irq(&qp->rhp->lock);
  1231. /* Wait for the dbfifo to drain */
  1232. while (cxgb4_dbfifo_count(qp->rhp->rdev.lldi.ports[0], 1) > 0) {
  1233. set_current_state(TASK_UNINTERRUPTIBLE);
  1234. schedule_timeout(usecs_to_jiffies(10));
  1235. }
  1236. }
  1237. }
  1238. static void recover_queues(struct uld_ctx *ctx)
  1239. {
  1240. int count = 0;
  1241. struct qp_list qp_list;
  1242. int ret;
  1243. /* slow everybody down */
  1244. set_current_state(TASK_UNINTERRUPTIBLE);
  1245. schedule_timeout(usecs_to_jiffies(1000));
  1246. /* flush the SGE contexts */
  1247. ret = cxgb4_flush_eq_cache(ctx->dev->rdev.lldi.ports[0]);
  1248. if (ret) {
  1249. printk(KERN_ERR MOD "%s: Fatal error - DB overflow recovery failed\n",
  1250. pci_name(ctx->lldi.pdev));
  1251. return;
  1252. }
  1253. /* Count active queues so we can build a list of queues to recover */
  1254. spin_lock_irq(&ctx->dev->lock);
  1255. WARN_ON(ctx->dev->db_state != STOPPED);
  1256. ctx->dev->db_state = RECOVERY;
  1257. idr_for_each(&ctx->dev->qpidr, count_qps, &count);
  1258. qp_list.qps = kzalloc(count * sizeof *qp_list.qps, GFP_ATOMIC);
  1259. if (!qp_list.qps) {
  1260. spin_unlock_irq(&ctx->dev->lock);
  1261. return;
  1262. }
  1263. qp_list.idx = 0;
  1264. /* add and ref each qp so it doesn't get freed */
  1265. idr_for_each(&ctx->dev->qpidr, add_and_ref_qp, &qp_list);
  1266. spin_unlock_irq(&ctx->dev->lock);
  1267. /* now traverse the list in a safe context to recover the db state*/
  1268. recover_lost_dbs(ctx, &qp_list);
  1269. /* we're almost done! deref the qps and clean up */
  1270. deref_qps(&qp_list);
  1271. kfree(qp_list.qps);
  1272. spin_lock_irq(&ctx->dev->lock);
  1273. WARN_ON(ctx->dev->db_state != RECOVERY);
  1274. ctx->dev->db_state = STOPPED;
  1275. spin_unlock_irq(&ctx->dev->lock);
  1276. }
  1277. static int c4iw_uld_control(void *handle, enum cxgb4_control control, ...)
  1278. {
  1279. struct uld_ctx *ctx = handle;
  1280. switch (control) {
  1281. case CXGB4_CONTROL_DB_FULL:
  1282. stop_queues(ctx);
  1283. ctx->dev->rdev.stats.db_full++;
  1284. break;
  1285. case CXGB4_CONTROL_DB_EMPTY:
  1286. resume_queues(ctx);
  1287. mutex_lock(&ctx->dev->rdev.stats.lock);
  1288. ctx->dev->rdev.stats.db_empty++;
  1289. mutex_unlock(&ctx->dev->rdev.stats.lock);
  1290. break;
  1291. case CXGB4_CONTROL_DB_DROP:
  1292. recover_queues(ctx);
  1293. mutex_lock(&ctx->dev->rdev.stats.lock);
  1294. ctx->dev->rdev.stats.db_drop++;
  1295. mutex_unlock(&ctx->dev->rdev.stats.lock);
  1296. break;
  1297. default:
  1298. printk(KERN_WARNING MOD "%s: unknown control cmd %u\n",
  1299. pci_name(ctx->lldi.pdev), control);
  1300. break;
  1301. }
  1302. return 0;
  1303. }
  1304. static struct cxgb4_uld_info c4iw_uld_info = {
  1305. .name = DRV_NAME,
  1306. .nrxq = MAX_ULD_QSETS,
  1307. .ntxq = MAX_ULD_QSETS,
  1308. .rxq_size = 511,
  1309. .ciq = true,
  1310. .lro = false,
  1311. .add = c4iw_uld_add,
  1312. .rx_handler = c4iw_uld_rx_handler,
  1313. .state_change = c4iw_uld_state_change,
  1314. .control = c4iw_uld_control,
  1315. };
  1316. static int __init c4iw_init_module(void)
  1317. {
  1318. int err;
  1319. err = c4iw_cm_init();
  1320. if (err)
  1321. return err;
  1322. c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL);
  1323. if (!c4iw_debugfs_root)
  1324. printk(KERN_WARNING MOD
  1325. "could not create debugfs entry, continuing\n");
  1326. cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info);
  1327. return 0;
  1328. }
  1329. static void __exit c4iw_exit_module(void)
  1330. {
  1331. struct uld_ctx *ctx, *tmp;
  1332. mutex_lock(&dev_mutex);
  1333. list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) {
  1334. if (ctx->dev)
  1335. c4iw_remove(ctx);
  1336. kfree(ctx);
  1337. }
  1338. mutex_unlock(&dev_mutex);
  1339. cxgb4_unregister_uld(CXGB4_ULD_RDMA);
  1340. c4iw_cm_term();
  1341. debugfs_remove_recursive(c4iw_debugfs_root);
  1342. }
  1343. module_init(c4iw_init_module);
  1344. module_exit(c4iw_exit_module);