zx_hdmi.c 15 KB

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  1. /*
  2. * Copyright 2016 Linaro Ltd.
  3. * Copyright 2016 ZTE Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/component.h>
  12. #include <linux/delay.h>
  13. #include <linux/err.h>
  14. #include <linux/hdmi.h>
  15. #include <linux/irq.h>
  16. #include <linux/mfd/syscon.h>
  17. #include <linux/module.h>
  18. #include <linux/mutex.h>
  19. #include <linux/of_device.h>
  20. #include <drm/drm_atomic_helper.h>
  21. #include <drm/drm_crtc_helper.h>
  22. #include <drm/drm_edid.h>
  23. #include <drm/drm_of.h>
  24. #include <drm/drmP.h>
  25. #include "zx_hdmi_regs.h"
  26. #include "zx_vou.h"
  27. #define ZX_HDMI_INFOFRAME_SIZE 31
  28. #define DDC_SEGMENT_ADDR 0x30
  29. struct zx_hdmi_i2c {
  30. struct i2c_adapter adap;
  31. struct mutex lock;
  32. };
  33. struct zx_hdmi {
  34. struct drm_connector connector;
  35. struct drm_encoder encoder;
  36. struct zx_hdmi_i2c *ddc;
  37. struct device *dev;
  38. struct drm_device *drm;
  39. void __iomem *mmio;
  40. struct clk *cec_clk;
  41. struct clk *osc_clk;
  42. struct clk *xclk;
  43. bool sink_is_hdmi;
  44. bool sink_has_audio;
  45. const struct vou_inf *inf;
  46. };
  47. #define to_zx_hdmi(x) container_of(x, struct zx_hdmi, x)
  48. static const struct vou_inf vou_inf_hdmi = {
  49. .id = VOU_HDMI,
  50. .data_sel = VOU_YUV444,
  51. .clocks_en_bits = BIT(24) | BIT(18) | BIT(6),
  52. .clocks_sel_bits = BIT(13) | BIT(2),
  53. };
  54. static inline u8 hdmi_readb(struct zx_hdmi *hdmi, u16 offset)
  55. {
  56. return readl_relaxed(hdmi->mmio + offset * 4);
  57. }
  58. static inline void hdmi_writeb(struct zx_hdmi *hdmi, u16 offset, u8 val)
  59. {
  60. writel_relaxed(val, hdmi->mmio + offset * 4);
  61. }
  62. static inline void hdmi_writeb_mask(struct zx_hdmi *hdmi, u16 offset,
  63. u8 mask, u8 val)
  64. {
  65. u8 tmp;
  66. tmp = hdmi_readb(hdmi, offset);
  67. tmp = (tmp & ~mask) | (val & mask);
  68. hdmi_writeb(hdmi, offset, tmp);
  69. }
  70. static int zx_hdmi_infoframe_trans(struct zx_hdmi *hdmi,
  71. union hdmi_infoframe *frame, u8 fsel)
  72. {
  73. u8 buffer[ZX_HDMI_INFOFRAME_SIZE];
  74. int num;
  75. int i;
  76. hdmi_writeb(hdmi, TPI_INFO_FSEL, fsel);
  77. num = hdmi_infoframe_pack(frame, buffer, ZX_HDMI_INFOFRAME_SIZE);
  78. if (num < 0) {
  79. DRM_DEV_ERROR(hdmi->dev, "failed to pack infoframe: %d\n", num);
  80. return num;
  81. }
  82. for (i = 0; i < num; i++)
  83. hdmi_writeb(hdmi, TPI_INFO_B0 + i, buffer[i]);
  84. hdmi_writeb_mask(hdmi, TPI_INFO_EN, TPI_INFO_TRANS_RPT,
  85. TPI_INFO_TRANS_RPT);
  86. hdmi_writeb_mask(hdmi, TPI_INFO_EN, TPI_INFO_TRANS_EN,
  87. TPI_INFO_TRANS_EN);
  88. return num;
  89. }
  90. static int zx_hdmi_config_video_vsi(struct zx_hdmi *hdmi,
  91. struct drm_display_mode *mode)
  92. {
  93. union hdmi_infoframe frame;
  94. int ret;
  95. ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
  96. mode);
  97. if (ret) {
  98. DRM_DEV_ERROR(hdmi->dev, "failed to get vendor infoframe: %d\n",
  99. ret);
  100. return ret;
  101. }
  102. return zx_hdmi_infoframe_trans(hdmi, &frame, FSEL_VSIF);
  103. }
  104. static int zx_hdmi_config_video_avi(struct zx_hdmi *hdmi,
  105. struct drm_display_mode *mode)
  106. {
  107. union hdmi_infoframe frame;
  108. int ret;
  109. ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode);
  110. if (ret) {
  111. DRM_DEV_ERROR(hdmi->dev, "failed to get avi infoframe: %d\n",
  112. ret);
  113. return ret;
  114. }
  115. /* We always use YUV444 for HDMI output. */
  116. frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
  117. return zx_hdmi_infoframe_trans(hdmi, &frame, FSEL_AVI);
  118. }
  119. static void zx_hdmi_encoder_mode_set(struct drm_encoder *encoder,
  120. struct drm_display_mode *mode,
  121. struct drm_display_mode *adj_mode)
  122. {
  123. struct zx_hdmi *hdmi = to_zx_hdmi(encoder);
  124. if (hdmi->sink_is_hdmi) {
  125. zx_hdmi_config_video_avi(hdmi, mode);
  126. zx_hdmi_config_video_vsi(hdmi, mode);
  127. }
  128. }
  129. static void zx_hdmi_phy_start(struct zx_hdmi *hdmi)
  130. {
  131. /* Copy from ZTE BSP code */
  132. hdmi_writeb(hdmi, 0x222, 0x0);
  133. hdmi_writeb(hdmi, 0x224, 0x4);
  134. hdmi_writeb(hdmi, 0x909, 0x0);
  135. hdmi_writeb(hdmi, 0x7b0, 0x90);
  136. hdmi_writeb(hdmi, 0x7b1, 0x00);
  137. hdmi_writeb(hdmi, 0x7b2, 0xa7);
  138. hdmi_writeb(hdmi, 0x7b8, 0xaa);
  139. hdmi_writeb(hdmi, 0x7b2, 0xa7);
  140. hdmi_writeb(hdmi, 0x7b3, 0x0f);
  141. hdmi_writeb(hdmi, 0x7b4, 0x0f);
  142. hdmi_writeb(hdmi, 0x7b5, 0x55);
  143. hdmi_writeb(hdmi, 0x7b7, 0x03);
  144. hdmi_writeb(hdmi, 0x7b9, 0x12);
  145. hdmi_writeb(hdmi, 0x7ba, 0x32);
  146. hdmi_writeb(hdmi, 0x7bc, 0x68);
  147. hdmi_writeb(hdmi, 0x7be, 0x40);
  148. hdmi_writeb(hdmi, 0x7bf, 0x84);
  149. hdmi_writeb(hdmi, 0x7c1, 0x0f);
  150. hdmi_writeb(hdmi, 0x7c8, 0x02);
  151. hdmi_writeb(hdmi, 0x7c9, 0x03);
  152. hdmi_writeb(hdmi, 0x7ca, 0x40);
  153. hdmi_writeb(hdmi, 0x7dc, 0x31);
  154. hdmi_writeb(hdmi, 0x7e2, 0x04);
  155. hdmi_writeb(hdmi, 0x7e0, 0x06);
  156. hdmi_writeb(hdmi, 0x7cb, 0x68);
  157. hdmi_writeb(hdmi, 0x7f9, 0x02);
  158. hdmi_writeb(hdmi, 0x7b6, 0x02);
  159. hdmi_writeb(hdmi, 0x7f3, 0x0);
  160. }
  161. static void zx_hdmi_hw_enable(struct zx_hdmi *hdmi)
  162. {
  163. /* Enable pclk */
  164. hdmi_writeb_mask(hdmi, CLKPWD, CLKPWD_PDIDCK, CLKPWD_PDIDCK);
  165. /* Enable HDMI for TX */
  166. hdmi_writeb_mask(hdmi, FUNC_SEL, FUNC_HDMI_EN, FUNC_HDMI_EN);
  167. /* Enable deep color packet */
  168. hdmi_writeb_mask(hdmi, P2T_CTRL, P2T_DC_PKT_EN, P2T_DC_PKT_EN);
  169. /* Enable HDMI/MHL mode for output */
  170. hdmi_writeb_mask(hdmi, TEST_TXCTRL, TEST_TXCTRL_HDMI_MODE,
  171. TEST_TXCTRL_HDMI_MODE);
  172. /* Configure reg_qc_sel */
  173. hdmi_writeb(hdmi, HDMICTL4, 0x3);
  174. /* Enable interrupt */
  175. hdmi_writeb_mask(hdmi, INTR1_MASK, INTR1_MONITOR_DETECT,
  176. INTR1_MONITOR_DETECT);
  177. /* Start up phy */
  178. zx_hdmi_phy_start(hdmi);
  179. }
  180. static void zx_hdmi_hw_disable(struct zx_hdmi *hdmi)
  181. {
  182. /* Disable interrupt */
  183. hdmi_writeb_mask(hdmi, INTR1_MASK, INTR1_MONITOR_DETECT, 0);
  184. /* Disable deep color packet */
  185. hdmi_writeb_mask(hdmi, P2T_CTRL, P2T_DC_PKT_EN, P2T_DC_PKT_EN);
  186. /* Disable HDMI for TX */
  187. hdmi_writeb_mask(hdmi, FUNC_SEL, FUNC_HDMI_EN, 0);
  188. /* Disable pclk */
  189. hdmi_writeb_mask(hdmi, CLKPWD, CLKPWD_PDIDCK, 0);
  190. }
  191. static void zx_hdmi_encoder_enable(struct drm_encoder *encoder)
  192. {
  193. struct zx_hdmi *hdmi = to_zx_hdmi(encoder);
  194. clk_prepare_enable(hdmi->cec_clk);
  195. clk_prepare_enable(hdmi->osc_clk);
  196. clk_prepare_enable(hdmi->xclk);
  197. zx_hdmi_hw_enable(hdmi);
  198. vou_inf_enable(hdmi->inf, encoder->crtc);
  199. }
  200. static void zx_hdmi_encoder_disable(struct drm_encoder *encoder)
  201. {
  202. struct zx_hdmi *hdmi = to_zx_hdmi(encoder);
  203. vou_inf_disable(hdmi->inf, encoder->crtc);
  204. zx_hdmi_hw_disable(hdmi);
  205. clk_disable_unprepare(hdmi->xclk);
  206. clk_disable_unprepare(hdmi->osc_clk);
  207. clk_disable_unprepare(hdmi->cec_clk);
  208. }
  209. static const struct drm_encoder_helper_funcs zx_hdmi_encoder_helper_funcs = {
  210. .enable = zx_hdmi_encoder_enable,
  211. .disable = zx_hdmi_encoder_disable,
  212. .mode_set = zx_hdmi_encoder_mode_set,
  213. };
  214. static const struct drm_encoder_funcs zx_hdmi_encoder_funcs = {
  215. .destroy = drm_encoder_cleanup,
  216. };
  217. static int zx_hdmi_connector_get_modes(struct drm_connector *connector)
  218. {
  219. struct zx_hdmi *hdmi = to_zx_hdmi(connector);
  220. struct edid *edid;
  221. int ret;
  222. edid = drm_get_edid(connector, &hdmi->ddc->adap);
  223. if (!edid)
  224. return 0;
  225. hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
  226. hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
  227. drm_mode_connector_update_edid_property(connector, edid);
  228. ret = drm_add_edid_modes(connector, edid);
  229. kfree(edid);
  230. return ret;
  231. }
  232. static enum drm_mode_status
  233. zx_hdmi_connector_mode_valid(struct drm_connector *connector,
  234. struct drm_display_mode *mode)
  235. {
  236. return MODE_OK;
  237. }
  238. static struct drm_connector_helper_funcs zx_hdmi_connector_helper_funcs = {
  239. .get_modes = zx_hdmi_connector_get_modes,
  240. .mode_valid = zx_hdmi_connector_mode_valid,
  241. };
  242. static enum drm_connector_status
  243. zx_hdmi_connector_detect(struct drm_connector *connector, bool force)
  244. {
  245. struct zx_hdmi *hdmi = to_zx_hdmi(connector);
  246. return (hdmi_readb(hdmi, TPI_HPD_RSEN) & TPI_HPD_CONNECTION) ?
  247. connector_status_connected : connector_status_disconnected;
  248. }
  249. static const struct drm_connector_funcs zx_hdmi_connector_funcs = {
  250. .dpms = drm_atomic_helper_connector_dpms,
  251. .fill_modes = drm_helper_probe_single_connector_modes,
  252. .detect = zx_hdmi_connector_detect,
  253. .destroy = drm_connector_cleanup,
  254. .reset = drm_atomic_helper_connector_reset,
  255. .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  256. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  257. };
  258. static int zx_hdmi_register(struct drm_device *drm, struct zx_hdmi *hdmi)
  259. {
  260. struct drm_encoder *encoder = &hdmi->encoder;
  261. encoder->possible_crtcs = VOU_CRTC_MASK;
  262. drm_encoder_init(drm, encoder, &zx_hdmi_encoder_funcs,
  263. DRM_MODE_ENCODER_TMDS, NULL);
  264. drm_encoder_helper_add(encoder, &zx_hdmi_encoder_helper_funcs);
  265. hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
  266. drm_connector_init(drm, &hdmi->connector, &zx_hdmi_connector_funcs,
  267. DRM_MODE_CONNECTOR_HDMIA);
  268. drm_connector_helper_add(&hdmi->connector,
  269. &zx_hdmi_connector_helper_funcs);
  270. drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
  271. return 0;
  272. }
  273. static irqreturn_t zx_hdmi_irq_thread(int irq, void *dev_id)
  274. {
  275. struct zx_hdmi *hdmi = dev_id;
  276. drm_helper_hpd_irq_event(hdmi->connector.dev);
  277. return IRQ_HANDLED;
  278. }
  279. static irqreturn_t zx_hdmi_irq_handler(int irq, void *dev_id)
  280. {
  281. struct zx_hdmi *hdmi = dev_id;
  282. u8 lstat;
  283. lstat = hdmi_readb(hdmi, L1_INTR_STAT);
  284. /* Monitor detect/HPD interrupt */
  285. if (lstat & L1_INTR_STAT_INTR1) {
  286. u8 stat;
  287. stat = hdmi_readb(hdmi, INTR1_STAT);
  288. hdmi_writeb(hdmi, INTR1_STAT, stat);
  289. if (stat & INTR1_MONITOR_DETECT)
  290. return IRQ_WAKE_THREAD;
  291. }
  292. return IRQ_NONE;
  293. }
  294. static int zx_hdmi_i2c_read(struct zx_hdmi *hdmi, struct i2c_msg *msg)
  295. {
  296. int len = msg->len;
  297. u8 *buf = msg->buf;
  298. int retry = 0;
  299. int ret = 0;
  300. /* Bits [9:8] of bytes */
  301. hdmi_writeb(hdmi, ZX_DDC_DIN_CNT2, (len >> 8) & 0xff);
  302. /* Bits [7:0] of bytes */
  303. hdmi_writeb(hdmi, ZX_DDC_DIN_CNT1, len & 0xff);
  304. /* Clear FIFO */
  305. hdmi_writeb_mask(hdmi, ZX_DDC_CMD, DDC_CMD_MASK, DDC_CMD_CLEAR_FIFO);
  306. /* Kick off the read */
  307. hdmi_writeb_mask(hdmi, ZX_DDC_CMD, DDC_CMD_MASK,
  308. DDC_CMD_SEQUENTIAL_READ);
  309. while (len > 0) {
  310. int cnt, i;
  311. /* FIFO needs some time to get ready */
  312. usleep_range(500, 1000);
  313. cnt = hdmi_readb(hdmi, ZX_DDC_DOUT_CNT) & DDC_DOUT_CNT_MASK;
  314. if (cnt == 0) {
  315. if (++retry > 5) {
  316. DRM_DEV_ERROR(hdmi->dev,
  317. "DDC FIFO read timed out!");
  318. return -ETIMEDOUT;
  319. }
  320. continue;
  321. }
  322. for (i = 0; i < cnt; i++)
  323. *buf++ = hdmi_readb(hdmi, ZX_DDC_DATA);
  324. len -= cnt;
  325. }
  326. return ret;
  327. }
  328. static int zx_hdmi_i2c_write(struct zx_hdmi *hdmi, struct i2c_msg *msg)
  329. {
  330. /*
  331. * The DDC I2C adapter is only for reading EDID data, so we assume
  332. * that the write to this adapter must be the EDID data offset.
  333. */
  334. if ((msg->len != 1) ||
  335. ((msg->addr != DDC_ADDR) && (msg->addr != DDC_SEGMENT_ADDR)))
  336. return -EINVAL;
  337. if (msg->addr == DDC_SEGMENT_ADDR)
  338. hdmi_writeb(hdmi, ZX_DDC_SEGM, msg->addr << 1);
  339. else if (msg->addr == DDC_ADDR)
  340. hdmi_writeb(hdmi, ZX_DDC_ADDR, msg->addr << 1);
  341. hdmi_writeb(hdmi, ZX_DDC_OFFSET, msg->buf[0]);
  342. return 0;
  343. }
  344. static int zx_hdmi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
  345. int num)
  346. {
  347. struct zx_hdmi *hdmi = i2c_get_adapdata(adap);
  348. struct zx_hdmi_i2c *ddc = hdmi->ddc;
  349. int i, ret = 0;
  350. mutex_lock(&ddc->lock);
  351. /* Enable DDC master access */
  352. hdmi_writeb_mask(hdmi, TPI_DDC_MASTER_EN, HW_DDC_MASTER, HW_DDC_MASTER);
  353. for (i = 0; i < num; i++) {
  354. DRM_DEV_DEBUG(hdmi->dev,
  355. "xfer: num: %d/%d, len: %d, flags: %#x\n",
  356. i + 1, num, msgs[i].len, msgs[i].flags);
  357. if (msgs[i].flags & I2C_M_RD)
  358. ret = zx_hdmi_i2c_read(hdmi, &msgs[i]);
  359. else
  360. ret = zx_hdmi_i2c_write(hdmi, &msgs[i]);
  361. if (ret < 0)
  362. break;
  363. }
  364. if (!ret)
  365. ret = num;
  366. /* Disable DDC master access */
  367. hdmi_writeb_mask(hdmi, TPI_DDC_MASTER_EN, HW_DDC_MASTER, 0);
  368. mutex_unlock(&ddc->lock);
  369. return ret;
  370. }
  371. static u32 zx_hdmi_i2c_func(struct i2c_adapter *adapter)
  372. {
  373. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  374. }
  375. static const struct i2c_algorithm zx_hdmi_algorithm = {
  376. .master_xfer = zx_hdmi_i2c_xfer,
  377. .functionality = zx_hdmi_i2c_func,
  378. };
  379. static int zx_hdmi_ddc_register(struct zx_hdmi *hdmi)
  380. {
  381. struct i2c_adapter *adap;
  382. struct zx_hdmi_i2c *ddc;
  383. int ret;
  384. ddc = devm_kzalloc(hdmi->dev, sizeof(*ddc), GFP_KERNEL);
  385. if (!ddc)
  386. return -ENOMEM;
  387. hdmi->ddc = ddc;
  388. mutex_init(&ddc->lock);
  389. adap = &ddc->adap;
  390. adap->owner = THIS_MODULE;
  391. adap->class = I2C_CLASS_DDC;
  392. adap->dev.parent = hdmi->dev;
  393. adap->algo = &zx_hdmi_algorithm;
  394. snprintf(adap->name, sizeof(adap->name), "zx hdmi i2c");
  395. ret = i2c_add_adapter(adap);
  396. if (ret) {
  397. DRM_DEV_ERROR(hdmi->dev, "failed to add I2C adapter: %d\n",
  398. ret);
  399. return ret;
  400. }
  401. i2c_set_adapdata(adap, hdmi);
  402. return 0;
  403. }
  404. static int zx_hdmi_bind(struct device *dev, struct device *master, void *data)
  405. {
  406. struct platform_device *pdev = to_platform_device(dev);
  407. struct drm_device *drm = data;
  408. struct resource *res;
  409. struct zx_hdmi *hdmi;
  410. int irq;
  411. int ret;
  412. hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
  413. if (!hdmi)
  414. return -ENOMEM;
  415. hdmi->dev = dev;
  416. hdmi->drm = drm;
  417. hdmi->inf = &vou_inf_hdmi;
  418. dev_set_drvdata(dev, hdmi);
  419. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  420. hdmi->mmio = devm_ioremap_resource(dev, res);
  421. if (IS_ERR(hdmi->mmio)) {
  422. ret = PTR_ERR(hdmi->mmio);
  423. DRM_DEV_ERROR(dev, "failed to remap hdmi region: %d\n", ret);
  424. return ret;
  425. }
  426. irq = platform_get_irq(pdev, 0);
  427. if (irq < 0)
  428. return irq;
  429. hdmi->cec_clk = devm_clk_get(hdmi->dev, "osc_cec");
  430. if (IS_ERR(hdmi->cec_clk)) {
  431. ret = PTR_ERR(hdmi->cec_clk);
  432. DRM_DEV_ERROR(dev, "failed to get cec_clk: %d\n", ret);
  433. return ret;
  434. }
  435. hdmi->osc_clk = devm_clk_get(hdmi->dev, "osc_clk");
  436. if (IS_ERR(hdmi->osc_clk)) {
  437. ret = PTR_ERR(hdmi->osc_clk);
  438. DRM_DEV_ERROR(dev, "failed to get osc_clk: %d\n", ret);
  439. return ret;
  440. }
  441. hdmi->xclk = devm_clk_get(hdmi->dev, "xclk");
  442. if (IS_ERR(hdmi->xclk)) {
  443. ret = PTR_ERR(hdmi->xclk);
  444. DRM_DEV_ERROR(dev, "failed to get xclk: %d\n", ret);
  445. return ret;
  446. }
  447. ret = zx_hdmi_ddc_register(hdmi);
  448. if (ret) {
  449. DRM_DEV_ERROR(dev, "failed to register ddc: %d\n", ret);
  450. return ret;
  451. }
  452. ret = zx_hdmi_register(drm, hdmi);
  453. if (ret) {
  454. DRM_DEV_ERROR(dev, "failed to register hdmi: %d\n", ret);
  455. return ret;
  456. }
  457. ret = devm_request_threaded_irq(dev, irq, zx_hdmi_irq_handler,
  458. zx_hdmi_irq_thread, IRQF_SHARED,
  459. dev_name(dev), hdmi);
  460. if (ret) {
  461. DRM_DEV_ERROR(dev, "failed to request threaded irq: %d\n", ret);
  462. return ret;
  463. }
  464. return 0;
  465. }
  466. static void zx_hdmi_unbind(struct device *dev, struct device *master,
  467. void *data)
  468. {
  469. struct zx_hdmi *hdmi = dev_get_drvdata(dev);
  470. hdmi->connector.funcs->destroy(&hdmi->connector);
  471. hdmi->encoder.funcs->destroy(&hdmi->encoder);
  472. }
  473. static const struct component_ops zx_hdmi_component_ops = {
  474. .bind = zx_hdmi_bind,
  475. .unbind = zx_hdmi_unbind,
  476. };
  477. static int zx_hdmi_probe(struct platform_device *pdev)
  478. {
  479. return component_add(&pdev->dev, &zx_hdmi_component_ops);
  480. }
  481. static int zx_hdmi_remove(struct platform_device *pdev)
  482. {
  483. component_del(&pdev->dev, &zx_hdmi_component_ops);
  484. return 0;
  485. }
  486. static const struct of_device_id zx_hdmi_of_match[] = {
  487. { .compatible = "zte,zx296718-hdmi", },
  488. { /* end */ },
  489. };
  490. MODULE_DEVICE_TABLE(of, zx_hdmi_of_match);
  491. struct platform_driver zx_hdmi_driver = {
  492. .probe = zx_hdmi_probe,
  493. .remove = zx_hdmi_remove,
  494. .driver = {
  495. .name = "zx-hdmi",
  496. .of_match_table = zx_hdmi_of_match,
  497. },
  498. };