hdmi5.c 18 KB

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  1. /*
  2. * HDMI driver for OMAP5
  3. *
  4. * Copyright (C) 2014 Texas Instruments Incorporated
  5. *
  6. * Authors:
  7. * Yong Zhi
  8. * Mythri pk
  9. * Archit Taneja <archit@ti.com>
  10. * Tomi Valkeinen <tomi.valkeinen@ti.com>
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms of the GNU General Public License version 2 as published by
  14. * the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope that it will be useful, but WITHOUT
  17. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  19. * more details.
  20. *
  21. * You should have received a copy of the GNU General Public License along with
  22. * this program. If not, see <http://www.gnu.org/licenses/>.
  23. */
  24. #define DSS_SUBSYS_NAME "HDMI"
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/err.h>
  28. #include <linux/io.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/mutex.h>
  31. #include <linux/delay.h>
  32. #include <linux/string.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/pm_runtime.h>
  35. #include <linux/clk.h>
  36. #include <linux/gpio.h>
  37. #include <linux/regulator/consumer.h>
  38. #include <linux/component.h>
  39. #include <linux/of.h>
  40. #include <sound/omap-hdmi-audio.h>
  41. #include "omapdss.h"
  42. #include "hdmi5_core.h"
  43. #include "dss.h"
  44. #include "dss_features.h"
  45. static struct omap_hdmi hdmi;
  46. static int hdmi_runtime_get(void)
  47. {
  48. int r;
  49. DSSDBG("hdmi_runtime_get\n");
  50. r = pm_runtime_get_sync(&hdmi.pdev->dev);
  51. WARN_ON(r < 0);
  52. if (r < 0)
  53. return r;
  54. return 0;
  55. }
  56. static void hdmi_runtime_put(void)
  57. {
  58. int r;
  59. DSSDBG("hdmi_runtime_put\n");
  60. r = pm_runtime_put_sync(&hdmi.pdev->dev);
  61. WARN_ON(r < 0 && r != -ENOSYS);
  62. }
  63. static irqreturn_t hdmi_irq_handler(int irq, void *data)
  64. {
  65. struct hdmi_wp_data *wp = data;
  66. u32 irqstatus;
  67. irqstatus = hdmi_wp_get_irqstatus(wp);
  68. hdmi_wp_set_irqstatus(wp, irqstatus);
  69. if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
  70. irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
  71. u32 v;
  72. /*
  73. * If we get both connect and disconnect interrupts at the same
  74. * time, turn off the PHY, clear interrupts, and restart, which
  75. * raises connect interrupt if a cable is connected, or nothing
  76. * if cable is not connected.
  77. */
  78. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
  79. /*
  80. * We always get bogus CONNECT & DISCONNECT interrupts when
  81. * setting the PHY to LDOON. To ignore those, we force the RXDET
  82. * line to 0 until the PHY power state has been changed.
  83. */
  84. v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
  85. v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
  86. v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
  87. hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
  88. hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
  89. HDMI_IRQ_LINK_DISCONNECT);
  90. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
  91. REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15);
  92. } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
  93. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
  94. } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
  95. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
  96. }
  97. return IRQ_HANDLED;
  98. }
  99. static int hdmi_init_regulator(void)
  100. {
  101. struct regulator *reg;
  102. if (hdmi.vdda_reg != NULL)
  103. return 0;
  104. reg = devm_regulator_get(&hdmi.pdev->dev, "vdda");
  105. if (IS_ERR(reg)) {
  106. DSSERR("can't get VDDA regulator\n");
  107. return PTR_ERR(reg);
  108. }
  109. hdmi.vdda_reg = reg;
  110. return 0;
  111. }
  112. static int hdmi_power_on_core(struct omap_dss_device *dssdev)
  113. {
  114. int r;
  115. r = regulator_enable(hdmi.vdda_reg);
  116. if (r)
  117. return r;
  118. r = hdmi_runtime_get();
  119. if (r)
  120. goto err_runtime_get;
  121. /* Make selection of HDMI in DSS */
  122. dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
  123. hdmi.core_enabled = true;
  124. return 0;
  125. err_runtime_get:
  126. regulator_disable(hdmi.vdda_reg);
  127. return r;
  128. }
  129. static void hdmi_power_off_core(struct omap_dss_device *dssdev)
  130. {
  131. hdmi.core_enabled = false;
  132. hdmi_runtime_put();
  133. regulator_disable(hdmi.vdda_reg);
  134. }
  135. static int hdmi_power_on_full(struct omap_dss_device *dssdev)
  136. {
  137. int r;
  138. struct videomode *vm;
  139. enum omap_channel channel = dssdev->dispc_channel;
  140. struct dss_pll_clock_info hdmi_cinfo = { 0 };
  141. unsigned pc;
  142. r = hdmi_power_on_core(dssdev);
  143. if (r)
  144. return r;
  145. vm = &hdmi.cfg.vm;
  146. DSSDBG("hdmi_power_on hactive= %d vactive = %d\n", vm->hactive,
  147. vm->vactive);
  148. pc = vm->pixelclock;
  149. if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
  150. pc *= 2;
  151. /* DSS_HDMI_TCLK is bitclk / 10 */
  152. pc *= 10;
  153. dss_pll_calc_b(&hdmi.pll.pll, clk_get_rate(hdmi.pll.pll.clkin),
  154. pc, &hdmi_cinfo);
  155. /* disable and clear irqs */
  156. hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
  157. hdmi_wp_set_irqstatus(&hdmi.wp,
  158. hdmi_wp_get_irqstatus(&hdmi.wp));
  159. r = dss_pll_enable(&hdmi.pll.pll);
  160. if (r) {
  161. DSSERR("Failed to enable PLL\n");
  162. goto err_pll_enable;
  163. }
  164. r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo);
  165. if (r) {
  166. DSSERR("Failed to configure PLL\n");
  167. goto err_pll_cfg;
  168. }
  169. r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco,
  170. hdmi_cinfo.clkout[0]);
  171. if (r) {
  172. DSSDBG("Failed to start PHY\n");
  173. goto err_phy_cfg;
  174. }
  175. r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON);
  176. if (r)
  177. goto err_phy_pwr;
  178. hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
  179. /* tv size */
  180. dss_mgr_set_timings(channel, vm);
  181. r = dss_mgr_enable(channel);
  182. if (r)
  183. goto err_mgr_enable;
  184. r = hdmi_wp_video_start(&hdmi.wp);
  185. if (r)
  186. goto err_vid_enable;
  187. hdmi_wp_set_irqenable(&hdmi.wp,
  188. HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
  189. return 0;
  190. err_vid_enable:
  191. dss_mgr_disable(channel);
  192. err_mgr_enable:
  193. hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
  194. err_phy_pwr:
  195. err_phy_cfg:
  196. err_pll_cfg:
  197. dss_pll_disable(&hdmi.pll.pll);
  198. err_pll_enable:
  199. hdmi_power_off_core(dssdev);
  200. return -EIO;
  201. }
  202. static void hdmi_power_off_full(struct omap_dss_device *dssdev)
  203. {
  204. enum omap_channel channel = dssdev->dispc_channel;
  205. hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
  206. hdmi_wp_video_stop(&hdmi.wp);
  207. dss_mgr_disable(channel);
  208. hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
  209. dss_pll_disable(&hdmi.pll.pll);
  210. hdmi_power_off_core(dssdev);
  211. }
  212. static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
  213. struct videomode *vm)
  214. {
  215. if (!dispc_mgr_timings_ok(dssdev->dispc_channel, vm))
  216. return -EINVAL;
  217. return 0;
  218. }
  219. static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
  220. struct videomode *vm)
  221. {
  222. mutex_lock(&hdmi.lock);
  223. hdmi.cfg.vm = *vm;
  224. dispc_set_tv_pclk(vm->pixelclock);
  225. mutex_unlock(&hdmi.lock);
  226. }
  227. static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
  228. struct videomode *vm)
  229. {
  230. *vm = hdmi.cfg.vm;
  231. }
  232. static void hdmi_dump_regs(struct seq_file *s)
  233. {
  234. mutex_lock(&hdmi.lock);
  235. if (hdmi_runtime_get()) {
  236. mutex_unlock(&hdmi.lock);
  237. return;
  238. }
  239. hdmi_wp_dump(&hdmi.wp, s);
  240. hdmi_pll_dump(&hdmi.pll, s);
  241. hdmi_phy_dump(&hdmi.phy, s);
  242. hdmi5_core_dump(&hdmi.core, s);
  243. hdmi_runtime_put();
  244. mutex_unlock(&hdmi.lock);
  245. }
  246. static int read_edid(u8 *buf, int len)
  247. {
  248. int r;
  249. int idlemode;
  250. mutex_lock(&hdmi.lock);
  251. r = hdmi_runtime_get();
  252. BUG_ON(r);
  253. idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
  254. /* No-idle mode */
  255. REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
  256. r = hdmi5_read_edid(&hdmi.core, buf, len);
  257. REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
  258. hdmi_runtime_put();
  259. mutex_unlock(&hdmi.lock);
  260. return r;
  261. }
  262. static void hdmi_start_audio_stream(struct omap_hdmi *hd)
  263. {
  264. REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
  265. hdmi_wp_audio_enable(&hd->wp, true);
  266. hdmi_wp_audio_core_req_enable(&hd->wp, true);
  267. }
  268. static void hdmi_stop_audio_stream(struct omap_hdmi *hd)
  269. {
  270. hdmi_wp_audio_core_req_enable(&hd->wp, false);
  271. hdmi_wp_audio_enable(&hd->wp, false);
  272. REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2);
  273. }
  274. static int hdmi_display_enable(struct omap_dss_device *dssdev)
  275. {
  276. struct omap_dss_device *out = &hdmi.output;
  277. unsigned long flags;
  278. int r = 0;
  279. DSSDBG("ENTER hdmi_display_enable\n");
  280. mutex_lock(&hdmi.lock);
  281. if (!out->dispc_channel_connected) {
  282. DSSERR("failed to enable display: no output/manager\n");
  283. r = -ENODEV;
  284. goto err0;
  285. }
  286. r = hdmi_power_on_full(dssdev);
  287. if (r) {
  288. DSSERR("failed to power on device\n");
  289. goto err0;
  290. }
  291. if (hdmi.audio_configured) {
  292. r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config,
  293. hdmi.cfg.vm.pixelclock);
  294. if (r) {
  295. DSSERR("Error restoring audio configuration: %d", r);
  296. hdmi.audio_abort_cb(&hdmi.pdev->dev);
  297. hdmi.audio_configured = false;
  298. }
  299. }
  300. spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
  301. if (hdmi.audio_configured && hdmi.audio_playing)
  302. hdmi_start_audio_stream(&hdmi);
  303. hdmi.display_enabled = true;
  304. spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
  305. mutex_unlock(&hdmi.lock);
  306. return 0;
  307. err0:
  308. mutex_unlock(&hdmi.lock);
  309. return r;
  310. }
  311. static void hdmi_display_disable(struct omap_dss_device *dssdev)
  312. {
  313. unsigned long flags;
  314. DSSDBG("Enter hdmi_display_disable\n");
  315. mutex_lock(&hdmi.lock);
  316. spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
  317. hdmi_stop_audio_stream(&hdmi);
  318. hdmi.display_enabled = false;
  319. spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
  320. hdmi_power_off_full(dssdev);
  321. mutex_unlock(&hdmi.lock);
  322. }
  323. static int hdmi_core_enable(struct omap_dss_device *dssdev)
  324. {
  325. int r = 0;
  326. DSSDBG("ENTER omapdss_hdmi_core_enable\n");
  327. mutex_lock(&hdmi.lock);
  328. r = hdmi_power_on_core(dssdev);
  329. if (r) {
  330. DSSERR("failed to power on device\n");
  331. goto err0;
  332. }
  333. mutex_unlock(&hdmi.lock);
  334. return 0;
  335. err0:
  336. mutex_unlock(&hdmi.lock);
  337. return r;
  338. }
  339. static void hdmi_core_disable(struct omap_dss_device *dssdev)
  340. {
  341. DSSDBG("Enter omapdss_hdmi_core_disable\n");
  342. mutex_lock(&hdmi.lock);
  343. hdmi_power_off_core(dssdev);
  344. mutex_unlock(&hdmi.lock);
  345. }
  346. static int hdmi_connect(struct omap_dss_device *dssdev,
  347. struct omap_dss_device *dst)
  348. {
  349. enum omap_channel channel = dssdev->dispc_channel;
  350. int r;
  351. r = hdmi_init_regulator();
  352. if (r)
  353. return r;
  354. r = dss_mgr_connect(channel, dssdev);
  355. if (r)
  356. return r;
  357. r = omapdss_output_set_device(dssdev, dst);
  358. if (r) {
  359. DSSERR("failed to connect output to new device: %s\n",
  360. dst->name);
  361. dss_mgr_disconnect(channel, dssdev);
  362. return r;
  363. }
  364. return 0;
  365. }
  366. static void hdmi_disconnect(struct omap_dss_device *dssdev,
  367. struct omap_dss_device *dst)
  368. {
  369. enum omap_channel channel = dssdev->dispc_channel;
  370. WARN_ON(dst != dssdev->dst);
  371. if (dst != dssdev->dst)
  372. return;
  373. omapdss_output_unset_device(dssdev);
  374. dss_mgr_disconnect(channel, dssdev);
  375. }
  376. static int hdmi_read_edid(struct omap_dss_device *dssdev,
  377. u8 *edid, int len)
  378. {
  379. bool need_enable;
  380. int r;
  381. need_enable = hdmi.core_enabled == false;
  382. if (need_enable) {
  383. r = hdmi_core_enable(dssdev);
  384. if (r)
  385. return r;
  386. }
  387. r = read_edid(edid, len);
  388. if (need_enable)
  389. hdmi_core_disable(dssdev);
  390. return r;
  391. }
  392. static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
  393. const struct hdmi_avi_infoframe *avi)
  394. {
  395. hdmi.cfg.infoframe = *avi;
  396. return 0;
  397. }
  398. static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
  399. bool hdmi_mode)
  400. {
  401. hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
  402. return 0;
  403. }
  404. static const struct omapdss_hdmi_ops hdmi_ops = {
  405. .connect = hdmi_connect,
  406. .disconnect = hdmi_disconnect,
  407. .enable = hdmi_display_enable,
  408. .disable = hdmi_display_disable,
  409. .check_timings = hdmi_display_check_timing,
  410. .set_timings = hdmi_display_set_timing,
  411. .get_timings = hdmi_display_get_timings,
  412. .read_edid = hdmi_read_edid,
  413. .set_infoframe = hdmi_set_infoframe,
  414. .set_hdmi_mode = hdmi_set_hdmi_mode,
  415. };
  416. static void hdmi_init_output(struct platform_device *pdev)
  417. {
  418. struct omap_dss_device *out = &hdmi.output;
  419. out->dev = &pdev->dev;
  420. out->id = OMAP_DSS_OUTPUT_HDMI;
  421. out->output_type = OMAP_DISPLAY_TYPE_HDMI;
  422. out->name = "hdmi.0";
  423. out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
  424. out->ops.hdmi = &hdmi_ops;
  425. out->owner = THIS_MODULE;
  426. omapdss_register_output(out);
  427. }
  428. static void hdmi_uninit_output(struct platform_device *pdev)
  429. {
  430. struct omap_dss_device *out = &hdmi.output;
  431. omapdss_unregister_output(out);
  432. }
  433. static int hdmi_probe_of(struct platform_device *pdev)
  434. {
  435. struct device_node *node = pdev->dev.of_node;
  436. struct device_node *ep;
  437. int r;
  438. ep = omapdss_of_get_first_endpoint(node);
  439. if (!ep)
  440. return 0;
  441. r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy);
  442. if (r)
  443. goto err;
  444. of_node_put(ep);
  445. return 0;
  446. err:
  447. of_node_put(ep);
  448. return r;
  449. }
  450. /* Audio callbacks */
  451. static int hdmi_audio_startup(struct device *dev,
  452. void (*abort_cb)(struct device *dev))
  453. {
  454. struct omap_hdmi *hd = dev_get_drvdata(dev);
  455. int ret = 0;
  456. mutex_lock(&hd->lock);
  457. if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
  458. ret = -EPERM;
  459. goto out;
  460. }
  461. hd->audio_abort_cb = abort_cb;
  462. out:
  463. mutex_unlock(&hd->lock);
  464. return ret;
  465. }
  466. static int hdmi_audio_shutdown(struct device *dev)
  467. {
  468. struct omap_hdmi *hd = dev_get_drvdata(dev);
  469. mutex_lock(&hd->lock);
  470. hd->audio_abort_cb = NULL;
  471. hd->audio_configured = false;
  472. hd->audio_playing = false;
  473. mutex_unlock(&hd->lock);
  474. return 0;
  475. }
  476. static int hdmi_audio_start(struct device *dev)
  477. {
  478. struct omap_hdmi *hd = dev_get_drvdata(dev);
  479. unsigned long flags;
  480. WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
  481. spin_lock_irqsave(&hd->audio_playing_lock, flags);
  482. if (hd->display_enabled)
  483. hdmi_start_audio_stream(hd);
  484. hd->audio_playing = true;
  485. spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
  486. return 0;
  487. }
  488. static void hdmi_audio_stop(struct device *dev)
  489. {
  490. struct omap_hdmi *hd = dev_get_drvdata(dev);
  491. unsigned long flags;
  492. WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
  493. spin_lock_irqsave(&hd->audio_playing_lock, flags);
  494. if (hd->display_enabled)
  495. hdmi_stop_audio_stream(hd);
  496. hd->audio_playing = false;
  497. spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
  498. }
  499. static int hdmi_audio_config(struct device *dev,
  500. struct omap_dss_audio *dss_audio)
  501. {
  502. struct omap_hdmi *hd = dev_get_drvdata(dev);
  503. int ret;
  504. mutex_lock(&hd->lock);
  505. if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
  506. ret = -EPERM;
  507. goto out;
  508. }
  509. ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,
  510. hd->cfg.vm.pixelclock);
  511. if (!ret) {
  512. hd->audio_configured = true;
  513. hd->audio_config = *dss_audio;
  514. }
  515. out:
  516. mutex_unlock(&hd->lock);
  517. return ret;
  518. }
  519. static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
  520. .audio_startup = hdmi_audio_startup,
  521. .audio_shutdown = hdmi_audio_shutdown,
  522. .audio_start = hdmi_audio_start,
  523. .audio_stop = hdmi_audio_stop,
  524. .audio_config = hdmi_audio_config,
  525. };
  526. static int hdmi_audio_register(struct device *dev)
  527. {
  528. struct omap_hdmi_audio_pdata pdata = {
  529. .dev = dev,
  530. .dss_version = omapdss_get_version(),
  531. .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp),
  532. .ops = &hdmi_audio_ops,
  533. };
  534. hdmi.audio_pdev = platform_device_register_data(
  535. dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
  536. &pdata, sizeof(pdata));
  537. if (IS_ERR(hdmi.audio_pdev))
  538. return PTR_ERR(hdmi.audio_pdev);
  539. hdmi_runtime_get();
  540. hdmi.wp_idlemode =
  541. REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
  542. hdmi_runtime_put();
  543. return 0;
  544. }
  545. /* HDMI HW IP initialisation */
  546. static int hdmi5_bind(struct device *dev, struct device *master, void *data)
  547. {
  548. struct platform_device *pdev = to_platform_device(dev);
  549. int r;
  550. int irq;
  551. hdmi.pdev = pdev;
  552. dev_set_drvdata(&pdev->dev, &hdmi);
  553. mutex_init(&hdmi.lock);
  554. spin_lock_init(&hdmi.audio_playing_lock);
  555. if (pdev->dev.of_node) {
  556. r = hdmi_probe_of(pdev);
  557. if (r)
  558. return r;
  559. }
  560. r = hdmi_wp_init(pdev, &hdmi.wp);
  561. if (r)
  562. return r;
  563. r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
  564. if (r)
  565. return r;
  566. r = hdmi_phy_init(pdev, &hdmi.phy);
  567. if (r)
  568. goto err;
  569. r = hdmi5_core_init(pdev, &hdmi.core);
  570. if (r)
  571. goto err;
  572. irq = platform_get_irq(pdev, 0);
  573. if (irq < 0) {
  574. DSSERR("platform_get_irq failed\n");
  575. r = -ENODEV;
  576. goto err;
  577. }
  578. r = devm_request_threaded_irq(&pdev->dev, irq,
  579. NULL, hdmi_irq_handler,
  580. IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
  581. if (r) {
  582. DSSERR("HDMI IRQ request failed\n");
  583. goto err;
  584. }
  585. pm_runtime_enable(&pdev->dev);
  586. hdmi_init_output(pdev);
  587. r = hdmi_audio_register(&pdev->dev);
  588. if (r) {
  589. DSSERR("Registering HDMI audio failed %d\n", r);
  590. hdmi_uninit_output(pdev);
  591. pm_runtime_disable(&pdev->dev);
  592. return r;
  593. }
  594. dss_debugfs_create_file("hdmi", hdmi_dump_regs);
  595. return 0;
  596. err:
  597. hdmi_pll_uninit(&hdmi.pll);
  598. return r;
  599. }
  600. static void hdmi5_unbind(struct device *dev, struct device *master, void *data)
  601. {
  602. struct platform_device *pdev = to_platform_device(dev);
  603. if (hdmi.audio_pdev)
  604. platform_device_unregister(hdmi.audio_pdev);
  605. hdmi_uninit_output(pdev);
  606. hdmi_pll_uninit(&hdmi.pll);
  607. pm_runtime_disable(&pdev->dev);
  608. }
  609. static const struct component_ops hdmi5_component_ops = {
  610. .bind = hdmi5_bind,
  611. .unbind = hdmi5_unbind,
  612. };
  613. static int hdmi5_probe(struct platform_device *pdev)
  614. {
  615. return component_add(&pdev->dev, &hdmi5_component_ops);
  616. }
  617. static int hdmi5_remove(struct platform_device *pdev)
  618. {
  619. component_del(&pdev->dev, &hdmi5_component_ops);
  620. return 0;
  621. }
  622. static int hdmi_runtime_suspend(struct device *dev)
  623. {
  624. dispc_runtime_put();
  625. return 0;
  626. }
  627. static int hdmi_runtime_resume(struct device *dev)
  628. {
  629. int r;
  630. r = dispc_runtime_get();
  631. if (r < 0)
  632. return r;
  633. return 0;
  634. }
  635. static const struct dev_pm_ops hdmi_pm_ops = {
  636. .runtime_suspend = hdmi_runtime_suspend,
  637. .runtime_resume = hdmi_runtime_resume,
  638. };
  639. static const struct of_device_id hdmi_of_match[] = {
  640. { .compatible = "ti,omap5-hdmi", },
  641. { .compatible = "ti,dra7-hdmi", },
  642. {},
  643. };
  644. static struct platform_driver omapdss_hdmihw_driver = {
  645. .probe = hdmi5_probe,
  646. .remove = hdmi5_remove,
  647. .driver = {
  648. .name = "omapdss_hdmi5",
  649. .pm = &hdmi_pm_ops,
  650. .of_match_table = hdmi_of_match,
  651. .suppress_bind_attrs = true,
  652. },
  653. };
  654. int __init hdmi5_init_platform_driver(void)
  655. {
  656. return platform_driver_register(&omapdss_hdmihw_driver);
  657. }
  658. void hdmi5_uninit_platform_driver(void)
  659. {
  660. platform_driver_unregister(&omapdss_hdmihw_driver);
  661. }