panel-tpo-td028ttec1.c 12 KB

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  1. /*
  2. * Toppoly TD028TTEC1 panel support
  3. *
  4. * Copyright (C) 2008 Nokia Corporation
  5. * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
  6. *
  7. * Neo 1973 code (jbt6k74.c):
  8. * Copyright (C) 2006-2007 by OpenMoko, Inc.
  9. * Author: Harald Welte <laforge@openmoko.org>
  10. *
  11. * Ported and adapted from Neo 1973 U-Boot by:
  12. * H. Nikolaus Schaller <hns@goldelico.com>
  13. *
  14. * This program is free software; you can redistribute it and/or modify it
  15. * under the terms of the GNU General Public License version 2 as published by
  16. * the Free Software Foundation.
  17. *
  18. * This program is distributed in the hope that it will be useful, but WITHOUT
  19. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  21. * more details.
  22. *
  23. * You should have received a copy of the GNU General Public License along with
  24. * this program. If not, see <http://www.gnu.org/licenses/>.
  25. */
  26. #include <linux/module.h>
  27. #include <linux/delay.h>
  28. #include <linux/spi/spi.h>
  29. #include <linux/gpio.h>
  30. #include "../dss/omapdss.h"
  31. struct panel_drv_data {
  32. struct omap_dss_device dssdev;
  33. struct omap_dss_device *in;
  34. int data_lines;
  35. struct videomode vm;
  36. struct spi_device *spi_dev;
  37. };
  38. static struct videomode td028ttec1_panel_vm = {
  39. .hactive = 480,
  40. .vactive = 640,
  41. .pixelclock = 22153000,
  42. .hfront_porch = 24,
  43. .hsync_len = 8,
  44. .hback_porch = 8,
  45. .vfront_porch = 4,
  46. .vsync_len = 2,
  47. .vback_porch = 2,
  48. .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
  49. DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_POSEDGE |
  50. DISPLAY_FLAGS_PIXDATA_NEGEDGE,
  51. /*
  52. * Note: According to the panel documentation:
  53. * SYNC needs to be driven on the FALLING edge
  54. */
  55. };
  56. #define JBT_COMMAND 0x000
  57. #define JBT_DATA 0x100
  58. static int jbt_ret_write_0(struct panel_drv_data *ddata, u8 reg)
  59. {
  60. int rc;
  61. u16 tx_buf = JBT_COMMAND | reg;
  62. rc = spi_write(ddata->spi_dev, (u8 *)&tx_buf,
  63. 1*sizeof(u16));
  64. if (rc != 0)
  65. dev_err(&ddata->spi_dev->dev,
  66. "jbt_ret_write_0 spi_write ret %d\n", rc);
  67. return rc;
  68. }
  69. static int jbt_reg_write_1(struct panel_drv_data *ddata, u8 reg, u8 data)
  70. {
  71. int rc;
  72. u16 tx_buf[2];
  73. tx_buf[0] = JBT_COMMAND | reg;
  74. tx_buf[1] = JBT_DATA | data;
  75. rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
  76. 2*sizeof(u16));
  77. if (rc != 0)
  78. dev_err(&ddata->spi_dev->dev,
  79. "jbt_reg_write_1 spi_write ret %d\n", rc);
  80. return rc;
  81. }
  82. static int jbt_reg_write_2(struct panel_drv_data *ddata, u8 reg, u16 data)
  83. {
  84. int rc;
  85. u16 tx_buf[3];
  86. tx_buf[0] = JBT_COMMAND | reg;
  87. tx_buf[1] = JBT_DATA | (data >> 8);
  88. tx_buf[2] = JBT_DATA | (data & 0xff);
  89. rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
  90. 3*sizeof(u16));
  91. if (rc != 0)
  92. dev_err(&ddata->spi_dev->dev,
  93. "jbt_reg_write_2 spi_write ret %d\n", rc);
  94. return rc;
  95. }
  96. enum jbt_register {
  97. JBT_REG_SLEEP_IN = 0x10,
  98. JBT_REG_SLEEP_OUT = 0x11,
  99. JBT_REG_DISPLAY_OFF = 0x28,
  100. JBT_REG_DISPLAY_ON = 0x29,
  101. JBT_REG_RGB_FORMAT = 0x3a,
  102. JBT_REG_QUAD_RATE = 0x3b,
  103. JBT_REG_POWER_ON_OFF = 0xb0,
  104. JBT_REG_BOOSTER_OP = 0xb1,
  105. JBT_REG_BOOSTER_MODE = 0xb2,
  106. JBT_REG_BOOSTER_FREQ = 0xb3,
  107. JBT_REG_OPAMP_SYSCLK = 0xb4,
  108. JBT_REG_VSC_VOLTAGE = 0xb5,
  109. JBT_REG_VCOM_VOLTAGE = 0xb6,
  110. JBT_REG_EXT_DISPL = 0xb7,
  111. JBT_REG_OUTPUT_CONTROL = 0xb8,
  112. JBT_REG_DCCLK_DCEV = 0xb9,
  113. JBT_REG_DISPLAY_MODE1 = 0xba,
  114. JBT_REG_DISPLAY_MODE2 = 0xbb,
  115. JBT_REG_DISPLAY_MODE = 0xbc,
  116. JBT_REG_ASW_SLEW = 0xbd,
  117. JBT_REG_DUMMY_DISPLAY = 0xbe,
  118. JBT_REG_DRIVE_SYSTEM = 0xbf,
  119. JBT_REG_SLEEP_OUT_FR_A = 0xc0,
  120. JBT_REG_SLEEP_OUT_FR_B = 0xc1,
  121. JBT_REG_SLEEP_OUT_FR_C = 0xc2,
  122. JBT_REG_SLEEP_IN_LCCNT_D = 0xc3,
  123. JBT_REG_SLEEP_IN_LCCNT_E = 0xc4,
  124. JBT_REG_SLEEP_IN_LCCNT_F = 0xc5,
  125. JBT_REG_SLEEP_IN_LCCNT_G = 0xc6,
  126. JBT_REG_GAMMA1_FINE_1 = 0xc7,
  127. JBT_REG_GAMMA1_FINE_2 = 0xc8,
  128. JBT_REG_GAMMA1_INCLINATION = 0xc9,
  129. JBT_REG_GAMMA1_BLUE_OFFSET = 0xca,
  130. JBT_REG_BLANK_CONTROL = 0xcf,
  131. JBT_REG_BLANK_TH_TV = 0xd0,
  132. JBT_REG_CKV_ON_OFF = 0xd1,
  133. JBT_REG_CKV_1_2 = 0xd2,
  134. JBT_REG_OEV_TIMING = 0xd3,
  135. JBT_REG_ASW_TIMING_1 = 0xd4,
  136. JBT_REG_ASW_TIMING_2 = 0xd5,
  137. JBT_REG_HCLOCK_VGA = 0xec,
  138. JBT_REG_HCLOCK_QVGA = 0xed,
  139. };
  140. #define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
  141. static int td028ttec1_panel_connect(struct omap_dss_device *dssdev)
  142. {
  143. struct panel_drv_data *ddata = to_panel_data(dssdev);
  144. struct omap_dss_device *in = ddata->in;
  145. int r;
  146. if (omapdss_device_is_connected(dssdev))
  147. return 0;
  148. r = in->ops.dpi->connect(in, dssdev);
  149. if (r)
  150. return r;
  151. return 0;
  152. }
  153. static void td028ttec1_panel_disconnect(struct omap_dss_device *dssdev)
  154. {
  155. struct panel_drv_data *ddata = to_panel_data(dssdev);
  156. struct omap_dss_device *in = ddata->in;
  157. if (!omapdss_device_is_connected(dssdev))
  158. return;
  159. in->ops.dpi->disconnect(in, dssdev);
  160. }
  161. static int td028ttec1_panel_enable(struct omap_dss_device *dssdev)
  162. {
  163. struct panel_drv_data *ddata = to_panel_data(dssdev);
  164. struct omap_dss_device *in = ddata->in;
  165. int r;
  166. if (!omapdss_device_is_connected(dssdev))
  167. return -ENODEV;
  168. if (omapdss_device_is_enabled(dssdev))
  169. return 0;
  170. if (ddata->data_lines)
  171. in->ops.dpi->set_data_lines(in, ddata->data_lines);
  172. in->ops.dpi->set_timings(in, &ddata->vm);
  173. r = in->ops.dpi->enable(in);
  174. if (r)
  175. return r;
  176. dev_dbg(dssdev->dev, "td028ttec1_panel_enable() - state %d\n",
  177. dssdev->state);
  178. /* three times command zero */
  179. r |= jbt_ret_write_0(ddata, 0x00);
  180. usleep_range(1000, 2000);
  181. r |= jbt_ret_write_0(ddata, 0x00);
  182. usleep_range(1000, 2000);
  183. r |= jbt_ret_write_0(ddata, 0x00);
  184. usleep_range(1000, 2000);
  185. if (r) {
  186. dev_warn(dssdev->dev, "transfer error\n");
  187. goto transfer_err;
  188. }
  189. /* deep standby out */
  190. r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x17);
  191. /* RGB I/F on, RAM write off, QVGA through, SIGCON enable */
  192. r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE, 0x80);
  193. /* Quad mode off */
  194. r |= jbt_reg_write_1(ddata, JBT_REG_QUAD_RATE, 0x00);
  195. /* AVDD on, XVDD on */
  196. r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x16);
  197. /* Output control */
  198. r |= jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0xfff9);
  199. /* Sleep mode off */
  200. r |= jbt_ret_write_0(ddata, JBT_REG_SLEEP_OUT);
  201. /* at this point we have like 50% grey */
  202. /* initialize register set */
  203. r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE1, 0x01);
  204. r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE2, 0x00);
  205. r |= jbt_reg_write_1(ddata, JBT_REG_RGB_FORMAT, 0x60);
  206. r |= jbt_reg_write_1(ddata, JBT_REG_DRIVE_SYSTEM, 0x10);
  207. r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_OP, 0x56);
  208. r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_MODE, 0x33);
  209. r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
  210. r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
  211. r |= jbt_reg_write_1(ddata, JBT_REG_OPAMP_SYSCLK, 0x02);
  212. r |= jbt_reg_write_1(ddata, JBT_REG_VSC_VOLTAGE, 0x2b);
  213. r |= jbt_reg_write_1(ddata, JBT_REG_VCOM_VOLTAGE, 0x40);
  214. r |= jbt_reg_write_1(ddata, JBT_REG_EXT_DISPL, 0x03);
  215. r |= jbt_reg_write_1(ddata, JBT_REG_DCCLK_DCEV, 0x04);
  216. /*
  217. * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
  218. * to avoid red / blue flicker
  219. */
  220. r |= jbt_reg_write_1(ddata, JBT_REG_ASW_SLEW, 0x04);
  221. r |= jbt_reg_write_1(ddata, JBT_REG_DUMMY_DISPLAY, 0x00);
  222. r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_A, 0x11);
  223. r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_B, 0x11);
  224. r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_C, 0x11);
  225. r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
  226. r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
  227. r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
  228. r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
  229. r |= jbt_reg_write_2(ddata, JBT_REG_GAMMA1_FINE_1, 0x5533);
  230. r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_FINE_2, 0x00);
  231. r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_INCLINATION, 0x00);
  232. r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
  233. r |= jbt_reg_write_2(ddata, JBT_REG_HCLOCK_VGA, 0x1f0);
  234. r |= jbt_reg_write_1(ddata, JBT_REG_BLANK_CONTROL, 0x02);
  235. r |= jbt_reg_write_2(ddata, JBT_REG_BLANK_TH_TV, 0x0804);
  236. r |= jbt_reg_write_1(ddata, JBT_REG_CKV_ON_OFF, 0x01);
  237. r |= jbt_reg_write_2(ddata, JBT_REG_CKV_1_2, 0x0000);
  238. r |= jbt_reg_write_2(ddata, JBT_REG_OEV_TIMING, 0x0d0e);
  239. r |= jbt_reg_write_2(ddata, JBT_REG_ASW_TIMING_1, 0x11a4);
  240. r |= jbt_reg_write_1(ddata, JBT_REG_ASW_TIMING_2, 0x0e);
  241. r |= jbt_ret_write_0(ddata, JBT_REG_DISPLAY_ON);
  242. dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
  243. transfer_err:
  244. return r ? -EIO : 0;
  245. }
  246. static void td028ttec1_panel_disable(struct omap_dss_device *dssdev)
  247. {
  248. struct panel_drv_data *ddata = to_panel_data(dssdev);
  249. struct omap_dss_device *in = ddata->in;
  250. if (!omapdss_device_is_enabled(dssdev))
  251. return;
  252. dev_dbg(dssdev->dev, "td028ttec1_panel_disable()\n");
  253. jbt_ret_write_0(ddata, JBT_REG_DISPLAY_OFF);
  254. jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0x8002);
  255. jbt_ret_write_0(ddata, JBT_REG_SLEEP_IN);
  256. jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x00);
  257. in->ops.dpi->disable(in);
  258. dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
  259. }
  260. static void td028ttec1_panel_set_timings(struct omap_dss_device *dssdev,
  261. struct videomode *vm)
  262. {
  263. struct panel_drv_data *ddata = to_panel_data(dssdev);
  264. struct omap_dss_device *in = ddata->in;
  265. ddata->vm = *vm;
  266. dssdev->panel.vm = *vm;
  267. in->ops.dpi->set_timings(in, vm);
  268. }
  269. static void td028ttec1_panel_get_timings(struct omap_dss_device *dssdev,
  270. struct videomode *vm)
  271. {
  272. struct panel_drv_data *ddata = to_panel_data(dssdev);
  273. *vm = ddata->vm;
  274. }
  275. static int td028ttec1_panel_check_timings(struct omap_dss_device *dssdev,
  276. struct videomode *vm)
  277. {
  278. struct panel_drv_data *ddata = to_panel_data(dssdev);
  279. struct omap_dss_device *in = ddata->in;
  280. return in->ops.dpi->check_timings(in, vm);
  281. }
  282. static struct omap_dss_driver td028ttec1_ops = {
  283. .connect = td028ttec1_panel_connect,
  284. .disconnect = td028ttec1_panel_disconnect,
  285. .enable = td028ttec1_panel_enable,
  286. .disable = td028ttec1_panel_disable,
  287. .set_timings = td028ttec1_panel_set_timings,
  288. .get_timings = td028ttec1_panel_get_timings,
  289. .check_timings = td028ttec1_panel_check_timings,
  290. };
  291. static int td028ttec1_probe_of(struct spi_device *spi)
  292. {
  293. struct device_node *node = spi->dev.of_node;
  294. struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
  295. struct omap_dss_device *in;
  296. in = omapdss_of_find_source_for_first_ep(node);
  297. if (IS_ERR(in)) {
  298. dev_err(&spi->dev, "failed to find video source\n");
  299. return PTR_ERR(in);
  300. }
  301. ddata->in = in;
  302. return 0;
  303. }
  304. static int td028ttec1_panel_probe(struct spi_device *spi)
  305. {
  306. struct panel_drv_data *ddata;
  307. struct omap_dss_device *dssdev;
  308. int r;
  309. dev_dbg(&spi->dev, "%s\n", __func__);
  310. spi->bits_per_word = 9;
  311. spi->mode = SPI_MODE_3;
  312. r = spi_setup(spi);
  313. if (r < 0) {
  314. dev_err(&spi->dev, "spi_setup failed: %d\n", r);
  315. return r;
  316. }
  317. ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
  318. if (ddata == NULL)
  319. return -ENOMEM;
  320. dev_set_drvdata(&spi->dev, ddata);
  321. ddata->spi_dev = spi;
  322. if (!spi->dev.of_node)
  323. return -ENODEV;
  324. r = td028ttec1_probe_of(spi);
  325. if (r)
  326. return r;
  327. ddata->vm = td028ttec1_panel_vm;
  328. dssdev = &ddata->dssdev;
  329. dssdev->dev = &spi->dev;
  330. dssdev->driver = &td028ttec1_ops;
  331. dssdev->type = OMAP_DISPLAY_TYPE_DPI;
  332. dssdev->owner = THIS_MODULE;
  333. dssdev->panel.vm = ddata->vm;
  334. dssdev->phy.dpi.data_lines = ddata->data_lines;
  335. r = omapdss_register_display(dssdev);
  336. if (r) {
  337. dev_err(&spi->dev, "Failed to register panel\n");
  338. goto err_reg;
  339. }
  340. return 0;
  341. err_reg:
  342. omap_dss_put_device(ddata->in);
  343. return r;
  344. }
  345. static int td028ttec1_panel_remove(struct spi_device *spi)
  346. {
  347. struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
  348. struct omap_dss_device *dssdev = &ddata->dssdev;
  349. struct omap_dss_device *in = ddata->in;
  350. dev_dbg(&ddata->spi_dev->dev, "%s\n", __func__);
  351. omapdss_unregister_display(dssdev);
  352. td028ttec1_panel_disable(dssdev);
  353. td028ttec1_panel_disconnect(dssdev);
  354. omap_dss_put_device(in);
  355. return 0;
  356. }
  357. static const struct of_device_id td028ttec1_of_match[] = {
  358. { .compatible = "omapdss,toppoly,td028ttec1", },
  359. {},
  360. };
  361. MODULE_DEVICE_TABLE(of, td028ttec1_of_match);
  362. static struct spi_driver td028ttec1_spi_driver = {
  363. .probe = td028ttec1_panel_probe,
  364. .remove = td028ttec1_panel_remove,
  365. .driver = {
  366. .name = "panel-tpo-td028ttec1",
  367. .of_match_table = td028ttec1_of_match,
  368. .suppress_bind_attrs = true,
  369. },
  370. };
  371. module_spi_driver(td028ttec1_spi_driver);
  372. MODULE_ALIAS("spi:toppoly,td028ttec1");
  373. MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
  374. MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver");
  375. MODULE_LICENSE("GPL");