nv05.c 4.3 KB

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  1. /*
  2. * Copyright (C) 2010 Francisco Jerez.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the
  14. * next paragraph) shall be included in all copies or substantial
  15. * portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20. * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21. * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22. * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23. * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24. *
  25. */
  26. #include "nv04.h"
  27. #include "fbmem.h"
  28. #include <subdev/bios.h>
  29. #include <subdev/bios/bmp.h>
  30. #include <subdev/bios/init.h>
  31. #include <subdev/vga.h>
  32. static void
  33. nv05_devinit_meminit(struct nvkm_devinit *init)
  34. {
  35. static const u8 default_config_tab[][2] = {
  36. { 0x24, 0x00 },
  37. { 0x28, 0x00 },
  38. { 0x24, 0x01 },
  39. { 0x1f, 0x00 },
  40. { 0x0f, 0x00 },
  41. { 0x17, 0x00 },
  42. { 0x06, 0x00 },
  43. { 0x00, 0x00 }
  44. };
  45. struct nvkm_subdev *subdev = &init->subdev;
  46. struct nvkm_device *device = subdev->device;
  47. struct nvkm_bios *bios = device->bios;
  48. struct io_mapping *fb;
  49. u32 patt = 0xdeadbeef;
  50. u16 data;
  51. u8 strap, ramcfg[2];
  52. int i, v;
  53. /* Map the framebuffer aperture */
  54. fb = fbmem_init(device);
  55. if (!fb) {
  56. nvkm_error(subdev, "failed to map fb\n");
  57. return;
  58. }
  59. strap = (nvkm_rd32(device, 0x101000) & 0x0000003c) >> 2;
  60. if ((data = bmp_mem_init_table(bios))) {
  61. ramcfg[0] = nvbios_rd08(bios, data + 2 * strap + 0);
  62. ramcfg[1] = nvbios_rd08(bios, data + 2 * strap + 1);
  63. } else {
  64. ramcfg[0] = default_config_tab[strap][0];
  65. ramcfg[1] = default_config_tab[strap][1];
  66. }
  67. /* Sequencer off */
  68. nvkm_wrvgas(device, 0, 1, nvkm_rdvgas(device, 0, 1) | 0x20);
  69. if (nvkm_rd32(device, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
  70. goto out;
  71. nvkm_mask(device, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
  72. /* If present load the hardcoded scrambling table */
  73. if (data) {
  74. for (i = 0, data += 0x10; i < 8; i++, data += 4) {
  75. u32 scramble = nvbios_rd32(bios, data);
  76. nvkm_wr32(device, NV04_PFB_SCRAMBLE(i), scramble);
  77. }
  78. }
  79. /* Set memory type/width/length defaults depending on the straps */
  80. nvkm_mask(device, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
  81. if (ramcfg[1] & 0x80)
  82. nvkm_mask(device, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
  83. nvkm_mask(device, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
  84. nvkm_mask(device, NV04_PFB_CFG1, 0, 1);
  85. /* Probe memory bus width */
  86. for (i = 0; i < 4; i++)
  87. fbmem_poke(fb, 4 * i, patt);
  88. if (fbmem_peek(fb, 0xc) != patt)
  89. nvkm_mask(device, NV04_PFB_BOOT_0,
  90. NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
  91. /* Probe memory length */
  92. v = nvkm_rd32(device, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
  93. if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
  94. (!fbmem_readback(fb, 0x1000000, ++patt) ||
  95. !fbmem_readback(fb, 0, ++patt)))
  96. nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
  97. NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
  98. if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
  99. !fbmem_readback(fb, 0x800000, ++patt))
  100. nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
  101. NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
  102. if (!fbmem_readback(fb, 0x400000, ++patt))
  103. nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
  104. NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
  105. out:
  106. /* Sequencer on */
  107. nvkm_wrvgas(device, 0, 1, nvkm_rdvgas(device, 0, 1) & ~0x20);
  108. fbmem_fini(fb);
  109. }
  110. static const struct nvkm_devinit_func
  111. nv05_devinit = {
  112. .dtor = nv04_devinit_dtor,
  113. .preinit = nv04_devinit_preinit,
  114. .post = nv04_devinit_post,
  115. .meminit = nv05_devinit_meminit,
  116. .pll_set = nv04_devinit_pll_set,
  117. };
  118. int
  119. nv05_devinit_new(struct nvkm_device *device, int index,
  120. struct nvkm_devinit **pinit)
  121. {
  122. return nv04_devinit_new_(&nv05_devinit, device, index, pinit);
  123. }