gf100.c 4.5 KB

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  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include "nv50.h"
  25. #include <core/gpuobj.h>
  26. #include <subdev/bar.h>
  27. #include <engine/disp.h>
  28. #include <engine/fifo.h>
  29. #include <nvif/class.h>
  30. #include <nvif/event.h>
  31. /*******************************************************************************
  32. * software context
  33. ******************************************************************************/
  34. static int
  35. gf100_sw_chan_vblsem_release(struct nvkm_notify *notify)
  36. {
  37. struct nv50_sw_chan *chan =
  38. container_of(notify, typeof(*chan), vblank.notify[notify->index]);
  39. struct nvkm_sw *sw = chan->base.sw;
  40. struct nvkm_device *device = sw->engine.subdev.device;
  41. u32 inst = chan->base.fifo->inst->addr >> 12;
  42. nvkm_wr32(device, 0x001718, 0x80000000 | inst);
  43. nvkm_bar_flush(device->bar);
  44. nvkm_wr32(device, 0x06000c, upper_32_bits(chan->vblank.offset));
  45. nvkm_wr32(device, 0x060010, lower_32_bits(chan->vblank.offset));
  46. nvkm_wr32(device, 0x060014, chan->vblank.value);
  47. return NVKM_NOTIFY_DROP;
  48. }
  49. static bool
  50. gf100_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data)
  51. {
  52. struct nv50_sw_chan *chan = nv50_sw_chan(base);
  53. struct nvkm_engine *engine = chan->base.object.engine;
  54. struct nvkm_device *device = engine->subdev.device;
  55. switch (mthd) {
  56. case 0x0400:
  57. chan->vblank.offset &= 0x00ffffffffULL;
  58. chan->vblank.offset |= (u64)data << 32;
  59. return true;
  60. case 0x0404:
  61. chan->vblank.offset &= 0xff00000000ULL;
  62. chan->vblank.offset |= data;
  63. return true;
  64. case 0x0408:
  65. chan->vblank.value = data;
  66. return true;
  67. case 0x040c:
  68. if (data < device->disp->vblank.index_nr) {
  69. nvkm_notify_get(&chan->vblank.notify[data]);
  70. return true;
  71. }
  72. break;
  73. case 0x600: /* MP.PM_UNK000 */
  74. nvkm_wr32(device, 0x419e00, data);
  75. return true;
  76. case 0x644: /* MP.TRAP_WARP_ERROR_EN */
  77. if (!(data & ~0x001ffffe)) {
  78. nvkm_wr32(device, 0x419e44, data);
  79. return true;
  80. }
  81. break;
  82. case 0x6ac: /* MP.PM_UNK0AC */
  83. nvkm_wr32(device, 0x419eac, data);
  84. return true;
  85. default:
  86. break;
  87. }
  88. return false;
  89. }
  90. static const struct nvkm_sw_chan_func
  91. gf100_sw_chan = {
  92. .dtor = nv50_sw_chan_dtor,
  93. .mthd = gf100_sw_chan_mthd,
  94. };
  95. static int
  96. gf100_sw_chan_new(struct nvkm_sw *sw, struct nvkm_fifo_chan *fifoch,
  97. const struct nvkm_oclass *oclass,
  98. struct nvkm_object **pobject)
  99. {
  100. struct nvkm_disp *disp = sw->engine.subdev.device->disp;
  101. struct nv50_sw_chan *chan;
  102. int ret, i;
  103. if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
  104. return -ENOMEM;
  105. *pobject = &chan->base.object;
  106. ret = nvkm_sw_chan_ctor(&gf100_sw_chan, sw, fifoch, oclass,
  107. &chan->base);
  108. if (ret)
  109. return ret;
  110. for (i = 0; disp && i < disp->vblank.index_nr; i++) {
  111. ret = nvkm_notify_init(NULL, &disp->vblank,
  112. gf100_sw_chan_vblsem_release, false,
  113. &(struct nvif_notify_head_req_v0) {
  114. .head = i,
  115. },
  116. sizeof(struct nvif_notify_head_req_v0),
  117. sizeof(struct nvif_notify_head_rep_v0),
  118. &chan->vblank.notify[i]);
  119. if (ret)
  120. return ret;
  121. }
  122. return 0;
  123. }
  124. /*******************************************************************************
  125. * software engine/subdev functions
  126. ******************************************************************************/
  127. static const struct nvkm_sw_func
  128. gf100_sw = {
  129. .chan_new = gf100_sw_chan_new,
  130. .sclass = {
  131. { nvkm_nvsw_new, { -1, -1, NVIF_CLASS_SW_GF100 } },
  132. {}
  133. }
  134. };
  135. int
  136. gf100_sw_new(struct nvkm_device *device, int index, struct nvkm_sw **psw)
  137. {
  138. return nvkm_sw_new_(&gf100_sw, device, index, psw);
  139. }