nv50.c 4.0 KB

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  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include "nv50.h"
  25. #include "channv50.h"
  26. #include <core/gpuobj.h>
  27. static void
  28. nv50_fifo_runlist_update_locked(struct nv50_fifo *fifo)
  29. {
  30. struct nvkm_device *device = fifo->base.engine.subdev.device;
  31. struct nvkm_memory *cur;
  32. int i, p;
  33. cur = fifo->runlist[fifo->cur_runlist];
  34. fifo->cur_runlist = !fifo->cur_runlist;
  35. nvkm_kmap(cur);
  36. for (i = 0, p = 0; i < fifo->base.nr; i++) {
  37. if (nvkm_rd32(device, 0x002600 + (i * 4)) & 0x80000000)
  38. nvkm_wo32(cur, p++ * 4, i);
  39. }
  40. nvkm_done(cur);
  41. nvkm_wr32(device, 0x0032f4, nvkm_memory_addr(cur) >> 12);
  42. nvkm_wr32(device, 0x0032ec, p);
  43. nvkm_wr32(device, 0x002500, 0x00000101);
  44. }
  45. void
  46. nv50_fifo_runlist_update(struct nv50_fifo *fifo)
  47. {
  48. mutex_lock(&fifo->base.engine.subdev.mutex);
  49. nv50_fifo_runlist_update_locked(fifo);
  50. mutex_unlock(&fifo->base.engine.subdev.mutex);
  51. }
  52. int
  53. nv50_fifo_oneinit(struct nvkm_fifo *base)
  54. {
  55. struct nv50_fifo *fifo = nv50_fifo(base);
  56. struct nvkm_device *device = fifo->base.engine.subdev.device;
  57. int ret;
  58. ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000,
  59. false, &fifo->runlist[0]);
  60. if (ret)
  61. return ret;
  62. return nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000,
  63. false, &fifo->runlist[1]);
  64. }
  65. void
  66. nv50_fifo_init(struct nvkm_fifo *base)
  67. {
  68. struct nv50_fifo *fifo = nv50_fifo(base);
  69. struct nvkm_device *device = fifo->base.engine.subdev.device;
  70. int i;
  71. nvkm_mask(device, 0x000200, 0x00000100, 0x00000000);
  72. nvkm_mask(device, 0x000200, 0x00000100, 0x00000100);
  73. nvkm_wr32(device, 0x00250c, 0x6f3cfc34);
  74. nvkm_wr32(device, 0x002044, 0x01003fff);
  75. nvkm_wr32(device, 0x002100, 0xffffffff);
  76. nvkm_wr32(device, 0x002140, 0xbfffffff);
  77. for (i = 0; i < 128; i++)
  78. nvkm_wr32(device, 0x002600 + (i * 4), 0x00000000);
  79. nv50_fifo_runlist_update_locked(fifo);
  80. nvkm_wr32(device, 0x003200, 0x00000001);
  81. nvkm_wr32(device, 0x003250, 0x00000001);
  82. nvkm_wr32(device, 0x002500, 0x00000001);
  83. }
  84. void *
  85. nv50_fifo_dtor(struct nvkm_fifo *base)
  86. {
  87. struct nv50_fifo *fifo = nv50_fifo(base);
  88. nvkm_memory_del(&fifo->runlist[1]);
  89. nvkm_memory_del(&fifo->runlist[0]);
  90. return fifo;
  91. }
  92. int
  93. nv50_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device,
  94. int index, struct nvkm_fifo **pfifo)
  95. {
  96. struct nv50_fifo *fifo;
  97. int ret;
  98. if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL)))
  99. return -ENOMEM;
  100. *pfifo = &fifo->base;
  101. ret = nvkm_fifo_ctor(func, device, index, 128, &fifo->base);
  102. if (ret)
  103. return ret;
  104. set_bit(0, fifo->base.mask); /* PIO channel */
  105. set_bit(127, fifo->base.mask); /* inactive channel */
  106. return 0;
  107. }
  108. static const struct nvkm_fifo_func
  109. nv50_fifo = {
  110. .dtor = nv50_fifo_dtor,
  111. .oneinit = nv50_fifo_oneinit,
  112. .init = nv50_fifo_init,
  113. .intr = nv04_fifo_intr,
  114. .pause = nv04_fifo_pause,
  115. .start = nv04_fifo_start,
  116. .chan = {
  117. &nv50_fifo_dma_oclass,
  118. &nv50_fifo_gpfifo_oclass,
  119. NULL
  120. },
  121. };
  122. int
  123. nv50_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
  124. {
  125. return nv50_fifo_new_(&nv50_fifo, device, index, pfifo);
  126. }