usergf100.c 4.1 KB

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  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #define gf100_dmaobj(p) container_of((p), struct gf100_dmaobj, base)
  25. #include "user.h"
  26. #include <core/client.h>
  27. #include <core/gpuobj.h>
  28. #include <subdev/fb.h>
  29. #include <nvif/cl0002.h>
  30. #include <nvif/unpack.h>
  31. struct gf100_dmaobj {
  32. struct nvkm_dmaobj base;
  33. u32 flags0;
  34. u32 flags5;
  35. };
  36. static int
  37. gf100_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent,
  38. int align, struct nvkm_gpuobj **pgpuobj)
  39. {
  40. struct gf100_dmaobj *dmaobj = gf100_dmaobj(base);
  41. struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
  42. int ret;
  43. ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj);
  44. if (ret == 0) {
  45. nvkm_kmap(*pgpuobj);
  46. nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
  47. nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit));
  48. nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start));
  49. nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 |
  50. upper_32_bits(dmaobj->base.start));
  51. nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
  52. nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5);
  53. nvkm_done(*pgpuobj);
  54. }
  55. return ret;
  56. }
  57. static const struct nvkm_dmaobj_func
  58. gf100_dmaobj_func = {
  59. .bind = gf100_dmaobj_bind,
  60. };
  61. int
  62. gf100_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
  63. void *data, u32 size, struct nvkm_dmaobj **pdmaobj)
  64. {
  65. union {
  66. struct gf100_dma_v0 v0;
  67. } *args;
  68. struct nvkm_object *parent = oclass->parent;
  69. struct gf100_dmaobj *dmaobj;
  70. u32 kind, user, unkn;
  71. int ret;
  72. if (!(dmaobj = kzalloc(sizeof(*dmaobj), GFP_KERNEL)))
  73. return -ENOMEM;
  74. *pdmaobj = &dmaobj->base;
  75. ret = nvkm_dmaobj_ctor(&gf100_dmaobj_func, dma, oclass,
  76. &data, &size, &dmaobj->base);
  77. if (ret)
  78. return ret;
  79. ret = -ENOSYS;
  80. args = data;
  81. nvif_ioctl(parent, "create gf100 dma size %d\n", size);
  82. if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
  83. nvif_ioctl(parent,
  84. "create gf100 dma vers %d priv %d kind %02x\n",
  85. args->v0.version, args->v0.priv, args->v0.kind);
  86. kind = args->v0.kind;
  87. user = args->v0.priv;
  88. unkn = 0;
  89. } else
  90. if (size == 0) {
  91. if (dmaobj->base.target != NV_MEM_TARGET_VM) {
  92. kind = GF100_DMA_V0_KIND_PITCH;
  93. user = GF100_DMA_V0_PRIV_US;
  94. unkn = 2;
  95. } else {
  96. kind = GF100_DMA_V0_KIND_VM;
  97. user = GF100_DMA_V0_PRIV_VM;
  98. unkn = 0;
  99. }
  100. } else
  101. return ret;
  102. if (user > 2)
  103. return -EINVAL;
  104. dmaobj->flags0 |= (kind << 22) | (user << 20) | oclass->base.oclass;
  105. dmaobj->flags5 |= (unkn << 16);
  106. switch (dmaobj->base.target) {
  107. case NV_MEM_TARGET_VM:
  108. dmaobj->flags0 |= 0x00000000;
  109. break;
  110. case NV_MEM_TARGET_VRAM:
  111. dmaobj->flags0 |= 0x00010000;
  112. break;
  113. case NV_MEM_TARGET_PCI:
  114. dmaobj->flags0 |= 0x00020000;
  115. break;
  116. case NV_MEM_TARGET_PCI_NOSNOOP:
  117. dmaobj->flags0 |= 0x00030000;
  118. break;
  119. default:
  120. return -EINVAL;
  121. }
  122. switch (dmaobj->base.access) {
  123. case NV_MEM_ACCESS_VM:
  124. break;
  125. case NV_MEM_ACCESS_RO:
  126. dmaobj->flags0 |= 0x00040000;
  127. break;
  128. case NV_MEM_ACCESS_WO:
  129. case NV_MEM_ACCESS_RW:
  130. dmaobj->flags0 |= 0x00080000;
  131. break;
  132. }
  133. return 0;
  134. }