sorgm200.c 4.2 KB

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  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include "nv50.h"
  25. #include "outpdp.h"
  26. #include <subdev/timer.h>
  27. static inline u32
  28. gm200_sor_soff(struct nvkm_output_dp *outp)
  29. {
  30. return (ffs(outp->base.info.or) - 1) * 0x800;
  31. }
  32. static inline u32
  33. gm200_sor_loff(struct nvkm_output_dp *outp)
  34. {
  35. return gm200_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
  36. }
  37. void
  38. gm200_sor_magic(struct nvkm_output *outp)
  39. {
  40. struct nvkm_device *device = outp->disp->engine.subdev.device;
  41. const u32 soff = outp->or * 0x100;
  42. const u32 data = outp->or + 1;
  43. if (outp->info.sorconf.link & 1)
  44. nvkm_mask(device, 0x612308 + soff, 0x0000001f, 0x00000000 | data);
  45. if (outp->info.sorconf.link & 2)
  46. nvkm_mask(device, 0x612388 + soff, 0x0000001f, 0x00000010 | data);
  47. }
  48. static inline u32
  49. gm200_sor_dp_lane_map(struct nvkm_device *device, u8 lane)
  50. {
  51. return lane * 0x08;
  52. }
  53. static int
  54. gm200_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
  55. {
  56. struct nvkm_device *device = outp->base.disp->engine.subdev.device;
  57. const u32 soff = gm200_sor_soff(outp);
  58. const u32 loff = gm200_sor_loff(outp);
  59. u32 mask = 0, i;
  60. for (i = 0; i < nr; i++)
  61. mask |= 1 << (gm200_sor_dp_lane_map(device, i) >> 3);
  62. nvkm_mask(device, 0x61c130 + loff, 0x0000000f, mask);
  63. nvkm_mask(device, 0x61c034 + soff, 0x80000000, 0x80000000);
  64. nvkm_msec(device, 2000,
  65. if (!(nvkm_rd32(device, 0x61c034 + soff) & 0x80000000))
  66. break;
  67. );
  68. return 0;
  69. }
  70. static int
  71. gm200_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
  72. int ln, int vs, int pe, int pc)
  73. {
  74. struct nvkm_device *device = outp->base.disp->engine.subdev.device;
  75. struct nvkm_bios *bios = device->bios;
  76. const u32 shift = gm200_sor_dp_lane_map(device, ln);
  77. const u32 loff = gm200_sor_loff(outp);
  78. u32 addr, data[4];
  79. u8 ver, hdr, cnt, len;
  80. struct nvbios_dpout info;
  81. struct nvbios_dpcfg ocfg;
  82. addr = nvbios_dpout_match(bios, outp->base.info.hasht,
  83. outp->base.info.hashm,
  84. &ver, &hdr, &cnt, &len, &info);
  85. if (!addr)
  86. return -ENODEV;
  87. addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe,
  88. &ver, &hdr, &cnt, &len, &ocfg);
  89. if (!addr)
  90. return -EINVAL;
  91. ocfg.tx_pu &= 0x0f;
  92. data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift);
  93. data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift);
  94. data[2] = nvkm_rd32(device, 0x61c130 + loff);
  95. if ((data[2] & 0x00000f00) < (ocfg.tx_pu << 8) || ln == 0)
  96. data[2] = (data[2] & ~0x00000f00) | (ocfg.tx_pu << 8);
  97. nvkm_wr32(device, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
  98. nvkm_wr32(device, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
  99. nvkm_wr32(device, 0x61c130 + loff, data[2]);
  100. data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift);
  101. nvkm_wr32(device, 0x61c13c + loff, data[3] | (ocfg.pc << shift));
  102. return 0;
  103. }
  104. static const struct nvkm_output_dp_func
  105. gm200_sor_dp_func = {
  106. .pattern = gm107_sor_dp_pattern,
  107. .lnk_pwr = gm200_sor_dp_lnk_pwr,
  108. .lnk_ctl = gf119_sor_dp_lnk_ctl,
  109. .drv_ctl = gm200_sor_dp_drv_ctl,
  110. .vcpi = gf119_sor_dp_vcpi,
  111. };
  112. int
  113. gm200_sor_dp_new(struct nvkm_disp *disp, int index, struct dcb_output *dcbE,
  114. struct nvkm_output **poutp)
  115. {
  116. return nvkm_output_dp_new_(&gm200_sor_dp_func, disp, index, dcbE, poutp);
  117. }