nv17_fence.c 4.1 KB

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  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs <bskeggs@redhat.com>
  23. */
  24. #include <nvif/os.h>
  25. #include <nvif/class.h>
  26. #include <nvif/cl0002.h>
  27. #include "nouveau_drv.h"
  28. #include "nouveau_dma.h"
  29. #include "nv10_fence.h"
  30. int
  31. nv17_fence_sync(struct nouveau_fence *fence,
  32. struct nouveau_channel *prev, struct nouveau_channel *chan)
  33. {
  34. struct nouveau_cli *cli = (void *)prev->user.client;
  35. struct nv10_fence_priv *priv = chan->drm->fence;
  36. struct nv10_fence_chan *fctx = chan->fence;
  37. u32 value;
  38. int ret;
  39. if (!mutex_trylock(&cli->mutex))
  40. return -EBUSY;
  41. spin_lock(&priv->lock);
  42. value = priv->sequence;
  43. priv->sequence += 2;
  44. spin_unlock(&priv->lock);
  45. ret = RING_SPACE(prev, 5);
  46. if (!ret) {
  47. BEGIN_NV04(prev, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
  48. OUT_RING (prev, fctx->sema.handle);
  49. OUT_RING (prev, 0);
  50. OUT_RING (prev, value + 0);
  51. OUT_RING (prev, value + 1);
  52. FIRE_RING (prev);
  53. }
  54. if (!ret && !(ret = RING_SPACE(chan, 5))) {
  55. BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
  56. OUT_RING (chan, fctx->sema.handle);
  57. OUT_RING (chan, 0);
  58. OUT_RING (chan, value + 1);
  59. OUT_RING (chan, value + 2);
  60. FIRE_RING (chan);
  61. }
  62. mutex_unlock(&cli->mutex);
  63. return 0;
  64. }
  65. static int
  66. nv17_fence_context_new(struct nouveau_channel *chan)
  67. {
  68. struct nv10_fence_priv *priv = chan->drm->fence;
  69. struct nv10_fence_chan *fctx;
  70. struct ttm_mem_reg *mem = &priv->bo->bo.mem;
  71. u32 start = mem->start * PAGE_SIZE;
  72. u32 limit = start + mem->size - 1;
  73. int ret = 0;
  74. fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
  75. if (!fctx)
  76. return -ENOMEM;
  77. nouveau_fence_context_new(chan, &fctx->base);
  78. fctx->base.emit = nv10_fence_emit;
  79. fctx->base.read = nv10_fence_read;
  80. fctx->base.sync = nv17_fence_sync;
  81. ret = nvif_object_init(&chan->user, NvSema, NV_DMA_FROM_MEMORY,
  82. &(struct nv_dma_v0) {
  83. .target = NV_DMA_V0_TARGET_VRAM,
  84. .access = NV_DMA_V0_ACCESS_RDWR,
  85. .start = start,
  86. .limit = limit,
  87. }, sizeof(struct nv_dma_v0),
  88. &fctx->sema);
  89. if (ret)
  90. nv10_fence_context_del(chan);
  91. return ret;
  92. }
  93. void
  94. nv17_fence_resume(struct nouveau_drm *drm)
  95. {
  96. struct nv10_fence_priv *priv = drm->fence;
  97. nouveau_bo_wr32(priv->bo, 0, priv->sequence);
  98. }
  99. int
  100. nv17_fence_create(struct nouveau_drm *drm)
  101. {
  102. struct nv10_fence_priv *priv;
  103. int ret = 0;
  104. priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
  105. if (!priv)
  106. return -ENOMEM;
  107. priv->base.dtor = nv10_fence_destroy;
  108. priv->base.resume = nv17_fence_resume;
  109. priv->base.context_new = nv17_fence_context_new;
  110. priv->base.context_del = nv10_fence_context_del;
  111. priv->base.contexts = 31;
  112. priv->base.context_base = dma_fence_context_alloc(priv->base.contexts);
  113. spin_lock_init(&priv->lock);
  114. ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
  115. 0, 0x0000, NULL, NULL, &priv->bo);
  116. if (!ret) {
  117. ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM, false);
  118. if (!ret) {
  119. ret = nouveau_bo_map(priv->bo);
  120. if (ret)
  121. nouveau_bo_unpin(priv->bo);
  122. }
  123. if (ret)
  124. nouveau_bo_ref(NULL, &priv->bo);
  125. }
  126. if (ret) {
  127. nv10_fence_destroy(drm);
  128. return ret;
  129. }
  130. nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
  131. return ret;
  132. }