nouveau_drm.c 29 KB

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  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include <linux/console.h>
  25. #include <linux/delay.h>
  26. #include <linux/module.h>
  27. #include <linux/pci.h>
  28. #include <linux/pm_runtime.h>
  29. #include <linux/vga_switcheroo.h>
  30. #include "drmP.h"
  31. #include "drm_crtc_helper.h"
  32. #include <core/gpuobj.h>
  33. #include <core/option.h>
  34. #include <core/pci.h>
  35. #include <core/tegra.h>
  36. #include <nvif/class.h>
  37. #include <nvif/cl0002.h>
  38. #include <nvif/cla06f.h>
  39. #include <nvif/if0004.h>
  40. #include "nouveau_drv.h"
  41. #include "nouveau_dma.h"
  42. #include "nouveau_ttm.h"
  43. #include "nouveau_gem.h"
  44. #include "nouveau_vga.h"
  45. #include "nouveau_led.h"
  46. #include "nouveau_hwmon.h"
  47. #include "nouveau_acpi.h"
  48. #include "nouveau_bios.h"
  49. #include "nouveau_ioctl.h"
  50. #include "nouveau_abi16.h"
  51. #include "nouveau_fbcon.h"
  52. #include "nouveau_fence.h"
  53. #include "nouveau_debugfs.h"
  54. #include "nouveau_usif.h"
  55. #include "nouveau_connector.h"
  56. #include "nouveau_platform.h"
  57. MODULE_PARM_DESC(config, "option string to pass to driver core");
  58. static char *nouveau_config;
  59. module_param_named(config, nouveau_config, charp, 0400);
  60. MODULE_PARM_DESC(debug, "debug string to pass to driver core");
  61. static char *nouveau_debug;
  62. module_param_named(debug, nouveau_debug, charp, 0400);
  63. MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
  64. static int nouveau_noaccel = 0;
  65. module_param_named(noaccel, nouveau_noaccel, int, 0400);
  66. MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
  67. "0 = disabled, 1 = enabled, 2 = headless)");
  68. int nouveau_modeset = -1;
  69. module_param_named(modeset, nouveau_modeset, int, 0400);
  70. MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
  71. int nouveau_runtime_pm = -1;
  72. module_param_named(runpm, nouveau_runtime_pm, int, 0400);
  73. static struct drm_driver driver_stub;
  74. static struct drm_driver driver_pci;
  75. static struct drm_driver driver_platform;
  76. static u64
  77. nouveau_pci_name(struct pci_dev *pdev)
  78. {
  79. u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
  80. name |= pdev->bus->number << 16;
  81. name |= PCI_SLOT(pdev->devfn) << 8;
  82. return name | PCI_FUNC(pdev->devfn);
  83. }
  84. static u64
  85. nouveau_platform_name(struct platform_device *platformdev)
  86. {
  87. return platformdev->id;
  88. }
  89. static u64
  90. nouveau_name(struct drm_device *dev)
  91. {
  92. if (dev->pdev)
  93. return nouveau_pci_name(dev->pdev);
  94. else
  95. return nouveau_platform_name(dev->platformdev);
  96. }
  97. static int
  98. nouveau_cli_create(struct drm_device *dev, const char *sname,
  99. int size, void **pcli)
  100. {
  101. struct nouveau_cli *cli = *pcli = kzalloc(size, GFP_KERNEL);
  102. int ret;
  103. if (cli) {
  104. snprintf(cli->name, sizeof(cli->name), "%s", sname);
  105. cli->dev = dev;
  106. ret = nvif_client_init(NULL, cli->name, nouveau_name(dev),
  107. nouveau_config, nouveau_debug,
  108. &cli->base);
  109. if (ret == 0) {
  110. mutex_init(&cli->mutex);
  111. usif_client_init(cli);
  112. }
  113. return ret;
  114. }
  115. return -ENOMEM;
  116. }
  117. static void
  118. nouveau_cli_destroy(struct nouveau_cli *cli)
  119. {
  120. nvkm_vm_ref(NULL, &nvxx_client(&cli->base)->vm, NULL);
  121. nvif_client_fini(&cli->base);
  122. usif_client_fini(cli);
  123. kfree(cli);
  124. }
  125. static void
  126. nouveau_accel_fini(struct nouveau_drm *drm)
  127. {
  128. nouveau_channel_idle(drm->channel);
  129. nvif_object_fini(&drm->ntfy);
  130. nvkm_gpuobj_del(&drm->notify);
  131. nvif_notify_fini(&drm->flip);
  132. nvif_object_fini(&drm->nvsw);
  133. nouveau_channel_del(&drm->channel);
  134. nouveau_channel_idle(drm->cechan);
  135. nvif_object_fini(&drm->ttm.copy);
  136. nouveau_channel_del(&drm->cechan);
  137. if (drm->fence)
  138. nouveau_fence(drm)->dtor(drm);
  139. }
  140. static void
  141. nouveau_accel_init(struct nouveau_drm *drm)
  142. {
  143. struct nvif_device *device = &drm->device;
  144. struct nvif_sclass *sclass;
  145. u32 arg0, arg1;
  146. int ret, i, n;
  147. if (nouveau_noaccel)
  148. return;
  149. /* initialise synchronisation routines */
  150. /*XXX: this is crap, but the fence/channel stuff is a little
  151. * backwards in some places. this will be fixed.
  152. */
  153. ret = n = nvif_object_sclass_get(&device->object, &sclass);
  154. if (ret < 0)
  155. return;
  156. for (ret = -ENOSYS, i = 0; i < n; i++) {
  157. switch (sclass[i].oclass) {
  158. case NV03_CHANNEL_DMA:
  159. ret = nv04_fence_create(drm);
  160. break;
  161. case NV10_CHANNEL_DMA:
  162. ret = nv10_fence_create(drm);
  163. break;
  164. case NV17_CHANNEL_DMA:
  165. case NV40_CHANNEL_DMA:
  166. ret = nv17_fence_create(drm);
  167. break;
  168. case NV50_CHANNEL_GPFIFO:
  169. ret = nv50_fence_create(drm);
  170. break;
  171. case G82_CHANNEL_GPFIFO:
  172. ret = nv84_fence_create(drm);
  173. break;
  174. case FERMI_CHANNEL_GPFIFO:
  175. case KEPLER_CHANNEL_GPFIFO_A:
  176. case KEPLER_CHANNEL_GPFIFO_B:
  177. case MAXWELL_CHANNEL_GPFIFO_A:
  178. case PASCAL_CHANNEL_GPFIFO_A:
  179. ret = nvc0_fence_create(drm);
  180. break;
  181. default:
  182. break;
  183. }
  184. }
  185. nvif_object_sclass_put(&sclass);
  186. if (ret) {
  187. NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
  188. nouveau_accel_fini(drm);
  189. return;
  190. }
  191. if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
  192. ret = nouveau_channel_new(drm, &drm->device,
  193. NVA06F_V0_ENGINE_CE0 |
  194. NVA06F_V0_ENGINE_CE1,
  195. 0, &drm->cechan);
  196. if (ret)
  197. NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
  198. arg0 = NVA06F_V0_ENGINE_GR;
  199. arg1 = 1;
  200. } else
  201. if (device->info.chipset >= 0xa3 &&
  202. device->info.chipset != 0xaa &&
  203. device->info.chipset != 0xac) {
  204. ret = nouveau_channel_new(drm, &drm->device,
  205. NvDmaFB, NvDmaTT, &drm->cechan);
  206. if (ret)
  207. NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
  208. arg0 = NvDmaFB;
  209. arg1 = NvDmaTT;
  210. } else {
  211. arg0 = NvDmaFB;
  212. arg1 = NvDmaTT;
  213. }
  214. ret = nouveau_channel_new(drm, &drm->device, arg0, arg1, &drm->channel);
  215. if (ret) {
  216. NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
  217. nouveau_accel_fini(drm);
  218. return;
  219. }
  220. ret = nvif_object_init(&drm->channel->user, NVDRM_NVSW,
  221. nouveau_abi16_swclass(drm), NULL, 0, &drm->nvsw);
  222. if (ret == 0) {
  223. ret = RING_SPACE(drm->channel, 2);
  224. if (ret == 0) {
  225. if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
  226. BEGIN_NV04(drm->channel, NvSubSw, 0, 1);
  227. OUT_RING (drm->channel, NVDRM_NVSW);
  228. } else
  229. if (device->info.family < NV_DEVICE_INFO_V0_KEPLER) {
  230. BEGIN_NVC0(drm->channel, FermiSw, 0, 1);
  231. OUT_RING (drm->channel, 0x001f0000);
  232. }
  233. }
  234. ret = nvif_notify_init(&drm->nvsw, nouveau_flip_complete,
  235. false, NV04_NVSW_NTFY_UEVENT,
  236. NULL, 0, 0, &drm->flip);
  237. if (ret == 0)
  238. ret = nvif_notify_get(&drm->flip);
  239. if (ret) {
  240. nouveau_accel_fini(drm);
  241. return;
  242. }
  243. }
  244. if (ret) {
  245. NV_ERROR(drm, "failed to allocate software object, %d\n", ret);
  246. nouveau_accel_fini(drm);
  247. return;
  248. }
  249. if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
  250. ret = nvkm_gpuobj_new(nvxx_device(&drm->device), 32, 0, false,
  251. NULL, &drm->notify);
  252. if (ret) {
  253. NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
  254. nouveau_accel_fini(drm);
  255. return;
  256. }
  257. ret = nvif_object_init(&drm->channel->user, NvNotify0,
  258. NV_DMA_IN_MEMORY,
  259. &(struct nv_dma_v0) {
  260. .target = NV_DMA_V0_TARGET_VRAM,
  261. .access = NV_DMA_V0_ACCESS_RDWR,
  262. .start = drm->notify->addr,
  263. .limit = drm->notify->addr + 31
  264. }, sizeof(struct nv_dma_v0),
  265. &drm->ntfy);
  266. if (ret) {
  267. nouveau_accel_fini(drm);
  268. return;
  269. }
  270. }
  271. nouveau_bo_move_init(drm);
  272. }
  273. static int nouveau_drm_probe(struct pci_dev *pdev,
  274. const struct pci_device_id *pent)
  275. {
  276. struct nvkm_device *device;
  277. struct apertures_struct *aper;
  278. bool boot = false;
  279. int ret;
  280. if (vga_switcheroo_client_probe_defer(pdev))
  281. return -EPROBE_DEFER;
  282. /* We need to check that the chipset is supported before booting
  283. * fbdev off the hardware, as there's no way to put it back.
  284. */
  285. ret = nvkm_device_pci_new(pdev, NULL, "error", true, false, 0, &device);
  286. if (ret)
  287. return ret;
  288. nvkm_device_del(&device);
  289. /* Remove conflicting drivers (vesafb, efifb etc). */
  290. aper = alloc_apertures(3);
  291. if (!aper)
  292. return -ENOMEM;
  293. aper->ranges[0].base = pci_resource_start(pdev, 1);
  294. aper->ranges[0].size = pci_resource_len(pdev, 1);
  295. aper->count = 1;
  296. if (pci_resource_len(pdev, 2)) {
  297. aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
  298. aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
  299. aper->count++;
  300. }
  301. if (pci_resource_len(pdev, 3)) {
  302. aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
  303. aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
  304. aper->count++;
  305. }
  306. #ifdef CONFIG_X86
  307. boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
  308. #endif
  309. if (nouveau_modeset != 2)
  310. drm_fb_helper_remove_conflicting_framebuffers(aper, "nouveaufb", boot);
  311. kfree(aper);
  312. ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug,
  313. true, true, ~0ULL, &device);
  314. if (ret)
  315. return ret;
  316. pci_set_master(pdev);
  317. ret = drm_get_pci_dev(pdev, pent, &driver_pci);
  318. if (ret) {
  319. nvkm_device_del(&device);
  320. return ret;
  321. }
  322. return 0;
  323. }
  324. #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
  325. static void
  326. nouveau_get_hdmi_dev(struct nouveau_drm *drm)
  327. {
  328. struct pci_dev *pdev = drm->dev->pdev;
  329. if (!pdev) {
  330. NV_DEBUG(drm, "not a PCI device; no HDMI\n");
  331. drm->hdmi_device = NULL;
  332. return;
  333. }
  334. /* subfunction one is a hdmi audio device? */
  335. drm->hdmi_device = pci_get_bus_and_slot((unsigned int)pdev->bus->number,
  336. PCI_DEVFN(PCI_SLOT(pdev->devfn), 1));
  337. if (!drm->hdmi_device) {
  338. NV_DEBUG(drm, "hdmi device not found %d %d %d\n", pdev->bus->number, PCI_SLOT(pdev->devfn), 1);
  339. return;
  340. }
  341. if ((drm->hdmi_device->class >> 8) != PCI_CLASS_MULTIMEDIA_HD_AUDIO) {
  342. NV_DEBUG(drm, "possible hdmi device not audio %d\n", drm->hdmi_device->class);
  343. pci_dev_put(drm->hdmi_device);
  344. drm->hdmi_device = NULL;
  345. return;
  346. }
  347. }
  348. static int
  349. nouveau_drm_load(struct drm_device *dev, unsigned long flags)
  350. {
  351. struct nouveau_drm *drm;
  352. int ret;
  353. ret = nouveau_cli_create(dev, "DRM", sizeof(*drm), (void **)&drm);
  354. if (ret)
  355. return ret;
  356. dev->dev_private = drm;
  357. drm->dev = dev;
  358. nvxx_client(&drm->client.base)->debug =
  359. nvkm_dbgopt(nouveau_debug, "DRM");
  360. INIT_LIST_HEAD(&drm->clients);
  361. spin_lock_init(&drm->tile.lock);
  362. nouveau_get_hdmi_dev(drm);
  363. ret = nvif_device_init(&drm->client.base.object, 0, NV_DEVICE,
  364. &(struct nv_device_v0) {
  365. .device = ~0,
  366. }, sizeof(struct nv_device_v0),
  367. &drm->device);
  368. if (ret)
  369. goto fail_device;
  370. dev->irq_enabled = true;
  371. /* workaround an odd issue on nvc1 by disabling the device's
  372. * nosnoop capability. hopefully won't cause issues until a
  373. * better fix is found - assuming there is one...
  374. */
  375. if (drm->device.info.chipset == 0xc1)
  376. nvif_mask(&drm->device.object, 0x00088080, 0x00000800, 0x00000000);
  377. nouveau_vga_init(drm);
  378. if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
  379. if (!nvxx_device(&drm->device)->mmu) {
  380. ret = -ENOSYS;
  381. goto fail_device;
  382. }
  383. ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40),
  384. 0x1000, NULL, &drm->client.vm);
  385. if (ret)
  386. goto fail_device;
  387. nvxx_client(&drm->client.base)->vm = drm->client.vm;
  388. }
  389. ret = nouveau_ttm_init(drm);
  390. if (ret)
  391. goto fail_ttm;
  392. ret = nouveau_bios_init(dev);
  393. if (ret)
  394. goto fail_bios;
  395. ret = nouveau_display_create(dev);
  396. if (ret)
  397. goto fail_dispctor;
  398. if (dev->mode_config.num_crtc) {
  399. ret = nouveau_display_init(dev);
  400. if (ret)
  401. goto fail_dispinit;
  402. }
  403. nouveau_debugfs_init(drm);
  404. nouveau_hwmon_init(dev);
  405. nouveau_accel_init(drm);
  406. nouveau_fbcon_init(dev);
  407. nouveau_led_init(dev);
  408. if (nouveau_runtime_pm != 0) {
  409. pm_runtime_use_autosuspend(dev->dev);
  410. pm_runtime_set_autosuspend_delay(dev->dev, 5000);
  411. pm_runtime_set_active(dev->dev);
  412. pm_runtime_allow(dev->dev);
  413. pm_runtime_mark_last_busy(dev->dev);
  414. pm_runtime_put(dev->dev);
  415. }
  416. return 0;
  417. fail_dispinit:
  418. nouveau_display_destroy(dev);
  419. fail_dispctor:
  420. nouveau_bios_takedown(dev);
  421. fail_bios:
  422. nouveau_ttm_fini(drm);
  423. fail_ttm:
  424. nouveau_vga_fini(drm);
  425. fail_device:
  426. nvif_device_fini(&drm->device);
  427. nouveau_cli_destroy(&drm->client);
  428. return ret;
  429. }
  430. static void
  431. nouveau_drm_unload(struct drm_device *dev)
  432. {
  433. struct nouveau_drm *drm = nouveau_drm(dev);
  434. if (nouveau_runtime_pm != 0) {
  435. pm_runtime_get_sync(dev->dev);
  436. pm_runtime_forbid(dev->dev);
  437. }
  438. nouveau_led_fini(dev);
  439. nouveau_fbcon_fini(dev);
  440. nouveau_accel_fini(drm);
  441. nouveau_hwmon_fini(dev);
  442. nouveau_debugfs_fini(drm);
  443. if (dev->mode_config.num_crtc)
  444. nouveau_display_fini(dev, false);
  445. nouveau_display_destroy(dev);
  446. nouveau_bios_takedown(dev);
  447. nouveau_ttm_fini(drm);
  448. nouveau_vga_fini(drm);
  449. nvif_device_fini(&drm->device);
  450. if (drm->hdmi_device)
  451. pci_dev_put(drm->hdmi_device);
  452. nouveau_cli_destroy(&drm->client);
  453. }
  454. void
  455. nouveau_drm_device_remove(struct drm_device *dev)
  456. {
  457. struct nouveau_drm *drm = nouveau_drm(dev);
  458. struct nvkm_client *client;
  459. struct nvkm_device *device;
  460. dev->irq_enabled = false;
  461. client = nvxx_client(&drm->client.base);
  462. device = nvkm_device_find(client->device);
  463. drm_put_dev(dev);
  464. nvkm_device_del(&device);
  465. }
  466. static void
  467. nouveau_drm_remove(struct pci_dev *pdev)
  468. {
  469. struct drm_device *dev = pci_get_drvdata(pdev);
  470. nouveau_drm_device_remove(dev);
  471. }
  472. static int
  473. nouveau_do_suspend(struct drm_device *dev, bool runtime)
  474. {
  475. struct nouveau_drm *drm = nouveau_drm(dev);
  476. struct nouveau_cli *cli;
  477. int ret;
  478. nouveau_led_suspend(dev);
  479. if (dev->mode_config.num_crtc) {
  480. NV_INFO(drm, "suspending console...\n");
  481. nouveau_fbcon_set_suspend(dev, 1);
  482. NV_INFO(drm, "suspending display...\n");
  483. ret = nouveau_display_suspend(dev, runtime);
  484. if (ret)
  485. return ret;
  486. }
  487. NV_INFO(drm, "evicting buffers...\n");
  488. ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM);
  489. NV_INFO(drm, "waiting for kernel channels to go idle...\n");
  490. if (drm->cechan) {
  491. ret = nouveau_channel_idle(drm->cechan);
  492. if (ret)
  493. goto fail_display;
  494. }
  495. if (drm->channel) {
  496. ret = nouveau_channel_idle(drm->channel);
  497. if (ret)
  498. goto fail_display;
  499. }
  500. NV_INFO(drm, "suspending client object trees...\n");
  501. if (drm->fence && nouveau_fence(drm)->suspend) {
  502. if (!nouveau_fence(drm)->suspend(drm)) {
  503. ret = -ENOMEM;
  504. goto fail_display;
  505. }
  506. }
  507. list_for_each_entry(cli, &drm->clients, head) {
  508. ret = nvif_client_suspend(&cli->base);
  509. if (ret)
  510. goto fail_client;
  511. }
  512. NV_INFO(drm, "suspending kernel object tree...\n");
  513. ret = nvif_client_suspend(&drm->client.base);
  514. if (ret)
  515. goto fail_client;
  516. return 0;
  517. fail_client:
  518. list_for_each_entry_continue_reverse(cli, &drm->clients, head) {
  519. nvif_client_resume(&cli->base);
  520. }
  521. if (drm->fence && nouveau_fence(drm)->resume)
  522. nouveau_fence(drm)->resume(drm);
  523. fail_display:
  524. if (dev->mode_config.num_crtc) {
  525. NV_INFO(drm, "resuming display...\n");
  526. nouveau_display_resume(dev, runtime);
  527. }
  528. return ret;
  529. }
  530. static int
  531. nouveau_do_resume(struct drm_device *dev, bool runtime)
  532. {
  533. struct nouveau_drm *drm = nouveau_drm(dev);
  534. struct nouveau_cli *cli;
  535. NV_INFO(drm, "resuming kernel object tree...\n");
  536. nvif_client_resume(&drm->client.base);
  537. NV_INFO(drm, "resuming client object trees...\n");
  538. if (drm->fence && nouveau_fence(drm)->resume)
  539. nouveau_fence(drm)->resume(drm);
  540. list_for_each_entry(cli, &drm->clients, head) {
  541. nvif_client_resume(&cli->base);
  542. }
  543. nouveau_run_vbios_init(dev);
  544. if (dev->mode_config.num_crtc) {
  545. NV_INFO(drm, "resuming display...\n");
  546. nouveau_display_resume(dev, runtime);
  547. NV_INFO(drm, "resuming console...\n");
  548. nouveau_fbcon_set_suspend(dev, 0);
  549. }
  550. nouveau_led_resume(dev);
  551. return 0;
  552. }
  553. int
  554. nouveau_pmops_suspend(struct device *dev)
  555. {
  556. struct pci_dev *pdev = to_pci_dev(dev);
  557. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  558. int ret;
  559. if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
  560. drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
  561. return 0;
  562. ret = nouveau_do_suspend(drm_dev, false);
  563. if (ret)
  564. return ret;
  565. pci_save_state(pdev);
  566. pci_disable_device(pdev);
  567. pci_set_power_state(pdev, PCI_D3hot);
  568. udelay(200);
  569. return 0;
  570. }
  571. int
  572. nouveau_pmops_resume(struct device *dev)
  573. {
  574. struct pci_dev *pdev = to_pci_dev(dev);
  575. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  576. int ret;
  577. if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
  578. drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
  579. return 0;
  580. pci_set_power_state(pdev, PCI_D0);
  581. pci_restore_state(pdev);
  582. ret = pci_enable_device(pdev);
  583. if (ret)
  584. return ret;
  585. pci_set_master(pdev);
  586. ret = nouveau_do_resume(drm_dev, false);
  587. /* Monitors may have been connected / disconnected during suspend */
  588. schedule_work(&nouveau_drm(drm_dev)->hpd_work);
  589. return ret;
  590. }
  591. static int
  592. nouveau_pmops_freeze(struct device *dev)
  593. {
  594. struct pci_dev *pdev = to_pci_dev(dev);
  595. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  596. return nouveau_do_suspend(drm_dev, false);
  597. }
  598. static int
  599. nouveau_pmops_thaw(struct device *dev)
  600. {
  601. struct pci_dev *pdev = to_pci_dev(dev);
  602. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  603. return nouveau_do_resume(drm_dev, false);
  604. }
  605. static int
  606. nouveau_pmops_runtime_suspend(struct device *dev)
  607. {
  608. struct pci_dev *pdev = to_pci_dev(dev);
  609. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  610. int ret;
  611. if (nouveau_runtime_pm == 0) {
  612. pm_runtime_forbid(dev);
  613. return -EBUSY;
  614. }
  615. /* are we optimus enabled? */
  616. if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) {
  617. DRM_DEBUG_DRIVER("failing to power off - not optimus\n");
  618. pm_runtime_forbid(dev);
  619. return -EBUSY;
  620. }
  621. drm_kms_helper_poll_disable(drm_dev);
  622. vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
  623. nouveau_switcheroo_optimus_dsm();
  624. ret = nouveau_do_suspend(drm_dev, true);
  625. pci_save_state(pdev);
  626. pci_disable_device(pdev);
  627. pci_ignore_hotplug(pdev);
  628. pci_set_power_state(pdev, PCI_D3cold);
  629. drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
  630. return ret;
  631. }
  632. static int
  633. nouveau_pmops_runtime_resume(struct device *dev)
  634. {
  635. struct pci_dev *pdev = to_pci_dev(dev);
  636. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  637. struct nvif_device *device = &nouveau_drm(drm_dev)->device;
  638. int ret;
  639. if (nouveau_runtime_pm == 0)
  640. return -EINVAL;
  641. pci_set_power_state(pdev, PCI_D0);
  642. pci_restore_state(pdev);
  643. ret = pci_enable_device(pdev);
  644. if (ret)
  645. return ret;
  646. pci_set_master(pdev);
  647. ret = nouveau_do_resume(drm_dev, true);
  648. drm_kms_helper_poll_enable(drm_dev);
  649. /* do magic */
  650. nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
  651. vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
  652. drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
  653. /* Monitors may have been connected / disconnected during suspend */
  654. schedule_work(&nouveau_drm(drm_dev)->hpd_work);
  655. return ret;
  656. }
  657. static int
  658. nouveau_pmops_runtime_idle(struct device *dev)
  659. {
  660. struct pci_dev *pdev = to_pci_dev(dev);
  661. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  662. struct nouveau_drm *drm = nouveau_drm(drm_dev);
  663. struct drm_crtc *crtc;
  664. if (nouveau_runtime_pm == 0) {
  665. pm_runtime_forbid(dev);
  666. return -EBUSY;
  667. }
  668. /* are we optimus enabled? */
  669. if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) {
  670. DRM_DEBUG_DRIVER("failing to power off - not optimus\n");
  671. pm_runtime_forbid(dev);
  672. return -EBUSY;
  673. }
  674. /* if we have a hdmi audio device - make sure it has a driver loaded */
  675. if (drm->hdmi_device) {
  676. if (!drm->hdmi_device->driver) {
  677. DRM_DEBUG_DRIVER("failing to power off - no HDMI audio driver loaded\n");
  678. pm_runtime_mark_last_busy(dev);
  679. return -EBUSY;
  680. }
  681. }
  682. list_for_each_entry(crtc, &drm->dev->mode_config.crtc_list, head) {
  683. if (crtc->enabled) {
  684. DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
  685. return -EBUSY;
  686. }
  687. }
  688. pm_runtime_mark_last_busy(dev);
  689. pm_runtime_autosuspend(dev);
  690. /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
  691. return 1;
  692. }
  693. static int
  694. nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
  695. {
  696. struct nouveau_drm *drm = nouveau_drm(dev);
  697. struct nouveau_cli *cli;
  698. char name[32], tmpname[TASK_COMM_LEN];
  699. int ret;
  700. /* need to bring up power immediately if opening device */
  701. ret = pm_runtime_get_sync(dev->dev);
  702. if (ret < 0 && ret != -EACCES)
  703. return ret;
  704. get_task_comm(tmpname, current);
  705. snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
  706. ret = nouveau_cli_create(dev, name, sizeof(*cli), (void **)&cli);
  707. if (ret)
  708. goto out_suspend;
  709. cli->base.super = false;
  710. if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
  711. ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40),
  712. 0x1000, NULL, &cli->vm);
  713. if (ret) {
  714. nouveau_cli_destroy(cli);
  715. goto out_suspend;
  716. }
  717. nvxx_client(&cli->base)->vm = cli->vm;
  718. }
  719. fpriv->driver_priv = cli;
  720. mutex_lock(&drm->client.mutex);
  721. list_add(&cli->head, &drm->clients);
  722. mutex_unlock(&drm->client.mutex);
  723. out_suspend:
  724. pm_runtime_mark_last_busy(dev->dev);
  725. pm_runtime_put_autosuspend(dev->dev);
  726. return ret;
  727. }
  728. static void
  729. nouveau_drm_preclose(struct drm_device *dev, struct drm_file *fpriv)
  730. {
  731. struct nouveau_cli *cli = nouveau_cli(fpriv);
  732. struct nouveau_drm *drm = nouveau_drm(dev);
  733. pm_runtime_get_sync(dev->dev);
  734. mutex_lock(&cli->mutex);
  735. if (cli->abi16)
  736. nouveau_abi16_fini(cli->abi16);
  737. mutex_unlock(&cli->mutex);
  738. mutex_lock(&drm->client.mutex);
  739. list_del(&cli->head);
  740. mutex_unlock(&drm->client.mutex);
  741. }
  742. static void
  743. nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
  744. {
  745. struct nouveau_cli *cli = nouveau_cli(fpriv);
  746. nouveau_cli_destroy(cli);
  747. pm_runtime_mark_last_busy(dev->dev);
  748. pm_runtime_put_autosuspend(dev->dev);
  749. }
  750. static const struct drm_ioctl_desc
  751. nouveau_ioctls[] = {
  752. DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
  753. DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  754. DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
  755. DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_AUTH|DRM_RENDER_ALLOW),
  756. DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
  757. DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
  758. DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_AUTH|DRM_RENDER_ALLOW),
  759. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH|DRM_RENDER_ALLOW),
  760. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH|DRM_RENDER_ALLOW),
  761. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
  762. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
  763. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH|DRM_RENDER_ALLOW),
  764. };
  765. long
  766. nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  767. {
  768. struct drm_file *filp = file->private_data;
  769. struct drm_device *dev = filp->minor->dev;
  770. long ret;
  771. ret = pm_runtime_get_sync(dev->dev);
  772. if (ret < 0 && ret != -EACCES)
  773. return ret;
  774. switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
  775. case DRM_NOUVEAU_NVIF:
  776. ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
  777. break;
  778. default:
  779. ret = drm_ioctl(file, cmd, arg);
  780. break;
  781. }
  782. pm_runtime_mark_last_busy(dev->dev);
  783. pm_runtime_put_autosuspend(dev->dev);
  784. return ret;
  785. }
  786. static const struct file_operations
  787. nouveau_driver_fops = {
  788. .owner = THIS_MODULE,
  789. .open = drm_open,
  790. .release = drm_release,
  791. .unlocked_ioctl = nouveau_drm_ioctl,
  792. .mmap = nouveau_ttm_mmap,
  793. .poll = drm_poll,
  794. .read = drm_read,
  795. #if defined(CONFIG_COMPAT)
  796. .compat_ioctl = nouveau_compat_ioctl,
  797. #endif
  798. .llseek = noop_llseek,
  799. };
  800. static struct drm_driver
  801. driver_stub = {
  802. .driver_features =
  803. DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER |
  804. DRIVER_KMS_LEGACY_CONTEXT,
  805. .load = nouveau_drm_load,
  806. .unload = nouveau_drm_unload,
  807. .open = nouveau_drm_open,
  808. .preclose = nouveau_drm_preclose,
  809. .postclose = nouveau_drm_postclose,
  810. .lastclose = nouveau_vga_lastclose,
  811. #if defined(CONFIG_DEBUG_FS)
  812. .debugfs_init = nouveau_drm_debugfs_init,
  813. .debugfs_cleanup = nouveau_drm_debugfs_cleanup,
  814. #endif
  815. .get_vblank_counter = drm_vblank_no_hw_counter,
  816. .enable_vblank = nouveau_display_vblank_enable,
  817. .disable_vblank = nouveau_display_vblank_disable,
  818. .get_scanout_position = nouveau_display_scanoutpos,
  819. .get_vblank_timestamp = nouveau_display_vblstamp,
  820. .ioctls = nouveau_ioctls,
  821. .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
  822. .fops = &nouveau_driver_fops,
  823. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  824. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  825. .gem_prime_export = drm_gem_prime_export,
  826. .gem_prime_import = drm_gem_prime_import,
  827. .gem_prime_pin = nouveau_gem_prime_pin,
  828. .gem_prime_res_obj = nouveau_gem_prime_res_obj,
  829. .gem_prime_unpin = nouveau_gem_prime_unpin,
  830. .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
  831. .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
  832. .gem_prime_vmap = nouveau_gem_prime_vmap,
  833. .gem_prime_vunmap = nouveau_gem_prime_vunmap,
  834. .gem_free_object_unlocked = nouveau_gem_object_del,
  835. .gem_open_object = nouveau_gem_object_open,
  836. .gem_close_object = nouveau_gem_object_close,
  837. .dumb_create = nouveau_display_dumb_create,
  838. .dumb_map_offset = nouveau_display_dumb_map_offset,
  839. .dumb_destroy = drm_gem_dumb_destroy,
  840. .name = DRIVER_NAME,
  841. .desc = DRIVER_DESC,
  842. #ifdef GIT_REVISION
  843. .date = GIT_REVISION,
  844. #else
  845. .date = DRIVER_DATE,
  846. #endif
  847. .major = DRIVER_MAJOR,
  848. .minor = DRIVER_MINOR,
  849. .patchlevel = DRIVER_PATCHLEVEL,
  850. };
  851. static struct pci_device_id
  852. nouveau_drm_pci_table[] = {
  853. {
  854. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
  855. .class = PCI_BASE_CLASS_DISPLAY << 16,
  856. .class_mask = 0xff << 16,
  857. },
  858. {
  859. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
  860. .class = PCI_BASE_CLASS_DISPLAY << 16,
  861. .class_mask = 0xff << 16,
  862. },
  863. {}
  864. };
  865. static void nouveau_display_options(void)
  866. {
  867. DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
  868. DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
  869. DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
  870. DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
  871. DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel);
  872. DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
  873. DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
  874. DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
  875. DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
  876. DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
  877. DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
  878. DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz);
  879. }
  880. static const struct dev_pm_ops nouveau_pm_ops = {
  881. .suspend = nouveau_pmops_suspend,
  882. .resume = nouveau_pmops_resume,
  883. .freeze = nouveau_pmops_freeze,
  884. .thaw = nouveau_pmops_thaw,
  885. .poweroff = nouveau_pmops_freeze,
  886. .restore = nouveau_pmops_resume,
  887. .runtime_suspend = nouveau_pmops_runtime_suspend,
  888. .runtime_resume = nouveau_pmops_runtime_resume,
  889. .runtime_idle = nouveau_pmops_runtime_idle,
  890. };
  891. static struct pci_driver
  892. nouveau_drm_pci_driver = {
  893. .name = "nouveau",
  894. .id_table = nouveau_drm_pci_table,
  895. .probe = nouveau_drm_probe,
  896. .remove = nouveau_drm_remove,
  897. .driver.pm = &nouveau_pm_ops,
  898. };
  899. struct drm_device *
  900. nouveau_platform_device_create(const struct nvkm_device_tegra_func *func,
  901. struct platform_device *pdev,
  902. struct nvkm_device **pdevice)
  903. {
  904. struct drm_device *drm;
  905. int err;
  906. err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug,
  907. true, true, ~0ULL, pdevice);
  908. if (err)
  909. goto err_free;
  910. drm = drm_dev_alloc(&driver_platform, &pdev->dev);
  911. if (IS_ERR(drm)) {
  912. err = PTR_ERR(drm);
  913. goto err_free;
  914. }
  915. drm->platformdev = pdev;
  916. platform_set_drvdata(pdev, drm);
  917. return drm;
  918. err_free:
  919. nvkm_device_del(pdevice);
  920. return ERR_PTR(err);
  921. }
  922. static int __init
  923. nouveau_drm_init(void)
  924. {
  925. driver_pci = driver_stub;
  926. driver_pci.set_busid = drm_pci_set_busid;
  927. driver_platform = driver_stub;
  928. nouveau_display_options();
  929. if (nouveau_modeset == -1) {
  930. if (vgacon_text_force())
  931. nouveau_modeset = 0;
  932. }
  933. if (!nouveau_modeset)
  934. return 0;
  935. #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
  936. platform_driver_register(&nouveau_platform_driver);
  937. #endif
  938. nouveau_register_dsm_handler();
  939. nouveau_backlight_ctor();
  940. return drm_pci_init(&driver_pci, &nouveau_drm_pci_driver);
  941. }
  942. static void __exit
  943. nouveau_drm_exit(void)
  944. {
  945. if (!nouveau_modeset)
  946. return;
  947. drm_pci_exit(&driver_pci, &nouveau_drm_pci_driver);
  948. nouveau_backlight_dtor();
  949. nouveau_unregister_dsm_handler();
  950. #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
  951. platform_driver_unregister(&nouveau_platform_driver);
  952. #endif
  953. }
  954. module_init(nouveau_drm_init);
  955. module_exit(nouveau_drm_exit);
  956. MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
  957. MODULE_AUTHOR(DRIVER_AUTHOR);
  958. MODULE_DESCRIPTION(DRIVER_DESC);
  959. MODULE_LICENSE("GPL and additional rights");