mgag200_mode.c 42 KB

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  1. /*
  2. * Copyright 2010 Matt Turner.
  3. * Copyright 2012 Red Hat
  4. *
  5. * This file is subject to the terms and conditions of the GNU General
  6. * Public License version 2. See the file COPYING in the main
  7. * directory of this archive for more details.
  8. *
  9. * Authors: Matthew Garrett
  10. * Matt Turner
  11. * Dave Airlie
  12. */
  13. #include <linux/delay.h>
  14. #include <drm/drmP.h>
  15. #include <drm/drm_crtc_helper.h>
  16. #include <drm/drm_plane_helper.h>
  17. #include "mgag200_drv.h"
  18. #define MGAG200_LUT_SIZE 256
  19. /*
  20. * This file contains setup code for the CRTC.
  21. */
  22. static void mga_crtc_load_lut(struct drm_crtc *crtc)
  23. {
  24. struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
  25. struct drm_device *dev = crtc->dev;
  26. struct mga_device *mdev = dev->dev_private;
  27. struct drm_framebuffer *fb = crtc->primary->fb;
  28. int i;
  29. if (!crtc->enabled)
  30. return;
  31. WREG8(DAC_INDEX + MGA1064_INDEX, 0);
  32. if (fb && fb->format->cpp[0] * 8 == 16) {
  33. int inc = (fb->format->depth == 15) ? 8 : 4;
  34. u8 r, b;
  35. for (i = 0; i < MGAG200_LUT_SIZE; i += inc) {
  36. if (fb->format->depth == 16) {
  37. if (i > (MGAG200_LUT_SIZE >> 1)) {
  38. r = b = 0;
  39. } else {
  40. r = mga_crtc->lut_r[i << 1];
  41. b = mga_crtc->lut_b[i << 1];
  42. }
  43. } else {
  44. r = mga_crtc->lut_r[i];
  45. b = mga_crtc->lut_b[i];
  46. }
  47. /* VGA registers */
  48. WREG8(DAC_INDEX + MGA1064_COL_PAL, r);
  49. WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
  50. WREG8(DAC_INDEX + MGA1064_COL_PAL, b);
  51. }
  52. return;
  53. }
  54. for (i = 0; i < MGAG200_LUT_SIZE; i++) {
  55. /* VGA registers */
  56. WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_r[i]);
  57. WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
  58. WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_b[i]);
  59. }
  60. }
  61. static inline void mga_wait_vsync(struct mga_device *mdev)
  62. {
  63. unsigned long timeout = jiffies + HZ/10;
  64. unsigned int status = 0;
  65. do {
  66. status = RREG32(MGAREG_Status);
  67. } while ((status & 0x08) && time_before(jiffies, timeout));
  68. timeout = jiffies + HZ/10;
  69. status = 0;
  70. do {
  71. status = RREG32(MGAREG_Status);
  72. } while (!(status & 0x08) && time_before(jiffies, timeout));
  73. }
  74. static inline void mga_wait_busy(struct mga_device *mdev)
  75. {
  76. unsigned long timeout = jiffies + HZ;
  77. unsigned int status = 0;
  78. do {
  79. status = RREG8(MGAREG_Status + 2);
  80. } while ((status & 0x01) && time_before(jiffies, timeout));
  81. }
  82. #define P_ARRAY_SIZE 9
  83. static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
  84. {
  85. unsigned int vcomax, vcomin, pllreffreq;
  86. unsigned int delta, tmpdelta, permitteddelta;
  87. unsigned int testp, testm, testn;
  88. unsigned int p, m, n;
  89. unsigned int computed;
  90. unsigned int pvalues_e4[P_ARRAY_SIZE] = {16, 14, 12, 10, 8, 6, 4, 2, 1};
  91. unsigned int fvv;
  92. unsigned int i;
  93. if (mdev->unique_rev_id <= 0x03) {
  94. m = n = p = 0;
  95. vcomax = 320000;
  96. vcomin = 160000;
  97. pllreffreq = 25000;
  98. delta = 0xffffffff;
  99. permitteddelta = clock * 5 / 1000;
  100. for (testp = 8; testp > 0; testp /= 2) {
  101. if (clock * testp > vcomax)
  102. continue;
  103. if (clock * testp < vcomin)
  104. continue;
  105. for (testn = 17; testn < 256; testn++) {
  106. for (testm = 1; testm < 32; testm++) {
  107. computed = (pllreffreq * testn) /
  108. (testm * testp);
  109. if (computed > clock)
  110. tmpdelta = computed - clock;
  111. else
  112. tmpdelta = clock - computed;
  113. if (tmpdelta < delta) {
  114. delta = tmpdelta;
  115. m = testm - 1;
  116. n = testn - 1;
  117. p = testp - 1;
  118. }
  119. }
  120. }
  121. }
  122. } else {
  123. m = n = p = 0;
  124. vcomax = 1600000;
  125. vcomin = 800000;
  126. pllreffreq = 25000;
  127. if (clock < 25000)
  128. clock = 25000;
  129. clock = clock * 2;
  130. delta = 0xFFFFFFFF;
  131. /* Permited delta is 0.5% as VESA Specification */
  132. permitteddelta = clock * 5 / 1000;
  133. for (i = 0 ; i < P_ARRAY_SIZE ; i++) {
  134. testp = pvalues_e4[i];
  135. if ((clock * testp) > vcomax)
  136. continue;
  137. if ((clock * testp) < vcomin)
  138. continue;
  139. for (testn = 50; testn <= 256; testn++) {
  140. for (testm = 1; testm <= 32; testm++) {
  141. computed = (pllreffreq * testn) /
  142. (testm * testp);
  143. if (computed > clock)
  144. tmpdelta = computed - clock;
  145. else
  146. tmpdelta = clock - computed;
  147. if (tmpdelta < delta) {
  148. delta = tmpdelta;
  149. m = testm - 1;
  150. n = testn - 1;
  151. p = testp - 1;
  152. }
  153. }
  154. }
  155. }
  156. fvv = pllreffreq * (n + 1) / (m + 1);
  157. fvv = (fvv - 800000) / 50000;
  158. if (fvv > 15)
  159. fvv = 15;
  160. p |= (fvv << 4);
  161. m |= 0x80;
  162. clock = clock / 2;
  163. }
  164. if (delta > permitteddelta) {
  165. printk(KERN_WARNING "PLL delta too large\n");
  166. return 1;
  167. }
  168. WREG_DAC(MGA1064_PIX_PLLC_M, m);
  169. WREG_DAC(MGA1064_PIX_PLLC_N, n);
  170. WREG_DAC(MGA1064_PIX_PLLC_P, p);
  171. if (mdev->unique_rev_id >= 0x04) {
  172. WREG_DAC(0x1a, 0x09);
  173. msleep(20);
  174. WREG_DAC(0x1a, 0x01);
  175. }
  176. return 0;
  177. }
  178. static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
  179. {
  180. unsigned int vcomax, vcomin, pllreffreq;
  181. unsigned int delta, tmpdelta;
  182. unsigned int testp, testm, testn, testp2;
  183. unsigned int p, m, n;
  184. unsigned int computed;
  185. int i, j, tmpcount, vcount;
  186. bool pll_locked = false;
  187. u8 tmp;
  188. m = n = p = 0;
  189. delta = 0xffffffff;
  190. if (mdev->type == G200_EW3) {
  191. vcomax = 800000;
  192. vcomin = 400000;
  193. pllreffreq = 25000;
  194. for (testp = 1; testp < 8; testp++) {
  195. for (testp2 = 1; testp2 < 8; testp2++) {
  196. if (testp < testp2)
  197. continue;
  198. if ((clock * testp * testp2) > vcomax)
  199. continue;
  200. if ((clock * testp * testp2) < vcomin)
  201. continue;
  202. for (testm = 1; testm < 26; testm++) {
  203. for (testn = 32; testn < 2048 ; testn++) {
  204. computed = (pllreffreq * testn) /
  205. (testm * testp * testp2);
  206. if (computed > clock)
  207. tmpdelta = computed - clock;
  208. else
  209. tmpdelta = clock - computed;
  210. if (tmpdelta < delta) {
  211. delta = tmpdelta;
  212. m = ((testn & 0x100) >> 1) |
  213. (testm);
  214. n = (testn & 0xFF);
  215. p = ((testn & 0x600) >> 3) |
  216. (testp2 << 3) |
  217. (testp);
  218. }
  219. }
  220. }
  221. }
  222. }
  223. } else {
  224. vcomax = 550000;
  225. vcomin = 150000;
  226. pllreffreq = 48000;
  227. for (testp = 1; testp < 9; testp++) {
  228. if (clock * testp > vcomax)
  229. continue;
  230. if (clock * testp < vcomin)
  231. continue;
  232. for (testm = 1; testm < 17; testm++) {
  233. for (testn = 1; testn < 151; testn++) {
  234. computed = (pllreffreq * testn) /
  235. (testm * testp);
  236. if (computed > clock)
  237. tmpdelta = computed - clock;
  238. else
  239. tmpdelta = clock - computed;
  240. if (tmpdelta < delta) {
  241. delta = tmpdelta;
  242. n = testn - 1;
  243. m = (testm - 1) |
  244. ((n >> 1) & 0x80);
  245. p = testp - 1;
  246. }
  247. }
  248. }
  249. }
  250. }
  251. for (i = 0; i <= 32 && pll_locked == false; i++) {
  252. if (i > 0) {
  253. WREG8(MGAREG_CRTC_INDEX, 0x1e);
  254. tmp = RREG8(MGAREG_CRTC_DATA);
  255. if (tmp < 0xff)
  256. WREG8(MGAREG_CRTC_DATA, tmp+1);
  257. }
  258. /* set pixclkdis to 1 */
  259. WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
  260. tmp = RREG8(DAC_DATA);
  261. tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
  262. WREG8(DAC_DATA, tmp);
  263. WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
  264. tmp = RREG8(DAC_DATA);
  265. tmp |= MGA1064_REMHEADCTL_CLKDIS;
  266. WREG8(DAC_DATA, tmp);
  267. /* select PLL Set C */
  268. tmp = RREG8(MGAREG_MEM_MISC_READ);
  269. tmp |= 0x3 << 2;
  270. WREG8(MGAREG_MEM_MISC_WRITE, tmp);
  271. WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
  272. tmp = RREG8(DAC_DATA);
  273. tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
  274. WREG8(DAC_DATA, tmp);
  275. udelay(500);
  276. /* reset the PLL */
  277. WREG8(DAC_INDEX, MGA1064_VREF_CTL);
  278. tmp = RREG8(DAC_DATA);
  279. tmp &= ~0x04;
  280. WREG8(DAC_DATA, tmp);
  281. udelay(50);
  282. /* program pixel pll register */
  283. WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
  284. WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
  285. WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
  286. udelay(50);
  287. /* turn pll on */
  288. WREG8(DAC_INDEX, MGA1064_VREF_CTL);
  289. tmp = RREG8(DAC_DATA);
  290. tmp |= 0x04;
  291. WREG_DAC(MGA1064_VREF_CTL, tmp);
  292. udelay(500);
  293. /* select the pixel pll */
  294. WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
  295. tmp = RREG8(DAC_DATA);
  296. tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
  297. tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
  298. WREG8(DAC_DATA, tmp);
  299. WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
  300. tmp = RREG8(DAC_DATA);
  301. tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
  302. tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
  303. WREG8(DAC_DATA, tmp);
  304. /* reset dotclock rate bit */
  305. WREG8(MGAREG_SEQ_INDEX, 1);
  306. tmp = RREG8(MGAREG_SEQ_DATA);
  307. tmp &= ~0x8;
  308. WREG8(MGAREG_SEQ_DATA, tmp);
  309. WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
  310. tmp = RREG8(DAC_DATA);
  311. tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
  312. WREG8(DAC_DATA, tmp);
  313. vcount = RREG8(MGAREG_VCOUNT);
  314. for (j = 0; j < 30 && pll_locked == false; j++) {
  315. tmpcount = RREG8(MGAREG_VCOUNT);
  316. if (tmpcount < vcount)
  317. vcount = 0;
  318. if ((tmpcount - vcount) > 2)
  319. pll_locked = true;
  320. else
  321. udelay(5);
  322. }
  323. }
  324. WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
  325. tmp = RREG8(DAC_DATA);
  326. tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
  327. WREG_DAC(MGA1064_REMHEADCTL, tmp);
  328. return 0;
  329. }
  330. static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
  331. {
  332. unsigned int vcomax, vcomin, pllreffreq;
  333. unsigned int delta, tmpdelta;
  334. unsigned int testp, testm, testn;
  335. unsigned int p, m, n;
  336. unsigned int computed;
  337. u8 tmp;
  338. m = n = p = 0;
  339. vcomax = 550000;
  340. vcomin = 150000;
  341. pllreffreq = 50000;
  342. delta = 0xffffffff;
  343. for (testp = 16; testp > 0; testp--) {
  344. if (clock * testp > vcomax)
  345. continue;
  346. if (clock * testp < vcomin)
  347. continue;
  348. for (testn = 1; testn < 257; testn++) {
  349. for (testm = 1; testm < 17; testm++) {
  350. computed = (pllreffreq * testn) /
  351. (testm * testp);
  352. if (computed > clock)
  353. tmpdelta = computed - clock;
  354. else
  355. tmpdelta = clock - computed;
  356. if (tmpdelta < delta) {
  357. delta = tmpdelta;
  358. n = testn - 1;
  359. m = testm - 1;
  360. p = testp - 1;
  361. }
  362. }
  363. }
  364. }
  365. WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
  366. tmp = RREG8(DAC_DATA);
  367. tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
  368. WREG8(DAC_DATA, tmp);
  369. tmp = RREG8(MGAREG_MEM_MISC_READ);
  370. tmp |= 0x3 << 2;
  371. WREG8(MGAREG_MEM_MISC_WRITE, tmp);
  372. WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
  373. tmp = RREG8(DAC_DATA);
  374. WREG8(DAC_DATA, tmp & ~0x40);
  375. WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
  376. tmp = RREG8(DAC_DATA);
  377. tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
  378. WREG8(DAC_DATA, tmp);
  379. WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
  380. WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
  381. WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
  382. udelay(50);
  383. WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
  384. tmp = RREG8(DAC_DATA);
  385. tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
  386. WREG8(DAC_DATA, tmp);
  387. udelay(500);
  388. WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
  389. tmp = RREG8(DAC_DATA);
  390. tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
  391. tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
  392. WREG8(DAC_DATA, tmp);
  393. WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
  394. tmp = RREG8(DAC_DATA);
  395. WREG8(DAC_DATA, tmp | 0x40);
  396. tmp = RREG8(MGAREG_MEM_MISC_READ);
  397. tmp |= (0x3 << 2);
  398. WREG8(MGAREG_MEM_MISC_WRITE, tmp);
  399. WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
  400. tmp = RREG8(DAC_DATA);
  401. tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
  402. WREG8(DAC_DATA, tmp);
  403. return 0;
  404. }
  405. static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
  406. {
  407. unsigned int vcomax, vcomin, pllreffreq;
  408. unsigned int delta, tmpdelta;
  409. unsigned int testp, testm, testn;
  410. unsigned int p, m, n;
  411. unsigned int computed;
  412. int i, j, tmpcount, vcount;
  413. u8 tmp;
  414. bool pll_locked = false;
  415. m = n = p = 0;
  416. if (mdev->type == G200_EH3) {
  417. vcomax = 3000000;
  418. vcomin = 1500000;
  419. pllreffreq = 25000;
  420. delta = 0xffffffff;
  421. testp = 0;
  422. for (testm = 150; testm >= 6; testm--) {
  423. if (clock * testm > vcomax)
  424. continue;
  425. if (clock * testm < vcomin)
  426. continue;
  427. for (testn = 120; testn >= 60; testn--) {
  428. computed = (pllreffreq * testn) / testm;
  429. if (computed > clock)
  430. tmpdelta = computed - clock;
  431. else
  432. tmpdelta = clock - computed;
  433. if (tmpdelta < delta) {
  434. delta = tmpdelta;
  435. n = testn;
  436. m = testm;
  437. p = testp;
  438. }
  439. if (delta == 0)
  440. break;
  441. }
  442. if (delta == 0)
  443. break;
  444. }
  445. } else {
  446. vcomax = 800000;
  447. vcomin = 400000;
  448. pllreffreq = 33333;
  449. delta = 0xffffffff;
  450. for (testp = 16; testp > 0; testp >>= 1) {
  451. if (clock * testp > vcomax)
  452. continue;
  453. if (clock * testp < vcomin)
  454. continue;
  455. for (testm = 1; testm < 33; testm++) {
  456. for (testn = 17; testn < 257; testn++) {
  457. computed = (pllreffreq * testn) /
  458. (testm * testp);
  459. if (computed > clock)
  460. tmpdelta = computed - clock;
  461. else
  462. tmpdelta = clock - computed;
  463. if (tmpdelta < delta) {
  464. delta = tmpdelta;
  465. n = testn - 1;
  466. m = (testm - 1);
  467. p = testp - 1;
  468. }
  469. if ((clock * testp) >= 600000)
  470. p |= 0x80;
  471. }
  472. }
  473. }
  474. }
  475. for (i = 0; i <= 32 && pll_locked == false; i++) {
  476. WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
  477. tmp = RREG8(DAC_DATA);
  478. tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
  479. WREG8(DAC_DATA, tmp);
  480. tmp = RREG8(MGAREG_MEM_MISC_READ);
  481. tmp |= 0x3 << 2;
  482. WREG8(MGAREG_MEM_MISC_WRITE, tmp);
  483. WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
  484. tmp = RREG8(DAC_DATA);
  485. tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
  486. WREG8(DAC_DATA, tmp);
  487. udelay(500);
  488. WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
  489. WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
  490. WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
  491. udelay(500);
  492. WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
  493. tmp = RREG8(DAC_DATA);
  494. tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
  495. tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
  496. WREG8(DAC_DATA, tmp);
  497. WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
  498. tmp = RREG8(DAC_DATA);
  499. tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
  500. tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
  501. WREG8(DAC_DATA, tmp);
  502. vcount = RREG8(MGAREG_VCOUNT);
  503. for (j = 0; j < 30 && pll_locked == false; j++) {
  504. tmpcount = RREG8(MGAREG_VCOUNT);
  505. if (tmpcount < vcount)
  506. vcount = 0;
  507. if ((tmpcount - vcount) > 2)
  508. pll_locked = true;
  509. else
  510. udelay(5);
  511. }
  512. }
  513. return 0;
  514. }
  515. static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
  516. {
  517. unsigned int vcomax, vcomin, pllreffreq;
  518. unsigned int delta, tmpdelta;
  519. int testr, testn, testm, testo;
  520. unsigned int p, m, n;
  521. unsigned int computed, vco;
  522. int tmp;
  523. const unsigned int m_div_val[] = { 1, 2, 4, 8 };
  524. m = n = p = 0;
  525. vcomax = 1488000;
  526. vcomin = 1056000;
  527. pllreffreq = 48000;
  528. delta = 0xffffffff;
  529. for (testr = 0; testr < 4; testr++) {
  530. if (delta == 0)
  531. break;
  532. for (testn = 5; testn < 129; testn++) {
  533. if (delta == 0)
  534. break;
  535. for (testm = 3; testm >= 0; testm--) {
  536. if (delta == 0)
  537. break;
  538. for (testo = 5; testo < 33; testo++) {
  539. vco = pllreffreq * (testn + 1) /
  540. (testr + 1);
  541. if (vco < vcomin)
  542. continue;
  543. if (vco > vcomax)
  544. continue;
  545. computed = vco / (m_div_val[testm] * (testo + 1));
  546. if (computed > clock)
  547. tmpdelta = computed - clock;
  548. else
  549. tmpdelta = clock - computed;
  550. if (tmpdelta < delta) {
  551. delta = tmpdelta;
  552. m = testm | (testo << 3);
  553. n = testn;
  554. p = testr | (testr << 3);
  555. }
  556. }
  557. }
  558. }
  559. }
  560. WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
  561. tmp = RREG8(DAC_DATA);
  562. tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
  563. WREG8(DAC_DATA, tmp);
  564. WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
  565. tmp = RREG8(DAC_DATA);
  566. tmp |= MGA1064_REMHEADCTL_CLKDIS;
  567. WREG8(DAC_DATA, tmp);
  568. tmp = RREG8(MGAREG_MEM_MISC_READ);
  569. tmp |= (0x3<<2) | 0xc0;
  570. WREG8(MGAREG_MEM_MISC_WRITE, tmp);
  571. WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
  572. tmp = RREG8(DAC_DATA);
  573. tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
  574. tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
  575. WREG8(DAC_DATA, tmp);
  576. udelay(500);
  577. WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
  578. WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
  579. WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
  580. udelay(50);
  581. return 0;
  582. }
  583. static int mga_crtc_set_plls(struct mga_device *mdev, long clock)
  584. {
  585. switch(mdev->type) {
  586. case G200_SE_A:
  587. case G200_SE_B:
  588. return mga_g200se_set_plls(mdev, clock);
  589. break;
  590. case G200_WB:
  591. case G200_EW3:
  592. return mga_g200wb_set_plls(mdev, clock);
  593. break;
  594. case G200_EV:
  595. return mga_g200ev_set_plls(mdev, clock);
  596. break;
  597. case G200_EH:
  598. case G200_EH3:
  599. return mga_g200eh_set_plls(mdev, clock);
  600. break;
  601. case G200_ER:
  602. return mga_g200er_set_plls(mdev, clock);
  603. break;
  604. }
  605. return 0;
  606. }
  607. static void mga_g200wb_prepare(struct drm_crtc *crtc)
  608. {
  609. struct mga_device *mdev = crtc->dev->dev_private;
  610. u8 tmp;
  611. int iter_max;
  612. /* 1- The first step is to warn the BMC of an upcoming mode change.
  613. * We are putting the misc<0> to output.*/
  614. WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
  615. tmp = RREG8(DAC_DATA);
  616. tmp |= 0x10;
  617. WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
  618. /* we are putting a 1 on the misc<0> line */
  619. WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
  620. tmp = RREG8(DAC_DATA);
  621. tmp |= 0x10;
  622. WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
  623. /* 2- Second step to mask and further scan request
  624. * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
  625. */
  626. WREG8(DAC_INDEX, MGA1064_SPAREREG);
  627. tmp = RREG8(DAC_DATA);
  628. tmp |= 0x80;
  629. WREG_DAC(MGA1064_SPAREREG, tmp);
  630. /* 3a- the third step is to verifu if there is an active scan
  631. * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
  632. */
  633. iter_max = 300;
  634. while (!(tmp & 0x1) && iter_max) {
  635. WREG8(DAC_INDEX, MGA1064_SPAREREG);
  636. tmp = RREG8(DAC_DATA);
  637. udelay(1000);
  638. iter_max--;
  639. }
  640. /* 3b- this step occurs only if the remove is actually scanning
  641. * we are waiting for the end of the frame which is a 1 on
  642. * remvsyncsts (XSPAREREG<1>)
  643. */
  644. if (iter_max) {
  645. iter_max = 300;
  646. while ((tmp & 0x2) && iter_max) {
  647. WREG8(DAC_INDEX, MGA1064_SPAREREG);
  648. tmp = RREG8(DAC_DATA);
  649. udelay(1000);
  650. iter_max--;
  651. }
  652. }
  653. }
  654. static void mga_g200wb_commit(struct drm_crtc *crtc)
  655. {
  656. u8 tmp;
  657. struct mga_device *mdev = crtc->dev->dev_private;
  658. /* 1- The first step is to ensure that the vrsten and hrsten are set */
  659. WREG8(MGAREG_CRTCEXT_INDEX, 1);
  660. tmp = RREG8(MGAREG_CRTCEXT_DATA);
  661. WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
  662. /* 2- second step is to assert the rstlvl2 */
  663. WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
  664. tmp = RREG8(DAC_DATA);
  665. tmp |= 0x8;
  666. WREG8(DAC_DATA, tmp);
  667. /* wait 10 us */
  668. udelay(10);
  669. /* 3- deassert rstlvl2 */
  670. tmp &= ~0x08;
  671. WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
  672. WREG8(DAC_DATA, tmp);
  673. /* 4- remove mask of scan request */
  674. WREG8(DAC_INDEX, MGA1064_SPAREREG);
  675. tmp = RREG8(DAC_DATA);
  676. tmp &= ~0x80;
  677. WREG8(DAC_DATA, tmp);
  678. /* 5- put back a 0 on the misc<0> line */
  679. WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
  680. tmp = RREG8(DAC_DATA);
  681. tmp &= ~0x10;
  682. WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
  683. }
  684. /*
  685. This is how the framebuffer base address is stored in g200 cards:
  686. * Assume @offset is the gpu_addr variable of the framebuffer object
  687. * Then addr is the number of _pixels_ (not bytes) from the start of
  688. VRAM to the first pixel we want to display. (divided by 2 for 32bit
  689. framebuffers)
  690. * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
  691. addr<20> -> CRTCEXT0<6>
  692. addr<19-16> -> CRTCEXT0<3-0>
  693. addr<15-8> -> CRTCC<7-0>
  694. addr<7-0> -> CRTCD<7-0>
  695. CRTCEXT0 has to be programmed last to trigger an update and make the
  696. new addr variable take effect.
  697. */
  698. static void mga_set_start_address(struct drm_crtc *crtc, unsigned offset)
  699. {
  700. struct mga_device *mdev = crtc->dev->dev_private;
  701. u32 addr;
  702. int count;
  703. u8 crtcext0;
  704. while (RREG8(0x1fda) & 0x08);
  705. while (!(RREG8(0x1fda) & 0x08));
  706. count = RREG8(MGAREG_VCOUNT) + 2;
  707. while (RREG8(MGAREG_VCOUNT) < count);
  708. WREG8(MGAREG_CRTCEXT_INDEX, 0);
  709. crtcext0 = RREG8(MGAREG_CRTCEXT_DATA);
  710. crtcext0 &= 0xB0;
  711. addr = offset / 8;
  712. /* Can't store addresses any higher than that...
  713. but we also don't have more than 16MB of memory, so it should be fine. */
  714. WARN_ON(addr > 0x1fffff);
  715. crtcext0 |= (!!(addr & (1<<20)))<<6;
  716. WREG_CRT(0x0d, (u8)(addr & 0xff));
  717. WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff);
  718. WREG_ECRT(0x0, ((u8)(addr >> 16) & 0xf) | crtcext0);
  719. }
  720. /* ast is different - we will force move buffers out of VRAM */
  721. static int mga_crtc_do_set_base(struct drm_crtc *crtc,
  722. struct drm_framebuffer *fb,
  723. int x, int y, int atomic)
  724. {
  725. struct mga_device *mdev = crtc->dev->dev_private;
  726. struct drm_gem_object *obj;
  727. struct mga_framebuffer *mga_fb;
  728. struct mgag200_bo *bo;
  729. int ret;
  730. u64 gpu_addr;
  731. /* push the previous fb to system ram */
  732. if (!atomic && fb) {
  733. mga_fb = to_mga_framebuffer(fb);
  734. obj = mga_fb->obj;
  735. bo = gem_to_mga_bo(obj);
  736. ret = mgag200_bo_reserve(bo, false);
  737. if (ret)
  738. return ret;
  739. mgag200_bo_push_sysram(bo);
  740. mgag200_bo_unreserve(bo);
  741. }
  742. mga_fb = to_mga_framebuffer(crtc->primary->fb);
  743. obj = mga_fb->obj;
  744. bo = gem_to_mga_bo(obj);
  745. ret = mgag200_bo_reserve(bo, false);
  746. if (ret)
  747. return ret;
  748. ret = mgag200_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
  749. if (ret) {
  750. mgag200_bo_unreserve(bo);
  751. return ret;
  752. }
  753. if (&mdev->mfbdev->mfb == mga_fb) {
  754. /* if pushing console in kmap it */
  755. ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
  756. if (ret)
  757. DRM_ERROR("failed to kmap fbcon\n");
  758. }
  759. mgag200_bo_unreserve(bo);
  760. mga_set_start_address(crtc, (u32)gpu_addr);
  761. return 0;
  762. }
  763. static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
  764. struct drm_framebuffer *old_fb)
  765. {
  766. return mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
  767. }
  768. static int mga_crtc_mode_set(struct drm_crtc *crtc,
  769. struct drm_display_mode *mode,
  770. struct drm_display_mode *adjusted_mode,
  771. int x, int y, struct drm_framebuffer *old_fb)
  772. {
  773. struct drm_device *dev = crtc->dev;
  774. struct mga_device *mdev = dev->dev_private;
  775. const struct drm_framebuffer *fb = crtc->primary->fb;
  776. int hdisplay, hsyncstart, hsyncend, htotal;
  777. int vdisplay, vsyncstart, vsyncend, vtotal;
  778. int pitch;
  779. int option = 0, option2 = 0;
  780. int i;
  781. unsigned char misc = 0;
  782. unsigned char ext_vga[6];
  783. u8 bppshift;
  784. static unsigned char dacvalue[] = {
  785. /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
  786. /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
  787. /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
  788. /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
  789. /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  790. /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
  791. /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
  792. /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
  793. /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
  794. /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
  795. };
  796. bppshift = mdev->bpp_shifts[fb->format->cpp[0] - 1];
  797. switch (mdev->type) {
  798. case G200_SE_A:
  799. case G200_SE_B:
  800. dacvalue[MGA1064_VREF_CTL] = 0x03;
  801. dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
  802. dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
  803. MGA1064_MISC_CTL_VGA8 |
  804. MGA1064_MISC_CTL_DAC_RAM_CS;
  805. if (mdev->has_sdram)
  806. option = 0x40049120;
  807. else
  808. option = 0x4004d120;
  809. option2 = 0x00008000;
  810. break;
  811. case G200_WB:
  812. case G200_EW3:
  813. dacvalue[MGA1064_VREF_CTL] = 0x07;
  814. option = 0x41049120;
  815. option2 = 0x0000b000;
  816. break;
  817. case G200_EV:
  818. dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
  819. dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
  820. MGA1064_MISC_CTL_DAC_RAM_CS;
  821. option = 0x00000120;
  822. option2 = 0x0000b000;
  823. break;
  824. case G200_EH:
  825. case G200_EH3:
  826. dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
  827. MGA1064_MISC_CTL_DAC_RAM_CS;
  828. option = 0x00000120;
  829. option2 = 0x0000b000;
  830. break;
  831. case G200_ER:
  832. break;
  833. }
  834. switch (fb->format->cpp[0] * 8) {
  835. case 8:
  836. dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits;
  837. break;
  838. case 16:
  839. if (fb->format->depth == 15)
  840. dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits;
  841. else
  842. dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits;
  843. break;
  844. case 24:
  845. dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits;
  846. break;
  847. case 32:
  848. dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits;
  849. break;
  850. }
  851. if (mode->flags & DRM_MODE_FLAG_NHSYNC)
  852. misc |= 0x40;
  853. if (mode->flags & DRM_MODE_FLAG_NVSYNC)
  854. misc |= 0x80;
  855. for (i = 0; i < sizeof(dacvalue); i++) {
  856. if ((i <= 0x17) ||
  857. (i == 0x1b) ||
  858. (i == 0x1c) ||
  859. ((i >= 0x1f) && (i <= 0x29)) ||
  860. ((i >= 0x30) && (i <= 0x37)))
  861. continue;
  862. if (IS_G200_SE(mdev) &&
  863. ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
  864. continue;
  865. if ((mdev->type == G200_EV ||
  866. mdev->type == G200_WB ||
  867. mdev->type == G200_EH ||
  868. mdev->type == G200_EW3 ||
  869. mdev->type == G200_EH3) &&
  870. (i >= 0x44) && (i <= 0x4e))
  871. continue;
  872. WREG_DAC(i, dacvalue[i]);
  873. }
  874. if (mdev->type == G200_ER)
  875. WREG_DAC(0x90, 0);
  876. if (option)
  877. pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
  878. if (option2)
  879. pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
  880. WREG_SEQ(2, 0xf);
  881. WREG_SEQ(3, 0);
  882. WREG_SEQ(4, 0xe);
  883. pitch = fb->pitches[0] / fb->format->cpp[0];
  884. if (fb->format->cpp[0] * 8 == 24)
  885. pitch = (pitch * 3) >> (4 - bppshift);
  886. else
  887. pitch = pitch >> (4 - bppshift);
  888. hdisplay = mode->hdisplay / 8 - 1;
  889. hsyncstart = mode->hsync_start / 8 - 1;
  890. hsyncend = mode->hsync_end / 8 - 1;
  891. htotal = mode->htotal / 8 - 1;
  892. /* Work around hardware quirk */
  893. if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
  894. htotal++;
  895. vdisplay = mode->vdisplay - 1;
  896. vsyncstart = mode->vsync_start - 1;
  897. vsyncend = mode->vsync_end - 1;
  898. vtotal = mode->vtotal - 2;
  899. WREG_GFX(0, 0);
  900. WREG_GFX(1, 0);
  901. WREG_GFX(2, 0);
  902. WREG_GFX(3, 0);
  903. WREG_GFX(4, 0);
  904. WREG_GFX(5, 0x40);
  905. WREG_GFX(6, 0x5);
  906. WREG_GFX(7, 0xf);
  907. WREG_GFX(8, 0xf);
  908. WREG_CRT(0, htotal - 4);
  909. WREG_CRT(1, hdisplay);
  910. WREG_CRT(2, hdisplay);
  911. WREG_CRT(3, (htotal & 0x1F) | 0x80);
  912. WREG_CRT(4, hsyncstart);
  913. WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
  914. WREG_CRT(6, vtotal & 0xFF);
  915. WREG_CRT(7, ((vtotal & 0x100) >> 8) |
  916. ((vdisplay & 0x100) >> 7) |
  917. ((vsyncstart & 0x100) >> 6) |
  918. ((vdisplay & 0x100) >> 5) |
  919. ((vdisplay & 0x100) >> 4) | /* linecomp */
  920. ((vtotal & 0x200) >> 4)|
  921. ((vdisplay & 0x200) >> 3) |
  922. ((vsyncstart & 0x200) >> 2));
  923. WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
  924. ((vdisplay & 0x200) >> 3));
  925. WREG_CRT(10, 0);
  926. WREG_CRT(11, 0);
  927. WREG_CRT(12, 0);
  928. WREG_CRT(13, 0);
  929. WREG_CRT(14, 0);
  930. WREG_CRT(15, 0);
  931. WREG_CRT(16, vsyncstart & 0xFF);
  932. WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
  933. WREG_CRT(18, vdisplay & 0xFF);
  934. WREG_CRT(19, pitch & 0xFF);
  935. WREG_CRT(20, 0);
  936. WREG_CRT(21, vdisplay & 0xFF);
  937. WREG_CRT(22, (vtotal + 1) & 0xFF);
  938. WREG_CRT(23, 0xc3);
  939. WREG_CRT(24, vdisplay & 0xFF);
  940. ext_vga[0] = 0;
  941. ext_vga[5] = 0;
  942. /* TODO interlace */
  943. ext_vga[0] |= (pitch & 0x300) >> 4;
  944. ext_vga[1] = (((htotal - 4) & 0x100) >> 8) |
  945. ((hdisplay & 0x100) >> 7) |
  946. ((hsyncstart & 0x100) >> 6) |
  947. (htotal & 0x40);
  948. ext_vga[2] = ((vtotal & 0xc00) >> 10) |
  949. ((vdisplay & 0x400) >> 8) |
  950. ((vdisplay & 0xc00) >> 7) |
  951. ((vsyncstart & 0xc00) >> 5) |
  952. ((vdisplay & 0x400) >> 3);
  953. if (fb->format->cpp[0] * 8 == 24)
  954. ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80;
  955. else
  956. ext_vga[3] = ((1 << bppshift) - 1) | 0x80;
  957. ext_vga[4] = 0;
  958. if (mdev->type == G200_WB || mdev->type == G200_EW3)
  959. ext_vga[1] |= 0x88;
  960. /* Set pixel clocks */
  961. misc = 0x2d;
  962. WREG8(MGA_MISC_OUT, misc);
  963. mga_crtc_set_plls(mdev, mode->clock);
  964. for (i = 0; i < 6; i++) {
  965. WREG_ECRT(i, ext_vga[i]);
  966. }
  967. if (mdev->type == G200_ER)
  968. WREG_ECRT(0x24, 0x5);
  969. if (mdev->type == G200_EW3)
  970. WREG_ECRT(0x34, 0x5);
  971. if (mdev->type == G200_EV) {
  972. WREG_ECRT(6, 0);
  973. }
  974. WREG_ECRT(0, ext_vga[0]);
  975. /* Enable mga pixel clock */
  976. misc = 0x2d;
  977. WREG8(MGA_MISC_OUT, misc);
  978. if (adjusted_mode)
  979. memcpy(&mdev->mode, mode, sizeof(struct drm_display_mode));
  980. mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
  981. /* reset tagfifo */
  982. if (mdev->type == G200_ER) {
  983. u32 mem_ctl = RREG32(MGAREG_MEMCTL);
  984. u8 seq1;
  985. /* screen off */
  986. WREG8(MGAREG_SEQ_INDEX, 0x01);
  987. seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20;
  988. WREG8(MGAREG_SEQ_DATA, seq1);
  989. WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000);
  990. udelay(1000);
  991. WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000);
  992. WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20);
  993. }
  994. if (IS_G200_SE(mdev)) {
  995. if (mdev->unique_rev_id >= 0x02) {
  996. u8 hi_pri_lvl;
  997. u32 bpp;
  998. u32 mb;
  999. if (fb->format->cpp[0] * 8 > 16)
  1000. bpp = 32;
  1001. else if (fb->format->cpp[0] * 8 > 8)
  1002. bpp = 16;
  1003. else
  1004. bpp = 8;
  1005. mb = (mode->clock * bpp) / 1000;
  1006. if (mb > 3100)
  1007. hi_pri_lvl = 0;
  1008. else if (mb > 2600)
  1009. hi_pri_lvl = 1;
  1010. else if (mb > 1900)
  1011. hi_pri_lvl = 2;
  1012. else if (mb > 1160)
  1013. hi_pri_lvl = 3;
  1014. else if (mb > 440)
  1015. hi_pri_lvl = 4;
  1016. else
  1017. hi_pri_lvl = 5;
  1018. WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
  1019. WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl);
  1020. } else {
  1021. WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
  1022. if (mdev->unique_rev_id >= 0x01)
  1023. WREG8(MGAREG_CRTCEXT_DATA, 0x03);
  1024. else
  1025. WREG8(MGAREG_CRTCEXT_DATA, 0x04);
  1026. }
  1027. }
  1028. return 0;
  1029. }
  1030. #if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */
  1031. static int mga_suspend(struct drm_crtc *crtc)
  1032. {
  1033. struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
  1034. struct drm_device *dev = crtc->dev;
  1035. struct mga_device *mdev = dev->dev_private;
  1036. struct pci_dev *pdev = dev->pdev;
  1037. int option;
  1038. if (mdev->suspended)
  1039. return 0;
  1040. WREG_SEQ(1, 0x20);
  1041. WREG_ECRT(1, 0x30);
  1042. /* Disable the pixel clock */
  1043. WREG_DAC(0x1a, 0x05);
  1044. /* Power down the DAC */
  1045. WREG_DAC(0x1e, 0x18);
  1046. /* Power down the pixel PLL */
  1047. WREG_DAC(0x1a, 0x0d);
  1048. /* Disable PLLs and clocks */
  1049. pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
  1050. option &= ~(0x1F8024);
  1051. pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
  1052. pci_set_power_state(pdev, PCI_D3hot);
  1053. pci_disable_device(pdev);
  1054. mdev->suspended = true;
  1055. return 0;
  1056. }
  1057. static int mga_resume(struct drm_crtc *crtc)
  1058. {
  1059. struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
  1060. struct drm_device *dev = crtc->dev;
  1061. struct mga_device *mdev = dev->dev_private;
  1062. struct pci_dev *pdev = dev->pdev;
  1063. int option;
  1064. if (!mdev->suspended)
  1065. return 0;
  1066. pci_set_power_state(pdev, PCI_D0);
  1067. pci_enable_device(pdev);
  1068. /* Disable sysclk */
  1069. pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
  1070. option &= ~(0x4);
  1071. pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
  1072. mdev->suspended = false;
  1073. return 0;
  1074. }
  1075. #endif
  1076. static void mga_crtc_dpms(struct drm_crtc *crtc, int mode)
  1077. {
  1078. struct drm_device *dev = crtc->dev;
  1079. struct mga_device *mdev = dev->dev_private;
  1080. u8 seq1 = 0, crtcext1 = 0;
  1081. switch (mode) {
  1082. case DRM_MODE_DPMS_ON:
  1083. seq1 = 0;
  1084. crtcext1 = 0;
  1085. mga_crtc_load_lut(crtc);
  1086. break;
  1087. case DRM_MODE_DPMS_STANDBY:
  1088. seq1 = 0x20;
  1089. crtcext1 = 0x10;
  1090. break;
  1091. case DRM_MODE_DPMS_SUSPEND:
  1092. seq1 = 0x20;
  1093. crtcext1 = 0x20;
  1094. break;
  1095. case DRM_MODE_DPMS_OFF:
  1096. seq1 = 0x20;
  1097. crtcext1 = 0x30;
  1098. break;
  1099. }
  1100. #if 0
  1101. if (mode == DRM_MODE_DPMS_OFF) {
  1102. mga_suspend(crtc);
  1103. }
  1104. #endif
  1105. WREG8(MGAREG_SEQ_INDEX, 0x01);
  1106. seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20;
  1107. mga_wait_vsync(mdev);
  1108. mga_wait_busy(mdev);
  1109. WREG8(MGAREG_SEQ_DATA, seq1);
  1110. msleep(20);
  1111. WREG8(MGAREG_CRTCEXT_INDEX, 0x01);
  1112. crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30;
  1113. WREG8(MGAREG_CRTCEXT_DATA, crtcext1);
  1114. #if 0
  1115. if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) {
  1116. mga_resume(crtc);
  1117. drm_helper_resume_force_mode(dev);
  1118. }
  1119. #endif
  1120. }
  1121. /*
  1122. * This is called before a mode is programmed. A typical use might be to
  1123. * enable DPMS during the programming to avoid seeing intermediate stages,
  1124. * but that's not relevant to us
  1125. */
  1126. static void mga_crtc_prepare(struct drm_crtc *crtc)
  1127. {
  1128. struct drm_device *dev = crtc->dev;
  1129. struct mga_device *mdev = dev->dev_private;
  1130. u8 tmp;
  1131. /* mga_resume(crtc);*/
  1132. WREG8(MGAREG_CRTC_INDEX, 0x11);
  1133. tmp = RREG8(MGAREG_CRTC_DATA);
  1134. WREG_CRT(0x11, tmp | 0x80);
  1135. if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
  1136. WREG_SEQ(0, 1);
  1137. msleep(50);
  1138. WREG_SEQ(1, 0x20);
  1139. msleep(20);
  1140. } else {
  1141. WREG8(MGAREG_SEQ_INDEX, 0x1);
  1142. tmp = RREG8(MGAREG_SEQ_DATA);
  1143. /* start sync reset */
  1144. WREG_SEQ(0, 1);
  1145. WREG_SEQ(1, tmp | 0x20);
  1146. }
  1147. if (mdev->type == G200_WB || mdev->type == G200_EW3)
  1148. mga_g200wb_prepare(crtc);
  1149. WREG_CRT(17, 0);
  1150. }
  1151. /*
  1152. * This is called after a mode is programmed. It should reverse anything done
  1153. * by the prepare function
  1154. */
  1155. static void mga_crtc_commit(struct drm_crtc *crtc)
  1156. {
  1157. struct drm_device *dev = crtc->dev;
  1158. struct mga_device *mdev = dev->dev_private;
  1159. const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  1160. u8 tmp;
  1161. if (mdev->type == G200_WB || mdev->type == G200_EW3)
  1162. mga_g200wb_commit(crtc);
  1163. if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
  1164. msleep(50);
  1165. WREG_SEQ(1, 0x0);
  1166. msleep(20);
  1167. WREG_SEQ(0, 0x3);
  1168. } else {
  1169. WREG8(MGAREG_SEQ_INDEX, 0x1);
  1170. tmp = RREG8(MGAREG_SEQ_DATA);
  1171. tmp &= ~0x20;
  1172. WREG_SEQ(0x1, tmp);
  1173. WREG_SEQ(0, 3);
  1174. }
  1175. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  1176. }
  1177. /*
  1178. * The core can pass us a set of gamma values to program. We actually only
  1179. * use this for 8-bit mode so can't perform smooth fades on deeper modes,
  1180. * but it's a requirement that we provide the function
  1181. */
  1182. static int mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  1183. u16 *blue, uint32_t size)
  1184. {
  1185. struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
  1186. int i;
  1187. for (i = 0; i < size; i++) {
  1188. mga_crtc->lut_r[i] = red[i] >> 8;
  1189. mga_crtc->lut_g[i] = green[i] >> 8;
  1190. mga_crtc->lut_b[i] = blue[i] >> 8;
  1191. }
  1192. mga_crtc_load_lut(crtc);
  1193. return 0;
  1194. }
  1195. /* Simple cleanup function */
  1196. static void mga_crtc_destroy(struct drm_crtc *crtc)
  1197. {
  1198. struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
  1199. drm_crtc_cleanup(crtc);
  1200. kfree(mga_crtc);
  1201. }
  1202. static void mga_crtc_disable(struct drm_crtc *crtc)
  1203. {
  1204. int ret;
  1205. DRM_DEBUG_KMS("\n");
  1206. mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
  1207. if (crtc->primary->fb) {
  1208. struct mga_framebuffer *mga_fb = to_mga_framebuffer(crtc->primary->fb);
  1209. struct drm_gem_object *obj = mga_fb->obj;
  1210. struct mgag200_bo *bo = gem_to_mga_bo(obj);
  1211. ret = mgag200_bo_reserve(bo, false);
  1212. if (ret)
  1213. return;
  1214. mgag200_bo_push_sysram(bo);
  1215. mgag200_bo_unreserve(bo);
  1216. }
  1217. crtc->primary->fb = NULL;
  1218. }
  1219. /* These provide the minimum set of functions required to handle a CRTC */
  1220. static const struct drm_crtc_funcs mga_crtc_funcs = {
  1221. .cursor_set = mga_crtc_cursor_set,
  1222. .cursor_move = mga_crtc_cursor_move,
  1223. .gamma_set = mga_crtc_gamma_set,
  1224. .set_config = drm_crtc_helper_set_config,
  1225. .destroy = mga_crtc_destroy,
  1226. };
  1227. static const struct drm_crtc_helper_funcs mga_helper_funcs = {
  1228. .disable = mga_crtc_disable,
  1229. .dpms = mga_crtc_dpms,
  1230. .mode_set = mga_crtc_mode_set,
  1231. .mode_set_base = mga_crtc_mode_set_base,
  1232. .prepare = mga_crtc_prepare,
  1233. .commit = mga_crtc_commit,
  1234. .load_lut = mga_crtc_load_lut,
  1235. };
  1236. /* CRTC setup */
  1237. static void mga_crtc_init(struct mga_device *mdev)
  1238. {
  1239. struct mga_crtc *mga_crtc;
  1240. int i;
  1241. mga_crtc = kzalloc(sizeof(struct mga_crtc) +
  1242. (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)),
  1243. GFP_KERNEL);
  1244. if (mga_crtc == NULL)
  1245. return;
  1246. drm_crtc_init(mdev->dev, &mga_crtc->base, &mga_crtc_funcs);
  1247. drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE);
  1248. mdev->mode_info.crtc = mga_crtc;
  1249. for (i = 0; i < MGAG200_LUT_SIZE; i++) {
  1250. mga_crtc->lut_r[i] = i;
  1251. mga_crtc->lut_g[i] = i;
  1252. mga_crtc->lut_b[i] = i;
  1253. }
  1254. drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs);
  1255. }
  1256. /** Sets the color ramps on behalf of fbcon */
  1257. void mga_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  1258. u16 blue, int regno)
  1259. {
  1260. struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
  1261. mga_crtc->lut_r[regno] = red >> 8;
  1262. mga_crtc->lut_g[regno] = green >> 8;
  1263. mga_crtc->lut_b[regno] = blue >> 8;
  1264. }
  1265. /** Gets the color ramps on behalf of fbcon */
  1266. void mga_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  1267. u16 *blue, int regno)
  1268. {
  1269. struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
  1270. *red = (u16)mga_crtc->lut_r[regno] << 8;
  1271. *green = (u16)mga_crtc->lut_g[regno] << 8;
  1272. *blue = (u16)mga_crtc->lut_b[regno] << 8;
  1273. }
  1274. /*
  1275. * The encoder comes after the CRTC in the output pipeline, but before
  1276. * the connector. It's responsible for ensuring that the digital
  1277. * stream is appropriately converted into the output format. Setup is
  1278. * very simple in this case - all we have to do is inform qemu of the
  1279. * colour depth in order to ensure that it displays appropriately
  1280. */
  1281. /*
  1282. * These functions are analagous to those in the CRTC code, but are intended
  1283. * to handle any encoder-specific limitations
  1284. */
  1285. static void mga_encoder_mode_set(struct drm_encoder *encoder,
  1286. struct drm_display_mode *mode,
  1287. struct drm_display_mode *adjusted_mode)
  1288. {
  1289. }
  1290. static void mga_encoder_dpms(struct drm_encoder *encoder, int state)
  1291. {
  1292. return;
  1293. }
  1294. static void mga_encoder_prepare(struct drm_encoder *encoder)
  1295. {
  1296. }
  1297. static void mga_encoder_commit(struct drm_encoder *encoder)
  1298. {
  1299. }
  1300. static void mga_encoder_destroy(struct drm_encoder *encoder)
  1301. {
  1302. struct mga_encoder *mga_encoder = to_mga_encoder(encoder);
  1303. drm_encoder_cleanup(encoder);
  1304. kfree(mga_encoder);
  1305. }
  1306. static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs = {
  1307. .dpms = mga_encoder_dpms,
  1308. .mode_set = mga_encoder_mode_set,
  1309. .prepare = mga_encoder_prepare,
  1310. .commit = mga_encoder_commit,
  1311. };
  1312. static const struct drm_encoder_funcs mga_encoder_encoder_funcs = {
  1313. .destroy = mga_encoder_destroy,
  1314. };
  1315. static struct drm_encoder *mga_encoder_init(struct drm_device *dev)
  1316. {
  1317. struct drm_encoder *encoder;
  1318. struct mga_encoder *mga_encoder;
  1319. mga_encoder = kzalloc(sizeof(struct mga_encoder), GFP_KERNEL);
  1320. if (!mga_encoder)
  1321. return NULL;
  1322. encoder = &mga_encoder->base;
  1323. encoder->possible_crtcs = 0x1;
  1324. drm_encoder_init(dev, encoder, &mga_encoder_encoder_funcs,
  1325. DRM_MODE_ENCODER_DAC, NULL);
  1326. drm_encoder_helper_add(encoder, &mga_encoder_helper_funcs);
  1327. return encoder;
  1328. }
  1329. static int mga_vga_get_modes(struct drm_connector *connector)
  1330. {
  1331. struct mga_connector *mga_connector = to_mga_connector(connector);
  1332. struct edid *edid;
  1333. int ret = 0;
  1334. edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
  1335. if (edid) {
  1336. drm_mode_connector_update_edid_property(connector, edid);
  1337. ret = drm_add_edid_modes(connector, edid);
  1338. kfree(edid);
  1339. }
  1340. return ret;
  1341. }
  1342. static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode,
  1343. int bits_per_pixel)
  1344. {
  1345. uint32_t total_area, divisor;
  1346. uint64_t active_area, pixels_per_second, bandwidth;
  1347. uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8;
  1348. divisor = 1024;
  1349. if (!mode->htotal || !mode->vtotal || !mode->clock)
  1350. return 0;
  1351. active_area = mode->hdisplay * mode->vdisplay;
  1352. total_area = mode->htotal * mode->vtotal;
  1353. pixels_per_second = active_area * mode->clock * 1000;
  1354. do_div(pixels_per_second, total_area);
  1355. bandwidth = pixels_per_second * bytes_per_pixel * 100;
  1356. do_div(bandwidth, divisor);
  1357. return (uint32_t)(bandwidth);
  1358. }
  1359. #define MODE_BANDWIDTH MODE_BAD
  1360. static int mga_vga_mode_valid(struct drm_connector *connector,
  1361. struct drm_display_mode *mode)
  1362. {
  1363. struct drm_device *dev = connector->dev;
  1364. struct mga_device *mdev = (struct mga_device*)dev->dev_private;
  1365. int bpp = 32;
  1366. if (IS_G200_SE(mdev)) {
  1367. if (mdev->unique_rev_id == 0x01) {
  1368. if (mode->hdisplay > 1600)
  1369. return MODE_VIRTUAL_X;
  1370. if (mode->vdisplay > 1200)
  1371. return MODE_VIRTUAL_Y;
  1372. if (mga_vga_calculate_mode_bandwidth(mode, bpp)
  1373. > (24400 * 1024))
  1374. return MODE_BANDWIDTH;
  1375. } else if (mdev->unique_rev_id == 0x02) {
  1376. if (mode->hdisplay > 1920)
  1377. return MODE_VIRTUAL_X;
  1378. if (mode->vdisplay > 1200)
  1379. return MODE_VIRTUAL_Y;
  1380. if (mga_vga_calculate_mode_bandwidth(mode, bpp)
  1381. > (30100 * 1024))
  1382. return MODE_BANDWIDTH;
  1383. }
  1384. } else if (mdev->type == G200_WB) {
  1385. if (mode->hdisplay > 1280)
  1386. return MODE_VIRTUAL_X;
  1387. if (mode->vdisplay > 1024)
  1388. return MODE_VIRTUAL_Y;
  1389. if (mga_vga_calculate_mode_bandwidth(mode,
  1390. bpp > (31877 * 1024)))
  1391. return MODE_BANDWIDTH;
  1392. } else if (mdev->type == G200_EV &&
  1393. (mga_vga_calculate_mode_bandwidth(mode, bpp)
  1394. > (32700 * 1024))) {
  1395. return MODE_BANDWIDTH;
  1396. } else if (mdev->type == G200_EH &&
  1397. (mga_vga_calculate_mode_bandwidth(mode, bpp)
  1398. > (37500 * 1024))) {
  1399. return MODE_BANDWIDTH;
  1400. } else if (mdev->type == G200_ER &&
  1401. (mga_vga_calculate_mode_bandwidth(mode,
  1402. bpp) > (55000 * 1024))) {
  1403. return MODE_BANDWIDTH;
  1404. }
  1405. if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 ||
  1406. (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) {
  1407. return MODE_H_ILLEGAL;
  1408. }
  1409. if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
  1410. mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
  1411. mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
  1412. mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
  1413. return MODE_BAD;
  1414. }
  1415. /* Validate the mode input by the user */
  1416. if (connector->cmdline_mode.specified) {
  1417. if (connector->cmdline_mode.bpp_specified)
  1418. bpp = connector->cmdline_mode.bpp;
  1419. }
  1420. if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) {
  1421. if (connector->cmdline_mode.specified)
  1422. connector->cmdline_mode.specified = false;
  1423. return MODE_BAD;
  1424. }
  1425. return MODE_OK;
  1426. }
  1427. static struct drm_encoder *mga_connector_best_encoder(struct drm_connector
  1428. *connector)
  1429. {
  1430. int enc_id = connector->encoder_ids[0];
  1431. /* pick the encoder ids */
  1432. if (enc_id)
  1433. return drm_encoder_find(connector->dev, enc_id);
  1434. return NULL;
  1435. }
  1436. static void mga_connector_destroy(struct drm_connector *connector)
  1437. {
  1438. struct mga_connector *mga_connector = to_mga_connector(connector);
  1439. mgag200_i2c_destroy(mga_connector->i2c);
  1440. drm_connector_cleanup(connector);
  1441. kfree(connector);
  1442. }
  1443. static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
  1444. .get_modes = mga_vga_get_modes,
  1445. .mode_valid = mga_vga_mode_valid,
  1446. .best_encoder = mga_connector_best_encoder,
  1447. };
  1448. static const struct drm_connector_funcs mga_vga_connector_funcs = {
  1449. .dpms = drm_helper_connector_dpms,
  1450. .fill_modes = drm_helper_probe_single_connector_modes,
  1451. .destroy = mga_connector_destroy,
  1452. };
  1453. static struct drm_connector *mga_vga_init(struct drm_device *dev)
  1454. {
  1455. struct drm_connector *connector;
  1456. struct mga_connector *mga_connector;
  1457. mga_connector = kzalloc(sizeof(struct mga_connector), GFP_KERNEL);
  1458. if (!mga_connector)
  1459. return NULL;
  1460. connector = &mga_connector->base;
  1461. drm_connector_init(dev, connector,
  1462. &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  1463. drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
  1464. drm_connector_register(connector);
  1465. mga_connector->i2c = mgag200_i2c_create(dev);
  1466. if (!mga_connector->i2c)
  1467. DRM_ERROR("failed to add ddc bus\n");
  1468. return connector;
  1469. }
  1470. int mgag200_modeset_init(struct mga_device *mdev)
  1471. {
  1472. struct drm_encoder *encoder;
  1473. struct drm_connector *connector;
  1474. int ret;
  1475. mdev->mode_info.mode_config_initialized = true;
  1476. mdev->dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
  1477. mdev->dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
  1478. mdev->dev->mode_config.fb_base = mdev->mc.vram_base;
  1479. mga_crtc_init(mdev);
  1480. encoder = mga_encoder_init(mdev->dev);
  1481. if (!encoder) {
  1482. DRM_ERROR("mga_encoder_init failed\n");
  1483. return -1;
  1484. }
  1485. connector = mga_vga_init(mdev->dev);
  1486. if (!connector) {
  1487. DRM_ERROR("mga_vga_init failed\n");
  1488. return -1;
  1489. }
  1490. drm_mode_connector_attach_encoder(connector, encoder);
  1491. ret = mgag200_fbdev_init(mdev);
  1492. if (ret) {
  1493. DRM_ERROR("mga_fbdev_init failed\n");
  1494. return ret;
  1495. }
  1496. return 0;
  1497. }
  1498. void mgag200_modeset_fini(struct mga_device *mdev)
  1499. {
  1500. }