meson_vpp.c 5.7 KB

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  1. /*
  2. * Copyright (C) 2016 BayLibre, SAS
  3. * Author: Neil Armstrong <narmstrong@baylibre.com>
  4. * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
  5. * Copyright (C) 2014 Endless Mobile
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of the
  10. * License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/module.h>
  22. #include <drm/drmP.h>
  23. #include "meson_drv.h"
  24. #include "meson_vpp.h"
  25. #include "meson_registers.h"
  26. /*
  27. * VPP Handles all the Post Processing after the Scanout from the VIU
  28. * We handle the following post processings :
  29. * - Postblend : Blends the OSD1 only
  30. * We exclude OSD2, VS1, VS1 and Preblend output
  31. * - Vertical OSD Scaler for OSD1 only, we disable vertical scaler and
  32. * use it only for interlace scanout
  33. * - Intermediate FIFO with default Amlogic values
  34. *
  35. * What is missing :
  36. * - Preblend for video overlay pre-scaling
  37. * - OSD2 support for cursor framebuffer
  38. * - Video pre-scaling before postblend
  39. * - Full Vertical/Horizontal OSD scaling to support TV overscan
  40. * - HDR conversion
  41. */
  42. void meson_vpp_setup_mux(struct meson_drm *priv, unsigned int mux)
  43. {
  44. writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL));
  45. }
  46. /*
  47. * When the output is interlaced, the OSD must switch between
  48. * each field using the INTERLACE_SEL_ODD (0) of VIU_OSD1_BLK0_CFG_W0
  49. * at each vsync.
  50. * But the vertical scaler can provide such funtionnality if
  51. * is configured for 2:1 scaling with interlace options enabled.
  52. */
  53. void meson_vpp_setup_interlace_vscaler_osd1(struct meson_drm *priv,
  54. struct drm_rect *input)
  55. {
  56. writel_relaxed(BIT(3) /* Enable scaler */ |
  57. BIT(2), /* Select OSD1 */
  58. priv->io_base + _REG(VPP_OSD_SC_CTRL0));
  59. writel_relaxed(((drm_rect_width(input) - 1) << 16) |
  60. (drm_rect_height(input) - 1),
  61. priv->io_base + _REG(VPP_OSD_SCI_WH_M1));
  62. /* 2:1 scaling */
  63. writel_relaxed(((input->x1) << 16) | (input->x2),
  64. priv->io_base + _REG(VPP_OSD_SCO_H_START_END));
  65. writel_relaxed(((input->y1 >> 1) << 16) | (input->y2 >> 1),
  66. priv->io_base + _REG(VPP_OSD_SCO_V_START_END));
  67. /* 2:1 scaling values */
  68. writel_relaxed(BIT(16), priv->io_base + _REG(VPP_OSD_VSC_INI_PHASE));
  69. writel_relaxed(BIT(25), priv->io_base + _REG(VPP_OSD_VSC_PHASE_STEP));
  70. writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
  71. writel_relaxed((4 << 0) /* osd_vsc_bank_length */ |
  72. (4 << 3) /* osd_vsc_top_ini_rcv_num0 */ |
  73. (1 << 8) /* osd_vsc_top_rpt_p0_num0 */ |
  74. (6 << 11) /* osd_vsc_bot_ini_rcv_num0 */ |
  75. (2 << 16) /* osd_vsc_bot_rpt_p0_num0 */ |
  76. BIT(23) /* osd_prog_interlace */ |
  77. BIT(24), /* Enable vertical scaler */
  78. priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
  79. }
  80. void meson_vpp_disable_interlace_vscaler_osd1(struct meson_drm *priv)
  81. {
  82. writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
  83. writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
  84. writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
  85. }
  86. static unsigned int vpp_filter_coefs_4point_bspline[] = {
  87. 0x15561500, 0x14561600, 0x13561700, 0x12561800,
  88. 0x11551a00, 0x11541b00, 0x10541c00, 0x0f541d00,
  89. 0x0f531e00, 0x0e531f00, 0x0d522100, 0x0c522200,
  90. 0x0b522300, 0x0b512400, 0x0a502600, 0x0a4f2700,
  91. 0x094e2900, 0x084e2a00, 0x084d2b00, 0x074c2c01,
  92. 0x074b2d01, 0x064a2f01, 0x06493001, 0x05483201,
  93. 0x05473301, 0x05463401, 0x04453601, 0x04433702,
  94. 0x04423802, 0x03413a02, 0x03403b02, 0x033f3c02,
  95. 0x033d3d03
  96. };
  97. static void meson_vpp_write_scaling_filter_coefs(struct meson_drm *priv,
  98. const unsigned int *coefs,
  99. bool is_horizontal)
  100. {
  101. int i;
  102. writel_relaxed(is_horizontal ? BIT(8) : 0,
  103. priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX));
  104. for (i = 0; i < 33; i++)
  105. writel_relaxed(coefs[i],
  106. priv->io_base + _REG(VPP_OSD_SCALE_COEF));
  107. }
  108. void meson_vpp_init(struct meson_drm *priv)
  109. {
  110. /* set dummy data default YUV black */
  111. if (meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
  112. writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1));
  113. else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu")) {
  114. writel_bits_relaxed(0xff << 16, 0xff << 16,
  115. priv->io_base + _REG(VIU_MISC_CTRL1));
  116. writel_relaxed(0x20000, priv->io_base + _REG(VPP_DOLBY_CTRL));
  117. writel_relaxed(0x1020080,
  118. priv->io_base + _REG(VPP_DUMMY_DATA1));
  119. }
  120. /* Initialize vpu fifo control registers */
  121. writel_relaxed(readl_relaxed(priv->io_base + _REG(VPP_OFIFO_SIZE)) |
  122. 0x77f, priv->io_base + _REG(VPP_OFIFO_SIZE));
  123. writel_relaxed(0x08080808, priv->io_base + _REG(VPP_HOLD_LINES));
  124. /* Turn off preblend */
  125. writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0,
  126. priv->io_base + _REG(VPP_MISC));
  127. /* Turn off POSTBLEND */
  128. writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,
  129. priv->io_base + _REG(VPP_MISC));
  130. /* Force all planes off */
  131. writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND |
  132. VPP_VD1_POSTBLEND | VPP_VD2_POSTBLEND, 0,
  133. priv->io_base + _REG(VPP_MISC));
  134. /* Disable Scalers */
  135. writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
  136. writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
  137. writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
  138. /* Write in the proper filter coefficients. */
  139. meson_vpp_write_scaling_filter_coefs(priv,
  140. vpp_filter_coefs_4point_bspline, false);
  141. meson_vpp_write_scaling_filter_coefs(priv,
  142. vpp_filter_coefs_4point_bspline, true);
  143. }