fsl_dcu_drm_drv.c 11 KB

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  1. /*
  2. * Copyright 2015 Freescale Semiconductor, Inc.
  3. *
  4. * Freescale DCU drm device driver
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/clk-provider.h>
  13. #include <linux/console.h>
  14. #include <linux/io.h>
  15. #include <linux/mfd/syscon.h>
  16. #include <linux/mm.h>
  17. #include <linux/module.h>
  18. #include <linux/of_platform.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pm.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/regmap.h>
  23. #include <drm/drmP.h>
  24. #include <drm/drm_atomic_helper.h>
  25. #include <drm/drm_crtc_helper.h>
  26. #include <drm/drm_fb_cma_helper.h>
  27. #include <drm/drm_gem_cma_helper.h>
  28. #include "fsl_dcu_drm_crtc.h"
  29. #include "fsl_dcu_drm_drv.h"
  30. #include "fsl_tcon.h"
  31. static int legacyfb_depth = 24;
  32. module_param(legacyfb_depth, int, 0444);
  33. static bool fsl_dcu_drm_is_volatile_reg(struct device *dev, unsigned int reg)
  34. {
  35. if (reg == DCU_INT_STATUS || reg == DCU_UPDATE_MODE)
  36. return true;
  37. return false;
  38. }
  39. static const struct regmap_config fsl_dcu_regmap_config = {
  40. .reg_bits = 32,
  41. .reg_stride = 4,
  42. .val_bits = 32,
  43. .volatile_reg = fsl_dcu_drm_is_volatile_reg,
  44. };
  45. static int fsl_dcu_drm_irq_init(struct drm_device *dev)
  46. {
  47. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  48. int ret;
  49. ret = drm_irq_install(dev, fsl_dev->irq);
  50. if (ret < 0)
  51. dev_err(dev->dev, "failed to install IRQ handler\n");
  52. regmap_write(fsl_dev->regmap, DCU_INT_STATUS, 0);
  53. regmap_write(fsl_dev->regmap, DCU_INT_MASK, ~0);
  54. return ret;
  55. }
  56. static int fsl_dcu_load(struct drm_device *dev, unsigned long flags)
  57. {
  58. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  59. int ret;
  60. ret = fsl_dcu_drm_modeset_init(fsl_dev);
  61. if (ret < 0) {
  62. dev_err(dev->dev, "failed to initialize mode setting\n");
  63. return ret;
  64. }
  65. ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
  66. if (ret < 0) {
  67. dev_err(dev->dev, "failed to initialize vblank\n");
  68. goto done;
  69. }
  70. ret = fsl_dcu_drm_irq_init(dev);
  71. if (ret < 0)
  72. goto done;
  73. dev->irq_enabled = true;
  74. if (legacyfb_depth != 16 && legacyfb_depth != 24 &&
  75. legacyfb_depth != 32) {
  76. dev_warn(dev->dev,
  77. "Invalid legacyfb_depth. Defaulting to 24bpp\n");
  78. legacyfb_depth = 24;
  79. }
  80. fsl_dev->fbdev = drm_fbdev_cma_init(dev, legacyfb_depth, 1, 1);
  81. if (IS_ERR(fsl_dev->fbdev)) {
  82. ret = PTR_ERR(fsl_dev->fbdev);
  83. fsl_dev->fbdev = NULL;
  84. goto done;
  85. }
  86. return 0;
  87. done:
  88. drm_kms_helper_poll_fini(dev);
  89. if (fsl_dev->fbdev)
  90. drm_fbdev_cma_fini(fsl_dev->fbdev);
  91. drm_mode_config_cleanup(dev);
  92. drm_vblank_cleanup(dev);
  93. drm_irq_uninstall(dev);
  94. dev->dev_private = NULL;
  95. return ret;
  96. }
  97. static void fsl_dcu_unload(struct drm_device *dev)
  98. {
  99. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  100. drm_crtc_force_disable_all(dev);
  101. drm_kms_helper_poll_fini(dev);
  102. if (fsl_dev->fbdev)
  103. drm_fbdev_cma_fini(fsl_dev->fbdev);
  104. drm_mode_config_cleanup(dev);
  105. drm_vblank_cleanup(dev);
  106. drm_irq_uninstall(dev);
  107. dev->dev_private = NULL;
  108. }
  109. static irqreturn_t fsl_dcu_drm_irq(int irq, void *arg)
  110. {
  111. struct drm_device *dev = arg;
  112. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  113. unsigned int int_status;
  114. int ret;
  115. ret = regmap_read(fsl_dev->regmap, DCU_INT_STATUS, &int_status);
  116. if (ret) {
  117. dev_err(dev->dev, "read DCU_INT_STATUS failed\n");
  118. return IRQ_NONE;
  119. }
  120. if (int_status & DCU_INT_STATUS_VBLANK)
  121. drm_handle_vblank(dev, 0);
  122. regmap_write(fsl_dev->regmap, DCU_INT_STATUS, int_status);
  123. return IRQ_HANDLED;
  124. }
  125. static int fsl_dcu_drm_enable_vblank(struct drm_device *dev, unsigned int pipe)
  126. {
  127. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  128. unsigned int value;
  129. regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value);
  130. value &= ~DCU_INT_MASK_VBLANK;
  131. regmap_write(fsl_dev->regmap, DCU_INT_MASK, value);
  132. return 0;
  133. }
  134. static void fsl_dcu_drm_disable_vblank(struct drm_device *dev,
  135. unsigned int pipe)
  136. {
  137. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  138. unsigned int value;
  139. regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value);
  140. value |= DCU_INT_MASK_VBLANK;
  141. regmap_write(fsl_dev->regmap, DCU_INT_MASK, value);
  142. }
  143. static void fsl_dcu_drm_lastclose(struct drm_device *dev)
  144. {
  145. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  146. drm_fbdev_cma_restore_mode(fsl_dev->fbdev);
  147. }
  148. static const struct file_operations fsl_dcu_drm_fops = {
  149. .owner = THIS_MODULE,
  150. .open = drm_open,
  151. .release = drm_release,
  152. .unlocked_ioctl = drm_ioctl,
  153. .compat_ioctl = drm_compat_ioctl,
  154. .poll = drm_poll,
  155. .read = drm_read,
  156. .llseek = no_llseek,
  157. .mmap = drm_gem_cma_mmap,
  158. };
  159. static struct drm_driver fsl_dcu_drm_driver = {
  160. .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET
  161. | DRIVER_PRIME | DRIVER_ATOMIC,
  162. .lastclose = fsl_dcu_drm_lastclose,
  163. .load = fsl_dcu_load,
  164. .unload = fsl_dcu_unload,
  165. .irq_handler = fsl_dcu_drm_irq,
  166. .get_vblank_counter = drm_vblank_no_hw_counter,
  167. .enable_vblank = fsl_dcu_drm_enable_vblank,
  168. .disable_vblank = fsl_dcu_drm_disable_vblank,
  169. .gem_free_object_unlocked = drm_gem_cma_free_object,
  170. .gem_vm_ops = &drm_gem_cma_vm_ops,
  171. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  172. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  173. .gem_prime_import = drm_gem_prime_import,
  174. .gem_prime_export = drm_gem_prime_export,
  175. .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
  176. .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
  177. .gem_prime_vmap = drm_gem_cma_prime_vmap,
  178. .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
  179. .gem_prime_mmap = drm_gem_cma_prime_mmap,
  180. .dumb_create = drm_gem_cma_dumb_create,
  181. .dumb_map_offset = drm_gem_cma_dumb_map_offset,
  182. .dumb_destroy = drm_gem_dumb_destroy,
  183. .fops = &fsl_dcu_drm_fops,
  184. .name = "fsl-dcu-drm",
  185. .desc = "Freescale DCU DRM",
  186. .date = "20160425",
  187. .major = 1,
  188. .minor = 1,
  189. };
  190. #ifdef CONFIG_PM_SLEEP
  191. static int fsl_dcu_drm_pm_suspend(struct device *dev)
  192. {
  193. struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev);
  194. if (!fsl_dev)
  195. return 0;
  196. disable_irq(fsl_dev->irq);
  197. drm_kms_helper_poll_disable(fsl_dev->drm);
  198. console_lock();
  199. drm_fbdev_cma_set_suspend(fsl_dev->fbdev, 1);
  200. console_unlock();
  201. fsl_dev->state = drm_atomic_helper_suspend(fsl_dev->drm);
  202. if (IS_ERR(fsl_dev->state)) {
  203. console_lock();
  204. drm_fbdev_cma_set_suspend(fsl_dev->fbdev, 0);
  205. console_unlock();
  206. drm_kms_helper_poll_enable(fsl_dev->drm);
  207. enable_irq(fsl_dev->irq);
  208. return PTR_ERR(fsl_dev->state);
  209. }
  210. clk_disable_unprepare(fsl_dev->pix_clk);
  211. clk_disable_unprepare(fsl_dev->clk);
  212. return 0;
  213. }
  214. static int fsl_dcu_drm_pm_resume(struct device *dev)
  215. {
  216. struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev);
  217. int ret;
  218. if (!fsl_dev)
  219. return 0;
  220. ret = clk_prepare_enable(fsl_dev->clk);
  221. if (ret < 0) {
  222. dev_err(dev, "failed to enable dcu clk\n");
  223. return ret;
  224. }
  225. if (fsl_dev->tcon)
  226. fsl_tcon_bypass_enable(fsl_dev->tcon);
  227. fsl_dcu_drm_init_planes(fsl_dev->drm);
  228. drm_atomic_helper_resume(fsl_dev->drm, fsl_dev->state);
  229. console_lock();
  230. drm_fbdev_cma_set_suspend(fsl_dev->fbdev, 0);
  231. console_unlock();
  232. drm_kms_helper_poll_enable(fsl_dev->drm);
  233. enable_irq(fsl_dev->irq);
  234. return 0;
  235. }
  236. #endif
  237. static const struct dev_pm_ops fsl_dcu_drm_pm_ops = {
  238. SET_SYSTEM_SLEEP_PM_OPS(fsl_dcu_drm_pm_suspend, fsl_dcu_drm_pm_resume)
  239. };
  240. static const struct fsl_dcu_soc_data fsl_dcu_ls1021a_data = {
  241. .name = "ls1021a",
  242. .total_layer = 16,
  243. .max_layer = 4,
  244. .layer_regs = LS1021A_LAYER_REG_NUM,
  245. };
  246. static const struct fsl_dcu_soc_data fsl_dcu_vf610_data = {
  247. .name = "vf610",
  248. .total_layer = 64,
  249. .max_layer = 6,
  250. .layer_regs = VF610_LAYER_REG_NUM,
  251. };
  252. static const struct of_device_id fsl_dcu_of_match[] = {
  253. {
  254. .compatible = "fsl,ls1021a-dcu",
  255. .data = &fsl_dcu_ls1021a_data,
  256. }, {
  257. .compatible = "fsl,vf610-dcu",
  258. .data = &fsl_dcu_vf610_data,
  259. }, {
  260. },
  261. };
  262. MODULE_DEVICE_TABLE(of, fsl_dcu_of_match);
  263. static int fsl_dcu_drm_probe(struct platform_device *pdev)
  264. {
  265. struct fsl_dcu_drm_device *fsl_dev;
  266. struct drm_device *drm;
  267. struct device *dev = &pdev->dev;
  268. struct resource *res;
  269. void __iomem *base;
  270. struct drm_driver *driver = &fsl_dcu_drm_driver;
  271. struct clk *pix_clk_in;
  272. char pix_clk_name[32];
  273. const char *pix_clk_in_name;
  274. const struct of_device_id *id;
  275. int ret;
  276. u8 div_ratio_shift = 0;
  277. fsl_dev = devm_kzalloc(dev, sizeof(*fsl_dev), GFP_KERNEL);
  278. if (!fsl_dev)
  279. return -ENOMEM;
  280. id = of_match_node(fsl_dcu_of_match, pdev->dev.of_node);
  281. if (!id)
  282. return -ENODEV;
  283. fsl_dev->soc = id->data;
  284. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  285. base = devm_ioremap_resource(dev, res);
  286. if (IS_ERR(base)) {
  287. ret = PTR_ERR(base);
  288. return ret;
  289. }
  290. fsl_dev->irq = platform_get_irq(pdev, 0);
  291. if (fsl_dev->irq < 0) {
  292. dev_err(dev, "failed to get irq\n");
  293. return fsl_dev->irq;
  294. }
  295. fsl_dev->regmap = devm_regmap_init_mmio(dev, base,
  296. &fsl_dcu_regmap_config);
  297. if (IS_ERR(fsl_dev->regmap)) {
  298. dev_err(dev, "regmap init failed\n");
  299. return PTR_ERR(fsl_dev->regmap);
  300. }
  301. fsl_dev->clk = devm_clk_get(dev, "dcu");
  302. if (IS_ERR(fsl_dev->clk)) {
  303. dev_err(dev, "failed to get dcu clock\n");
  304. return PTR_ERR(fsl_dev->clk);
  305. }
  306. ret = clk_prepare_enable(fsl_dev->clk);
  307. if (ret < 0) {
  308. dev_err(dev, "failed to enable dcu clk\n");
  309. return ret;
  310. }
  311. pix_clk_in = devm_clk_get(dev, "pix");
  312. if (IS_ERR(pix_clk_in)) {
  313. /* legancy binding, use dcu clock as pixel clock input */
  314. pix_clk_in = fsl_dev->clk;
  315. }
  316. if (of_property_read_bool(dev->of_node, "big-endian"))
  317. div_ratio_shift = 24;
  318. pix_clk_in_name = __clk_get_name(pix_clk_in);
  319. snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix", pix_clk_in_name);
  320. fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
  321. pix_clk_in_name, 0, base + DCU_DIV_RATIO,
  322. div_ratio_shift, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
  323. if (IS_ERR(fsl_dev->pix_clk)) {
  324. dev_err(dev, "failed to register pix clk\n");
  325. ret = PTR_ERR(fsl_dev->pix_clk);
  326. goto disable_clk;
  327. }
  328. fsl_dev->tcon = fsl_tcon_init(dev);
  329. drm = drm_dev_alloc(driver, dev);
  330. if (IS_ERR(drm)) {
  331. ret = PTR_ERR(drm);
  332. goto unregister_pix_clk;
  333. }
  334. fsl_dev->dev = dev;
  335. fsl_dev->drm = drm;
  336. fsl_dev->np = dev->of_node;
  337. drm->dev_private = fsl_dev;
  338. dev_set_drvdata(dev, fsl_dev);
  339. ret = drm_dev_register(drm, 0);
  340. if (ret < 0)
  341. goto unref;
  342. return 0;
  343. unref:
  344. drm_dev_unref(drm);
  345. unregister_pix_clk:
  346. clk_unregister(fsl_dev->pix_clk);
  347. disable_clk:
  348. clk_disable_unprepare(fsl_dev->clk);
  349. return ret;
  350. }
  351. static int fsl_dcu_drm_remove(struct platform_device *pdev)
  352. {
  353. struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);
  354. drm_dev_unregister(fsl_dev->drm);
  355. drm_dev_unref(fsl_dev->drm);
  356. clk_disable_unprepare(fsl_dev->clk);
  357. clk_unregister(fsl_dev->pix_clk);
  358. return 0;
  359. }
  360. static struct platform_driver fsl_dcu_drm_platform_driver = {
  361. .probe = fsl_dcu_drm_probe,
  362. .remove = fsl_dcu_drm_remove,
  363. .driver = {
  364. .name = "fsl-dcu",
  365. .pm = &fsl_dcu_drm_pm_ops,
  366. .of_match_table = fsl_dcu_of_match,
  367. },
  368. };
  369. module_platform_driver(fsl_dcu_drm_platform_driver);
  370. MODULE_DESCRIPTION("Freescale DCU DRM Driver");
  371. MODULE_LICENSE("GPL");