armada_overlay.c 15 KB

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  1. /*
  2. * Copyright (C) 2012 Russell King
  3. * Rewritten from the dovefb driver, and Armada510 manuals.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. */
  9. #include <drm/drmP.h>
  10. #include <drm/drm_plane_helper.h>
  11. #include "armada_crtc.h"
  12. #include "armada_drm.h"
  13. #include "armada_fb.h"
  14. #include "armada_gem.h"
  15. #include "armada_hw.h"
  16. #include <drm/armada_drm.h>
  17. #include "armada_ioctlP.h"
  18. #include "armada_trace.h"
  19. struct armada_ovl_plane_properties {
  20. uint32_t colorkey_yr;
  21. uint32_t colorkey_ug;
  22. uint32_t colorkey_vb;
  23. #define K2R(val) (((val) >> 0) & 0xff)
  24. #define K2G(val) (((val) >> 8) & 0xff)
  25. #define K2B(val) (((val) >> 16) & 0xff)
  26. int16_t brightness;
  27. uint16_t contrast;
  28. uint16_t saturation;
  29. uint32_t colorkey_mode;
  30. };
  31. struct armada_ovl_plane {
  32. struct armada_plane base;
  33. struct drm_framebuffer *old_fb;
  34. struct {
  35. struct armada_plane_work work;
  36. struct armada_regs regs[13];
  37. } vbl;
  38. struct armada_ovl_plane_properties prop;
  39. };
  40. #define drm_to_armada_ovl_plane(p) \
  41. container_of(p, struct armada_ovl_plane, base.base)
  42. static void
  43. armada_ovl_update_attr(struct armada_ovl_plane_properties *prop,
  44. struct armada_crtc *dcrtc)
  45. {
  46. writel_relaxed(prop->colorkey_yr, dcrtc->base + LCD_SPU_COLORKEY_Y);
  47. writel_relaxed(prop->colorkey_ug, dcrtc->base + LCD_SPU_COLORKEY_U);
  48. writel_relaxed(prop->colorkey_vb, dcrtc->base + LCD_SPU_COLORKEY_V);
  49. writel_relaxed(prop->brightness << 16 | prop->contrast,
  50. dcrtc->base + LCD_SPU_CONTRAST);
  51. /* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */
  52. writel_relaxed(prop->saturation << 16,
  53. dcrtc->base + LCD_SPU_SATURATION);
  54. writel_relaxed(0x00002000, dcrtc->base + LCD_SPU_CBSH_HUE);
  55. spin_lock_irq(&dcrtc->irq_lock);
  56. armada_updatel(prop->colorkey_mode | CFG_ALPHAM_GRA,
  57. CFG_CKMODE_MASK | CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
  58. dcrtc->base + LCD_SPU_DMA_CTRL1);
  59. armada_updatel(ADV_GRACOLORKEY, 0, dcrtc->base + LCD_SPU_ADV_REG);
  60. spin_unlock_irq(&dcrtc->irq_lock);
  61. }
  62. static void armada_ovl_retire_fb(struct armada_ovl_plane *dplane,
  63. struct drm_framebuffer *fb)
  64. {
  65. struct drm_framebuffer *old_fb;
  66. old_fb = xchg(&dplane->old_fb, fb);
  67. if (old_fb)
  68. armada_drm_queue_unref_work(dplane->base.base.dev, old_fb);
  69. }
  70. /* === Plane support === */
  71. static void armada_ovl_plane_work(struct armada_crtc *dcrtc,
  72. struct armada_plane *plane, struct armada_plane_work *work)
  73. {
  74. struct armada_ovl_plane *dplane = container_of(plane, struct armada_ovl_plane, base);
  75. trace_armada_ovl_plane_work(&dcrtc->crtc, &plane->base);
  76. armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs);
  77. armada_ovl_retire_fb(dplane, NULL);
  78. }
  79. static int
  80. armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
  81. struct drm_framebuffer *fb,
  82. int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
  83. uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h)
  84. {
  85. struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
  86. struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
  87. struct drm_rect src = {
  88. .x1 = src_x,
  89. .y1 = src_y,
  90. .x2 = src_x + src_w,
  91. .y2 = src_y + src_h,
  92. };
  93. struct drm_rect dest = {
  94. .x1 = crtc_x,
  95. .y1 = crtc_y,
  96. .x2 = crtc_x + crtc_w,
  97. .y2 = crtc_y + crtc_h,
  98. };
  99. const struct drm_rect clip = {
  100. .x2 = crtc->mode.hdisplay,
  101. .y2 = crtc->mode.vdisplay,
  102. };
  103. uint32_t val, ctrl0;
  104. unsigned idx = 0;
  105. bool visible;
  106. int ret;
  107. trace_armada_ovl_plane_update(plane, crtc, fb,
  108. crtc_x, crtc_y, crtc_w, crtc_h,
  109. src_x, src_y, src_w, src_h);
  110. ret = drm_plane_helper_check_update(plane, crtc, fb, &src, &dest, &clip,
  111. DRM_ROTATE_0,
  112. 0, INT_MAX, true, false, &visible);
  113. if (ret)
  114. return ret;
  115. ctrl0 = CFG_DMA_FMT(drm_fb_to_armada_fb(fb)->fmt) |
  116. CFG_DMA_MOD(drm_fb_to_armada_fb(fb)->mod) |
  117. CFG_CBSH_ENA | CFG_DMA_HSMOOTH | CFG_DMA_ENA;
  118. /* Does the position/size result in nothing to display? */
  119. if (!visible)
  120. ctrl0 &= ~CFG_DMA_ENA;
  121. if (!dcrtc->plane) {
  122. dcrtc->plane = plane;
  123. armada_ovl_update_attr(&dplane->prop, dcrtc);
  124. }
  125. /* FIXME: overlay on an interlaced display */
  126. /* Just updating the position/size? */
  127. if (plane->fb == fb && dplane->base.state.ctrl0 == ctrl0) {
  128. val = (drm_rect_height(&src) & 0xffff0000) |
  129. drm_rect_width(&src) >> 16;
  130. dplane->base.state.src_hw = val;
  131. writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_HPXL_VLN);
  132. val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest);
  133. dplane->base.state.dst_hw = val;
  134. writel_relaxed(val, dcrtc->base + LCD_SPU_DZM_HPXL_VLN);
  135. val = dest.y1 << 16 | dest.x1;
  136. dplane->base.state.dst_yx = val;
  137. writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_OVSA_HPXL_VLN);
  138. return 0;
  139. } else if (~dplane->base.state.ctrl0 & ctrl0 & CFG_DMA_ENA) {
  140. /* Power up the Y/U/V FIFOs on ENA 0->1 transitions */
  141. armada_updatel(0, CFG_PDWN16x66 | CFG_PDWN32x66,
  142. dcrtc->base + LCD_SPU_SRAM_PARA1);
  143. }
  144. if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0)
  145. armada_drm_plane_work_cancel(dcrtc, &dplane->base);
  146. if (plane->fb != fb) {
  147. u32 addrs[3], pixel_format;
  148. int num_planes, hsub;
  149. /*
  150. * Take a reference on the new framebuffer - we want to
  151. * hold on to it while the hardware is displaying it.
  152. */
  153. drm_framebuffer_reference(fb);
  154. if (plane->fb)
  155. armada_ovl_retire_fb(dplane, plane->fb);
  156. src_y = src.y1 >> 16;
  157. src_x = src.x1 >> 16;
  158. armada_drm_plane_calc_addrs(addrs, fb, src_x, src_y);
  159. pixel_format = fb->format->format;
  160. hsub = drm_format_horz_chroma_subsampling(pixel_format);
  161. num_planes = fb->format->num_planes;
  162. /*
  163. * Annoyingly, shifting a YUYV-format image by one pixel
  164. * causes the U/V planes to toggle. Toggle the UV swap.
  165. * (Unfortunately, this causes momentary colour flickering.)
  166. */
  167. if (src_x & (hsub - 1) && num_planes == 1)
  168. ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV);
  169. armada_reg_queue_set(dplane->vbl.regs, idx, addrs[0],
  170. LCD_SPU_DMA_START_ADDR_Y0);
  171. armada_reg_queue_set(dplane->vbl.regs, idx, addrs[1],
  172. LCD_SPU_DMA_START_ADDR_U0);
  173. armada_reg_queue_set(dplane->vbl.regs, idx, addrs[2],
  174. LCD_SPU_DMA_START_ADDR_V0);
  175. armada_reg_queue_set(dplane->vbl.regs, idx, addrs[0],
  176. LCD_SPU_DMA_START_ADDR_Y1);
  177. armada_reg_queue_set(dplane->vbl.regs, idx, addrs[1],
  178. LCD_SPU_DMA_START_ADDR_U1);
  179. armada_reg_queue_set(dplane->vbl.regs, idx, addrs[2],
  180. LCD_SPU_DMA_START_ADDR_V1);
  181. val = fb->pitches[0] << 16 | fb->pitches[0];
  182. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  183. LCD_SPU_DMA_PITCH_YC);
  184. val = fb->pitches[1] << 16 | fb->pitches[2];
  185. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  186. LCD_SPU_DMA_PITCH_UV);
  187. }
  188. val = (drm_rect_height(&src) & 0xffff0000) | drm_rect_width(&src) >> 16;
  189. if (dplane->base.state.src_hw != val) {
  190. dplane->base.state.src_hw = val;
  191. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  192. LCD_SPU_DMA_HPXL_VLN);
  193. }
  194. val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest);
  195. if (dplane->base.state.dst_hw != val) {
  196. dplane->base.state.dst_hw = val;
  197. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  198. LCD_SPU_DZM_HPXL_VLN);
  199. }
  200. val = dest.y1 << 16 | dest.x1;
  201. if (dplane->base.state.dst_yx != val) {
  202. dplane->base.state.dst_yx = val;
  203. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  204. LCD_SPU_DMA_OVSA_HPXL_VLN);
  205. }
  206. if (dplane->base.state.ctrl0 != ctrl0) {
  207. dplane->base.state.ctrl0 = ctrl0;
  208. armada_reg_queue_mod(dplane->vbl.regs, idx, ctrl0,
  209. CFG_CBSH_ENA | CFG_DMAFORMAT | CFG_DMA_FTOGGLE |
  210. CFG_DMA_HSMOOTH | CFG_DMA_TSTMODE |
  211. CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | CFG_SWAPYU |
  212. CFG_YUV2RGB) | CFG_DMA_ENA,
  213. LCD_SPU_DMA_CTRL0);
  214. }
  215. if (idx) {
  216. armada_reg_queue_end(dplane->vbl.regs, idx);
  217. armada_drm_plane_work_queue(dcrtc, &dplane->base,
  218. &dplane->vbl.work);
  219. }
  220. return 0;
  221. }
  222. static int armada_ovl_plane_disable(struct drm_plane *plane)
  223. {
  224. struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
  225. struct drm_framebuffer *fb;
  226. struct armada_crtc *dcrtc;
  227. if (!dplane->base.base.crtc)
  228. return 0;
  229. dcrtc = drm_to_armada_crtc(dplane->base.base.crtc);
  230. armada_drm_plane_work_cancel(dcrtc, &dplane->base);
  231. armada_drm_crtc_plane_disable(dcrtc, plane);
  232. dcrtc->plane = NULL;
  233. dplane->base.state.ctrl0 = 0;
  234. fb = xchg(&dplane->old_fb, NULL);
  235. if (fb)
  236. drm_framebuffer_unreference(fb);
  237. return 0;
  238. }
  239. static void armada_ovl_plane_destroy(struct drm_plane *plane)
  240. {
  241. struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
  242. drm_plane_cleanup(plane);
  243. kfree(dplane);
  244. }
  245. static int armada_ovl_plane_set_property(struct drm_plane *plane,
  246. struct drm_property *property, uint64_t val)
  247. {
  248. struct armada_private *priv = plane->dev->dev_private;
  249. struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
  250. bool update_attr = false;
  251. if (property == priv->colorkey_prop) {
  252. #define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8)
  253. dplane->prop.colorkey_yr = CCC(K2R(val));
  254. dplane->prop.colorkey_ug = CCC(K2G(val));
  255. dplane->prop.colorkey_vb = CCC(K2B(val));
  256. #undef CCC
  257. update_attr = true;
  258. } else if (property == priv->colorkey_min_prop) {
  259. dplane->prop.colorkey_yr &= ~0x00ff0000;
  260. dplane->prop.colorkey_yr |= K2R(val) << 16;
  261. dplane->prop.colorkey_ug &= ~0x00ff0000;
  262. dplane->prop.colorkey_ug |= K2G(val) << 16;
  263. dplane->prop.colorkey_vb &= ~0x00ff0000;
  264. dplane->prop.colorkey_vb |= K2B(val) << 16;
  265. update_attr = true;
  266. } else if (property == priv->colorkey_max_prop) {
  267. dplane->prop.colorkey_yr &= ~0xff000000;
  268. dplane->prop.colorkey_yr |= K2R(val) << 24;
  269. dplane->prop.colorkey_ug &= ~0xff000000;
  270. dplane->prop.colorkey_ug |= K2G(val) << 24;
  271. dplane->prop.colorkey_vb &= ~0xff000000;
  272. dplane->prop.colorkey_vb |= K2B(val) << 24;
  273. update_attr = true;
  274. } else if (property == priv->colorkey_val_prop) {
  275. dplane->prop.colorkey_yr &= ~0x0000ff00;
  276. dplane->prop.colorkey_yr |= K2R(val) << 8;
  277. dplane->prop.colorkey_ug &= ~0x0000ff00;
  278. dplane->prop.colorkey_ug |= K2G(val) << 8;
  279. dplane->prop.colorkey_vb &= ~0x0000ff00;
  280. dplane->prop.colorkey_vb |= K2B(val) << 8;
  281. update_attr = true;
  282. } else if (property == priv->colorkey_alpha_prop) {
  283. dplane->prop.colorkey_yr &= ~0x000000ff;
  284. dplane->prop.colorkey_yr |= K2R(val);
  285. dplane->prop.colorkey_ug &= ~0x000000ff;
  286. dplane->prop.colorkey_ug |= K2G(val);
  287. dplane->prop.colorkey_vb &= ~0x000000ff;
  288. dplane->prop.colorkey_vb |= K2B(val);
  289. update_attr = true;
  290. } else if (property == priv->colorkey_mode_prop) {
  291. dplane->prop.colorkey_mode &= ~CFG_CKMODE_MASK;
  292. dplane->prop.colorkey_mode |= CFG_CKMODE(val);
  293. update_attr = true;
  294. } else if (property == priv->brightness_prop) {
  295. dplane->prop.brightness = val - 256;
  296. update_attr = true;
  297. } else if (property == priv->contrast_prop) {
  298. dplane->prop.contrast = val;
  299. update_attr = true;
  300. } else if (property == priv->saturation_prop) {
  301. dplane->prop.saturation = val;
  302. update_attr = true;
  303. }
  304. if (update_attr && dplane->base.base.crtc)
  305. armada_ovl_update_attr(&dplane->prop,
  306. drm_to_armada_crtc(dplane->base.base.crtc));
  307. return 0;
  308. }
  309. static const struct drm_plane_funcs armada_ovl_plane_funcs = {
  310. .update_plane = armada_ovl_plane_update,
  311. .disable_plane = armada_ovl_plane_disable,
  312. .destroy = armada_ovl_plane_destroy,
  313. .set_property = armada_ovl_plane_set_property,
  314. };
  315. static const uint32_t armada_ovl_formats[] = {
  316. DRM_FORMAT_UYVY,
  317. DRM_FORMAT_YUYV,
  318. DRM_FORMAT_YUV420,
  319. DRM_FORMAT_YVU420,
  320. DRM_FORMAT_YUV422,
  321. DRM_FORMAT_YVU422,
  322. DRM_FORMAT_VYUY,
  323. DRM_FORMAT_YVYU,
  324. DRM_FORMAT_ARGB8888,
  325. DRM_FORMAT_ABGR8888,
  326. DRM_FORMAT_XRGB8888,
  327. DRM_FORMAT_XBGR8888,
  328. DRM_FORMAT_RGB888,
  329. DRM_FORMAT_BGR888,
  330. DRM_FORMAT_ARGB1555,
  331. DRM_FORMAT_ABGR1555,
  332. DRM_FORMAT_RGB565,
  333. DRM_FORMAT_BGR565,
  334. };
  335. static struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = {
  336. { CKMODE_DISABLE, "disabled" },
  337. { CKMODE_Y, "Y component" },
  338. { CKMODE_U, "U component" },
  339. { CKMODE_V, "V component" },
  340. { CKMODE_RGB, "RGB" },
  341. { CKMODE_R, "R component" },
  342. { CKMODE_G, "G component" },
  343. { CKMODE_B, "B component" },
  344. };
  345. static int armada_overlay_create_properties(struct drm_device *dev)
  346. {
  347. struct armada_private *priv = dev->dev_private;
  348. if (priv->colorkey_prop)
  349. return 0;
  350. priv->colorkey_prop = drm_property_create_range(dev, 0,
  351. "colorkey", 0, 0xffffff);
  352. priv->colorkey_min_prop = drm_property_create_range(dev, 0,
  353. "colorkey_min", 0, 0xffffff);
  354. priv->colorkey_max_prop = drm_property_create_range(dev, 0,
  355. "colorkey_max", 0, 0xffffff);
  356. priv->colorkey_val_prop = drm_property_create_range(dev, 0,
  357. "colorkey_val", 0, 0xffffff);
  358. priv->colorkey_alpha_prop = drm_property_create_range(dev, 0,
  359. "colorkey_alpha", 0, 0xffffff);
  360. priv->colorkey_mode_prop = drm_property_create_enum(dev, 0,
  361. "colorkey_mode",
  362. armada_drm_colorkey_enum_list,
  363. ARRAY_SIZE(armada_drm_colorkey_enum_list));
  364. priv->brightness_prop = drm_property_create_range(dev, 0,
  365. "brightness", 0, 256 + 255);
  366. priv->contrast_prop = drm_property_create_range(dev, 0,
  367. "contrast", 0, 0x7fff);
  368. priv->saturation_prop = drm_property_create_range(dev, 0,
  369. "saturation", 0, 0x7fff);
  370. if (!priv->colorkey_prop)
  371. return -ENOMEM;
  372. return 0;
  373. }
  374. int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
  375. {
  376. struct armada_private *priv = dev->dev_private;
  377. struct drm_mode_object *mobj;
  378. struct armada_ovl_plane *dplane;
  379. int ret;
  380. ret = armada_overlay_create_properties(dev);
  381. if (ret)
  382. return ret;
  383. dplane = kzalloc(sizeof(*dplane), GFP_KERNEL);
  384. if (!dplane)
  385. return -ENOMEM;
  386. ret = armada_drm_plane_init(&dplane->base);
  387. if (ret) {
  388. kfree(dplane);
  389. return ret;
  390. }
  391. dplane->vbl.work.fn = armada_ovl_plane_work;
  392. ret = drm_universal_plane_init(dev, &dplane->base.base, crtcs,
  393. &armada_ovl_plane_funcs,
  394. armada_ovl_formats,
  395. ARRAY_SIZE(armada_ovl_formats),
  396. DRM_PLANE_TYPE_OVERLAY, NULL);
  397. if (ret) {
  398. kfree(dplane);
  399. return ret;
  400. }
  401. dplane->prop.colorkey_yr = 0xfefefe00;
  402. dplane->prop.colorkey_ug = 0x01010100;
  403. dplane->prop.colorkey_vb = 0x01010100;
  404. dplane->prop.colorkey_mode = CFG_CKMODE(CKMODE_RGB);
  405. dplane->prop.brightness = 0;
  406. dplane->prop.contrast = 0x4000;
  407. dplane->prop.saturation = 0x4000;
  408. mobj = &dplane->base.base.base;
  409. drm_object_attach_property(mobj, priv->colorkey_prop,
  410. 0x0101fe);
  411. drm_object_attach_property(mobj, priv->colorkey_min_prop,
  412. 0x0101fe);
  413. drm_object_attach_property(mobj, priv->colorkey_max_prop,
  414. 0x0101fe);
  415. drm_object_attach_property(mobj, priv->colorkey_val_prop,
  416. 0x0101fe);
  417. drm_object_attach_property(mobj, priv->colorkey_alpha_prop,
  418. 0x000000);
  419. drm_object_attach_property(mobj, priv->colorkey_mode_prop,
  420. CKMODE_RGB);
  421. drm_object_attach_property(mobj, priv->brightness_prop, 256);
  422. drm_object_attach_property(mobj, priv->contrast_prop,
  423. dplane->prop.contrast);
  424. drm_object_attach_property(mobj, priv->saturation_prop,
  425. dplane->prop.saturation);
  426. return 0;
  427. }