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drivers
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gpu
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amd
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amdgpu
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vi.h

vi.h 4.6 KB
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  1. /*
    2. 

  2.  * Copyright 2014 Advanced Micro Devices, Inc.
    3. 

  3.  *
    4. 

  4.  * Permission is hereby granted, free of charge, to any person obtaining a
    5. 

  5.  * copy of this software and associated documentation files (the "Software"),
    6. 

  6.  * to deal in the Software without restriction, including without limitation
    7. 

  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
    8. 

  8.  * and/or sell copies of the Software, and to permit persons to whom the
    9. 

  9.  * Software is furnished to do so, subject to the following conditions:
    10. 

  10.  *
    11. 

  11.  * The above copyright notice and this permission notice shall be included in
    12. 

  12.  * all copies or substantial portions of the Software.
    13. 

  13.  *
    14. 

  14.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    15. 

  15.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    16. 

  16.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
    17. 

  17.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
    18. 

  18.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
    19. 

  19.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
    20. 

  20.  * OTHER DEALINGS IN THE SOFTWARE.
    21. 

  21.  *
    22. 

  22.  */
    23. 

  23. 

  24. #ifndef __VI_H__
    25. 

  25. #define __VI_H__
    26. 

  26. 

  27. void vi_srbm_select(struct amdgpu_device *adev,
    28. 

  28. 		    u32 me, u32 pipe, u32 queue, u32 vmid);
    29. 

  29. int vi_set_ip_blocks(struct amdgpu_device *adev);
    30. 

  30. 

  31. struct amdgpu_ce_ib_state
    32. 

  32. {
    33. 

  33. 	uint32_t    ce_ib_completion_status;
    34. 

  34. 	uint32_t    ce_constegnine_count;
    35. 

  35. 	uint32_t    ce_ibOffset_ib1;
    36. 

  36. 	uint32_t    ce_ibOffset_ib2;
    37. 

  37. }; /* Total of 4 DWORD */
    38. 

  38. 

  39. struct amdgpu_de_ib_state
    40. 

  40. {
    41. 

  41. 	uint32_t    ib_completion_status;
    42. 

  42. 	uint32_t    de_constEngine_count;
    43. 

  43. 	uint32_t    ib_offset_ib1;
    44. 

  44. 	uint32_t    ib_offset_ib2;
    45. 

  45. 	uint32_t    preamble_begin_ib1;
    46. 

  46. 	uint32_t    preamble_begin_ib2;
    47. 

  47. 	uint32_t    preamble_end_ib1;
    48. 

  48. 	uint32_t    preamble_end_ib2;
    49. 

  49. 	uint32_t    draw_indirect_baseLo;
    50. 

  50. 	uint32_t    draw_indirect_baseHi;
    51. 

  51. 	uint32_t    disp_indirect_baseLo;
    52. 

  52. 	uint32_t    disp_indirect_baseHi;
    53. 

  53. 	uint32_t    gds_backup_addrlo;
    54. 

  54. 	uint32_t    gds_backup_addrhi;
    55. 

  55. 	uint32_t    index_base_addrlo;
    56. 

  56. 	uint32_t    index_base_addrhi;
    57. 

  57. 	uint32_t    sample_cntl;
    58. 

  58. }; /* Total of 17 DWORD */
    59. 

  59. 

  60. struct amdgpu_ce_ib_state_chained_ib
    61. 

  61. {
    62. 

  62. 	/* section of non chained ib part */
    63. 

  63. 	uint32_t    ce_ib_completion_status;
    64. 

  64. 	uint32_t    ce_constegnine_count;
    65. 

  65. 	uint32_t    ce_ibOffset_ib1;
    66. 

  66. 	uint32_t    ce_ibOffset_ib2;
    67. 

  67. 

  68. 	/* section of chained ib */
    69. 

  69. 	uint32_t    ce_chainib_addrlo_ib1;
    70. 

  70. 	uint32_t    ce_chainib_addrlo_ib2;
    71. 

  71. 	uint32_t    ce_chainib_addrhi_ib1;
    72. 

  72. 	uint32_t    ce_chainib_addrhi_ib2;
    73. 

  73. 	uint32_t    ce_chainib_size_ib1;
    74. 

  74. 	uint32_t    ce_chainib_size_ib2;
    75. 

  75. }; /* total 10 DWORD */
    76. 

  76. 

  77. struct amdgpu_de_ib_state_chained_ib
    78. 

  78. {
    79. 

  79. 	/* section of non chained ib part */
    80. 

  80. 	uint32_t    ib_completion_status;
    81. 

  81. 	uint32_t    de_constEngine_count;
    82. 

  82. 	uint32_t    ib_offset_ib1;
    83. 

  83. 	uint32_t    ib_offset_ib2;
    84. 

  84. 

  85. 	/* section of chained ib */
    86. 

  86. 	uint32_t    chain_ib_addrlo_ib1;
    87. 

  87. 	uint32_t    chain_ib_addrlo_ib2;
    88. 

  88. 	uint32_t    chain_ib_addrhi_ib1;
    89. 

  89. 	uint32_t    chain_ib_addrhi_ib2;
    90. 

  90. 	uint32_t    chain_ib_size_ib1;
    91. 

  91. 	uint32_t    chain_ib_size_ib2;
    92. 

  92. 

  93. 	/* section of non chained ib part */
    94. 

  94. 	uint32_t    preamble_begin_ib1;
    95. 

  95. 	uint32_t    preamble_begin_ib2;
    96. 

  96. 	uint32_t    preamble_end_ib1;
    97. 

  97. 	uint32_t    preamble_end_ib2;
    98. 

  98. 

  99. 	/* section of chained ib */
    100. 

  100. 	uint32_t    chain_ib_pream_addrlo_ib1;
    101. 

  101. 	uint32_t    chain_ib_pream_addrlo_ib2;
    102. 

  102. 	uint32_t    chain_ib_pream_addrhi_ib1;
    103. 

  103. 	uint32_t    chain_ib_pream_addrhi_ib2;
    104. 

  104. 

  105. 	/* section of non chained ib part */
    106. 

  106. 	uint32_t    draw_indirect_baseLo;
    107. 

  107. 	uint32_t    draw_indirect_baseHi;
    108. 

  108. 	uint32_t    disp_indirect_baseLo;
    109. 

  109. 	uint32_t    disp_indirect_baseHi;
    110. 

  110. 	uint32_t    gds_backup_addrlo;
    111. 

  111. 	uint32_t    gds_backup_addrhi;
    112. 

  112. 	uint32_t    index_base_addrlo;
    113. 

  113. 	uint32_t    index_base_addrhi;
    114. 

  114. 	uint32_t    sample_cntl;
    115. 

  115. }; /* Total of 27 DWORD */
    116. 

  116. 

  117. struct amdgpu_gfx_meta_data
    118. 

  118. {
    119. 

  119. 	/* 4 DWORD, address must be 4KB aligned */
    120. 

  120. 	struct amdgpu_ce_ib_state    ce_payload;
    121. 

  121. 	uint32_t                     reserved1[60];
    122. 

  122. 	/* 17 DWORD, address must be 64B aligned */
    123. 

  123. 	struct amdgpu_de_ib_state    de_payload;
    124. 

  124. 	/* PFP IB base address which get pre-empted */
    125. 

  125. 	uint32_t                     DeIbBaseAddrLo;
    126. 

  126. 	uint32_t                     DeIbBaseAddrHi;
    127. 

  127. 	uint32_t                     reserved2[941];
    128. 

  128. }; /* Total of 4K Bytes */
    129. 

  129. 

  130. struct amdgpu_gfx_meta_data_chained_ib
    131. 

  131. {
    132. 

  132. 	/* 10 DWORD, address must be 4KB aligned */
    133. 

  133. 	struct amdgpu_ce_ib_state_chained_ib   ce_payload;
    134. 

  134. 	uint32_t                               reserved1[54];
    135. 

  135. 	/* 27 DWORD, address must be 64B aligned */
    136. 

  136. 	struct amdgpu_de_ib_state_chained_ib   de_payload;
    137. 

  137. 	/* PFP IB base address which get pre-empted */
    138. 

  138. 	uint32_t                               DeIbBaseAddrLo;
    139. 

  139. 	uint32_t                               DeIbBaseAddrHi;
    140. 

  140. 	uint32_t                               reserved2[931];
    141. 

  141. }; /* Total of 4K Bytes */
    142. 

  142. 

  143. #endif
    144.