caamalg.c 95 KB

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  1. /*
  2. * caam - Freescale FSL CAAM support for crypto API
  3. *
  4. * Copyright 2008-2011 Freescale Semiconductor, Inc.
  5. * Copyright 2016 NXP
  6. *
  7. * Based on talitos crypto API driver.
  8. *
  9. * relationship of job descriptors to shared descriptors (SteveC Dec 10 2008):
  10. *
  11. * --------------- ---------------
  12. * | JobDesc #1 |-------------------->| ShareDesc |
  13. * | *(packet 1) | | (PDB) |
  14. * --------------- |------------->| (hashKey) |
  15. * . | | (cipherKey) |
  16. * . | |-------->| (operation) |
  17. * --------------- | | ---------------
  18. * | JobDesc #2 |------| |
  19. * | *(packet 2) | |
  20. * --------------- |
  21. * . |
  22. * . |
  23. * --------------- |
  24. * | JobDesc #3 |------------
  25. * | *(packet 3) |
  26. * ---------------
  27. *
  28. * The SharedDesc never changes for a connection unless rekeyed, but
  29. * each packet will likely be in a different place. So all we need
  30. * to know to process the packet is where the input is, where the
  31. * output goes, and what context we want to process with. Context is
  32. * in the SharedDesc, packet references in the JobDesc.
  33. *
  34. * So, a job desc looks like:
  35. *
  36. * ---------------------
  37. * | Header |
  38. * | ShareDesc Pointer |
  39. * | SEQ_OUT_PTR |
  40. * | (output buffer) |
  41. * | (output length) |
  42. * | SEQ_IN_PTR |
  43. * | (input buffer) |
  44. * | (input length) |
  45. * ---------------------
  46. */
  47. #include "compat.h"
  48. #include "regs.h"
  49. #include "intern.h"
  50. #include "desc_constr.h"
  51. #include "jr.h"
  52. #include "error.h"
  53. #include "sg_sw_sec4.h"
  54. #include "key_gen.h"
  55. #include "caamalg_desc.h"
  56. /*
  57. * crypto alg
  58. */
  59. #define CAAM_CRA_PRIORITY 3000
  60. /* max key is sum of AES_MAX_KEY_SIZE, max split key size */
  61. #define CAAM_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + \
  62. CTR_RFC3686_NONCE_SIZE + \
  63. SHA512_DIGEST_SIZE * 2)
  64. #define AEAD_DESC_JOB_IO_LEN (DESC_JOB_IO_LEN + CAAM_CMD_SZ * 2)
  65. #define GCM_DESC_JOB_IO_LEN (AEAD_DESC_JOB_IO_LEN + \
  66. CAAM_CMD_SZ * 4)
  67. #define AUTHENC_DESC_JOB_IO_LEN (AEAD_DESC_JOB_IO_LEN + \
  68. CAAM_CMD_SZ * 5)
  69. #define DESC_MAX_USED_BYTES (CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN)
  70. #define DESC_MAX_USED_LEN (DESC_MAX_USED_BYTES / CAAM_CMD_SZ)
  71. #ifdef DEBUG
  72. /* for print_hex_dumps with line references */
  73. #define debug(format, arg...) printk(format, arg)
  74. #else
  75. #define debug(format, arg...)
  76. #endif
  77. #ifdef DEBUG
  78. #include <linux/highmem.h>
  79. static void dbg_dump_sg(const char *level, const char *prefix_str,
  80. int prefix_type, int rowsize, int groupsize,
  81. struct scatterlist *sg, size_t tlen, bool ascii)
  82. {
  83. struct scatterlist *it;
  84. void *it_page;
  85. size_t len;
  86. void *buf;
  87. for (it = sg; it != NULL && tlen > 0 ; it = sg_next(sg)) {
  88. /*
  89. * make sure the scatterlist's page
  90. * has a valid virtual memory mapping
  91. */
  92. it_page = kmap_atomic(sg_page(it));
  93. if (unlikely(!it_page)) {
  94. printk(KERN_ERR "dbg_dump_sg: kmap failed\n");
  95. return;
  96. }
  97. buf = it_page + it->offset;
  98. len = min_t(size_t, tlen, it->length);
  99. print_hex_dump(level, prefix_str, prefix_type, rowsize,
  100. groupsize, buf, len, ascii);
  101. tlen -= len;
  102. kunmap_atomic(it_page);
  103. }
  104. }
  105. #endif
  106. static struct list_head alg_list;
  107. struct caam_alg_entry {
  108. int class1_alg_type;
  109. int class2_alg_type;
  110. bool rfc3686;
  111. bool geniv;
  112. };
  113. struct caam_aead_alg {
  114. struct aead_alg aead;
  115. struct caam_alg_entry caam;
  116. bool registered;
  117. };
  118. /*
  119. * per-session context
  120. */
  121. struct caam_ctx {
  122. struct device *jrdev;
  123. u32 sh_desc_enc[DESC_MAX_USED_LEN];
  124. u32 sh_desc_dec[DESC_MAX_USED_LEN];
  125. u32 sh_desc_givenc[DESC_MAX_USED_LEN];
  126. dma_addr_t sh_desc_enc_dma;
  127. dma_addr_t sh_desc_dec_dma;
  128. dma_addr_t sh_desc_givenc_dma;
  129. u8 key[CAAM_MAX_KEY_SIZE];
  130. dma_addr_t key_dma;
  131. struct alginfo adata;
  132. struct alginfo cdata;
  133. unsigned int authsize;
  134. };
  135. static int aead_null_set_sh_desc(struct crypto_aead *aead)
  136. {
  137. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  138. struct device *jrdev = ctx->jrdev;
  139. u32 *desc;
  140. int rem_bytes = CAAM_DESC_BYTES_MAX - AEAD_DESC_JOB_IO_LEN -
  141. ctx->adata.keylen_pad;
  142. /*
  143. * Job Descriptor and Shared Descriptors
  144. * must all fit into the 64-word Descriptor h/w Buffer
  145. */
  146. if (rem_bytes >= DESC_AEAD_NULL_ENC_LEN) {
  147. ctx->adata.key_inline = true;
  148. ctx->adata.key_virt = ctx->key;
  149. } else {
  150. ctx->adata.key_inline = false;
  151. ctx->adata.key_dma = ctx->key_dma;
  152. }
  153. /* aead_encrypt shared descriptor */
  154. desc = ctx->sh_desc_enc;
  155. cnstr_shdsc_aead_null_encap(desc, &ctx->adata, ctx->authsize);
  156. ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
  157. desc_bytes(desc),
  158. DMA_TO_DEVICE);
  159. if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
  160. dev_err(jrdev, "unable to map shared descriptor\n");
  161. return -ENOMEM;
  162. }
  163. /*
  164. * Job Descriptor and Shared Descriptors
  165. * must all fit into the 64-word Descriptor h/w Buffer
  166. */
  167. if (rem_bytes >= DESC_AEAD_NULL_DEC_LEN) {
  168. ctx->adata.key_inline = true;
  169. ctx->adata.key_virt = ctx->key;
  170. } else {
  171. ctx->adata.key_inline = false;
  172. ctx->adata.key_dma = ctx->key_dma;
  173. }
  174. /* aead_decrypt shared descriptor */
  175. desc = ctx->sh_desc_dec;
  176. cnstr_shdsc_aead_null_decap(desc, &ctx->adata, ctx->authsize);
  177. ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
  178. desc_bytes(desc),
  179. DMA_TO_DEVICE);
  180. if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
  181. dev_err(jrdev, "unable to map shared descriptor\n");
  182. return -ENOMEM;
  183. }
  184. return 0;
  185. }
  186. static int aead_set_sh_desc(struct crypto_aead *aead)
  187. {
  188. struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead),
  189. struct caam_aead_alg, aead);
  190. unsigned int ivsize = crypto_aead_ivsize(aead);
  191. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  192. struct device *jrdev = ctx->jrdev;
  193. u32 ctx1_iv_off = 0;
  194. u32 *desc, *nonce = NULL;
  195. u32 inl_mask;
  196. unsigned int data_len[2];
  197. const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
  198. OP_ALG_AAI_CTR_MOD128);
  199. const bool is_rfc3686 = alg->caam.rfc3686;
  200. if (!ctx->authsize)
  201. return 0;
  202. /* NULL encryption / decryption */
  203. if (!ctx->cdata.keylen)
  204. return aead_null_set_sh_desc(aead);
  205. /*
  206. * AES-CTR needs to load IV in CONTEXT1 reg
  207. * at an offset of 128bits (16bytes)
  208. * CONTEXT1[255:128] = IV
  209. */
  210. if (ctr_mode)
  211. ctx1_iv_off = 16;
  212. /*
  213. * RFC3686 specific:
  214. * CONTEXT1[255:128] = {NONCE, IV, COUNTER}
  215. */
  216. if (is_rfc3686) {
  217. ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE;
  218. nonce = (u32 *)((void *)ctx->key + ctx->adata.keylen_pad +
  219. ctx->cdata.keylen - CTR_RFC3686_NONCE_SIZE);
  220. }
  221. data_len[0] = ctx->adata.keylen_pad;
  222. data_len[1] = ctx->cdata.keylen;
  223. if (alg->caam.geniv)
  224. goto skip_enc;
  225. /*
  226. * Job Descriptor and Shared Descriptors
  227. * must all fit into the 64-word Descriptor h/w Buffer
  228. */
  229. if (desc_inline_query(DESC_AEAD_ENC_LEN +
  230. (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
  231. AUTHENC_DESC_JOB_IO_LEN, data_len, &inl_mask,
  232. ARRAY_SIZE(data_len)) < 0)
  233. return -EINVAL;
  234. if (inl_mask & 1)
  235. ctx->adata.key_virt = ctx->key;
  236. else
  237. ctx->adata.key_dma = ctx->key_dma;
  238. if (inl_mask & 2)
  239. ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
  240. else
  241. ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
  242. ctx->adata.key_inline = !!(inl_mask & 1);
  243. ctx->cdata.key_inline = !!(inl_mask & 2);
  244. /* aead_encrypt shared descriptor */
  245. desc = ctx->sh_desc_enc;
  246. cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata, ctx->authsize,
  247. is_rfc3686, nonce, ctx1_iv_off);
  248. ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
  249. desc_bytes(desc),
  250. DMA_TO_DEVICE);
  251. if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
  252. dev_err(jrdev, "unable to map shared descriptor\n");
  253. return -ENOMEM;
  254. }
  255. skip_enc:
  256. /*
  257. * Job Descriptor and Shared Descriptors
  258. * must all fit into the 64-word Descriptor h/w Buffer
  259. */
  260. if (desc_inline_query(DESC_AEAD_DEC_LEN +
  261. (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
  262. AUTHENC_DESC_JOB_IO_LEN, data_len, &inl_mask,
  263. ARRAY_SIZE(data_len)) < 0)
  264. return -EINVAL;
  265. if (inl_mask & 1)
  266. ctx->adata.key_virt = ctx->key;
  267. else
  268. ctx->adata.key_dma = ctx->key_dma;
  269. if (inl_mask & 2)
  270. ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
  271. else
  272. ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
  273. ctx->adata.key_inline = !!(inl_mask & 1);
  274. ctx->cdata.key_inline = !!(inl_mask & 2);
  275. /* aead_decrypt shared descriptor */
  276. desc = ctx->sh_desc_dec;
  277. cnstr_shdsc_aead_decap(desc, &ctx->cdata, &ctx->adata, ivsize,
  278. ctx->authsize, alg->caam.geniv, is_rfc3686,
  279. nonce, ctx1_iv_off);
  280. ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
  281. desc_bytes(desc),
  282. DMA_TO_DEVICE);
  283. if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
  284. dev_err(jrdev, "unable to map shared descriptor\n");
  285. return -ENOMEM;
  286. }
  287. if (!alg->caam.geniv)
  288. goto skip_givenc;
  289. /*
  290. * Job Descriptor and Shared Descriptors
  291. * must all fit into the 64-word Descriptor h/w Buffer
  292. */
  293. if (desc_inline_query(DESC_AEAD_GIVENC_LEN +
  294. (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
  295. AUTHENC_DESC_JOB_IO_LEN, data_len, &inl_mask,
  296. ARRAY_SIZE(data_len)) < 0)
  297. return -EINVAL;
  298. if (inl_mask & 1)
  299. ctx->adata.key_virt = ctx->key;
  300. else
  301. ctx->adata.key_dma = ctx->key_dma;
  302. if (inl_mask & 2)
  303. ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
  304. else
  305. ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
  306. ctx->adata.key_inline = !!(inl_mask & 1);
  307. ctx->cdata.key_inline = !!(inl_mask & 2);
  308. /* aead_givencrypt shared descriptor */
  309. desc = ctx->sh_desc_enc;
  310. cnstr_shdsc_aead_givencap(desc, &ctx->cdata, &ctx->adata, ivsize,
  311. ctx->authsize, is_rfc3686, nonce,
  312. ctx1_iv_off);
  313. ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
  314. desc_bytes(desc),
  315. DMA_TO_DEVICE);
  316. if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
  317. dev_err(jrdev, "unable to map shared descriptor\n");
  318. return -ENOMEM;
  319. }
  320. skip_givenc:
  321. return 0;
  322. }
  323. static int aead_setauthsize(struct crypto_aead *authenc,
  324. unsigned int authsize)
  325. {
  326. struct caam_ctx *ctx = crypto_aead_ctx(authenc);
  327. ctx->authsize = authsize;
  328. aead_set_sh_desc(authenc);
  329. return 0;
  330. }
  331. static int gcm_set_sh_desc(struct crypto_aead *aead)
  332. {
  333. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  334. struct device *jrdev = ctx->jrdev;
  335. u32 *desc;
  336. int rem_bytes = CAAM_DESC_BYTES_MAX - GCM_DESC_JOB_IO_LEN -
  337. ctx->cdata.keylen;
  338. if (!ctx->cdata.keylen || !ctx->authsize)
  339. return 0;
  340. /*
  341. * AES GCM encrypt shared descriptor
  342. * Job Descriptor and Shared Descriptor
  343. * must fit into the 64-word Descriptor h/w Buffer
  344. */
  345. if (rem_bytes >= DESC_GCM_ENC_LEN) {
  346. ctx->cdata.key_inline = true;
  347. ctx->cdata.key_virt = ctx->key;
  348. } else {
  349. ctx->cdata.key_inline = false;
  350. ctx->cdata.key_dma = ctx->key_dma;
  351. }
  352. desc = ctx->sh_desc_enc;
  353. cnstr_shdsc_gcm_encap(desc, &ctx->cdata, ctx->authsize);
  354. ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
  355. desc_bytes(desc),
  356. DMA_TO_DEVICE);
  357. if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
  358. dev_err(jrdev, "unable to map shared descriptor\n");
  359. return -ENOMEM;
  360. }
  361. /*
  362. * Job Descriptor and Shared Descriptors
  363. * must all fit into the 64-word Descriptor h/w Buffer
  364. */
  365. if (rem_bytes >= DESC_GCM_DEC_LEN) {
  366. ctx->cdata.key_inline = true;
  367. ctx->cdata.key_virt = ctx->key;
  368. } else {
  369. ctx->cdata.key_inline = false;
  370. ctx->cdata.key_dma = ctx->key_dma;
  371. }
  372. desc = ctx->sh_desc_dec;
  373. cnstr_shdsc_gcm_decap(desc, &ctx->cdata, ctx->authsize);
  374. ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
  375. desc_bytes(desc),
  376. DMA_TO_DEVICE);
  377. if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
  378. dev_err(jrdev, "unable to map shared descriptor\n");
  379. return -ENOMEM;
  380. }
  381. return 0;
  382. }
  383. static int gcm_setauthsize(struct crypto_aead *authenc, unsigned int authsize)
  384. {
  385. struct caam_ctx *ctx = crypto_aead_ctx(authenc);
  386. ctx->authsize = authsize;
  387. gcm_set_sh_desc(authenc);
  388. return 0;
  389. }
  390. static int rfc4106_set_sh_desc(struct crypto_aead *aead)
  391. {
  392. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  393. struct device *jrdev = ctx->jrdev;
  394. u32 *desc;
  395. int rem_bytes = CAAM_DESC_BYTES_MAX - GCM_DESC_JOB_IO_LEN -
  396. ctx->cdata.keylen;
  397. if (!ctx->cdata.keylen || !ctx->authsize)
  398. return 0;
  399. /*
  400. * RFC4106 encrypt shared descriptor
  401. * Job Descriptor and Shared Descriptor
  402. * must fit into the 64-word Descriptor h/w Buffer
  403. */
  404. if (rem_bytes >= DESC_RFC4106_ENC_LEN) {
  405. ctx->cdata.key_inline = true;
  406. ctx->cdata.key_virt = ctx->key;
  407. } else {
  408. ctx->cdata.key_inline = false;
  409. ctx->cdata.key_dma = ctx->key_dma;
  410. }
  411. desc = ctx->sh_desc_enc;
  412. cnstr_shdsc_rfc4106_encap(desc, &ctx->cdata, ctx->authsize);
  413. ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
  414. desc_bytes(desc),
  415. DMA_TO_DEVICE);
  416. if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
  417. dev_err(jrdev, "unable to map shared descriptor\n");
  418. return -ENOMEM;
  419. }
  420. /*
  421. * Job Descriptor and Shared Descriptors
  422. * must all fit into the 64-word Descriptor h/w Buffer
  423. */
  424. if (rem_bytes >= DESC_RFC4106_DEC_LEN) {
  425. ctx->cdata.key_inline = true;
  426. ctx->cdata.key_virt = ctx->key;
  427. } else {
  428. ctx->cdata.key_inline = false;
  429. ctx->cdata.key_dma = ctx->key_dma;
  430. }
  431. desc = ctx->sh_desc_dec;
  432. cnstr_shdsc_rfc4106_decap(desc, &ctx->cdata, ctx->authsize);
  433. ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
  434. desc_bytes(desc),
  435. DMA_TO_DEVICE);
  436. if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
  437. dev_err(jrdev, "unable to map shared descriptor\n");
  438. return -ENOMEM;
  439. }
  440. return 0;
  441. }
  442. static int rfc4106_setauthsize(struct crypto_aead *authenc,
  443. unsigned int authsize)
  444. {
  445. struct caam_ctx *ctx = crypto_aead_ctx(authenc);
  446. ctx->authsize = authsize;
  447. rfc4106_set_sh_desc(authenc);
  448. return 0;
  449. }
  450. static int rfc4543_set_sh_desc(struct crypto_aead *aead)
  451. {
  452. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  453. struct device *jrdev = ctx->jrdev;
  454. u32 *desc;
  455. int rem_bytes = CAAM_DESC_BYTES_MAX - GCM_DESC_JOB_IO_LEN -
  456. ctx->cdata.keylen;
  457. if (!ctx->cdata.keylen || !ctx->authsize)
  458. return 0;
  459. /*
  460. * RFC4543 encrypt shared descriptor
  461. * Job Descriptor and Shared Descriptor
  462. * must fit into the 64-word Descriptor h/w Buffer
  463. */
  464. if (rem_bytes >= DESC_RFC4543_ENC_LEN) {
  465. ctx->cdata.key_inline = true;
  466. ctx->cdata.key_virt = ctx->key;
  467. } else {
  468. ctx->cdata.key_inline = false;
  469. ctx->cdata.key_dma = ctx->key_dma;
  470. }
  471. desc = ctx->sh_desc_enc;
  472. cnstr_shdsc_rfc4543_encap(desc, &ctx->cdata, ctx->authsize);
  473. ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
  474. desc_bytes(desc),
  475. DMA_TO_DEVICE);
  476. if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
  477. dev_err(jrdev, "unable to map shared descriptor\n");
  478. return -ENOMEM;
  479. }
  480. /*
  481. * Job Descriptor and Shared Descriptors
  482. * must all fit into the 64-word Descriptor h/w Buffer
  483. */
  484. if (rem_bytes >= DESC_RFC4543_DEC_LEN) {
  485. ctx->cdata.key_inline = true;
  486. ctx->cdata.key_virt = ctx->key;
  487. } else {
  488. ctx->cdata.key_inline = false;
  489. ctx->cdata.key_dma = ctx->key_dma;
  490. }
  491. desc = ctx->sh_desc_dec;
  492. cnstr_shdsc_rfc4543_decap(desc, &ctx->cdata, ctx->authsize);
  493. ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
  494. desc_bytes(desc),
  495. DMA_TO_DEVICE);
  496. if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
  497. dev_err(jrdev, "unable to map shared descriptor\n");
  498. return -ENOMEM;
  499. }
  500. return 0;
  501. }
  502. static int rfc4543_setauthsize(struct crypto_aead *authenc,
  503. unsigned int authsize)
  504. {
  505. struct caam_ctx *ctx = crypto_aead_ctx(authenc);
  506. ctx->authsize = authsize;
  507. rfc4543_set_sh_desc(authenc);
  508. return 0;
  509. }
  510. static int aead_setkey(struct crypto_aead *aead,
  511. const u8 *key, unsigned int keylen)
  512. {
  513. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  514. struct device *jrdev = ctx->jrdev;
  515. struct crypto_authenc_keys keys;
  516. int ret = 0;
  517. if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
  518. goto badkey;
  519. #ifdef DEBUG
  520. printk(KERN_ERR "keylen %d enckeylen %d authkeylen %d\n",
  521. keys.authkeylen + keys.enckeylen, keys.enckeylen,
  522. keys.authkeylen);
  523. print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
  524. DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
  525. #endif
  526. ret = gen_split_key(ctx->jrdev, ctx->key, &ctx->adata, keys.authkey,
  527. keys.authkeylen, CAAM_MAX_KEY_SIZE -
  528. keys.enckeylen);
  529. if (ret) {
  530. goto badkey;
  531. }
  532. /* postpend encryption key to auth split key */
  533. memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen);
  534. ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->adata.keylen_pad +
  535. keys.enckeylen, DMA_TO_DEVICE);
  536. if (dma_mapping_error(jrdev, ctx->key_dma)) {
  537. dev_err(jrdev, "unable to map key i/o memory\n");
  538. return -ENOMEM;
  539. }
  540. #ifdef DEBUG
  541. print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
  542. DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
  543. ctx->adata.keylen_pad + keys.enckeylen, 1);
  544. #endif
  545. ctx->cdata.keylen = keys.enckeylen;
  546. ret = aead_set_sh_desc(aead);
  547. if (ret) {
  548. dma_unmap_single(jrdev, ctx->key_dma, ctx->adata.keylen_pad +
  549. keys.enckeylen, DMA_TO_DEVICE);
  550. }
  551. return ret;
  552. badkey:
  553. crypto_aead_set_flags(aead, CRYPTO_TFM_RES_BAD_KEY_LEN);
  554. return -EINVAL;
  555. }
  556. static int gcm_setkey(struct crypto_aead *aead,
  557. const u8 *key, unsigned int keylen)
  558. {
  559. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  560. struct device *jrdev = ctx->jrdev;
  561. int ret = 0;
  562. #ifdef DEBUG
  563. print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
  564. DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
  565. #endif
  566. memcpy(ctx->key, key, keylen);
  567. ctx->key_dma = dma_map_single(jrdev, ctx->key, keylen,
  568. DMA_TO_DEVICE);
  569. if (dma_mapping_error(jrdev, ctx->key_dma)) {
  570. dev_err(jrdev, "unable to map key i/o memory\n");
  571. return -ENOMEM;
  572. }
  573. ctx->cdata.keylen = keylen;
  574. ret = gcm_set_sh_desc(aead);
  575. if (ret) {
  576. dma_unmap_single(jrdev, ctx->key_dma, ctx->cdata.keylen,
  577. DMA_TO_DEVICE);
  578. }
  579. return ret;
  580. }
  581. static int rfc4106_setkey(struct crypto_aead *aead,
  582. const u8 *key, unsigned int keylen)
  583. {
  584. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  585. struct device *jrdev = ctx->jrdev;
  586. int ret = 0;
  587. if (keylen < 4)
  588. return -EINVAL;
  589. #ifdef DEBUG
  590. print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
  591. DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
  592. #endif
  593. memcpy(ctx->key, key, keylen);
  594. /*
  595. * The last four bytes of the key material are used as the salt value
  596. * in the nonce. Update the AES key length.
  597. */
  598. ctx->cdata.keylen = keylen - 4;
  599. ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->cdata.keylen,
  600. DMA_TO_DEVICE);
  601. if (dma_mapping_error(jrdev, ctx->key_dma)) {
  602. dev_err(jrdev, "unable to map key i/o memory\n");
  603. return -ENOMEM;
  604. }
  605. ret = rfc4106_set_sh_desc(aead);
  606. if (ret) {
  607. dma_unmap_single(jrdev, ctx->key_dma, ctx->cdata.keylen,
  608. DMA_TO_DEVICE);
  609. }
  610. return ret;
  611. }
  612. static int rfc4543_setkey(struct crypto_aead *aead,
  613. const u8 *key, unsigned int keylen)
  614. {
  615. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  616. struct device *jrdev = ctx->jrdev;
  617. int ret = 0;
  618. if (keylen < 4)
  619. return -EINVAL;
  620. #ifdef DEBUG
  621. print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
  622. DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
  623. #endif
  624. memcpy(ctx->key, key, keylen);
  625. /*
  626. * The last four bytes of the key material are used as the salt value
  627. * in the nonce. Update the AES key length.
  628. */
  629. ctx->cdata.keylen = keylen - 4;
  630. ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->cdata.keylen,
  631. DMA_TO_DEVICE);
  632. if (dma_mapping_error(jrdev, ctx->key_dma)) {
  633. dev_err(jrdev, "unable to map key i/o memory\n");
  634. return -ENOMEM;
  635. }
  636. ret = rfc4543_set_sh_desc(aead);
  637. if (ret) {
  638. dma_unmap_single(jrdev, ctx->key_dma, ctx->cdata.keylen,
  639. DMA_TO_DEVICE);
  640. }
  641. return ret;
  642. }
  643. static int ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher,
  644. const u8 *key, unsigned int keylen)
  645. {
  646. struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
  647. struct crypto_tfm *tfm = crypto_ablkcipher_tfm(ablkcipher);
  648. const char *alg_name = crypto_tfm_alg_name(tfm);
  649. struct device *jrdev = ctx->jrdev;
  650. unsigned int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
  651. u32 *desc;
  652. u32 ctx1_iv_off = 0;
  653. const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
  654. OP_ALG_AAI_CTR_MOD128);
  655. const bool is_rfc3686 = (ctr_mode &&
  656. (strstr(alg_name, "rfc3686") != NULL));
  657. memcpy(ctx->key, key, keylen);
  658. #ifdef DEBUG
  659. print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
  660. DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
  661. #endif
  662. /*
  663. * AES-CTR needs to load IV in CONTEXT1 reg
  664. * at an offset of 128bits (16bytes)
  665. * CONTEXT1[255:128] = IV
  666. */
  667. if (ctr_mode)
  668. ctx1_iv_off = 16;
  669. /*
  670. * RFC3686 specific:
  671. * | CONTEXT1[255:128] = {NONCE, IV, COUNTER}
  672. * | *key = {KEY, NONCE}
  673. */
  674. if (is_rfc3686) {
  675. ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE;
  676. keylen -= CTR_RFC3686_NONCE_SIZE;
  677. }
  678. ctx->key_dma = dma_map_single(jrdev, ctx->key, keylen,
  679. DMA_TO_DEVICE);
  680. if (dma_mapping_error(jrdev, ctx->key_dma)) {
  681. dev_err(jrdev, "unable to map key i/o memory\n");
  682. return -ENOMEM;
  683. }
  684. ctx->cdata.keylen = keylen;
  685. ctx->cdata.key_virt = ctx->key;
  686. ctx->cdata.key_inline = true;
  687. /* ablkcipher_encrypt shared descriptor */
  688. desc = ctx->sh_desc_enc;
  689. cnstr_shdsc_ablkcipher_encap(desc, &ctx->cdata, ivsize, is_rfc3686,
  690. ctx1_iv_off);
  691. ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
  692. desc_bytes(desc),
  693. DMA_TO_DEVICE);
  694. if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
  695. dev_err(jrdev, "unable to map shared descriptor\n");
  696. return -ENOMEM;
  697. }
  698. /* ablkcipher_decrypt shared descriptor */
  699. desc = ctx->sh_desc_dec;
  700. cnstr_shdsc_ablkcipher_decap(desc, &ctx->cdata, ivsize, is_rfc3686,
  701. ctx1_iv_off);
  702. ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
  703. desc_bytes(desc),
  704. DMA_TO_DEVICE);
  705. if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
  706. dev_err(jrdev, "unable to map shared descriptor\n");
  707. return -ENOMEM;
  708. }
  709. /* ablkcipher_givencrypt shared descriptor */
  710. desc = ctx->sh_desc_givenc;
  711. cnstr_shdsc_ablkcipher_givencap(desc, &ctx->cdata, ivsize, is_rfc3686,
  712. ctx1_iv_off);
  713. ctx->sh_desc_givenc_dma = dma_map_single(jrdev, desc,
  714. desc_bytes(desc),
  715. DMA_TO_DEVICE);
  716. if (dma_mapping_error(jrdev, ctx->sh_desc_givenc_dma)) {
  717. dev_err(jrdev, "unable to map shared descriptor\n");
  718. return -ENOMEM;
  719. }
  720. return 0;
  721. }
  722. static int xts_ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher,
  723. const u8 *key, unsigned int keylen)
  724. {
  725. struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
  726. struct device *jrdev = ctx->jrdev;
  727. u32 *desc;
  728. if (keylen != 2 * AES_MIN_KEY_SIZE && keylen != 2 * AES_MAX_KEY_SIZE) {
  729. crypto_ablkcipher_set_flags(ablkcipher,
  730. CRYPTO_TFM_RES_BAD_KEY_LEN);
  731. dev_err(jrdev, "key size mismatch\n");
  732. return -EINVAL;
  733. }
  734. memcpy(ctx->key, key, keylen);
  735. ctx->key_dma = dma_map_single(jrdev, ctx->key, keylen, DMA_TO_DEVICE);
  736. if (dma_mapping_error(jrdev, ctx->key_dma)) {
  737. dev_err(jrdev, "unable to map key i/o memory\n");
  738. return -ENOMEM;
  739. }
  740. ctx->cdata.keylen = keylen;
  741. ctx->cdata.key_virt = ctx->key;
  742. ctx->cdata.key_inline = true;
  743. /* xts_ablkcipher_encrypt shared descriptor */
  744. desc = ctx->sh_desc_enc;
  745. cnstr_shdsc_xts_ablkcipher_encap(desc, &ctx->cdata);
  746. ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
  747. DMA_TO_DEVICE);
  748. if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
  749. dev_err(jrdev, "unable to map shared descriptor\n");
  750. return -ENOMEM;
  751. }
  752. /* xts_ablkcipher_decrypt shared descriptor */
  753. desc = ctx->sh_desc_dec;
  754. cnstr_shdsc_xts_ablkcipher_decap(desc, &ctx->cdata);
  755. ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
  756. DMA_TO_DEVICE);
  757. if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
  758. dma_unmap_single(jrdev, ctx->sh_desc_enc_dma,
  759. desc_bytes(ctx->sh_desc_enc), DMA_TO_DEVICE);
  760. dev_err(jrdev, "unable to map shared descriptor\n");
  761. return -ENOMEM;
  762. }
  763. return 0;
  764. }
  765. /*
  766. * aead_edesc - s/w-extended aead descriptor
  767. * @src_nents: number of segments in input scatterlist
  768. * @dst_nents: number of segments in output scatterlist
  769. * @sec4_sg_bytes: length of dma mapped sec4_sg space
  770. * @sec4_sg_dma: bus physical mapped address of h/w link table
  771. * @sec4_sg: pointer to h/w link table
  772. * @hw_desc: the h/w job descriptor followed by any referenced link tables
  773. */
  774. struct aead_edesc {
  775. int src_nents;
  776. int dst_nents;
  777. int sec4_sg_bytes;
  778. dma_addr_t sec4_sg_dma;
  779. struct sec4_sg_entry *sec4_sg;
  780. u32 hw_desc[];
  781. };
  782. /*
  783. * ablkcipher_edesc - s/w-extended ablkcipher descriptor
  784. * @src_nents: number of segments in input scatterlist
  785. * @dst_nents: number of segments in output scatterlist
  786. * @iv_dma: dma address of iv for checking continuity and link table
  787. * @sec4_sg_bytes: length of dma mapped sec4_sg space
  788. * @sec4_sg_dma: bus physical mapped address of h/w link table
  789. * @sec4_sg: pointer to h/w link table
  790. * @hw_desc: the h/w job descriptor followed by any referenced link tables
  791. */
  792. struct ablkcipher_edesc {
  793. int src_nents;
  794. int dst_nents;
  795. dma_addr_t iv_dma;
  796. int sec4_sg_bytes;
  797. dma_addr_t sec4_sg_dma;
  798. struct sec4_sg_entry *sec4_sg;
  799. u32 hw_desc[0];
  800. };
  801. static void caam_unmap(struct device *dev, struct scatterlist *src,
  802. struct scatterlist *dst, int src_nents,
  803. int dst_nents,
  804. dma_addr_t iv_dma, int ivsize, dma_addr_t sec4_sg_dma,
  805. int sec4_sg_bytes)
  806. {
  807. if (dst != src) {
  808. dma_unmap_sg(dev, src, src_nents ? : 1, DMA_TO_DEVICE);
  809. dma_unmap_sg(dev, dst, dst_nents ? : 1, DMA_FROM_DEVICE);
  810. } else {
  811. dma_unmap_sg(dev, src, src_nents ? : 1, DMA_BIDIRECTIONAL);
  812. }
  813. if (iv_dma)
  814. dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE);
  815. if (sec4_sg_bytes)
  816. dma_unmap_single(dev, sec4_sg_dma, sec4_sg_bytes,
  817. DMA_TO_DEVICE);
  818. }
  819. static void aead_unmap(struct device *dev,
  820. struct aead_edesc *edesc,
  821. struct aead_request *req)
  822. {
  823. caam_unmap(dev, req->src, req->dst,
  824. edesc->src_nents, edesc->dst_nents, 0, 0,
  825. edesc->sec4_sg_dma, edesc->sec4_sg_bytes);
  826. }
  827. static void ablkcipher_unmap(struct device *dev,
  828. struct ablkcipher_edesc *edesc,
  829. struct ablkcipher_request *req)
  830. {
  831. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  832. int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
  833. caam_unmap(dev, req->src, req->dst,
  834. edesc->src_nents, edesc->dst_nents,
  835. edesc->iv_dma, ivsize,
  836. edesc->sec4_sg_dma, edesc->sec4_sg_bytes);
  837. }
  838. static void aead_encrypt_done(struct device *jrdev, u32 *desc, u32 err,
  839. void *context)
  840. {
  841. struct aead_request *req = context;
  842. struct aead_edesc *edesc;
  843. #ifdef DEBUG
  844. dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
  845. #endif
  846. edesc = container_of(desc, struct aead_edesc, hw_desc[0]);
  847. if (err)
  848. caam_jr_strstatus(jrdev, err);
  849. aead_unmap(jrdev, edesc, req);
  850. kfree(edesc);
  851. aead_request_complete(req, err);
  852. }
  853. static void aead_decrypt_done(struct device *jrdev, u32 *desc, u32 err,
  854. void *context)
  855. {
  856. struct aead_request *req = context;
  857. struct aead_edesc *edesc;
  858. #ifdef DEBUG
  859. dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
  860. #endif
  861. edesc = container_of(desc, struct aead_edesc, hw_desc[0]);
  862. if (err)
  863. caam_jr_strstatus(jrdev, err);
  864. aead_unmap(jrdev, edesc, req);
  865. /*
  866. * verify hw auth check passed else return -EBADMSG
  867. */
  868. if ((err & JRSTA_CCBERR_ERRID_MASK) == JRSTA_CCBERR_ERRID_ICVCHK)
  869. err = -EBADMSG;
  870. kfree(edesc);
  871. aead_request_complete(req, err);
  872. }
  873. static void ablkcipher_encrypt_done(struct device *jrdev, u32 *desc, u32 err,
  874. void *context)
  875. {
  876. struct ablkcipher_request *req = context;
  877. struct ablkcipher_edesc *edesc;
  878. #ifdef DEBUG
  879. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  880. int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
  881. dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
  882. #endif
  883. edesc = container_of(desc, struct ablkcipher_edesc, hw_desc[0]);
  884. if (err)
  885. caam_jr_strstatus(jrdev, err);
  886. #ifdef DEBUG
  887. print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ",
  888. DUMP_PREFIX_ADDRESS, 16, 4, req->info,
  889. edesc->src_nents > 1 ? 100 : ivsize, 1);
  890. dbg_dump_sg(KERN_ERR, "dst @"__stringify(__LINE__)": ",
  891. DUMP_PREFIX_ADDRESS, 16, 4, req->dst,
  892. edesc->dst_nents > 1 ? 100 : req->nbytes, 1);
  893. #endif
  894. ablkcipher_unmap(jrdev, edesc, req);
  895. kfree(edesc);
  896. ablkcipher_request_complete(req, err);
  897. }
  898. static void ablkcipher_decrypt_done(struct device *jrdev, u32 *desc, u32 err,
  899. void *context)
  900. {
  901. struct ablkcipher_request *req = context;
  902. struct ablkcipher_edesc *edesc;
  903. #ifdef DEBUG
  904. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  905. int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
  906. dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
  907. #endif
  908. edesc = container_of(desc, struct ablkcipher_edesc, hw_desc[0]);
  909. if (err)
  910. caam_jr_strstatus(jrdev, err);
  911. #ifdef DEBUG
  912. print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ",
  913. DUMP_PREFIX_ADDRESS, 16, 4, req->info,
  914. ivsize, 1);
  915. dbg_dump_sg(KERN_ERR, "dst @"__stringify(__LINE__)": ",
  916. DUMP_PREFIX_ADDRESS, 16, 4, req->dst,
  917. edesc->dst_nents > 1 ? 100 : req->nbytes, 1);
  918. #endif
  919. ablkcipher_unmap(jrdev, edesc, req);
  920. kfree(edesc);
  921. ablkcipher_request_complete(req, err);
  922. }
  923. /*
  924. * Fill in aead job descriptor
  925. */
  926. static void init_aead_job(struct aead_request *req,
  927. struct aead_edesc *edesc,
  928. bool all_contig, bool encrypt)
  929. {
  930. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  931. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  932. int authsize = ctx->authsize;
  933. u32 *desc = edesc->hw_desc;
  934. u32 out_options, in_options;
  935. dma_addr_t dst_dma, src_dma;
  936. int len, sec4_sg_index = 0;
  937. dma_addr_t ptr;
  938. u32 *sh_desc;
  939. sh_desc = encrypt ? ctx->sh_desc_enc : ctx->sh_desc_dec;
  940. ptr = encrypt ? ctx->sh_desc_enc_dma : ctx->sh_desc_dec_dma;
  941. len = desc_len(sh_desc);
  942. init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
  943. if (all_contig) {
  944. src_dma = sg_dma_address(req->src);
  945. in_options = 0;
  946. } else {
  947. src_dma = edesc->sec4_sg_dma;
  948. sec4_sg_index += edesc->src_nents;
  949. in_options = LDST_SGF;
  950. }
  951. append_seq_in_ptr(desc, src_dma, req->assoclen + req->cryptlen,
  952. in_options);
  953. dst_dma = src_dma;
  954. out_options = in_options;
  955. if (unlikely(req->src != req->dst)) {
  956. if (!edesc->dst_nents) {
  957. dst_dma = sg_dma_address(req->dst);
  958. } else {
  959. dst_dma = edesc->sec4_sg_dma +
  960. sec4_sg_index *
  961. sizeof(struct sec4_sg_entry);
  962. out_options = LDST_SGF;
  963. }
  964. }
  965. if (encrypt)
  966. append_seq_out_ptr(desc, dst_dma,
  967. req->assoclen + req->cryptlen + authsize,
  968. out_options);
  969. else
  970. append_seq_out_ptr(desc, dst_dma,
  971. req->assoclen + req->cryptlen - authsize,
  972. out_options);
  973. /* REG3 = assoclen */
  974. append_math_add_imm_u32(desc, REG3, ZERO, IMM, req->assoclen);
  975. }
  976. static void init_gcm_job(struct aead_request *req,
  977. struct aead_edesc *edesc,
  978. bool all_contig, bool encrypt)
  979. {
  980. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  981. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  982. unsigned int ivsize = crypto_aead_ivsize(aead);
  983. u32 *desc = edesc->hw_desc;
  984. bool generic_gcm = (ivsize == 12);
  985. unsigned int last;
  986. init_aead_job(req, edesc, all_contig, encrypt);
  987. /* BUG This should not be specific to generic GCM. */
  988. last = 0;
  989. if (encrypt && generic_gcm && !(req->assoclen + req->cryptlen))
  990. last = FIFOLD_TYPE_LAST1;
  991. /* Read GCM IV */
  992. append_cmd(desc, CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | IMMEDIATE |
  993. FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1 | 12 | last);
  994. /* Append Salt */
  995. if (!generic_gcm)
  996. append_data(desc, ctx->key + ctx->cdata.keylen, 4);
  997. /* Append IV */
  998. append_data(desc, req->iv, ivsize);
  999. /* End of blank commands */
  1000. }
  1001. static void init_authenc_job(struct aead_request *req,
  1002. struct aead_edesc *edesc,
  1003. bool all_contig, bool encrypt)
  1004. {
  1005. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  1006. struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead),
  1007. struct caam_aead_alg, aead);
  1008. unsigned int ivsize = crypto_aead_ivsize(aead);
  1009. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  1010. const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
  1011. OP_ALG_AAI_CTR_MOD128);
  1012. const bool is_rfc3686 = alg->caam.rfc3686;
  1013. u32 *desc = edesc->hw_desc;
  1014. u32 ivoffset = 0;
  1015. /*
  1016. * AES-CTR needs to load IV in CONTEXT1 reg
  1017. * at an offset of 128bits (16bytes)
  1018. * CONTEXT1[255:128] = IV
  1019. */
  1020. if (ctr_mode)
  1021. ivoffset = 16;
  1022. /*
  1023. * RFC3686 specific:
  1024. * CONTEXT1[255:128] = {NONCE, IV, COUNTER}
  1025. */
  1026. if (is_rfc3686)
  1027. ivoffset = 16 + CTR_RFC3686_NONCE_SIZE;
  1028. init_aead_job(req, edesc, all_contig, encrypt);
  1029. if (ivsize && ((is_rfc3686 && encrypt) || !alg->caam.geniv))
  1030. append_load_as_imm(desc, req->iv, ivsize,
  1031. LDST_CLASS_1_CCB |
  1032. LDST_SRCDST_BYTE_CONTEXT |
  1033. (ivoffset << LDST_OFFSET_SHIFT));
  1034. }
  1035. /*
  1036. * Fill in ablkcipher job descriptor
  1037. */
  1038. static void init_ablkcipher_job(u32 *sh_desc, dma_addr_t ptr,
  1039. struct ablkcipher_edesc *edesc,
  1040. struct ablkcipher_request *req,
  1041. bool iv_contig)
  1042. {
  1043. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  1044. int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
  1045. u32 *desc = edesc->hw_desc;
  1046. u32 out_options = 0, in_options;
  1047. dma_addr_t dst_dma, src_dma;
  1048. int len, sec4_sg_index = 0;
  1049. #ifdef DEBUG
  1050. print_hex_dump(KERN_ERR, "presciv@"__stringify(__LINE__)": ",
  1051. DUMP_PREFIX_ADDRESS, 16, 4, req->info,
  1052. ivsize, 1);
  1053. printk(KERN_ERR "asked=%d, nbytes%d\n", (int)edesc->src_nents ? 100 : req->nbytes, req->nbytes);
  1054. dbg_dump_sg(KERN_ERR, "src @"__stringify(__LINE__)": ",
  1055. DUMP_PREFIX_ADDRESS, 16, 4, req->src,
  1056. edesc->src_nents ? 100 : req->nbytes, 1);
  1057. #endif
  1058. len = desc_len(sh_desc);
  1059. init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
  1060. if (iv_contig) {
  1061. src_dma = edesc->iv_dma;
  1062. in_options = 0;
  1063. } else {
  1064. src_dma = edesc->sec4_sg_dma;
  1065. sec4_sg_index += edesc->src_nents + 1;
  1066. in_options = LDST_SGF;
  1067. }
  1068. append_seq_in_ptr(desc, src_dma, req->nbytes + ivsize, in_options);
  1069. if (likely(req->src == req->dst)) {
  1070. if (!edesc->src_nents && iv_contig) {
  1071. dst_dma = sg_dma_address(req->src);
  1072. } else {
  1073. dst_dma = edesc->sec4_sg_dma +
  1074. sizeof(struct sec4_sg_entry);
  1075. out_options = LDST_SGF;
  1076. }
  1077. } else {
  1078. if (!edesc->dst_nents) {
  1079. dst_dma = sg_dma_address(req->dst);
  1080. } else {
  1081. dst_dma = edesc->sec4_sg_dma +
  1082. sec4_sg_index * sizeof(struct sec4_sg_entry);
  1083. out_options = LDST_SGF;
  1084. }
  1085. }
  1086. append_seq_out_ptr(desc, dst_dma, req->nbytes, out_options);
  1087. }
  1088. /*
  1089. * Fill in ablkcipher givencrypt job descriptor
  1090. */
  1091. static void init_ablkcipher_giv_job(u32 *sh_desc, dma_addr_t ptr,
  1092. struct ablkcipher_edesc *edesc,
  1093. struct ablkcipher_request *req,
  1094. bool iv_contig)
  1095. {
  1096. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  1097. int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
  1098. u32 *desc = edesc->hw_desc;
  1099. u32 out_options, in_options;
  1100. dma_addr_t dst_dma, src_dma;
  1101. int len, sec4_sg_index = 0;
  1102. #ifdef DEBUG
  1103. print_hex_dump(KERN_ERR, "presciv@" __stringify(__LINE__) ": ",
  1104. DUMP_PREFIX_ADDRESS, 16, 4, req->info,
  1105. ivsize, 1);
  1106. dbg_dump_sg(KERN_ERR, "src @" __stringify(__LINE__) ": ",
  1107. DUMP_PREFIX_ADDRESS, 16, 4, req->src,
  1108. edesc->src_nents ? 100 : req->nbytes, 1);
  1109. #endif
  1110. len = desc_len(sh_desc);
  1111. init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
  1112. if (!edesc->src_nents) {
  1113. src_dma = sg_dma_address(req->src);
  1114. in_options = 0;
  1115. } else {
  1116. src_dma = edesc->sec4_sg_dma;
  1117. sec4_sg_index += edesc->src_nents;
  1118. in_options = LDST_SGF;
  1119. }
  1120. append_seq_in_ptr(desc, src_dma, req->nbytes, in_options);
  1121. if (iv_contig) {
  1122. dst_dma = edesc->iv_dma;
  1123. out_options = 0;
  1124. } else {
  1125. dst_dma = edesc->sec4_sg_dma +
  1126. sec4_sg_index * sizeof(struct sec4_sg_entry);
  1127. out_options = LDST_SGF;
  1128. }
  1129. append_seq_out_ptr(desc, dst_dma, req->nbytes + ivsize, out_options);
  1130. }
  1131. /*
  1132. * allocate and map the aead extended descriptor
  1133. */
  1134. static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
  1135. int desc_bytes, bool *all_contig_ptr,
  1136. bool encrypt)
  1137. {
  1138. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  1139. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  1140. struct device *jrdev = ctx->jrdev;
  1141. gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
  1142. CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
  1143. int src_nents, dst_nents = 0;
  1144. struct aead_edesc *edesc;
  1145. int sgc;
  1146. bool all_contig = true;
  1147. int sec4_sg_index, sec4_sg_len = 0, sec4_sg_bytes;
  1148. unsigned int authsize = ctx->authsize;
  1149. if (unlikely(req->dst != req->src)) {
  1150. src_nents = sg_count(req->src, req->assoclen + req->cryptlen);
  1151. dst_nents = sg_count(req->dst,
  1152. req->assoclen + req->cryptlen +
  1153. (encrypt ? authsize : (-authsize)));
  1154. } else {
  1155. src_nents = sg_count(req->src,
  1156. req->assoclen + req->cryptlen +
  1157. (encrypt ? authsize : 0));
  1158. }
  1159. /* Check if data are contiguous. */
  1160. all_contig = !src_nents;
  1161. if (!all_contig)
  1162. sec4_sg_len = src_nents;
  1163. sec4_sg_len += dst_nents;
  1164. sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
  1165. /* allocate space for base edesc and hw desc commands, link tables */
  1166. edesc = kzalloc(sizeof(*edesc) + desc_bytes + sec4_sg_bytes,
  1167. GFP_DMA | flags);
  1168. if (!edesc) {
  1169. dev_err(jrdev, "could not allocate extended descriptor\n");
  1170. return ERR_PTR(-ENOMEM);
  1171. }
  1172. if (likely(req->src == req->dst)) {
  1173. sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
  1174. DMA_BIDIRECTIONAL);
  1175. if (unlikely(!sgc)) {
  1176. dev_err(jrdev, "unable to map source\n");
  1177. kfree(edesc);
  1178. return ERR_PTR(-ENOMEM);
  1179. }
  1180. } else {
  1181. sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
  1182. DMA_TO_DEVICE);
  1183. if (unlikely(!sgc)) {
  1184. dev_err(jrdev, "unable to map source\n");
  1185. kfree(edesc);
  1186. return ERR_PTR(-ENOMEM);
  1187. }
  1188. sgc = dma_map_sg(jrdev, req->dst, dst_nents ? : 1,
  1189. DMA_FROM_DEVICE);
  1190. if (unlikely(!sgc)) {
  1191. dev_err(jrdev, "unable to map destination\n");
  1192. dma_unmap_sg(jrdev, req->src, src_nents ? : 1,
  1193. DMA_TO_DEVICE);
  1194. kfree(edesc);
  1195. return ERR_PTR(-ENOMEM);
  1196. }
  1197. }
  1198. edesc->src_nents = src_nents;
  1199. edesc->dst_nents = dst_nents;
  1200. edesc->sec4_sg = (void *)edesc + sizeof(struct aead_edesc) +
  1201. desc_bytes;
  1202. *all_contig_ptr = all_contig;
  1203. sec4_sg_index = 0;
  1204. if (!all_contig) {
  1205. sg_to_sec4_sg_last(req->src, src_nents,
  1206. edesc->sec4_sg + sec4_sg_index, 0);
  1207. sec4_sg_index += src_nents;
  1208. }
  1209. if (dst_nents) {
  1210. sg_to_sec4_sg_last(req->dst, dst_nents,
  1211. edesc->sec4_sg + sec4_sg_index, 0);
  1212. }
  1213. if (!sec4_sg_bytes)
  1214. return edesc;
  1215. edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
  1216. sec4_sg_bytes, DMA_TO_DEVICE);
  1217. if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
  1218. dev_err(jrdev, "unable to map S/G table\n");
  1219. aead_unmap(jrdev, edesc, req);
  1220. kfree(edesc);
  1221. return ERR_PTR(-ENOMEM);
  1222. }
  1223. edesc->sec4_sg_bytes = sec4_sg_bytes;
  1224. return edesc;
  1225. }
  1226. static int gcm_encrypt(struct aead_request *req)
  1227. {
  1228. struct aead_edesc *edesc;
  1229. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  1230. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  1231. struct device *jrdev = ctx->jrdev;
  1232. bool all_contig;
  1233. u32 *desc;
  1234. int ret = 0;
  1235. /* allocate extended descriptor */
  1236. edesc = aead_edesc_alloc(req, GCM_DESC_JOB_IO_LEN, &all_contig, true);
  1237. if (IS_ERR(edesc))
  1238. return PTR_ERR(edesc);
  1239. /* Create and submit job descriptor */
  1240. init_gcm_job(req, edesc, all_contig, true);
  1241. #ifdef DEBUG
  1242. print_hex_dump(KERN_ERR, "aead jobdesc@"__stringify(__LINE__)": ",
  1243. DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
  1244. desc_bytes(edesc->hw_desc), 1);
  1245. #endif
  1246. desc = edesc->hw_desc;
  1247. ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req);
  1248. if (!ret) {
  1249. ret = -EINPROGRESS;
  1250. } else {
  1251. aead_unmap(jrdev, edesc, req);
  1252. kfree(edesc);
  1253. }
  1254. return ret;
  1255. }
  1256. static int ipsec_gcm_encrypt(struct aead_request *req)
  1257. {
  1258. if (req->assoclen < 8)
  1259. return -EINVAL;
  1260. return gcm_encrypt(req);
  1261. }
  1262. static int aead_encrypt(struct aead_request *req)
  1263. {
  1264. struct aead_edesc *edesc;
  1265. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  1266. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  1267. struct device *jrdev = ctx->jrdev;
  1268. bool all_contig;
  1269. u32 *desc;
  1270. int ret = 0;
  1271. /* allocate extended descriptor */
  1272. edesc = aead_edesc_alloc(req, AUTHENC_DESC_JOB_IO_LEN,
  1273. &all_contig, true);
  1274. if (IS_ERR(edesc))
  1275. return PTR_ERR(edesc);
  1276. /* Create and submit job descriptor */
  1277. init_authenc_job(req, edesc, all_contig, true);
  1278. #ifdef DEBUG
  1279. print_hex_dump(KERN_ERR, "aead jobdesc@"__stringify(__LINE__)": ",
  1280. DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
  1281. desc_bytes(edesc->hw_desc), 1);
  1282. #endif
  1283. desc = edesc->hw_desc;
  1284. ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req);
  1285. if (!ret) {
  1286. ret = -EINPROGRESS;
  1287. } else {
  1288. aead_unmap(jrdev, edesc, req);
  1289. kfree(edesc);
  1290. }
  1291. return ret;
  1292. }
  1293. static int gcm_decrypt(struct aead_request *req)
  1294. {
  1295. struct aead_edesc *edesc;
  1296. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  1297. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  1298. struct device *jrdev = ctx->jrdev;
  1299. bool all_contig;
  1300. u32 *desc;
  1301. int ret = 0;
  1302. /* allocate extended descriptor */
  1303. edesc = aead_edesc_alloc(req, GCM_DESC_JOB_IO_LEN, &all_contig, false);
  1304. if (IS_ERR(edesc))
  1305. return PTR_ERR(edesc);
  1306. /* Create and submit job descriptor*/
  1307. init_gcm_job(req, edesc, all_contig, false);
  1308. #ifdef DEBUG
  1309. print_hex_dump(KERN_ERR, "aead jobdesc@"__stringify(__LINE__)": ",
  1310. DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
  1311. desc_bytes(edesc->hw_desc), 1);
  1312. #endif
  1313. desc = edesc->hw_desc;
  1314. ret = caam_jr_enqueue(jrdev, desc, aead_decrypt_done, req);
  1315. if (!ret) {
  1316. ret = -EINPROGRESS;
  1317. } else {
  1318. aead_unmap(jrdev, edesc, req);
  1319. kfree(edesc);
  1320. }
  1321. return ret;
  1322. }
  1323. static int ipsec_gcm_decrypt(struct aead_request *req)
  1324. {
  1325. if (req->assoclen < 8)
  1326. return -EINVAL;
  1327. return gcm_decrypt(req);
  1328. }
  1329. static int aead_decrypt(struct aead_request *req)
  1330. {
  1331. struct aead_edesc *edesc;
  1332. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  1333. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  1334. struct device *jrdev = ctx->jrdev;
  1335. bool all_contig;
  1336. u32 *desc;
  1337. int ret = 0;
  1338. #ifdef DEBUG
  1339. dbg_dump_sg(KERN_ERR, "dec src@"__stringify(__LINE__)": ",
  1340. DUMP_PREFIX_ADDRESS, 16, 4, req->src,
  1341. req->assoclen + req->cryptlen, 1);
  1342. #endif
  1343. /* allocate extended descriptor */
  1344. edesc = aead_edesc_alloc(req, AUTHENC_DESC_JOB_IO_LEN,
  1345. &all_contig, false);
  1346. if (IS_ERR(edesc))
  1347. return PTR_ERR(edesc);
  1348. /* Create and submit job descriptor*/
  1349. init_authenc_job(req, edesc, all_contig, false);
  1350. #ifdef DEBUG
  1351. print_hex_dump(KERN_ERR, "aead jobdesc@"__stringify(__LINE__)": ",
  1352. DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
  1353. desc_bytes(edesc->hw_desc), 1);
  1354. #endif
  1355. desc = edesc->hw_desc;
  1356. ret = caam_jr_enqueue(jrdev, desc, aead_decrypt_done, req);
  1357. if (!ret) {
  1358. ret = -EINPROGRESS;
  1359. } else {
  1360. aead_unmap(jrdev, edesc, req);
  1361. kfree(edesc);
  1362. }
  1363. return ret;
  1364. }
  1365. /*
  1366. * allocate and map the ablkcipher extended descriptor for ablkcipher
  1367. */
  1368. static struct ablkcipher_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request
  1369. *req, int desc_bytes,
  1370. bool *iv_contig_out)
  1371. {
  1372. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  1373. struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
  1374. struct device *jrdev = ctx->jrdev;
  1375. gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
  1376. CRYPTO_TFM_REQ_MAY_SLEEP)) ?
  1377. GFP_KERNEL : GFP_ATOMIC;
  1378. int src_nents, dst_nents = 0, sec4_sg_bytes;
  1379. struct ablkcipher_edesc *edesc;
  1380. dma_addr_t iv_dma = 0;
  1381. bool iv_contig = false;
  1382. int sgc;
  1383. int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
  1384. int sec4_sg_index;
  1385. src_nents = sg_count(req->src, req->nbytes);
  1386. if (req->dst != req->src)
  1387. dst_nents = sg_count(req->dst, req->nbytes);
  1388. if (likely(req->src == req->dst)) {
  1389. sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
  1390. DMA_BIDIRECTIONAL);
  1391. if (unlikely(!sgc)) {
  1392. dev_err(jrdev, "unable to map source\n");
  1393. return ERR_PTR(-ENOMEM);
  1394. }
  1395. } else {
  1396. sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
  1397. DMA_TO_DEVICE);
  1398. if (unlikely(!sgc)) {
  1399. dev_err(jrdev, "unable to map source\n");
  1400. return ERR_PTR(-ENOMEM);
  1401. }
  1402. sgc = dma_map_sg(jrdev, req->dst, dst_nents ? : 1,
  1403. DMA_FROM_DEVICE);
  1404. if (unlikely(!sgc)) {
  1405. dev_err(jrdev, "unable to map destination\n");
  1406. dma_unmap_sg(jrdev, req->src, src_nents ? : 1,
  1407. DMA_TO_DEVICE);
  1408. return ERR_PTR(-ENOMEM);
  1409. }
  1410. }
  1411. iv_dma = dma_map_single(jrdev, req->info, ivsize, DMA_TO_DEVICE);
  1412. if (dma_mapping_error(jrdev, iv_dma)) {
  1413. dev_err(jrdev, "unable to map IV\n");
  1414. caam_unmap(jrdev, req->src, req->dst, src_nents, dst_nents, 0,
  1415. 0, 0, 0);
  1416. return ERR_PTR(-ENOMEM);
  1417. }
  1418. /*
  1419. * Check if iv can be contiguous with source and destination.
  1420. * If so, include it. If not, create scatterlist.
  1421. */
  1422. if (!src_nents && iv_dma + ivsize == sg_dma_address(req->src))
  1423. iv_contig = true;
  1424. else
  1425. src_nents = src_nents ? : 1;
  1426. sec4_sg_bytes = ((iv_contig ? 0 : 1) + src_nents + dst_nents) *
  1427. sizeof(struct sec4_sg_entry);
  1428. /* allocate space for base edesc and hw desc commands, link tables */
  1429. edesc = kzalloc(sizeof(*edesc) + desc_bytes + sec4_sg_bytes,
  1430. GFP_DMA | flags);
  1431. if (!edesc) {
  1432. dev_err(jrdev, "could not allocate extended descriptor\n");
  1433. caam_unmap(jrdev, req->src, req->dst, src_nents, dst_nents,
  1434. iv_dma, ivsize, 0, 0);
  1435. return ERR_PTR(-ENOMEM);
  1436. }
  1437. edesc->src_nents = src_nents;
  1438. edesc->dst_nents = dst_nents;
  1439. edesc->sec4_sg_bytes = sec4_sg_bytes;
  1440. edesc->sec4_sg = (void *)edesc + sizeof(struct ablkcipher_edesc) +
  1441. desc_bytes;
  1442. sec4_sg_index = 0;
  1443. if (!iv_contig) {
  1444. dma_to_sec4_sg_one(edesc->sec4_sg, iv_dma, ivsize, 0);
  1445. sg_to_sec4_sg_last(req->src, src_nents,
  1446. edesc->sec4_sg + 1, 0);
  1447. sec4_sg_index += 1 + src_nents;
  1448. }
  1449. if (dst_nents) {
  1450. sg_to_sec4_sg_last(req->dst, dst_nents,
  1451. edesc->sec4_sg + sec4_sg_index, 0);
  1452. }
  1453. edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
  1454. sec4_sg_bytes, DMA_TO_DEVICE);
  1455. if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
  1456. dev_err(jrdev, "unable to map S/G table\n");
  1457. caam_unmap(jrdev, req->src, req->dst, src_nents, dst_nents,
  1458. iv_dma, ivsize, 0, 0);
  1459. kfree(edesc);
  1460. return ERR_PTR(-ENOMEM);
  1461. }
  1462. edesc->iv_dma = iv_dma;
  1463. #ifdef DEBUG
  1464. print_hex_dump(KERN_ERR, "ablkcipher sec4_sg@"__stringify(__LINE__)": ",
  1465. DUMP_PREFIX_ADDRESS, 16, 4, edesc->sec4_sg,
  1466. sec4_sg_bytes, 1);
  1467. #endif
  1468. *iv_contig_out = iv_contig;
  1469. return edesc;
  1470. }
  1471. static int ablkcipher_encrypt(struct ablkcipher_request *req)
  1472. {
  1473. struct ablkcipher_edesc *edesc;
  1474. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  1475. struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
  1476. struct device *jrdev = ctx->jrdev;
  1477. bool iv_contig;
  1478. u32 *desc;
  1479. int ret = 0;
  1480. /* allocate extended descriptor */
  1481. edesc = ablkcipher_edesc_alloc(req, DESC_JOB_IO_LEN *
  1482. CAAM_CMD_SZ, &iv_contig);
  1483. if (IS_ERR(edesc))
  1484. return PTR_ERR(edesc);
  1485. /* Create and submit job descriptor*/
  1486. init_ablkcipher_job(ctx->sh_desc_enc,
  1487. ctx->sh_desc_enc_dma, edesc, req, iv_contig);
  1488. #ifdef DEBUG
  1489. print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"__stringify(__LINE__)": ",
  1490. DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
  1491. desc_bytes(edesc->hw_desc), 1);
  1492. #endif
  1493. desc = edesc->hw_desc;
  1494. ret = caam_jr_enqueue(jrdev, desc, ablkcipher_encrypt_done, req);
  1495. if (!ret) {
  1496. ret = -EINPROGRESS;
  1497. } else {
  1498. ablkcipher_unmap(jrdev, edesc, req);
  1499. kfree(edesc);
  1500. }
  1501. return ret;
  1502. }
  1503. static int ablkcipher_decrypt(struct ablkcipher_request *req)
  1504. {
  1505. struct ablkcipher_edesc *edesc;
  1506. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  1507. struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
  1508. struct device *jrdev = ctx->jrdev;
  1509. bool iv_contig;
  1510. u32 *desc;
  1511. int ret = 0;
  1512. /* allocate extended descriptor */
  1513. edesc = ablkcipher_edesc_alloc(req, DESC_JOB_IO_LEN *
  1514. CAAM_CMD_SZ, &iv_contig);
  1515. if (IS_ERR(edesc))
  1516. return PTR_ERR(edesc);
  1517. /* Create and submit job descriptor*/
  1518. init_ablkcipher_job(ctx->sh_desc_dec,
  1519. ctx->sh_desc_dec_dma, edesc, req, iv_contig);
  1520. desc = edesc->hw_desc;
  1521. #ifdef DEBUG
  1522. print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"__stringify(__LINE__)": ",
  1523. DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
  1524. desc_bytes(edesc->hw_desc), 1);
  1525. #endif
  1526. ret = caam_jr_enqueue(jrdev, desc, ablkcipher_decrypt_done, req);
  1527. if (!ret) {
  1528. ret = -EINPROGRESS;
  1529. } else {
  1530. ablkcipher_unmap(jrdev, edesc, req);
  1531. kfree(edesc);
  1532. }
  1533. return ret;
  1534. }
  1535. /*
  1536. * allocate and map the ablkcipher extended descriptor
  1537. * for ablkcipher givencrypt
  1538. */
  1539. static struct ablkcipher_edesc *ablkcipher_giv_edesc_alloc(
  1540. struct skcipher_givcrypt_request *greq,
  1541. int desc_bytes,
  1542. bool *iv_contig_out)
  1543. {
  1544. struct ablkcipher_request *req = &greq->creq;
  1545. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  1546. struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
  1547. struct device *jrdev = ctx->jrdev;
  1548. gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
  1549. CRYPTO_TFM_REQ_MAY_SLEEP)) ?
  1550. GFP_KERNEL : GFP_ATOMIC;
  1551. int src_nents, dst_nents = 0, sec4_sg_bytes;
  1552. struct ablkcipher_edesc *edesc;
  1553. dma_addr_t iv_dma = 0;
  1554. bool iv_contig = false;
  1555. int sgc;
  1556. int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
  1557. int sec4_sg_index;
  1558. src_nents = sg_count(req->src, req->nbytes);
  1559. if (unlikely(req->dst != req->src))
  1560. dst_nents = sg_count(req->dst, req->nbytes);
  1561. if (likely(req->src == req->dst)) {
  1562. sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
  1563. DMA_BIDIRECTIONAL);
  1564. if (unlikely(!sgc)) {
  1565. dev_err(jrdev, "unable to map source\n");
  1566. return ERR_PTR(-ENOMEM);
  1567. }
  1568. } else {
  1569. sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
  1570. DMA_TO_DEVICE);
  1571. if (unlikely(!sgc)) {
  1572. dev_err(jrdev, "unable to map source\n");
  1573. return ERR_PTR(-ENOMEM);
  1574. }
  1575. sgc = dma_map_sg(jrdev, req->dst, dst_nents ? : 1,
  1576. DMA_FROM_DEVICE);
  1577. if (unlikely(!sgc)) {
  1578. dev_err(jrdev, "unable to map destination\n");
  1579. dma_unmap_sg(jrdev, req->src, src_nents ? : 1,
  1580. DMA_TO_DEVICE);
  1581. return ERR_PTR(-ENOMEM);
  1582. }
  1583. }
  1584. /*
  1585. * Check if iv can be contiguous with source and destination.
  1586. * If so, include it. If not, create scatterlist.
  1587. */
  1588. iv_dma = dma_map_single(jrdev, greq->giv, ivsize, DMA_TO_DEVICE);
  1589. if (dma_mapping_error(jrdev, iv_dma)) {
  1590. dev_err(jrdev, "unable to map IV\n");
  1591. caam_unmap(jrdev, req->src, req->dst, src_nents, dst_nents, 0,
  1592. 0, 0, 0);
  1593. return ERR_PTR(-ENOMEM);
  1594. }
  1595. if (!dst_nents && iv_dma + ivsize == sg_dma_address(req->dst))
  1596. iv_contig = true;
  1597. else
  1598. dst_nents = dst_nents ? : 1;
  1599. sec4_sg_bytes = ((iv_contig ? 0 : 1) + src_nents + dst_nents) *
  1600. sizeof(struct sec4_sg_entry);
  1601. /* allocate space for base edesc and hw desc commands, link tables */
  1602. edesc = kzalloc(sizeof(*edesc) + desc_bytes + sec4_sg_bytes,
  1603. GFP_DMA | flags);
  1604. if (!edesc) {
  1605. dev_err(jrdev, "could not allocate extended descriptor\n");
  1606. caam_unmap(jrdev, req->src, req->dst, src_nents, dst_nents,
  1607. iv_dma, ivsize, 0, 0);
  1608. return ERR_PTR(-ENOMEM);
  1609. }
  1610. edesc->src_nents = src_nents;
  1611. edesc->dst_nents = dst_nents;
  1612. edesc->sec4_sg_bytes = sec4_sg_bytes;
  1613. edesc->sec4_sg = (void *)edesc + sizeof(struct ablkcipher_edesc) +
  1614. desc_bytes;
  1615. sec4_sg_index = 0;
  1616. if (src_nents) {
  1617. sg_to_sec4_sg_last(req->src, src_nents, edesc->sec4_sg, 0);
  1618. sec4_sg_index += src_nents;
  1619. }
  1620. if (!iv_contig) {
  1621. dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index,
  1622. iv_dma, ivsize, 0);
  1623. sec4_sg_index += 1;
  1624. sg_to_sec4_sg_last(req->dst, dst_nents,
  1625. edesc->sec4_sg + sec4_sg_index, 0);
  1626. }
  1627. edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
  1628. sec4_sg_bytes, DMA_TO_DEVICE);
  1629. if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
  1630. dev_err(jrdev, "unable to map S/G table\n");
  1631. caam_unmap(jrdev, req->src, req->dst, src_nents, dst_nents,
  1632. iv_dma, ivsize, 0, 0);
  1633. kfree(edesc);
  1634. return ERR_PTR(-ENOMEM);
  1635. }
  1636. edesc->iv_dma = iv_dma;
  1637. #ifdef DEBUG
  1638. print_hex_dump(KERN_ERR,
  1639. "ablkcipher sec4_sg@" __stringify(__LINE__) ": ",
  1640. DUMP_PREFIX_ADDRESS, 16, 4, edesc->sec4_sg,
  1641. sec4_sg_bytes, 1);
  1642. #endif
  1643. *iv_contig_out = iv_contig;
  1644. return edesc;
  1645. }
  1646. static int ablkcipher_givencrypt(struct skcipher_givcrypt_request *creq)
  1647. {
  1648. struct ablkcipher_request *req = &creq->creq;
  1649. struct ablkcipher_edesc *edesc;
  1650. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  1651. struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
  1652. struct device *jrdev = ctx->jrdev;
  1653. bool iv_contig;
  1654. u32 *desc;
  1655. int ret = 0;
  1656. /* allocate extended descriptor */
  1657. edesc = ablkcipher_giv_edesc_alloc(creq, DESC_JOB_IO_LEN *
  1658. CAAM_CMD_SZ, &iv_contig);
  1659. if (IS_ERR(edesc))
  1660. return PTR_ERR(edesc);
  1661. /* Create and submit job descriptor*/
  1662. init_ablkcipher_giv_job(ctx->sh_desc_givenc, ctx->sh_desc_givenc_dma,
  1663. edesc, req, iv_contig);
  1664. #ifdef DEBUG
  1665. print_hex_dump(KERN_ERR,
  1666. "ablkcipher jobdesc@" __stringify(__LINE__) ": ",
  1667. DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
  1668. desc_bytes(edesc->hw_desc), 1);
  1669. #endif
  1670. desc = edesc->hw_desc;
  1671. ret = caam_jr_enqueue(jrdev, desc, ablkcipher_encrypt_done, req);
  1672. if (!ret) {
  1673. ret = -EINPROGRESS;
  1674. } else {
  1675. ablkcipher_unmap(jrdev, edesc, req);
  1676. kfree(edesc);
  1677. }
  1678. return ret;
  1679. }
  1680. #define template_aead template_u.aead
  1681. #define template_ablkcipher template_u.ablkcipher
  1682. struct caam_alg_template {
  1683. char name[CRYPTO_MAX_ALG_NAME];
  1684. char driver_name[CRYPTO_MAX_ALG_NAME];
  1685. unsigned int blocksize;
  1686. u32 type;
  1687. union {
  1688. struct ablkcipher_alg ablkcipher;
  1689. } template_u;
  1690. u32 class1_alg_type;
  1691. u32 class2_alg_type;
  1692. };
  1693. static struct caam_alg_template driver_algs[] = {
  1694. /* ablkcipher descriptor */
  1695. {
  1696. .name = "cbc(aes)",
  1697. .driver_name = "cbc-aes-caam",
  1698. .blocksize = AES_BLOCK_SIZE,
  1699. .type = CRYPTO_ALG_TYPE_GIVCIPHER,
  1700. .template_ablkcipher = {
  1701. .setkey = ablkcipher_setkey,
  1702. .encrypt = ablkcipher_encrypt,
  1703. .decrypt = ablkcipher_decrypt,
  1704. .givencrypt = ablkcipher_givencrypt,
  1705. .geniv = "<built-in>",
  1706. .min_keysize = AES_MIN_KEY_SIZE,
  1707. .max_keysize = AES_MAX_KEY_SIZE,
  1708. .ivsize = AES_BLOCK_SIZE,
  1709. },
  1710. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  1711. },
  1712. {
  1713. .name = "cbc(des3_ede)",
  1714. .driver_name = "cbc-3des-caam",
  1715. .blocksize = DES3_EDE_BLOCK_SIZE,
  1716. .type = CRYPTO_ALG_TYPE_GIVCIPHER,
  1717. .template_ablkcipher = {
  1718. .setkey = ablkcipher_setkey,
  1719. .encrypt = ablkcipher_encrypt,
  1720. .decrypt = ablkcipher_decrypt,
  1721. .givencrypt = ablkcipher_givencrypt,
  1722. .geniv = "<built-in>",
  1723. .min_keysize = DES3_EDE_KEY_SIZE,
  1724. .max_keysize = DES3_EDE_KEY_SIZE,
  1725. .ivsize = DES3_EDE_BLOCK_SIZE,
  1726. },
  1727. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  1728. },
  1729. {
  1730. .name = "cbc(des)",
  1731. .driver_name = "cbc-des-caam",
  1732. .blocksize = DES_BLOCK_SIZE,
  1733. .type = CRYPTO_ALG_TYPE_GIVCIPHER,
  1734. .template_ablkcipher = {
  1735. .setkey = ablkcipher_setkey,
  1736. .encrypt = ablkcipher_encrypt,
  1737. .decrypt = ablkcipher_decrypt,
  1738. .givencrypt = ablkcipher_givencrypt,
  1739. .geniv = "<built-in>",
  1740. .min_keysize = DES_KEY_SIZE,
  1741. .max_keysize = DES_KEY_SIZE,
  1742. .ivsize = DES_BLOCK_SIZE,
  1743. },
  1744. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  1745. },
  1746. {
  1747. .name = "ctr(aes)",
  1748. .driver_name = "ctr-aes-caam",
  1749. .blocksize = 1,
  1750. .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
  1751. .template_ablkcipher = {
  1752. .setkey = ablkcipher_setkey,
  1753. .encrypt = ablkcipher_encrypt,
  1754. .decrypt = ablkcipher_decrypt,
  1755. .geniv = "chainiv",
  1756. .min_keysize = AES_MIN_KEY_SIZE,
  1757. .max_keysize = AES_MAX_KEY_SIZE,
  1758. .ivsize = AES_BLOCK_SIZE,
  1759. },
  1760. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128,
  1761. },
  1762. {
  1763. .name = "rfc3686(ctr(aes))",
  1764. .driver_name = "rfc3686-ctr-aes-caam",
  1765. .blocksize = 1,
  1766. .type = CRYPTO_ALG_TYPE_GIVCIPHER,
  1767. .template_ablkcipher = {
  1768. .setkey = ablkcipher_setkey,
  1769. .encrypt = ablkcipher_encrypt,
  1770. .decrypt = ablkcipher_decrypt,
  1771. .givencrypt = ablkcipher_givencrypt,
  1772. .geniv = "<built-in>",
  1773. .min_keysize = AES_MIN_KEY_SIZE +
  1774. CTR_RFC3686_NONCE_SIZE,
  1775. .max_keysize = AES_MAX_KEY_SIZE +
  1776. CTR_RFC3686_NONCE_SIZE,
  1777. .ivsize = CTR_RFC3686_IV_SIZE,
  1778. },
  1779. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128,
  1780. },
  1781. {
  1782. .name = "xts(aes)",
  1783. .driver_name = "xts-aes-caam",
  1784. .blocksize = AES_BLOCK_SIZE,
  1785. .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
  1786. .template_ablkcipher = {
  1787. .setkey = xts_ablkcipher_setkey,
  1788. .encrypt = ablkcipher_encrypt,
  1789. .decrypt = ablkcipher_decrypt,
  1790. .geniv = "eseqiv",
  1791. .min_keysize = 2 * AES_MIN_KEY_SIZE,
  1792. .max_keysize = 2 * AES_MAX_KEY_SIZE,
  1793. .ivsize = AES_BLOCK_SIZE,
  1794. },
  1795. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_XTS,
  1796. },
  1797. };
  1798. static struct caam_aead_alg driver_aeads[] = {
  1799. {
  1800. .aead = {
  1801. .base = {
  1802. .cra_name = "rfc4106(gcm(aes))",
  1803. .cra_driver_name = "rfc4106-gcm-aes-caam",
  1804. .cra_blocksize = 1,
  1805. },
  1806. .setkey = rfc4106_setkey,
  1807. .setauthsize = rfc4106_setauthsize,
  1808. .encrypt = ipsec_gcm_encrypt,
  1809. .decrypt = ipsec_gcm_decrypt,
  1810. .ivsize = 8,
  1811. .maxauthsize = AES_BLOCK_SIZE,
  1812. },
  1813. .caam = {
  1814. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
  1815. },
  1816. },
  1817. {
  1818. .aead = {
  1819. .base = {
  1820. .cra_name = "rfc4543(gcm(aes))",
  1821. .cra_driver_name = "rfc4543-gcm-aes-caam",
  1822. .cra_blocksize = 1,
  1823. },
  1824. .setkey = rfc4543_setkey,
  1825. .setauthsize = rfc4543_setauthsize,
  1826. .encrypt = ipsec_gcm_encrypt,
  1827. .decrypt = ipsec_gcm_decrypt,
  1828. .ivsize = 8,
  1829. .maxauthsize = AES_BLOCK_SIZE,
  1830. },
  1831. .caam = {
  1832. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
  1833. },
  1834. },
  1835. /* Galois Counter Mode */
  1836. {
  1837. .aead = {
  1838. .base = {
  1839. .cra_name = "gcm(aes)",
  1840. .cra_driver_name = "gcm-aes-caam",
  1841. .cra_blocksize = 1,
  1842. },
  1843. .setkey = gcm_setkey,
  1844. .setauthsize = gcm_setauthsize,
  1845. .encrypt = gcm_encrypt,
  1846. .decrypt = gcm_decrypt,
  1847. .ivsize = 12,
  1848. .maxauthsize = AES_BLOCK_SIZE,
  1849. },
  1850. .caam = {
  1851. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
  1852. },
  1853. },
  1854. /* single-pass ipsec_esp descriptor */
  1855. {
  1856. .aead = {
  1857. .base = {
  1858. .cra_name = "authenc(hmac(md5),"
  1859. "ecb(cipher_null))",
  1860. .cra_driver_name = "authenc-hmac-md5-"
  1861. "ecb-cipher_null-caam",
  1862. .cra_blocksize = NULL_BLOCK_SIZE,
  1863. },
  1864. .setkey = aead_setkey,
  1865. .setauthsize = aead_setauthsize,
  1866. .encrypt = aead_encrypt,
  1867. .decrypt = aead_decrypt,
  1868. .ivsize = NULL_IV_SIZE,
  1869. .maxauthsize = MD5_DIGEST_SIZE,
  1870. },
  1871. .caam = {
  1872. .class2_alg_type = OP_ALG_ALGSEL_MD5 |
  1873. OP_ALG_AAI_HMAC_PRECOMP,
  1874. },
  1875. },
  1876. {
  1877. .aead = {
  1878. .base = {
  1879. .cra_name = "authenc(hmac(sha1),"
  1880. "ecb(cipher_null))",
  1881. .cra_driver_name = "authenc-hmac-sha1-"
  1882. "ecb-cipher_null-caam",
  1883. .cra_blocksize = NULL_BLOCK_SIZE,
  1884. },
  1885. .setkey = aead_setkey,
  1886. .setauthsize = aead_setauthsize,
  1887. .encrypt = aead_encrypt,
  1888. .decrypt = aead_decrypt,
  1889. .ivsize = NULL_IV_SIZE,
  1890. .maxauthsize = SHA1_DIGEST_SIZE,
  1891. },
  1892. .caam = {
  1893. .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
  1894. OP_ALG_AAI_HMAC_PRECOMP,
  1895. },
  1896. },
  1897. {
  1898. .aead = {
  1899. .base = {
  1900. .cra_name = "authenc(hmac(sha224),"
  1901. "ecb(cipher_null))",
  1902. .cra_driver_name = "authenc-hmac-sha224-"
  1903. "ecb-cipher_null-caam",
  1904. .cra_blocksize = NULL_BLOCK_SIZE,
  1905. },
  1906. .setkey = aead_setkey,
  1907. .setauthsize = aead_setauthsize,
  1908. .encrypt = aead_encrypt,
  1909. .decrypt = aead_decrypt,
  1910. .ivsize = NULL_IV_SIZE,
  1911. .maxauthsize = SHA224_DIGEST_SIZE,
  1912. },
  1913. .caam = {
  1914. .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
  1915. OP_ALG_AAI_HMAC_PRECOMP,
  1916. },
  1917. },
  1918. {
  1919. .aead = {
  1920. .base = {
  1921. .cra_name = "authenc(hmac(sha256),"
  1922. "ecb(cipher_null))",
  1923. .cra_driver_name = "authenc-hmac-sha256-"
  1924. "ecb-cipher_null-caam",
  1925. .cra_blocksize = NULL_BLOCK_SIZE,
  1926. },
  1927. .setkey = aead_setkey,
  1928. .setauthsize = aead_setauthsize,
  1929. .encrypt = aead_encrypt,
  1930. .decrypt = aead_decrypt,
  1931. .ivsize = NULL_IV_SIZE,
  1932. .maxauthsize = SHA256_DIGEST_SIZE,
  1933. },
  1934. .caam = {
  1935. .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
  1936. OP_ALG_AAI_HMAC_PRECOMP,
  1937. },
  1938. },
  1939. {
  1940. .aead = {
  1941. .base = {
  1942. .cra_name = "authenc(hmac(sha384),"
  1943. "ecb(cipher_null))",
  1944. .cra_driver_name = "authenc-hmac-sha384-"
  1945. "ecb-cipher_null-caam",
  1946. .cra_blocksize = NULL_BLOCK_SIZE,
  1947. },
  1948. .setkey = aead_setkey,
  1949. .setauthsize = aead_setauthsize,
  1950. .encrypt = aead_encrypt,
  1951. .decrypt = aead_decrypt,
  1952. .ivsize = NULL_IV_SIZE,
  1953. .maxauthsize = SHA384_DIGEST_SIZE,
  1954. },
  1955. .caam = {
  1956. .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
  1957. OP_ALG_AAI_HMAC_PRECOMP,
  1958. },
  1959. },
  1960. {
  1961. .aead = {
  1962. .base = {
  1963. .cra_name = "authenc(hmac(sha512),"
  1964. "ecb(cipher_null))",
  1965. .cra_driver_name = "authenc-hmac-sha512-"
  1966. "ecb-cipher_null-caam",
  1967. .cra_blocksize = NULL_BLOCK_SIZE,
  1968. },
  1969. .setkey = aead_setkey,
  1970. .setauthsize = aead_setauthsize,
  1971. .encrypt = aead_encrypt,
  1972. .decrypt = aead_decrypt,
  1973. .ivsize = NULL_IV_SIZE,
  1974. .maxauthsize = SHA512_DIGEST_SIZE,
  1975. },
  1976. .caam = {
  1977. .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
  1978. OP_ALG_AAI_HMAC_PRECOMP,
  1979. },
  1980. },
  1981. {
  1982. .aead = {
  1983. .base = {
  1984. .cra_name = "authenc(hmac(md5),cbc(aes))",
  1985. .cra_driver_name = "authenc-hmac-md5-"
  1986. "cbc-aes-caam",
  1987. .cra_blocksize = AES_BLOCK_SIZE,
  1988. },
  1989. .setkey = aead_setkey,
  1990. .setauthsize = aead_setauthsize,
  1991. .encrypt = aead_encrypt,
  1992. .decrypt = aead_decrypt,
  1993. .ivsize = AES_BLOCK_SIZE,
  1994. .maxauthsize = MD5_DIGEST_SIZE,
  1995. },
  1996. .caam = {
  1997. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  1998. .class2_alg_type = OP_ALG_ALGSEL_MD5 |
  1999. OP_ALG_AAI_HMAC_PRECOMP,
  2000. },
  2001. },
  2002. {
  2003. .aead = {
  2004. .base = {
  2005. .cra_name = "echainiv(authenc(hmac(md5),"
  2006. "cbc(aes)))",
  2007. .cra_driver_name = "echainiv-authenc-hmac-md5-"
  2008. "cbc-aes-caam",
  2009. .cra_blocksize = AES_BLOCK_SIZE,
  2010. },
  2011. .setkey = aead_setkey,
  2012. .setauthsize = aead_setauthsize,
  2013. .encrypt = aead_encrypt,
  2014. .decrypt = aead_decrypt,
  2015. .ivsize = AES_BLOCK_SIZE,
  2016. .maxauthsize = MD5_DIGEST_SIZE,
  2017. },
  2018. .caam = {
  2019. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  2020. .class2_alg_type = OP_ALG_ALGSEL_MD5 |
  2021. OP_ALG_AAI_HMAC_PRECOMP,
  2022. .geniv = true,
  2023. },
  2024. },
  2025. {
  2026. .aead = {
  2027. .base = {
  2028. .cra_name = "authenc(hmac(sha1),cbc(aes))",
  2029. .cra_driver_name = "authenc-hmac-sha1-"
  2030. "cbc-aes-caam",
  2031. .cra_blocksize = AES_BLOCK_SIZE,
  2032. },
  2033. .setkey = aead_setkey,
  2034. .setauthsize = aead_setauthsize,
  2035. .encrypt = aead_encrypt,
  2036. .decrypt = aead_decrypt,
  2037. .ivsize = AES_BLOCK_SIZE,
  2038. .maxauthsize = SHA1_DIGEST_SIZE,
  2039. },
  2040. .caam = {
  2041. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  2042. .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
  2043. OP_ALG_AAI_HMAC_PRECOMP,
  2044. },
  2045. },
  2046. {
  2047. .aead = {
  2048. .base = {
  2049. .cra_name = "echainiv(authenc(hmac(sha1),"
  2050. "cbc(aes)))",
  2051. .cra_driver_name = "echainiv-authenc-"
  2052. "hmac-sha1-cbc-aes-caam",
  2053. .cra_blocksize = AES_BLOCK_SIZE,
  2054. },
  2055. .setkey = aead_setkey,
  2056. .setauthsize = aead_setauthsize,
  2057. .encrypt = aead_encrypt,
  2058. .decrypt = aead_decrypt,
  2059. .ivsize = AES_BLOCK_SIZE,
  2060. .maxauthsize = SHA1_DIGEST_SIZE,
  2061. },
  2062. .caam = {
  2063. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  2064. .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
  2065. OP_ALG_AAI_HMAC_PRECOMP,
  2066. .geniv = true,
  2067. },
  2068. },
  2069. {
  2070. .aead = {
  2071. .base = {
  2072. .cra_name = "authenc(hmac(sha224),cbc(aes))",
  2073. .cra_driver_name = "authenc-hmac-sha224-"
  2074. "cbc-aes-caam",
  2075. .cra_blocksize = AES_BLOCK_SIZE,
  2076. },
  2077. .setkey = aead_setkey,
  2078. .setauthsize = aead_setauthsize,
  2079. .encrypt = aead_encrypt,
  2080. .decrypt = aead_decrypt,
  2081. .ivsize = AES_BLOCK_SIZE,
  2082. .maxauthsize = SHA224_DIGEST_SIZE,
  2083. },
  2084. .caam = {
  2085. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  2086. .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
  2087. OP_ALG_AAI_HMAC_PRECOMP,
  2088. },
  2089. },
  2090. {
  2091. .aead = {
  2092. .base = {
  2093. .cra_name = "echainiv(authenc(hmac(sha224),"
  2094. "cbc(aes)))",
  2095. .cra_driver_name = "echainiv-authenc-"
  2096. "hmac-sha224-cbc-aes-caam",
  2097. .cra_blocksize = AES_BLOCK_SIZE,
  2098. },
  2099. .setkey = aead_setkey,
  2100. .setauthsize = aead_setauthsize,
  2101. .encrypt = aead_encrypt,
  2102. .decrypt = aead_decrypt,
  2103. .ivsize = AES_BLOCK_SIZE,
  2104. .maxauthsize = SHA224_DIGEST_SIZE,
  2105. },
  2106. .caam = {
  2107. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  2108. .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
  2109. OP_ALG_AAI_HMAC_PRECOMP,
  2110. .geniv = true,
  2111. },
  2112. },
  2113. {
  2114. .aead = {
  2115. .base = {
  2116. .cra_name = "authenc(hmac(sha256),cbc(aes))",
  2117. .cra_driver_name = "authenc-hmac-sha256-"
  2118. "cbc-aes-caam",
  2119. .cra_blocksize = AES_BLOCK_SIZE,
  2120. },
  2121. .setkey = aead_setkey,
  2122. .setauthsize = aead_setauthsize,
  2123. .encrypt = aead_encrypt,
  2124. .decrypt = aead_decrypt,
  2125. .ivsize = AES_BLOCK_SIZE,
  2126. .maxauthsize = SHA256_DIGEST_SIZE,
  2127. },
  2128. .caam = {
  2129. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  2130. .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
  2131. OP_ALG_AAI_HMAC_PRECOMP,
  2132. },
  2133. },
  2134. {
  2135. .aead = {
  2136. .base = {
  2137. .cra_name = "echainiv(authenc(hmac(sha256),"
  2138. "cbc(aes)))",
  2139. .cra_driver_name = "echainiv-authenc-"
  2140. "hmac-sha256-cbc-aes-caam",
  2141. .cra_blocksize = AES_BLOCK_SIZE,
  2142. },
  2143. .setkey = aead_setkey,
  2144. .setauthsize = aead_setauthsize,
  2145. .encrypt = aead_encrypt,
  2146. .decrypt = aead_decrypt,
  2147. .ivsize = AES_BLOCK_SIZE,
  2148. .maxauthsize = SHA256_DIGEST_SIZE,
  2149. },
  2150. .caam = {
  2151. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  2152. .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
  2153. OP_ALG_AAI_HMAC_PRECOMP,
  2154. .geniv = true,
  2155. },
  2156. },
  2157. {
  2158. .aead = {
  2159. .base = {
  2160. .cra_name = "authenc(hmac(sha384),cbc(aes))",
  2161. .cra_driver_name = "authenc-hmac-sha384-"
  2162. "cbc-aes-caam",
  2163. .cra_blocksize = AES_BLOCK_SIZE,
  2164. },
  2165. .setkey = aead_setkey,
  2166. .setauthsize = aead_setauthsize,
  2167. .encrypt = aead_encrypt,
  2168. .decrypt = aead_decrypt,
  2169. .ivsize = AES_BLOCK_SIZE,
  2170. .maxauthsize = SHA384_DIGEST_SIZE,
  2171. },
  2172. .caam = {
  2173. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  2174. .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
  2175. OP_ALG_AAI_HMAC_PRECOMP,
  2176. },
  2177. },
  2178. {
  2179. .aead = {
  2180. .base = {
  2181. .cra_name = "echainiv(authenc(hmac(sha384),"
  2182. "cbc(aes)))",
  2183. .cra_driver_name = "echainiv-authenc-"
  2184. "hmac-sha384-cbc-aes-caam",
  2185. .cra_blocksize = AES_BLOCK_SIZE,
  2186. },
  2187. .setkey = aead_setkey,
  2188. .setauthsize = aead_setauthsize,
  2189. .encrypt = aead_encrypt,
  2190. .decrypt = aead_decrypt,
  2191. .ivsize = AES_BLOCK_SIZE,
  2192. .maxauthsize = SHA384_DIGEST_SIZE,
  2193. },
  2194. .caam = {
  2195. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  2196. .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
  2197. OP_ALG_AAI_HMAC_PRECOMP,
  2198. .geniv = true,
  2199. },
  2200. },
  2201. {
  2202. .aead = {
  2203. .base = {
  2204. .cra_name = "authenc(hmac(sha512),cbc(aes))",
  2205. .cra_driver_name = "authenc-hmac-sha512-"
  2206. "cbc-aes-caam",
  2207. .cra_blocksize = AES_BLOCK_SIZE,
  2208. },
  2209. .setkey = aead_setkey,
  2210. .setauthsize = aead_setauthsize,
  2211. .encrypt = aead_encrypt,
  2212. .decrypt = aead_decrypt,
  2213. .ivsize = AES_BLOCK_SIZE,
  2214. .maxauthsize = SHA512_DIGEST_SIZE,
  2215. },
  2216. .caam = {
  2217. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  2218. .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
  2219. OP_ALG_AAI_HMAC_PRECOMP,
  2220. },
  2221. },
  2222. {
  2223. .aead = {
  2224. .base = {
  2225. .cra_name = "echainiv(authenc(hmac(sha512),"
  2226. "cbc(aes)))",
  2227. .cra_driver_name = "echainiv-authenc-"
  2228. "hmac-sha512-cbc-aes-caam",
  2229. .cra_blocksize = AES_BLOCK_SIZE,
  2230. },
  2231. .setkey = aead_setkey,
  2232. .setauthsize = aead_setauthsize,
  2233. .encrypt = aead_encrypt,
  2234. .decrypt = aead_decrypt,
  2235. .ivsize = AES_BLOCK_SIZE,
  2236. .maxauthsize = SHA512_DIGEST_SIZE,
  2237. },
  2238. .caam = {
  2239. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  2240. .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
  2241. OP_ALG_AAI_HMAC_PRECOMP,
  2242. .geniv = true,
  2243. },
  2244. },
  2245. {
  2246. .aead = {
  2247. .base = {
  2248. .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
  2249. .cra_driver_name = "authenc-hmac-md5-"
  2250. "cbc-des3_ede-caam",
  2251. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  2252. },
  2253. .setkey = aead_setkey,
  2254. .setauthsize = aead_setauthsize,
  2255. .encrypt = aead_encrypt,
  2256. .decrypt = aead_decrypt,
  2257. .ivsize = DES3_EDE_BLOCK_SIZE,
  2258. .maxauthsize = MD5_DIGEST_SIZE,
  2259. },
  2260. .caam = {
  2261. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  2262. .class2_alg_type = OP_ALG_ALGSEL_MD5 |
  2263. OP_ALG_AAI_HMAC_PRECOMP,
  2264. }
  2265. },
  2266. {
  2267. .aead = {
  2268. .base = {
  2269. .cra_name = "echainiv(authenc(hmac(md5),"
  2270. "cbc(des3_ede)))",
  2271. .cra_driver_name = "echainiv-authenc-hmac-md5-"
  2272. "cbc-des3_ede-caam",
  2273. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  2274. },
  2275. .setkey = aead_setkey,
  2276. .setauthsize = aead_setauthsize,
  2277. .encrypt = aead_encrypt,
  2278. .decrypt = aead_decrypt,
  2279. .ivsize = DES3_EDE_BLOCK_SIZE,
  2280. .maxauthsize = MD5_DIGEST_SIZE,
  2281. },
  2282. .caam = {
  2283. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  2284. .class2_alg_type = OP_ALG_ALGSEL_MD5 |
  2285. OP_ALG_AAI_HMAC_PRECOMP,
  2286. .geniv = true,
  2287. }
  2288. },
  2289. {
  2290. .aead = {
  2291. .base = {
  2292. .cra_name = "authenc(hmac(sha1),"
  2293. "cbc(des3_ede))",
  2294. .cra_driver_name = "authenc-hmac-sha1-"
  2295. "cbc-des3_ede-caam",
  2296. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  2297. },
  2298. .setkey = aead_setkey,
  2299. .setauthsize = aead_setauthsize,
  2300. .encrypt = aead_encrypt,
  2301. .decrypt = aead_decrypt,
  2302. .ivsize = DES3_EDE_BLOCK_SIZE,
  2303. .maxauthsize = SHA1_DIGEST_SIZE,
  2304. },
  2305. .caam = {
  2306. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  2307. .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
  2308. OP_ALG_AAI_HMAC_PRECOMP,
  2309. },
  2310. },
  2311. {
  2312. .aead = {
  2313. .base = {
  2314. .cra_name = "echainiv(authenc(hmac(sha1),"
  2315. "cbc(des3_ede)))",
  2316. .cra_driver_name = "echainiv-authenc-"
  2317. "hmac-sha1-"
  2318. "cbc-des3_ede-caam",
  2319. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  2320. },
  2321. .setkey = aead_setkey,
  2322. .setauthsize = aead_setauthsize,
  2323. .encrypt = aead_encrypt,
  2324. .decrypt = aead_decrypt,
  2325. .ivsize = DES3_EDE_BLOCK_SIZE,
  2326. .maxauthsize = SHA1_DIGEST_SIZE,
  2327. },
  2328. .caam = {
  2329. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  2330. .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
  2331. OP_ALG_AAI_HMAC_PRECOMP,
  2332. .geniv = true,
  2333. },
  2334. },
  2335. {
  2336. .aead = {
  2337. .base = {
  2338. .cra_name = "authenc(hmac(sha224),"
  2339. "cbc(des3_ede))",
  2340. .cra_driver_name = "authenc-hmac-sha224-"
  2341. "cbc-des3_ede-caam",
  2342. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  2343. },
  2344. .setkey = aead_setkey,
  2345. .setauthsize = aead_setauthsize,
  2346. .encrypt = aead_encrypt,
  2347. .decrypt = aead_decrypt,
  2348. .ivsize = DES3_EDE_BLOCK_SIZE,
  2349. .maxauthsize = SHA224_DIGEST_SIZE,
  2350. },
  2351. .caam = {
  2352. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  2353. .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
  2354. OP_ALG_AAI_HMAC_PRECOMP,
  2355. },
  2356. },
  2357. {
  2358. .aead = {
  2359. .base = {
  2360. .cra_name = "echainiv(authenc(hmac(sha224),"
  2361. "cbc(des3_ede)))",
  2362. .cra_driver_name = "echainiv-authenc-"
  2363. "hmac-sha224-"
  2364. "cbc-des3_ede-caam",
  2365. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  2366. },
  2367. .setkey = aead_setkey,
  2368. .setauthsize = aead_setauthsize,
  2369. .encrypt = aead_encrypt,
  2370. .decrypt = aead_decrypt,
  2371. .ivsize = DES3_EDE_BLOCK_SIZE,
  2372. .maxauthsize = SHA224_DIGEST_SIZE,
  2373. },
  2374. .caam = {
  2375. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  2376. .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
  2377. OP_ALG_AAI_HMAC_PRECOMP,
  2378. .geniv = true,
  2379. },
  2380. },
  2381. {
  2382. .aead = {
  2383. .base = {
  2384. .cra_name = "authenc(hmac(sha256),"
  2385. "cbc(des3_ede))",
  2386. .cra_driver_name = "authenc-hmac-sha256-"
  2387. "cbc-des3_ede-caam",
  2388. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  2389. },
  2390. .setkey = aead_setkey,
  2391. .setauthsize = aead_setauthsize,
  2392. .encrypt = aead_encrypt,
  2393. .decrypt = aead_decrypt,
  2394. .ivsize = DES3_EDE_BLOCK_SIZE,
  2395. .maxauthsize = SHA256_DIGEST_SIZE,
  2396. },
  2397. .caam = {
  2398. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  2399. .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
  2400. OP_ALG_AAI_HMAC_PRECOMP,
  2401. },
  2402. },
  2403. {
  2404. .aead = {
  2405. .base = {
  2406. .cra_name = "echainiv(authenc(hmac(sha256),"
  2407. "cbc(des3_ede)))",
  2408. .cra_driver_name = "echainiv-authenc-"
  2409. "hmac-sha256-"
  2410. "cbc-des3_ede-caam",
  2411. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  2412. },
  2413. .setkey = aead_setkey,
  2414. .setauthsize = aead_setauthsize,
  2415. .encrypt = aead_encrypt,
  2416. .decrypt = aead_decrypt,
  2417. .ivsize = DES3_EDE_BLOCK_SIZE,
  2418. .maxauthsize = SHA256_DIGEST_SIZE,
  2419. },
  2420. .caam = {
  2421. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  2422. .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
  2423. OP_ALG_AAI_HMAC_PRECOMP,
  2424. .geniv = true,
  2425. },
  2426. },
  2427. {
  2428. .aead = {
  2429. .base = {
  2430. .cra_name = "authenc(hmac(sha384),"
  2431. "cbc(des3_ede))",
  2432. .cra_driver_name = "authenc-hmac-sha384-"
  2433. "cbc-des3_ede-caam",
  2434. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  2435. },
  2436. .setkey = aead_setkey,
  2437. .setauthsize = aead_setauthsize,
  2438. .encrypt = aead_encrypt,
  2439. .decrypt = aead_decrypt,
  2440. .ivsize = DES3_EDE_BLOCK_SIZE,
  2441. .maxauthsize = SHA384_DIGEST_SIZE,
  2442. },
  2443. .caam = {
  2444. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  2445. .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
  2446. OP_ALG_AAI_HMAC_PRECOMP,
  2447. },
  2448. },
  2449. {
  2450. .aead = {
  2451. .base = {
  2452. .cra_name = "echainiv(authenc(hmac(sha384),"
  2453. "cbc(des3_ede)))",
  2454. .cra_driver_name = "echainiv-authenc-"
  2455. "hmac-sha384-"
  2456. "cbc-des3_ede-caam",
  2457. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  2458. },
  2459. .setkey = aead_setkey,
  2460. .setauthsize = aead_setauthsize,
  2461. .encrypt = aead_encrypt,
  2462. .decrypt = aead_decrypt,
  2463. .ivsize = DES3_EDE_BLOCK_SIZE,
  2464. .maxauthsize = SHA384_DIGEST_SIZE,
  2465. },
  2466. .caam = {
  2467. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  2468. .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
  2469. OP_ALG_AAI_HMAC_PRECOMP,
  2470. .geniv = true,
  2471. },
  2472. },
  2473. {
  2474. .aead = {
  2475. .base = {
  2476. .cra_name = "authenc(hmac(sha512),"
  2477. "cbc(des3_ede))",
  2478. .cra_driver_name = "authenc-hmac-sha512-"
  2479. "cbc-des3_ede-caam",
  2480. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  2481. },
  2482. .setkey = aead_setkey,
  2483. .setauthsize = aead_setauthsize,
  2484. .encrypt = aead_encrypt,
  2485. .decrypt = aead_decrypt,
  2486. .ivsize = DES3_EDE_BLOCK_SIZE,
  2487. .maxauthsize = SHA512_DIGEST_SIZE,
  2488. },
  2489. .caam = {
  2490. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  2491. .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
  2492. OP_ALG_AAI_HMAC_PRECOMP,
  2493. },
  2494. },
  2495. {
  2496. .aead = {
  2497. .base = {
  2498. .cra_name = "echainiv(authenc(hmac(sha512),"
  2499. "cbc(des3_ede)))",
  2500. .cra_driver_name = "echainiv-authenc-"
  2501. "hmac-sha512-"
  2502. "cbc-des3_ede-caam",
  2503. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  2504. },
  2505. .setkey = aead_setkey,
  2506. .setauthsize = aead_setauthsize,
  2507. .encrypt = aead_encrypt,
  2508. .decrypt = aead_decrypt,
  2509. .ivsize = DES3_EDE_BLOCK_SIZE,
  2510. .maxauthsize = SHA512_DIGEST_SIZE,
  2511. },
  2512. .caam = {
  2513. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  2514. .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
  2515. OP_ALG_AAI_HMAC_PRECOMP,
  2516. .geniv = true,
  2517. },
  2518. },
  2519. {
  2520. .aead = {
  2521. .base = {
  2522. .cra_name = "authenc(hmac(md5),cbc(des))",
  2523. .cra_driver_name = "authenc-hmac-md5-"
  2524. "cbc-des-caam",
  2525. .cra_blocksize = DES_BLOCK_SIZE,
  2526. },
  2527. .setkey = aead_setkey,
  2528. .setauthsize = aead_setauthsize,
  2529. .encrypt = aead_encrypt,
  2530. .decrypt = aead_decrypt,
  2531. .ivsize = DES_BLOCK_SIZE,
  2532. .maxauthsize = MD5_DIGEST_SIZE,
  2533. },
  2534. .caam = {
  2535. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  2536. .class2_alg_type = OP_ALG_ALGSEL_MD5 |
  2537. OP_ALG_AAI_HMAC_PRECOMP,
  2538. },
  2539. },
  2540. {
  2541. .aead = {
  2542. .base = {
  2543. .cra_name = "echainiv(authenc(hmac(md5),"
  2544. "cbc(des)))",
  2545. .cra_driver_name = "echainiv-authenc-hmac-md5-"
  2546. "cbc-des-caam",
  2547. .cra_blocksize = DES_BLOCK_SIZE,
  2548. },
  2549. .setkey = aead_setkey,
  2550. .setauthsize = aead_setauthsize,
  2551. .encrypt = aead_encrypt,
  2552. .decrypt = aead_decrypt,
  2553. .ivsize = DES_BLOCK_SIZE,
  2554. .maxauthsize = MD5_DIGEST_SIZE,
  2555. },
  2556. .caam = {
  2557. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  2558. .class2_alg_type = OP_ALG_ALGSEL_MD5 |
  2559. OP_ALG_AAI_HMAC_PRECOMP,
  2560. .geniv = true,
  2561. },
  2562. },
  2563. {
  2564. .aead = {
  2565. .base = {
  2566. .cra_name = "authenc(hmac(sha1),cbc(des))",
  2567. .cra_driver_name = "authenc-hmac-sha1-"
  2568. "cbc-des-caam",
  2569. .cra_blocksize = DES_BLOCK_SIZE,
  2570. },
  2571. .setkey = aead_setkey,
  2572. .setauthsize = aead_setauthsize,
  2573. .encrypt = aead_encrypt,
  2574. .decrypt = aead_decrypt,
  2575. .ivsize = DES_BLOCK_SIZE,
  2576. .maxauthsize = SHA1_DIGEST_SIZE,
  2577. },
  2578. .caam = {
  2579. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  2580. .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
  2581. OP_ALG_AAI_HMAC_PRECOMP,
  2582. },
  2583. },
  2584. {
  2585. .aead = {
  2586. .base = {
  2587. .cra_name = "echainiv(authenc(hmac(sha1),"
  2588. "cbc(des)))",
  2589. .cra_driver_name = "echainiv-authenc-"
  2590. "hmac-sha1-cbc-des-caam",
  2591. .cra_blocksize = DES_BLOCK_SIZE,
  2592. },
  2593. .setkey = aead_setkey,
  2594. .setauthsize = aead_setauthsize,
  2595. .encrypt = aead_encrypt,
  2596. .decrypt = aead_decrypt,
  2597. .ivsize = DES_BLOCK_SIZE,
  2598. .maxauthsize = SHA1_DIGEST_SIZE,
  2599. },
  2600. .caam = {
  2601. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  2602. .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
  2603. OP_ALG_AAI_HMAC_PRECOMP,
  2604. .geniv = true,
  2605. },
  2606. },
  2607. {
  2608. .aead = {
  2609. .base = {
  2610. .cra_name = "authenc(hmac(sha224),cbc(des))",
  2611. .cra_driver_name = "authenc-hmac-sha224-"
  2612. "cbc-des-caam",
  2613. .cra_blocksize = DES_BLOCK_SIZE,
  2614. },
  2615. .setkey = aead_setkey,
  2616. .setauthsize = aead_setauthsize,
  2617. .encrypt = aead_encrypt,
  2618. .decrypt = aead_decrypt,
  2619. .ivsize = DES_BLOCK_SIZE,
  2620. .maxauthsize = SHA224_DIGEST_SIZE,
  2621. },
  2622. .caam = {
  2623. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  2624. .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
  2625. OP_ALG_AAI_HMAC_PRECOMP,
  2626. },
  2627. },
  2628. {
  2629. .aead = {
  2630. .base = {
  2631. .cra_name = "echainiv(authenc(hmac(sha224),"
  2632. "cbc(des)))",
  2633. .cra_driver_name = "echainiv-authenc-"
  2634. "hmac-sha224-cbc-des-caam",
  2635. .cra_blocksize = DES_BLOCK_SIZE,
  2636. },
  2637. .setkey = aead_setkey,
  2638. .setauthsize = aead_setauthsize,
  2639. .encrypt = aead_encrypt,
  2640. .decrypt = aead_decrypt,
  2641. .ivsize = DES_BLOCK_SIZE,
  2642. .maxauthsize = SHA224_DIGEST_SIZE,
  2643. },
  2644. .caam = {
  2645. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  2646. .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
  2647. OP_ALG_AAI_HMAC_PRECOMP,
  2648. .geniv = true,
  2649. },
  2650. },
  2651. {
  2652. .aead = {
  2653. .base = {
  2654. .cra_name = "authenc(hmac(sha256),cbc(des))",
  2655. .cra_driver_name = "authenc-hmac-sha256-"
  2656. "cbc-des-caam",
  2657. .cra_blocksize = DES_BLOCK_SIZE,
  2658. },
  2659. .setkey = aead_setkey,
  2660. .setauthsize = aead_setauthsize,
  2661. .encrypt = aead_encrypt,
  2662. .decrypt = aead_decrypt,
  2663. .ivsize = DES_BLOCK_SIZE,
  2664. .maxauthsize = SHA256_DIGEST_SIZE,
  2665. },
  2666. .caam = {
  2667. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  2668. .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
  2669. OP_ALG_AAI_HMAC_PRECOMP,
  2670. },
  2671. },
  2672. {
  2673. .aead = {
  2674. .base = {
  2675. .cra_name = "echainiv(authenc(hmac(sha256),"
  2676. "cbc(des)))",
  2677. .cra_driver_name = "echainiv-authenc-"
  2678. "hmac-sha256-cbc-des-caam",
  2679. .cra_blocksize = DES_BLOCK_SIZE,
  2680. },
  2681. .setkey = aead_setkey,
  2682. .setauthsize = aead_setauthsize,
  2683. .encrypt = aead_encrypt,
  2684. .decrypt = aead_decrypt,
  2685. .ivsize = DES_BLOCK_SIZE,
  2686. .maxauthsize = SHA256_DIGEST_SIZE,
  2687. },
  2688. .caam = {
  2689. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  2690. .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
  2691. OP_ALG_AAI_HMAC_PRECOMP,
  2692. .geniv = true,
  2693. },
  2694. },
  2695. {
  2696. .aead = {
  2697. .base = {
  2698. .cra_name = "authenc(hmac(sha384),cbc(des))",
  2699. .cra_driver_name = "authenc-hmac-sha384-"
  2700. "cbc-des-caam",
  2701. .cra_blocksize = DES_BLOCK_SIZE,
  2702. },
  2703. .setkey = aead_setkey,
  2704. .setauthsize = aead_setauthsize,
  2705. .encrypt = aead_encrypt,
  2706. .decrypt = aead_decrypt,
  2707. .ivsize = DES_BLOCK_SIZE,
  2708. .maxauthsize = SHA384_DIGEST_SIZE,
  2709. },
  2710. .caam = {
  2711. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  2712. .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
  2713. OP_ALG_AAI_HMAC_PRECOMP,
  2714. },
  2715. },
  2716. {
  2717. .aead = {
  2718. .base = {
  2719. .cra_name = "echainiv(authenc(hmac(sha384),"
  2720. "cbc(des)))",
  2721. .cra_driver_name = "echainiv-authenc-"
  2722. "hmac-sha384-cbc-des-caam",
  2723. .cra_blocksize = DES_BLOCK_SIZE,
  2724. },
  2725. .setkey = aead_setkey,
  2726. .setauthsize = aead_setauthsize,
  2727. .encrypt = aead_encrypt,
  2728. .decrypt = aead_decrypt,
  2729. .ivsize = DES_BLOCK_SIZE,
  2730. .maxauthsize = SHA384_DIGEST_SIZE,
  2731. },
  2732. .caam = {
  2733. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  2734. .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
  2735. OP_ALG_AAI_HMAC_PRECOMP,
  2736. .geniv = true,
  2737. },
  2738. },
  2739. {
  2740. .aead = {
  2741. .base = {
  2742. .cra_name = "authenc(hmac(sha512),cbc(des))",
  2743. .cra_driver_name = "authenc-hmac-sha512-"
  2744. "cbc-des-caam",
  2745. .cra_blocksize = DES_BLOCK_SIZE,
  2746. },
  2747. .setkey = aead_setkey,
  2748. .setauthsize = aead_setauthsize,
  2749. .encrypt = aead_encrypt,
  2750. .decrypt = aead_decrypt,
  2751. .ivsize = DES_BLOCK_SIZE,
  2752. .maxauthsize = SHA512_DIGEST_SIZE,
  2753. },
  2754. .caam = {
  2755. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  2756. .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
  2757. OP_ALG_AAI_HMAC_PRECOMP,
  2758. },
  2759. },
  2760. {
  2761. .aead = {
  2762. .base = {
  2763. .cra_name = "echainiv(authenc(hmac(sha512),"
  2764. "cbc(des)))",
  2765. .cra_driver_name = "echainiv-authenc-"
  2766. "hmac-sha512-cbc-des-caam",
  2767. .cra_blocksize = DES_BLOCK_SIZE,
  2768. },
  2769. .setkey = aead_setkey,
  2770. .setauthsize = aead_setauthsize,
  2771. .encrypt = aead_encrypt,
  2772. .decrypt = aead_decrypt,
  2773. .ivsize = DES_BLOCK_SIZE,
  2774. .maxauthsize = SHA512_DIGEST_SIZE,
  2775. },
  2776. .caam = {
  2777. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  2778. .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
  2779. OP_ALG_AAI_HMAC_PRECOMP,
  2780. .geniv = true,
  2781. },
  2782. },
  2783. {
  2784. .aead = {
  2785. .base = {
  2786. .cra_name = "authenc(hmac(md5),"
  2787. "rfc3686(ctr(aes)))",
  2788. .cra_driver_name = "authenc-hmac-md5-"
  2789. "rfc3686-ctr-aes-caam",
  2790. .cra_blocksize = 1,
  2791. },
  2792. .setkey = aead_setkey,
  2793. .setauthsize = aead_setauthsize,
  2794. .encrypt = aead_encrypt,
  2795. .decrypt = aead_decrypt,
  2796. .ivsize = CTR_RFC3686_IV_SIZE,
  2797. .maxauthsize = MD5_DIGEST_SIZE,
  2798. },
  2799. .caam = {
  2800. .class1_alg_type = OP_ALG_ALGSEL_AES |
  2801. OP_ALG_AAI_CTR_MOD128,
  2802. .class2_alg_type = OP_ALG_ALGSEL_MD5 |
  2803. OP_ALG_AAI_HMAC_PRECOMP,
  2804. .rfc3686 = true,
  2805. },
  2806. },
  2807. {
  2808. .aead = {
  2809. .base = {
  2810. .cra_name = "seqiv(authenc("
  2811. "hmac(md5),rfc3686(ctr(aes))))",
  2812. .cra_driver_name = "seqiv-authenc-hmac-md5-"
  2813. "rfc3686-ctr-aes-caam",
  2814. .cra_blocksize = 1,
  2815. },
  2816. .setkey = aead_setkey,
  2817. .setauthsize = aead_setauthsize,
  2818. .encrypt = aead_encrypt,
  2819. .decrypt = aead_decrypt,
  2820. .ivsize = CTR_RFC3686_IV_SIZE,
  2821. .maxauthsize = MD5_DIGEST_SIZE,
  2822. },
  2823. .caam = {
  2824. .class1_alg_type = OP_ALG_ALGSEL_AES |
  2825. OP_ALG_AAI_CTR_MOD128,
  2826. .class2_alg_type = OP_ALG_ALGSEL_MD5 |
  2827. OP_ALG_AAI_HMAC_PRECOMP,
  2828. .rfc3686 = true,
  2829. .geniv = true,
  2830. },
  2831. },
  2832. {
  2833. .aead = {
  2834. .base = {
  2835. .cra_name = "authenc(hmac(sha1),"
  2836. "rfc3686(ctr(aes)))",
  2837. .cra_driver_name = "authenc-hmac-sha1-"
  2838. "rfc3686-ctr-aes-caam",
  2839. .cra_blocksize = 1,
  2840. },
  2841. .setkey = aead_setkey,
  2842. .setauthsize = aead_setauthsize,
  2843. .encrypt = aead_encrypt,
  2844. .decrypt = aead_decrypt,
  2845. .ivsize = CTR_RFC3686_IV_SIZE,
  2846. .maxauthsize = SHA1_DIGEST_SIZE,
  2847. },
  2848. .caam = {
  2849. .class1_alg_type = OP_ALG_ALGSEL_AES |
  2850. OP_ALG_AAI_CTR_MOD128,
  2851. .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
  2852. OP_ALG_AAI_HMAC_PRECOMP,
  2853. .rfc3686 = true,
  2854. },
  2855. },
  2856. {
  2857. .aead = {
  2858. .base = {
  2859. .cra_name = "seqiv(authenc("
  2860. "hmac(sha1),rfc3686(ctr(aes))))",
  2861. .cra_driver_name = "seqiv-authenc-hmac-sha1-"
  2862. "rfc3686-ctr-aes-caam",
  2863. .cra_blocksize = 1,
  2864. },
  2865. .setkey = aead_setkey,
  2866. .setauthsize = aead_setauthsize,
  2867. .encrypt = aead_encrypt,
  2868. .decrypt = aead_decrypt,
  2869. .ivsize = CTR_RFC3686_IV_SIZE,
  2870. .maxauthsize = SHA1_DIGEST_SIZE,
  2871. },
  2872. .caam = {
  2873. .class1_alg_type = OP_ALG_ALGSEL_AES |
  2874. OP_ALG_AAI_CTR_MOD128,
  2875. .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
  2876. OP_ALG_AAI_HMAC_PRECOMP,
  2877. .rfc3686 = true,
  2878. .geniv = true,
  2879. },
  2880. },
  2881. {
  2882. .aead = {
  2883. .base = {
  2884. .cra_name = "authenc(hmac(sha224),"
  2885. "rfc3686(ctr(aes)))",
  2886. .cra_driver_name = "authenc-hmac-sha224-"
  2887. "rfc3686-ctr-aes-caam",
  2888. .cra_blocksize = 1,
  2889. },
  2890. .setkey = aead_setkey,
  2891. .setauthsize = aead_setauthsize,
  2892. .encrypt = aead_encrypt,
  2893. .decrypt = aead_decrypt,
  2894. .ivsize = CTR_RFC3686_IV_SIZE,
  2895. .maxauthsize = SHA224_DIGEST_SIZE,
  2896. },
  2897. .caam = {
  2898. .class1_alg_type = OP_ALG_ALGSEL_AES |
  2899. OP_ALG_AAI_CTR_MOD128,
  2900. .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
  2901. OP_ALG_AAI_HMAC_PRECOMP,
  2902. .rfc3686 = true,
  2903. },
  2904. },
  2905. {
  2906. .aead = {
  2907. .base = {
  2908. .cra_name = "seqiv(authenc("
  2909. "hmac(sha224),rfc3686(ctr(aes))))",
  2910. .cra_driver_name = "seqiv-authenc-hmac-sha224-"
  2911. "rfc3686-ctr-aes-caam",
  2912. .cra_blocksize = 1,
  2913. },
  2914. .setkey = aead_setkey,
  2915. .setauthsize = aead_setauthsize,
  2916. .encrypt = aead_encrypt,
  2917. .decrypt = aead_decrypt,
  2918. .ivsize = CTR_RFC3686_IV_SIZE,
  2919. .maxauthsize = SHA224_DIGEST_SIZE,
  2920. },
  2921. .caam = {
  2922. .class1_alg_type = OP_ALG_ALGSEL_AES |
  2923. OP_ALG_AAI_CTR_MOD128,
  2924. .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
  2925. OP_ALG_AAI_HMAC_PRECOMP,
  2926. .rfc3686 = true,
  2927. .geniv = true,
  2928. },
  2929. },
  2930. {
  2931. .aead = {
  2932. .base = {
  2933. .cra_name = "authenc(hmac(sha256),"
  2934. "rfc3686(ctr(aes)))",
  2935. .cra_driver_name = "authenc-hmac-sha256-"
  2936. "rfc3686-ctr-aes-caam",
  2937. .cra_blocksize = 1,
  2938. },
  2939. .setkey = aead_setkey,
  2940. .setauthsize = aead_setauthsize,
  2941. .encrypt = aead_encrypt,
  2942. .decrypt = aead_decrypt,
  2943. .ivsize = CTR_RFC3686_IV_SIZE,
  2944. .maxauthsize = SHA256_DIGEST_SIZE,
  2945. },
  2946. .caam = {
  2947. .class1_alg_type = OP_ALG_ALGSEL_AES |
  2948. OP_ALG_AAI_CTR_MOD128,
  2949. .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
  2950. OP_ALG_AAI_HMAC_PRECOMP,
  2951. .rfc3686 = true,
  2952. },
  2953. },
  2954. {
  2955. .aead = {
  2956. .base = {
  2957. .cra_name = "seqiv(authenc(hmac(sha256),"
  2958. "rfc3686(ctr(aes))))",
  2959. .cra_driver_name = "seqiv-authenc-hmac-sha256-"
  2960. "rfc3686-ctr-aes-caam",
  2961. .cra_blocksize = 1,
  2962. },
  2963. .setkey = aead_setkey,
  2964. .setauthsize = aead_setauthsize,
  2965. .encrypt = aead_encrypt,
  2966. .decrypt = aead_decrypt,
  2967. .ivsize = CTR_RFC3686_IV_SIZE,
  2968. .maxauthsize = SHA256_DIGEST_SIZE,
  2969. },
  2970. .caam = {
  2971. .class1_alg_type = OP_ALG_ALGSEL_AES |
  2972. OP_ALG_AAI_CTR_MOD128,
  2973. .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
  2974. OP_ALG_AAI_HMAC_PRECOMP,
  2975. .rfc3686 = true,
  2976. .geniv = true,
  2977. },
  2978. },
  2979. {
  2980. .aead = {
  2981. .base = {
  2982. .cra_name = "authenc(hmac(sha384),"
  2983. "rfc3686(ctr(aes)))",
  2984. .cra_driver_name = "authenc-hmac-sha384-"
  2985. "rfc3686-ctr-aes-caam",
  2986. .cra_blocksize = 1,
  2987. },
  2988. .setkey = aead_setkey,
  2989. .setauthsize = aead_setauthsize,
  2990. .encrypt = aead_encrypt,
  2991. .decrypt = aead_decrypt,
  2992. .ivsize = CTR_RFC3686_IV_SIZE,
  2993. .maxauthsize = SHA384_DIGEST_SIZE,
  2994. },
  2995. .caam = {
  2996. .class1_alg_type = OP_ALG_ALGSEL_AES |
  2997. OP_ALG_AAI_CTR_MOD128,
  2998. .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
  2999. OP_ALG_AAI_HMAC_PRECOMP,
  3000. .rfc3686 = true,
  3001. },
  3002. },
  3003. {
  3004. .aead = {
  3005. .base = {
  3006. .cra_name = "seqiv(authenc(hmac(sha384),"
  3007. "rfc3686(ctr(aes))))",
  3008. .cra_driver_name = "seqiv-authenc-hmac-sha384-"
  3009. "rfc3686-ctr-aes-caam",
  3010. .cra_blocksize = 1,
  3011. },
  3012. .setkey = aead_setkey,
  3013. .setauthsize = aead_setauthsize,
  3014. .encrypt = aead_encrypt,
  3015. .decrypt = aead_decrypt,
  3016. .ivsize = CTR_RFC3686_IV_SIZE,
  3017. .maxauthsize = SHA384_DIGEST_SIZE,
  3018. },
  3019. .caam = {
  3020. .class1_alg_type = OP_ALG_ALGSEL_AES |
  3021. OP_ALG_AAI_CTR_MOD128,
  3022. .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
  3023. OP_ALG_AAI_HMAC_PRECOMP,
  3024. .rfc3686 = true,
  3025. .geniv = true,
  3026. },
  3027. },
  3028. {
  3029. .aead = {
  3030. .base = {
  3031. .cra_name = "authenc(hmac(sha512),"
  3032. "rfc3686(ctr(aes)))",
  3033. .cra_driver_name = "authenc-hmac-sha512-"
  3034. "rfc3686-ctr-aes-caam",
  3035. .cra_blocksize = 1,
  3036. },
  3037. .setkey = aead_setkey,
  3038. .setauthsize = aead_setauthsize,
  3039. .encrypt = aead_encrypt,
  3040. .decrypt = aead_decrypt,
  3041. .ivsize = CTR_RFC3686_IV_SIZE,
  3042. .maxauthsize = SHA512_DIGEST_SIZE,
  3043. },
  3044. .caam = {
  3045. .class1_alg_type = OP_ALG_ALGSEL_AES |
  3046. OP_ALG_AAI_CTR_MOD128,
  3047. .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
  3048. OP_ALG_AAI_HMAC_PRECOMP,
  3049. .rfc3686 = true,
  3050. },
  3051. },
  3052. {
  3053. .aead = {
  3054. .base = {
  3055. .cra_name = "seqiv(authenc(hmac(sha512),"
  3056. "rfc3686(ctr(aes))))",
  3057. .cra_driver_name = "seqiv-authenc-hmac-sha512-"
  3058. "rfc3686-ctr-aes-caam",
  3059. .cra_blocksize = 1,
  3060. },
  3061. .setkey = aead_setkey,
  3062. .setauthsize = aead_setauthsize,
  3063. .encrypt = aead_encrypt,
  3064. .decrypt = aead_decrypt,
  3065. .ivsize = CTR_RFC3686_IV_SIZE,
  3066. .maxauthsize = SHA512_DIGEST_SIZE,
  3067. },
  3068. .caam = {
  3069. .class1_alg_type = OP_ALG_ALGSEL_AES |
  3070. OP_ALG_AAI_CTR_MOD128,
  3071. .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
  3072. OP_ALG_AAI_HMAC_PRECOMP,
  3073. .rfc3686 = true,
  3074. .geniv = true,
  3075. },
  3076. },
  3077. };
  3078. struct caam_crypto_alg {
  3079. struct crypto_alg crypto_alg;
  3080. struct list_head entry;
  3081. struct caam_alg_entry caam;
  3082. };
  3083. static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam)
  3084. {
  3085. ctx->jrdev = caam_jr_alloc();
  3086. if (IS_ERR(ctx->jrdev)) {
  3087. pr_err("Job Ring Device allocation for transform failed\n");
  3088. return PTR_ERR(ctx->jrdev);
  3089. }
  3090. /* copy descriptor header template value */
  3091. ctx->cdata.algtype = OP_TYPE_CLASS1_ALG | caam->class1_alg_type;
  3092. ctx->adata.algtype = OP_TYPE_CLASS2_ALG | caam->class2_alg_type;
  3093. return 0;
  3094. }
  3095. static int caam_cra_init(struct crypto_tfm *tfm)
  3096. {
  3097. struct crypto_alg *alg = tfm->__crt_alg;
  3098. struct caam_crypto_alg *caam_alg =
  3099. container_of(alg, struct caam_crypto_alg, crypto_alg);
  3100. struct caam_ctx *ctx = crypto_tfm_ctx(tfm);
  3101. return caam_init_common(ctx, &caam_alg->caam);
  3102. }
  3103. static int caam_aead_init(struct crypto_aead *tfm)
  3104. {
  3105. struct aead_alg *alg = crypto_aead_alg(tfm);
  3106. struct caam_aead_alg *caam_alg =
  3107. container_of(alg, struct caam_aead_alg, aead);
  3108. struct caam_ctx *ctx = crypto_aead_ctx(tfm);
  3109. return caam_init_common(ctx, &caam_alg->caam);
  3110. }
  3111. static void caam_exit_common(struct caam_ctx *ctx)
  3112. {
  3113. if (ctx->sh_desc_enc_dma &&
  3114. !dma_mapping_error(ctx->jrdev, ctx->sh_desc_enc_dma))
  3115. dma_unmap_single(ctx->jrdev, ctx->sh_desc_enc_dma,
  3116. desc_bytes(ctx->sh_desc_enc), DMA_TO_DEVICE);
  3117. if (ctx->sh_desc_dec_dma &&
  3118. !dma_mapping_error(ctx->jrdev, ctx->sh_desc_dec_dma))
  3119. dma_unmap_single(ctx->jrdev, ctx->sh_desc_dec_dma,
  3120. desc_bytes(ctx->sh_desc_dec), DMA_TO_DEVICE);
  3121. if (ctx->sh_desc_givenc_dma &&
  3122. !dma_mapping_error(ctx->jrdev, ctx->sh_desc_givenc_dma))
  3123. dma_unmap_single(ctx->jrdev, ctx->sh_desc_givenc_dma,
  3124. desc_bytes(ctx->sh_desc_givenc),
  3125. DMA_TO_DEVICE);
  3126. if (ctx->key_dma &&
  3127. !dma_mapping_error(ctx->jrdev, ctx->key_dma))
  3128. dma_unmap_single(ctx->jrdev, ctx->key_dma,
  3129. ctx->cdata.keylen + ctx->adata.keylen_pad,
  3130. DMA_TO_DEVICE);
  3131. caam_jr_free(ctx->jrdev);
  3132. }
  3133. static void caam_cra_exit(struct crypto_tfm *tfm)
  3134. {
  3135. caam_exit_common(crypto_tfm_ctx(tfm));
  3136. }
  3137. static void caam_aead_exit(struct crypto_aead *tfm)
  3138. {
  3139. caam_exit_common(crypto_aead_ctx(tfm));
  3140. }
  3141. static void __exit caam_algapi_exit(void)
  3142. {
  3143. struct caam_crypto_alg *t_alg, *n;
  3144. int i;
  3145. for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) {
  3146. struct caam_aead_alg *t_alg = driver_aeads + i;
  3147. if (t_alg->registered)
  3148. crypto_unregister_aead(&t_alg->aead);
  3149. }
  3150. if (!alg_list.next)
  3151. return;
  3152. list_for_each_entry_safe(t_alg, n, &alg_list, entry) {
  3153. crypto_unregister_alg(&t_alg->crypto_alg);
  3154. list_del(&t_alg->entry);
  3155. kfree(t_alg);
  3156. }
  3157. }
  3158. static struct caam_crypto_alg *caam_alg_alloc(struct caam_alg_template
  3159. *template)
  3160. {
  3161. struct caam_crypto_alg *t_alg;
  3162. struct crypto_alg *alg;
  3163. t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL);
  3164. if (!t_alg) {
  3165. pr_err("failed to allocate t_alg\n");
  3166. return ERR_PTR(-ENOMEM);
  3167. }
  3168. alg = &t_alg->crypto_alg;
  3169. snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", template->name);
  3170. snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
  3171. template->driver_name);
  3172. alg->cra_module = THIS_MODULE;
  3173. alg->cra_init = caam_cra_init;
  3174. alg->cra_exit = caam_cra_exit;
  3175. alg->cra_priority = CAAM_CRA_PRIORITY;
  3176. alg->cra_blocksize = template->blocksize;
  3177. alg->cra_alignmask = 0;
  3178. alg->cra_ctxsize = sizeof(struct caam_ctx);
  3179. alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY |
  3180. template->type;
  3181. switch (template->type) {
  3182. case CRYPTO_ALG_TYPE_GIVCIPHER:
  3183. alg->cra_type = &crypto_givcipher_type;
  3184. alg->cra_ablkcipher = template->template_ablkcipher;
  3185. break;
  3186. case CRYPTO_ALG_TYPE_ABLKCIPHER:
  3187. alg->cra_type = &crypto_ablkcipher_type;
  3188. alg->cra_ablkcipher = template->template_ablkcipher;
  3189. break;
  3190. }
  3191. t_alg->caam.class1_alg_type = template->class1_alg_type;
  3192. t_alg->caam.class2_alg_type = template->class2_alg_type;
  3193. return t_alg;
  3194. }
  3195. static void caam_aead_alg_init(struct caam_aead_alg *t_alg)
  3196. {
  3197. struct aead_alg *alg = &t_alg->aead;
  3198. alg->base.cra_module = THIS_MODULE;
  3199. alg->base.cra_priority = CAAM_CRA_PRIORITY;
  3200. alg->base.cra_ctxsize = sizeof(struct caam_ctx);
  3201. alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY;
  3202. alg->init = caam_aead_init;
  3203. alg->exit = caam_aead_exit;
  3204. }
  3205. static int __init caam_algapi_init(void)
  3206. {
  3207. struct device_node *dev_node;
  3208. struct platform_device *pdev;
  3209. struct device *ctrldev;
  3210. struct caam_drv_private *priv;
  3211. int i = 0, err = 0;
  3212. u32 cha_vid, cha_inst, des_inst, aes_inst, md_inst;
  3213. unsigned int md_limit = SHA512_DIGEST_SIZE;
  3214. bool registered = false;
  3215. dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
  3216. if (!dev_node) {
  3217. dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
  3218. if (!dev_node)
  3219. return -ENODEV;
  3220. }
  3221. pdev = of_find_device_by_node(dev_node);
  3222. if (!pdev) {
  3223. of_node_put(dev_node);
  3224. return -ENODEV;
  3225. }
  3226. ctrldev = &pdev->dev;
  3227. priv = dev_get_drvdata(ctrldev);
  3228. of_node_put(dev_node);
  3229. /*
  3230. * If priv is NULL, it's probably because the caam driver wasn't
  3231. * properly initialized (e.g. RNG4 init failed). Thus, bail out here.
  3232. */
  3233. if (!priv)
  3234. return -ENODEV;
  3235. INIT_LIST_HEAD(&alg_list);
  3236. /*
  3237. * Register crypto algorithms the device supports.
  3238. * First, detect presence and attributes of DES, AES, and MD blocks.
  3239. */
  3240. cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
  3241. cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
  3242. des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >> CHA_ID_LS_DES_SHIFT;
  3243. aes_inst = (cha_inst & CHA_ID_LS_AES_MASK) >> CHA_ID_LS_AES_SHIFT;
  3244. md_inst = (cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
  3245. /* If MD is present, limit digest size based on LP256 */
  3246. if (md_inst && ((cha_vid & CHA_ID_LS_MD_MASK) == CHA_ID_LS_MD_LP256))
  3247. md_limit = SHA256_DIGEST_SIZE;
  3248. for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
  3249. struct caam_crypto_alg *t_alg;
  3250. struct caam_alg_template *alg = driver_algs + i;
  3251. u32 alg_sel = alg->class1_alg_type & OP_ALG_ALGSEL_MASK;
  3252. /* Skip DES algorithms if not supported by device */
  3253. if (!des_inst &&
  3254. ((alg_sel == OP_ALG_ALGSEL_3DES) ||
  3255. (alg_sel == OP_ALG_ALGSEL_DES)))
  3256. continue;
  3257. /* Skip AES algorithms if not supported by device */
  3258. if (!aes_inst && (alg_sel == OP_ALG_ALGSEL_AES))
  3259. continue;
  3260. /*
  3261. * Check support for AES modes not available
  3262. * on LP devices.
  3263. */
  3264. if ((cha_vid & CHA_ID_LS_AES_MASK) == CHA_ID_LS_AES_LP)
  3265. if ((alg->class1_alg_type & OP_ALG_AAI_MASK) ==
  3266. OP_ALG_AAI_XTS)
  3267. continue;
  3268. t_alg = caam_alg_alloc(alg);
  3269. if (IS_ERR(t_alg)) {
  3270. err = PTR_ERR(t_alg);
  3271. pr_warn("%s alg allocation failed\n", alg->driver_name);
  3272. continue;
  3273. }
  3274. err = crypto_register_alg(&t_alg->crypto_alg);
  3275. if (err) {
  3276. pr_warn("%s alg registration failed\n",
  3277. t_alg->crypto_alg.cra_driver_name);
  3278. kfree(t_alg);
  3279. continue;
  3280. }
  3281. list_add_tail(&t_alg->entry, &alg_list);
  3282. registered = true;
  3283. }
  3284. for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) {
  3285. struct caam_aead_alg *t_alg = driver_aeads + i;
  3286. u32 c1_alg_sel = t_alg->caam.class1_alg_type &
  3287. OP_ALG_ALGSEL_MASK;
  3288. u32 c2_alg_sel = t_alg->caam.class2_alg_type &
  3289. OP_ALG_ALGSEL_MASK;
  3290. u32 alg_aai = t_alg->caam.class1_alg_type & OP_ALG_AAI_MASK;
  3291. /* Skip DES algorithms if not supported by device */
  3292. if (!des_inst &&
  3293. ((c1_alg_sel == OP_ALG_ALGSEL_3DES) ||
  3294. (c1_alg_sel == OP_ALG_ALGSEL_DES)))
  3295. continue;
  3296. /* Skip AES algorithms if not supported by device */
  3297. if (!aes_inst && (c1_alg_sel == OP_ALG_ALGSEL_AES))
  3298. continue;
  3299. /*
  3300. * Check support for AES algorithms not available
  3301. * on LP devices.
  3302. */
  3303. if ((cha_vid & CHA_ID_LS_AES_MASK) == CHA_ID_LS_AES_LP)
  3304. if (alg_aai == OP_ALG_AAI_GCM)
  3305. continue;
  3306. /*
  3307. * Skip algorithms requiring message digests
  3308. * if MD or MD size is not supported by device.
  3309. */
  3310. if (c2_alg_sel &&
  3311. (!md_inst || (t_alg->aead.maxauthsize > md_limit)))
  3312. continue;
  3313. caam_aead_alg_init(t_alg);
  3314. err = crypto_register_aead(&t_alg->aead);
  3315. if (err) {
  3316. pr_warn("%s alg registration failed\n",
  3317. t_alg->aead.base.cra_driver_name);
  3318. continue;
  3319. }
  3320. t_alg->registered = true;
  3321. registered = true;
  3322. }
  3323. if (registered)
  3324. pr_info("caam algorithms registered in /proc/crypto\n");
  3325. return err;
  3326. }
  3327. module_init(caam_algapi_init);
  3328. module_exit(caam_algapi_exit);
  3329. MODULE_LICENSE("GPL");
  3330. MODULE_DESCRIPTION("FSL CAAM support for crypto API");
  3331. MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");