clk-uniphier-core.c 5.7 KB

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  1. /*
  2. * Copyright (C) 2016 Socionext Inc.
  3. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/clk-provider.h>
  16. #include <linux/init.h>
  17. #include <linux/mfd/syscon.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include <linux/platform_device.h>
  21. #include "clk-uniphier.h"
  22. static struct clk_hw *uniphier_clk_register(struct device *dev,
  23. struct regmap *regmap,
  24. const struct uniphier_clk_data *data)
  25. {
  26. switch (data->type) {
  27. case UNIPHIER_CLK_TYPE_CPUGEAR:
  28. return uniphier_clk_register_cpugear(dev, regmap, data->name,
  29. &data->data.cpugear);
  30. case UNIPHIER_CLK_TYPE_FIXED_FACTOR:
  31. return uniphier_clk_register_fixed_factor(dev, data->name,
  32. &data->data.factor);
  33. case UNIPHIER_CLK_TYPE_FIXED_RATE:
  34. return uniphier_clk_register_fixed_rate(dev, data->name,
  35. &data->data.rate);
  36. case UNIPHIER_CLK_TYPE_GATE:
  37. return uniphier_clk_register_gate(dev, regmap, data->name,
  38. &data->data.gate);
  39. case UNIPHIER_CLK_TYPE_MUX:
  40. return uniphier_clk_register_mux(dev, regmap, data->name,
  41. &data->data.mux);
  42. default:
  43. dev_err(dev, "unsupported clock type\n");
  44. return ERR_PTR(-EINVAL);
  45. }
  46. }
  47. static int uniphier_clk_probe(struct platform_device *pdev)
  48. {
  49. struct device *dev = &pdev->dev;
  50. struct clk_hw_onecell_data *hw_data;
  51. const struct uniphier_clk_data *p, *data;
  52. struct regmap *regmap;
  53. struct device_node *parent;
  54. int clk_num = 0;
  55. data = of_device_get_match_data(dev);
  56. if (WARN_ON(!data))
  57. return -EINVAL;
  58. parent = of_get_parent(dev->of_node); /* parent should be syscon node */
  59. regmap = syscon_node_to_regmap(parent);
  60. of_node_put(parent);
  61. if (IS_ERR(regmap)) {
  62. dev_err(dev, "failed to get regmap (error %ld)\n",
  63. PTR_ERR(regmap));
  64. return PTR_ERR(regmap);
  65. }
  66. for (p = data; p->name; p++)
  67. clk_num = max(clk_num, p->idx + 1);
  68. hw_data = devm_kzalloc(dev,
  69. sizeof(*hw_data) + clk_num * sizeof(struct clk_hw *),
  70. GFP_KERNEL);
  71. if (!hw_data)
  72. return -ENOMEM;
  73. hw_data->num = clk_num;
  74. /* avoid returning NULL for unused idx */
  75. while (--clk_num >= 0)
  76. hw_data->hws[clk_num] = ERR_PTR(-EINVAL);
  77. for (p = data; p->name; p++) {
  78. struct clk_hw *hw;
  79. dev_dbg(dev, "register %s (index=%d)\n", p->name, p->idx);
  80. hw = uniphier_clk_register(dev, regmap, p);
  81. if (IS_ERR(hw)) {
  82. dev_err(dev, "failed to register %s (error %ld)\n",
  83. p->name, PTR_ERR(hw));
  84. return PTR_ERR(hw);
  85. }
  86. if (p->idx >= 0)
  87. hw_data->hws[p->idx] = hw;
  88. }
  89. return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
  90. hw_data);
  91. }
  92. static int uniphier_clk_remove(struct platform_device *pdev)
  93. {
  94. of_clk_del_provider(pdev->dev.of_node);
  95. return 0;
  96. }
  97. static const struct of_device_id uniphier_clk_match[] = {
  98. /* System clock */
  99. {
  100. .compatible = "socionext,uniphier-sld3-clock",
  101. .data = uniphier_sld3_sys_clk_data,
  102. },
  103. {
  104. .compatible = "socionext,uniphier-ld4-clock",
  105. .data = uniphier_ld4_sys_clk_data,
  106. },
  107. {
  108. .compatible = "socionext,uniphier-pro4-clock",
  109. .data = uniphier_pro4_sys_clk_data,
  110. },
  111. {
  112. .compatible = "socionext,uniphier-sld8-clock",
  113. .data = uniphier_sld8_sys_clk_data,
  114. },
  115. {
  116. .compatible = "socionext,uniphier-pro5-clock",
  117. .data = uniphier_pro5_sys_clk_data,
  118. },
  119. {
  120. .compatible = "socionext,uniphier-pxs2-clock",
  121. .data = uniphier_pxs2_sys_clk_data,
  122. },
  123. {
  124. .compatible = "socionext,uniphier-ld11-clock",
  125. .data = uniphier_ld11_sys_clk_data,
  126. },
  127. {
  128. .compatible = "socionext,uniphier-ld20-clock",
  129. .data = uniphier_ld20_sys_clk_data,
  130. },
  131. /* Media I/O clock, SD clock */
  132. {
  133. .compatible = "socionext,uniphier-sld3-mio-clock",
  134. .data = uniphier_sld3_mio_clk_data,
  135. },
  136. {
  137. .compatible = "socionext,uniphier-ld4-mio-clock",
  138. .data = uniphier_sld3_mio_clk_data,
  139. },
  140. {
  141. .compatible = "socionext,uniphier-pro4-mio-clock",
  142. .data = uniphier_sld3_mio_clk_data,
  143. },
  144. {
  145. .compatible = "socionext,uniphier-sld8-mio-clock",
  146. .data = uniphier_sld3_mio_clk_data,
  147. },
  148. {
  149. .compatible = "socionext,uniphier-pro5-sd-clock",
  150. .data = uniphier_pro5_sd_clk_data,
  151. },
  152. {
  153. .compatible = "socionext,uniphier-pxs2-sd-clock",
  154. .data = uniphier_pro5_sd_clk_data,
  155. },
  156. {
  157. .compatible = "socionext,uniphier-ld11-mio-clock",
  158. .data = uniphier_sld3_mio_clk_data,
  159. },
  160. {
  161. .compatible = "socionext,uniphier-ld20-sd-clock",
  162. .data = uniphier_pro5_sd_clk_data,
  163. },
  164. /* Peripheral clock */
  165. {
  166. .compatible = "socionext,uniphier-ld4-peri-clock",
  167. .data = uniphier_ld4_peri_clk_data,
  168. },
  169. {
  170. .compatible = "socionext,uniphier-pro4-peri-clock",
  171. .data = uniphier_pro4_peri_clk_data,
  172. },
  173. {
  174. .compatible = "socionext,uniphier-sld8-peri-clock",
  175. .data = uniphier_ld4_peri_clk_data,
  176. },
  177. {
  178. .compatible = "socionext,uniphier-pro5-peri-clock",
  179. .data = uniphier_pro4_peri_clk_data,
  180. },
  181. {
  182. .compatible = "socionext,uniphier-pxs2-peri-clock",
  183. .data = uniphier_pro4_peri_clk_data,
  184. },
  185. {
  186. .compatible = "socionext,uniphier-ld11-peri-clock",
  187. .data = uniphier_pro4_peri_clk_data,
  188. },
  189. {
  190. .compatible = "socionext,uniphier-ld20-peri-clock",
  191. .data = uniphier_pro4_peri_clk_data,
  192. },
  193. { /* sentinel */ }
  194. };
  195. static struct platform_driver uniphier_clk_driver = {
  196. .probe = uniphier_clk_probe,
  197. .remove = uniphier_clk_remove,
  198. .driver = {
  199. .name = "uniphier-clk",
  200. .of_match_table = uniphier_clk_match,
  201. },
  202. };
  203. builtin_platform_driver(uniphier_clk_driver);