tpm_crb.c 11 KB

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  1. /*
  2. * Copyright (C) 2014 Intel Corporation
  3. *
  4. * Authors:
  5. * Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
  6. *
  7. * Maintained by: <tpmdd-devel@lists.sourceforge.net>
  8. *
  9. * This device driver implements the TPM interface as defined in
  10. * the TCG CRB 2.0 TPM specification.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License
  14. * as published by the Free Software Foundation; version 2
  15. * of the License.
  16. */
  17. #include <linux/acpi.h>
  18. #include <linux/highmem.h>
  19. #include <linux/rculist.h>
  20. #include <linux/module.h>
  21. #include <linux/pm_runtime.h>
  22. #include "tpm.h"
  23. #define ACPI_SIG_TPM2 "TPM2"
  24. static const u8 CRB_ACPI_START_UUID[] = {
  25. /* 0000 */ 0xAB, 0x6C, 0xBF, 0x6B, 0x63, 0x54, 0x14, 0x47,
  26. /* 0008 */ 0xB7, 0xCD, 0xF0, 0x20, 0x3C, 0x03, 0x68, 0xD4
  27. };
  28. enum crb_defaults {
  29. CRB_ACPI_START_REVISION_ID = 1,
  30. CRB_ACPI_START_INDEX = 1,
  31. };
  32. enum crb_ctrl_req {
  33. CRB_CTRL_REQ_CMD_READY = BIT(0),
  34. CRB_CTRL_REQ_GO_IDLE = BIT(1),
  35. };
  36. enum crb_ctrl_sts {
  37. CRB_CTRL_STS_ERROR = BIT(0),
  38. CRB_CTRL_STS_TPM_IDLE = BIT(1),
  39. };
  40. enum crb_start {
  41. CRB_START_INVOKE = BIT(0),
  42. };
  43. enum crb_cancel {
  44. CRB_CANCEL_INVOKE = BIT(0),
  45. };
  46. struct crb_control_area {
  47. u32 req;
  48. u32 sts;
  49. u32 cancel;
  50. u32 start;
  51. u32 int_enable;
  52. u32 int_sts;
  53. u32 cmd_size;
  54. u32 cmd_pa_low;
  55. u32 cmd_pa_high;
  56. u32 rsp_size;
  57. u64 rsp_pa;
  58. } __packed;
  59. enum crb_status {
  60. CRB_DRV_STS_COMPLETE = BIT(0),
  61. };
  62. enum crb_flags {
  63. CRB_FL_ACPI_START = BIT(0),
  64. CRB_FL_CRB_START = BIT(1),
  65. };
  66. struct crb_priv {
  67. unsigned int flags;
  68. void __iomem *iobase;
  69. struct crb_control_area __iomem *cca;
  70. u8 __iomem *cmd;
  71. u8 __iomem *rsp;
  72. u32 cmd_size;
  73. };
  74. /**
  75. * crb_go_idle - request tpm crb device to go the idle state
  76. *
  77. * @dev: crb device
  78. * @priv: crb private data
  79. *
  80. * Write CRB_CTRL_REQ_GO_IDLE to TPM_CRB_CTRL_REQ
  81. * The device should respond within TIMEOUT_C by clearing the bit.
  82. * Anyhow, we do not wait here as a consequent CMD_READY request
  83. * will be handled correctly even if idle was not completed.
  84. *
  85. * The function does nothing for devices with ACPI-start method.
  86. *
  87. * Return: 0 always
  88. */
  89. static int __maybe_unused crb_go_idle(struct device *dev, struct crb_priv *priv)
  90. {
  91. if (priv->flags & CRB_FL_ACPI_START)
  92. return 0;
  93. iowrite32(CRB_CTRL_REQ_GO_IDLE, &priv->cca->req);
  94. /* we don't really care when this settles */
  95. return 0;
  96. }
  97. /**
  98. * crb_cmd_ready - request tpm crb device to enter ready state
  99. *
  100. * @dev: crb device
  101. * @priv: crb private data
  102. *
  103. * Write CRB_CTRL_REQ_CMD_READY to TPM_CRB_CTRL_REQ
  104. * and poll till the device acknowledge it by clearing the bit.
  105. * The device should respond within TIMEOUT_C.
  106. *
  107. * The function does nothing for devices with ACPI-start method
  108. *
  109. * Return: 0 on success -ETIME on timeout;
  110. */
  111. static int __maybe_unused crb_cmd_ready(struct device *dev,
  112. struct crb_priv *priv)
  113. {
  114. ktime_t stop, start;
  115. if (priv->flags & CRB_FL_ACPI_START)
  116. return 0;
  117. iowrite32(CRB_CTRL_REQ_CMD_READY, &priv->cca->req);
  118. start = ktime_get();
  119. stop = ktime_add(start, ms_to_ktime(TPM2_TIMEOUT_C));
  120. do {
  121. if (!(ioread32(&priv->cca->req) & CRB_CTRL_REQ_CMD_READY))
  122. return 0;
  123. usleep_range(50, 100);
  124. } while (ktime_before(ktime_get(), stop));
  125. if (ioread32(&priv->cca->req) & CRB_CTRL_REQ_CMD_READY) {
  126. dev_warn(dev, "cmdReady timed out\n");
  127. return -ETIME;
  128. }
  129. return 0;
  130. }
  131. static u8 crb_status(struct tpm_chip *chip)
  132. {
  133. struct crb_priv *priv = dev_get_drvdata(&chip->dev);
  134. u8 sts = 0;
  135. if ((ioread32(&priv->cca->start) & CRB_START_INVOKE) !=
  136. CRB_START_INVOKE)
  137. sts |= CRB_DRV_STS_COMPLETE;
  138. return sts;
  139. }
  140. static int crb_recv(struct tpm_chip *chip, u8 *buf, size_t count)
  141. {
  142. struct crb_priv *priv = dev_get_drvdata(&chip->dev);
  143. unsigned int expected;
  144. /* sanity check */
  145. if (count < 6)
  146. return -EIO;
  147. if (ioread32(&priv->cca->sts) & CRB_CTRL_STS_ERROR)
  148. return -EIO;
  149. memcpy_fromio(buf, priv->rsp, 6);
  150. expected = be32_to_cpup((__be32 *) &buf[2]);
  151. if (expected > count)
  152. return -EIO;
  153. memcpy_fromio(&buf[6], &priv->rsp[6], expected - 6);
  154. return expected;
  155. }
  156. static int crb_do_acpi_start(struct tpm_chip *chip)
  157. {
  158. union acpi_object *obj;
  159. int rc;
  160. obj = acpi_evaluate_dsm(chip->acpi_dev_handle,
  161. CRB_ACPI_START_UUID,
  162. CRB_ACPI_START_REVISION_ID,
  163. CRB_ACPI_START_INDEX,
  164. NULL);
  165. if (!obj)
  166. return -ENXIO;
  167. rc = obj->integer.value == 0 ? 0 : -ENXIO;
  168. ACPI_FREE(obj);
  169. return rc;
  170. }
  171. static int crb_send(struct tpm_chip *chip, u8 *buf, size_t len)
  172. {
  173. struct crb_priv *priv = dev_get_drvdata(&chip->dev);
  174. int rc = 0;
  175. /* Zero the cancel register so that the next command will not get
  176. * canceled.
  177. */
  178. iowrite32(0, &priv->cca->cancel);
  179. if (len > priv->cmd_size) {
  180. dev_err(&chip->dev, "invalid command count value %zd %d\n",
  181. len, priv->cmd_size);
  182. return -E2BIG;
  183. }
  184. memcpy_toio(priv->cmd, buf, len);
  185. /* Make sure that cmd is populated before issuing start. */
  186. wmb();
  187. if (priv->flags & CRB_FL_CRB_START)
  188. iowrite32(CRB_START_INVOKE, &priv->cca->start);
  189. if (priv->flags & CRB_FL_ACPI_START)
  190. rc = crb_do_acpi_start(chip);
  191. return rc;
  192. }
  193. static void crb_cancel(struct tpm_chip *chip)
  194. {
  195. struct crb_priv *priv = dev_get_drvdata(&chip->dev);
  196. iowrite32(CRB_CANCEL_INVOKE, &priv->cca->cancel);
  197. if ((priv->flags & CRB_FL_ACPI_START) && crb_do_acpi_start(chip))
  198. dev_err(&chip->dev, "ACPI Start failed\n");
  199. }
  200. static bool crb_req_canceled(struct tpm_chip *chip, u8 status)
  201. {
  202. struct crb_priv *priv = dev_get_drvdata(&chip->dev);
  203. u32 cancel = ioread32(&priv->cca->cancel);
  204. return (cancel & CRB_CANCEL_INVOKE) == CRB_CANCEL_INVOKE;
  205. }
  206. static const struct tpm_class_ops tpm_crb = {
  207. .flags = TPM_OPS_AUTO_STARTUP,
  208. .status = crb_status,
  209. .recv = crb_recv,
  210. .send = crb_send,
  211. .cancel = crb_cancel,
  212. .req_canceled = crb_req_canceled,
  213. .req_complete_mask = CRB_DRV_STS_COMPLETE,
  214. .req_complete_val = CRB_DRV_STS_COMPLETE,
  215. };
  216. static int crb_check_resource(struct acpi_resource *ares, void *data)
  217. {
  218. struct resource *io_res = data;
  219. struct resource res;
  220. if (acpi_dev_resource_memory(ares, &res)) {
  221. *io_res = res;
  222. io_res->name = NULL;
  223. }
  224. return 1;
  225. }
  226. static void __iomem *crb_map_res(struct device *dev, struct crb_priv *priv,
  227. struct resource *io_res, u64 start, u32 size)
  228. {
  229. struct resource new_res = {
  230. .start = start,
  231. .end = start + size - 1,
  232. .flags = IORESOURCE_MEM,
  233. };
  234. /* Detect a 64 bit address on a 32 bit system */
  235. if (start != new_res.start)
  236. return (void __iomem *) ERR_PTR(-EINVAL);
  237. if (!resource_contains(io_res, &new_res))
  238. return devm_ioremap_resource(dev, &new_res);
  239. return priv->iobase + (new_res.start - io_res->start);
  240. }
  241. static int crb_map_io(struct acpi_device *device, struct crb_priv *priv,
  242. struct acpi_table_tpm2 *buf)
  243. {
  244. struct list_head resources;
  245. struct resource io_res;
  246. struct device *dev = &device->dev;
  247. u32 pa_high, pa_low;
  248. u64 cmd_pa;
  249. u32 cmd_size;
  250. u64 rsp_pa;
  251. u32 rsp_size;
  252. int ret;
  253. INIT_LIST_HEAD(&resources);
  254. ret = acpi_dev_get_resources(device, &resources, crb_check_resource,
  255. &io_res);
  256. if (ret < 0)
  257. return ret;
  258. acpi_dev_free_resource_list(&resources);
  259. if (resource_type(&io_res) != IORESOURCE_MEM) {
  260. dev_err(dev, FW_BUG "TPM2 ACPI table does not define a memory resource\n");
  261. return -EINVAL;
  262. }
  263. priv->iobase = devm_ioremap_resource(dev, &io_res);
  264. if (IS_ERR(priv->iobase))
  265. return PTR_ERR(priv->iobase);
  266. priv->cca = crb_map_res(dev, priv, &io_res, buf->control_address,
  267. sizeof(struct crb_control_area));
  268. if (IS_ERR(priv->cca))
  269. return PTR_ERR(priv->cca);
  270. /*
  271. * PTT HW bug w/a: wake up the device to access
  272. * possibly not retained registers.
  273. */
  274. ret = crb_cmd_ready(dev, priv);
  275. if (ret)
  276. return ret;
  277. pa_high = ioread32(&priv->cca->cmd_pa_high);
  278. pa_low = ioread32(&priv->cca->cmd_pa_low);
  279. cmd_pa = ((u64)pa_high << 32) | pa_low;
  280. cmd_size = ioread32(&priv->cca->cmd_size);
  281. dev_dbg(dev, "cmd_hi = %X cmd_low = %X cmd_size %X\n",
  282. pa_high, pa_low, cmd_size);
  283. priv->cmd = crb_map_res(dev, priv, &io_res, cmd_pa, cmd_size);
  284. if (IS_ERR(priv->cmd)) {
  285. ret = PTR_ERR(priv->cmd);
  286. goto out;
  287. }
  288. memcpy_fromio(&rsp_pa, &priv->cca->rsp_pa, 8);
  289. rsp_pa = le64_to_cpu(rsp_pa);
  290. rsp_size = ioread32(&priv->cca->rsp_size);
  291. if (cmd_pa != rsp_pa) {
  292. priv->rsp = crb_map_res(dev, priv, &io_res, rsp_pa, rsp_size);
  293. ret = PTR_ERR_OR_ZERO(priv->rsp);
  294. goto out;
  295. }
  296. /* According to the PTP specification, overlapping command and response
  297. * buffer sizes must be identical.
  298. */
  299. if (cmd_size != rsp_size) {
  300. dev_err(dev, FW_BUG "overlapping command and response buffer sizes are not identical");
  301. ret = -EINVAL;
  302. goto out;
  303. }
  304. priv->cmd_size = cmd_size;
  305. priv->rsp = priv->cmd;
  306. out:
  307. crb_go_idle(dev, priv);
  308. return ret;
  309. }
  310. static int crb_acpi_add(struct acpi_device *device)
  311. {
  312. struct acpi_table_tpm2 *buf;
  313. struct crb_priv *priv;
  314. struct tpm_chip *chip;
  315. struct device *dev = &device->dev;
  316. acpi_status status;
  317. u32 sm;
  318. int rc;
  319. status = acpi_get_table(ACPI_SIG_TPM2, 1,
  320. (struct acpi_table_header **) &buf);
  321. if (ACPI_FAILURE(status) || buf->header.length < sizeof(*buf)) {
  322. dev_err(dev, FW_BUG "failed to get TPM2 ACPI table\n");
  323. return -EINVAL;
  324. }
  325. /* Should the FIFO driver handle this? */
  326. sm = buf->start_method;
  327. if (sm == ACPI_TPM2_MEMORY_MAPPED)
  328. return -ENODEV;
  329. priv = devm_kzalloc(dev, sizeof(struct crb_priv), GFP_KERNEL);
  330. if (!priv)
  331. return -ENOMEM;
  332. /* The reason for the extra quirk is that the PTT in 4th Gen Core CPUs
  333. * report only ACPI start but in practice seems to require both
  334. * ACPI start and CRB start.
  335. */
  336. if (sm == ACPI_TPM2_COMMAND_BUFFER || sm == ACPI_TPM2_MEMORY_MAPPED ||
  337. !strcmp(acpi_device_hid(device), "MSFT0101"))
  338. priv->flags |= CRB_FL_CRB_START;
  339. if (sm == ACPI_TPM2_START_METHOD ||
  340. sm == ACPI_TPM2_COMMAND_BUFFER_WITH_START_METHOD)
  341. priv->flags |= CRB_FL_ACPI_START;
  342. rc = crb_map_io(device, priv, buf);
  343. if (rc)
  344. return rc;
  345. chip = tpmm_chip_alloc(dev, &tpm_crb);
  346. if (IS_ERR(chip))
  347. return PTR_ERR(chip);
  348. dev_set_drvdata(&chip->dev, priv);
  349. chip->acpi_dev_handle = device->handle;
  350. chip->flags = TPM_CHIP_FLAG_TPM2;
  351. rc = crb_cmd_ready(dev, priv);
  352. if (rc)
  353. return rc;
  354. pm_runtime_get_noresume(dev);
  355. pm_runtime_set_active(dev);
  356. pm_runtime_enable(dev);
  357. rc = tpm_chip_register(chip);
  358. if (rc) {
  359. crb_go_idle(dev, priv);
  360. pm_runtime_put_noidle(dev);
  361. pm_runtime_disable(dev);
  362. return rc;
  363. }
  364. pm_runtime_put(dev);
  365. return 0;
  366. }
  367. static int crb_acpi_remove(struct acpi_device *device)
  368. {
  369. struct device *dev = &device->dev;
  370. struct tpm_chip *chip = dev_get_drvdata(dev);
  371. tpm_chip_unregister(chip);
  372. pm_runtime_disable(dev);
  373. return 0;
  374. }
  375. #ifdef CONFIG_PM
  376. static int crb_pm_runtime_suspend(struct device *dev)
  377. {
  378. struct tpm_chip *chip = dev_get_drvdata(dev);
  379. struct crb_priv *priv = dev_get_drvdata(&chip->dev);
  380. return crb_go_idle(dev, priv);
  381. }
  382. static int crb_pm_runtime_resume(struct device *dev)
  383. {
  384. struct tpm_chip *chip = dev_get_drvdata(dev);
  385. struct crb_priv *priv = dev_get_drvdata(&chip->dev);
  386. return crb_cmd_ready(dev, priv);
  387. }
  388. #endif /* CONFIG_PM */
  389. static const struct dev_pm_ops crb_pm = {
  390. SET_SYSTEM_SLEEP_PM_OPS(tpm_pm_suspend, tpm_pm_resume)
  391. SET_RUNTIME_PM_OPS(crb_pm_runtime_suspend, crb_pm_runtime_resume, NULL)
  392. };
  393. static struct acpi_device_id crb_device_ids[] = {
  394. {"MSFT0101", 0},
  395. {"", 0},
  396. };
  397. MODULE_DEVICE_TABLE(acpi, crb_device_ids);
  398. static struct acpi_driver crb_acpi_driver = {
  399. .name = "tpm_crb",
  400. .ids = crb_device_ids,
  401. .ops = {
  402. .add = crb_acpi_add,
  403. .remove = crb_acpi_remove,
  404. },
  405. .drv = {
  406. .pm = &crb_pm,
  407. },
  408. };
  409. module_acpi_driver(crb_acpi_driver);
  410. MODULE_AUTHOR("Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>");
  411. MODULE_DESCRIPTION("TPM2 Driver");
  412. MODULE_VERSION("0.1");
  413. MODULE_LICENSE("GPL");