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arch
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xtensa
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platforms
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xtfpga
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include
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platform
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hardware.h

hardware.h 1.8 KB
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  1. /*
    2. 

  2.  * arch/xtensa/platform/xtavnet/include/platform/hardware.h
    3. 

  3.  *
    4. 

  4.  * This file is subject to the terms and conditions of the GNU General Public
    5. 

  5.  * License.  See the file "COPYING" in the main directory of this archive
    6. 

  6.  * for more details.
    7. 

  7.  *
    8. 

  8.  * Copyright (C) 2006 Tensilica Inc.
    9. 

  9.  */
    10. 

  10. 

  11. /*
    12. 

  12.  * This file contains the hardware configuration of the XTAVNET boards.
    13. 

  13.  */
    14. 

  14. 

  15. #include <asm/types.h>
    16. 

  16. 

  17. #ifndef __XTENSA_XTAVNET_HARDWARE_H
    18. 

  18. #define __XTENSA_XTAVNET_HARDWARE_H
    19. 

  19. 

  20. /* Memory configuration. */
    21. 

  21. 

  22. #define PLATFORM_DEFAULT_MEM_START __XTENSA_UL(CONFIG_DEFAULT_MEM_START)
    23. 

  23. #define PLATFORM_DEFAULT_MEM_SIZE  __XTENSA_UL(CONFIG_DEFAULT_MEM_SIZE)
    24. 

  24. 

  25. /* Interrupt configuration. */
    26. 

  26. 

  27. #define PLATFORM_NR_IRQS	10
    28. 

  28. 

  29. /* Default assignment of LX60 devices to external interrupts. */
    30. 

  30. 

  31. #ifdef CONFIG_XTENSA_MX
    32. 

  32. #define DUART16552_INTNUM	XCHAL_EXTINT3_NUM
    33. 

  33. #define OETH_IRQ		XCHAL_EXTINT4_NUM
    34. 

  34. #else
    35. 

  35. #define DUART16552_INTNUM	XCHAL_EXTINT0_NUM
    36. 

  36. #define OETH_IRQ		XCHAL_EXTINT1_NUM
    37. 

  37. #endif
    38. 

  38. 

  39. /*
    40. 

  40.  *  Device addresses and parameters.
    41. 

  41.  */
    42. 

  42. 

  43. /* UART */
    44. 

  44. #define DUART16552_PADDR	(XCHAL_KIO_PADDR + 0x0D050020)
    45. 

  45. 

  46. /* Misc. */
    47. 

  47. #define XTFPGA_FPGAREGS_VADDR	IOADDR(0x0D020000)
    48. 

  48. /* Clock frequency in Hz (read-only):  */
    49. 

  49. #define XTFPGA_CLKFRQ_VADDR	(XTFPGA_FPGAREGS_VADDR + 0x04)
    50. 

  50. /* Setting of 8 DIP switches:  */
    51. 

  51. #define DIP_SWITCHES_VADDR	(XTFPGA_FPGAREGS_VADDR + 0x0C)
    52. 

  52. /* Software reset (write 0xdead):  */
    53. 

  53. #define XTFPGA_SWRST_VADDR	(XTFPGA_FPGAREGS_VADDR + 0x10)
    54. 

  54. 

  55. /*  OpenCores Ethernet controller:  */
    56. 

  56. 				/* regs + RX/TX descriptors */
    57. 

  57. #define OETH_REGS_PADDR		(XCHAL_KIO_PADDR + 0x0D030000)
    58. 

  58. #define OETH_REGS_SIZE		0x1000
    59. 

  59. #define OETH_SRAMBUFF_PADDR	(XCHAL_KIO_PADDR + 0x0D800000)
    60. 

  60. 

  61. 				/* 5*rx buffs + 5*tx buffs */
    62. 

  62. #define OETH_SRAMBUFF_SIZE	(5 * 0x600 + 5 * 0x600)
    63. 

  63. 

  64. #define C67X00_PADDR		(XCHAL_KIO_PADDR + 0x0D0D0000)
    65. 

  65. #define C67X00_SIZE		0x10
    66. 

  66. #define C67X00_IRQ		5
    67. 

  67. #endif /* __XTENSA_XTAVNET_HARDWARE_H */
    68.