head64.S 3.2 KB

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  1. /*
  2. * Copyright IBM Corp. 1999, 2010
  3. *
  4. * Author(s): Hartmut Penner <hp@de.ibm.com>
  5. * Martin Schwidefsky <schwidefsky@de.ibm.com>
  6. * Rob van der Heij <rvdhei@iae.nl>
  7. * Heiko Carstens <heiko.carstens@de.ibm.com>
  8. *
  9. */
  10. #include <linux/init.h>
  11. #include <linux/linkage.h>
  12. #include <asm/asm-offsets.h>
  13. #include <asm/thread_info.h>
  14. #include <asm/page.h>
  15. __HEAD
  16. ENTRY(startup_continue)
  17. tm __LC_STFLE_FAC_LIST+5,0x80 # LPP available ?
  18. jz 0f
  19. xc __LC_LPP+1(7,0),__LC_LPP+1 # clear lpp and current_pid
  20. mvi __LC_LPP,0x80 # and set LPP_MAGIC
  21. .insn s,0xb2800000,__LC_LPP # load program parameter
  22. 0: larl %r1,sched_clock_base_cc
  23. mvc 0(8,%r1),__LC_LAST_UPDATE_CLOCK
  24. larl %r13,.LPG1 # get base
  25. lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers
  26. lg %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area
  27. # move IPL device to lowcore
  28. lghi %r0,__LC_PASTE
  29. stg %r0,__LC_VDSO_PER_CPU
  30. #
  31. # Setup stack
  32. #
  33. larl %r14,init_task
  34. stg %r14,__LC_CURRENT
  35. larl %r15,init_thread_union
  36. aghi %r15,1<<(PAGE_SHIFT+THREAD_SIZE_ORDER) # init_task_union + THREAD_SIZE
  37. stg %r15,__LC_KERNEL_STACK # set end of kernel stack
  38. aghi %r15,-160
  39. #
  40. # Save ipl parameters, clear bss memory, initialize storage key for kernel pages,
  41. # and create a kernel NSS if the SAVESYS= parm is defined
  42. #
  43. brasl %r14,startup_init
  44. lpswe .Lentry-.LPG1(13) # jump to _stext in primary-space,
  45. # virtual and never return ...
  46. .align 16
  47. .LPG1:
  48. .Lentry:.quad 0x0000000180000000,_stext
  49. .Lctl: .quad 0x04040000 # cr0: AFP registers & secondary space
  50. .quad 0 # cr1: primary space segment table
  51. .quad .Lduct # cr2: dispatchable unit control table
  52. .quad 0 # cr3: instruction authorization
  53. .quad 0 # cr4: instruction authorization
  54. .quad .Lduct # cr5: primary-aste origin
  55. .quad 0 # cr6: I/O interrupts
  56. .quad 0 # cr7: secondary space segment table
  57. .quad 0 # cr8: access registers translation
  58. .quad 0 # cr9: tracing off
  59. .quad 0 # cr10: tracing off
  60. .quad 0 # cr11: tracing off
  61. .quad 0 # cr12: tracing off
  62. .quad 0 # cr13: home space segment table
  63. .quad 0xc0000000 # cr14: machine check handling off
  64. .quad .Llinkage_stack # cr15: linkage stack operations
  65. .Lpcmsk:.quad 0x0000000180000000
  66. .L4malign:.quad 0xffffffffffc00000
  67. .Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8
  68. .Lnop: .long 0x07000700
  69. .Lparmaddr:
  70. .quad PARMAREA
  71. .align 64
  72. .Lduct: .long 0,.Laste,.Laste,0,.Lduald,0,0,0
  73. .long 0,0,0,0,0,0,0,0
  74. .Laste: .quad 0,0xffffffffffffffff,0,0,0,0,0,0
  75. .align 128
  76. .Lduald:.rept 8
  77. .long 0x80000000,0,0,0 # invalid access-list entries
  78. .endr
  79. .Llinkage_stack:
  80. .long 0,0,0x89000000,0,0,0,0x8a000000,0
  81. ENTRY(_ehead)
  82. .org 0x100000 - 0x11000 # head.o ends at 0x11000
  83. #
  84. # startup-code, running in absolute addressing mode
  85. #
  86. ENTRY(_stext)
  87. basr %r13,0 # get base
  88. .LPG3:
  89. # check control registers
  90. stctg %c0,%c15,0(%r15)
  91. oi 6(%r15),0x60 # enable sigp emergency & external call
  92. oi 4(%r15),0x10 # switch on low address proctection
  93. lctlg %c0,%c15,0(%r15)
  94. lam 0,15,.Laregs-.LPG3(%r13) # load acrs needed by uaccess
  95. brasl %r14,start_kernel # go to C code
  96. #
  97. # We returned from start_kernel ?!? PANIK
  98. #
  99. basr %r13,0
  100. lpswe .Ldw-.(%r13) # load disabled wait psw
  101. .align 8
  102. .Ldw: .quad 0x0002000180000000,0x0000000000000000
  103. .Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0