setup.c 9.2 KB

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  1. /*
  2. * OpenRISC setup.c
  3. *
  4. * Linux architectural port borrowing liberally from similar works of
  5. * others. All original copyrights apply as per the original source
  6. * declaration.
  7. *
  8. * Modifications for the OpenRISC architecture:
  9. * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
  10. * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License
  14. * as published by the Free Software Foundation; either version
  15. * 2 of the License, or (at your option) any later version.
  16. *
  17. * This file handles the architecture-dependent parts of initialization
  18. */
  19. #include <linux/errno.h>
  20. #include <linux/sched.h>
  21. #include <linux/kernel.h>
  22. #include <linux/mm.h>
  23. #include <linux/stddef.h>
  24. #include <linux/unistd.h>
  25. #include <linux/ptrace.h>
  26. #include <linux/slab.h>
  27. #include <linux/tty.h>
  28. #include <linux/ioport.h>
  29. #include <linux/delay.h>
  30. #include <linux/console.h>
  31. #include <linux/init.h>
  32. #include <linux/bootmem.h>
  33. #include <linux/seq_file.h>
  34. #include <linux/serial.h>
  35. #include <linux/initrd.h>
  36. #include <linux/of_fdt.h>
  37. #include <linux/of.h>
  38. #include <linux/memblock.h>
  39. #include <linux/device.h>
  40. #include <asm/sections.h>
  41. #include <asm/segment.h>
  42. #include <asm/pgtable.h>
  43. #include <asm/types.h>
  44. #include <asm/setup.h>
  45. #include <asm/io.h>
  46. #include <asm/cpuinfo.h>
  47. #include <asm/delay.h>
  48. #include "vmlinux.h"
  49. static void __init setup_memory(void)
  50. {
  51. unsigned long ram_start_pfn;
  52. unsigned long ram_end_pfn;
  53. phys_addr_t memory_start, memory_end;
  54. struct memblock_region *region;
  55. memory_end = memory_start = 0;
  56. /* Find main memory where is the kernel, we assume its the only one */
  57. for_each_memblock(memory, region) {
  58. memory_start = region->base;
  59. memory_end = region->base + region->size;
  60. printk(KERN_INFO "%s: Memory: 0x%x-0x%x\n", __func__,
  61. memory_start, memory_end);
  62. }
  63. if (!memory_end) {
  64. panic("No memory!");
  65. }
  66. ram_start_pfn = PFN_UP(memory_start);
  67. ram_end_pfn = PFN_DOWN(memblock_end_of_DRAM());
  68. /* setup bootmem globals (we use no_bootmem, but mm still depends on this) */
  69. min_low_pfn = ram_start_pfn;
  70. max_low_pfn = ram_end_pfn;
  71. max_pfn = ram_end_pfn;
  72. /*
  73. * initialize the boot-time allocator (with low memory only).
  74. *
  75. * This makes the memory from the end of the kernel to the end of
  76. * RAM usable.
  77. */
  78. memblock_reserve(__pa(_stext), _end - _stext);
  79. early_init_fdt_reserve_self();
  80. early_init_fdt_scan_reserved_mem();
  81. memblock_dump_all();
  82. }
  83. struct cpuinfo cpuinfo;
  84. static void print_cpuinfo(void)
  85. {
  86. unsigned long upr = mfspr(SPR_UPR);
  87. unsigned long vr = mfspr(SPR_VR);
  88. unsigned int version;
  89. unsigned int revision;
  90. version = (vr & SPR_VR_VER) >> 24;
  91. revision = (vr & SPR_VR_REV);
  92. printk(KERN_INFO "CPU: OpenRISC-%x (revision %d) @%d MHz\n",
  93. version, revision, cpuinfo.clock_frequency / 1000000);
  94. if (!(upr & SPR_UPR_UP)) {
  95. printk(KERN_INFO
  96. "-- no UPR register... unable to detect configuration\n");
  97. return;
  98. }
  99. if (upr & SPR_UPR_DCP)
  100. printk(KERN_INFO
  101. "-- dcache: %4d bytes total, %2d bytes/line, %d way(s)\n",
  102. cpuinfo.dcache_size, cpuinfo.dcache_block_size, 1);
  103. else
  104. printk(KERN_INFO "-- dcache disabled\n");
  105. if (upr & SPR_UPR_ICP)
  106. printk(KERN_INFO
  107. "-- icache: %4d bytes total, %2d bytes/line, %d way(s)\n",
  108. cpuinfo.icache_size, cpuinfo.icache_block_size, 1);
  109. else
  110. printk(KERN_INFO "-- icache disabled\n");
  111. if (upr & SPR_UPR_DMP)
  112. printk(KERN_INFO "-- dmmu: %4d entries, %lu way(s)\n",
  113. 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
  114. 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
  115. if (upr & SPR_UPR_IMP)
  116. printk(KERN_INFO "-- immu: %4d entries, %lu way(s)\n",
  117. 1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
  118. 1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW));
  119. printk(KERN_INFO "-- additional features:\n");
  120. if (upr & SPR_UPR_DUP)
  121. printk(KERN_INFO "-- debug unit\n");
  122. if (upr & SPR_UPR_PCUP)
  123. printk(KERN_INFO "-- performance counters\n");
  124. if (upr & SPR_UPR_PMP)
  125. printk(KERN_INFO "-- power management\n");
  126. if (upr & SPR_UPR_PICP)
  127. printk(KERN_INFO "-- PIC\n");
  128. if (upr & SPR_UPR_TTP)
  129. printk(KERN_INFO "-- timer\n");
  130. if (upr & SPR_UPR_CUP)
  131. printk(KERN_INFO "-- custom unit(s)\n");
  132. }
  133. void __init setup_cpuinfo(void)
  134. {
  135. struct device_node *cpu;
  136. unsigned long iccfgr, dccfgr;
  137. unsigned long cache_set_size, cache_ways;
  138. cpu = of_find_compatible_node(NULL, NULL, "opencores,or1200-rtlsvn481");
  139. if (!cpu)
  140. panic("No compatible CPU found in device tree...\n");
  141. iccfgr = mfspr(SPR_ICCFGR);
  142. cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
  143. cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
  144. cpuinfo.icache_block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
  145. cpuinfo.icache_size =
  146. cache_set_size * cache_ways * cpuinfo.icache_block_size;
  147. dccfgr = mfspr(SPR_DCCFGR);
  148. cache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
  149. cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
  150. cpuinfo.dcache_block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
  151. cpuinfo.dcache_size =
  152. cache_set_size * cache_ways * cpuinfo.dcache_block_size;
  153. if (of_property_read_u32(cpu, "clock-frequency",
  154. &cpuinfo.clock_frequency)) {
  155. printk(KERN_WARNING
  156. "Device tree missing CPU 'clock-frequency' parameter."
  157. "Assuming frequency 25MHZ"
  158. "This is probably not what you want.");
  159. }
  160. of_node_put(cpu);
  161. print_cpuinfo();
  162. }
  163. /**
  164. * or32_early_setup
  165. *
  166. * Handles the pointer to the device tree that this kernel is to use
  167. * for establishing the available platform devices.
  168. *
  169. * Falls back on built-in device tree in case null pointer is passed.
  170. */
  171. void __init or32_early_setup(void *fdt)
  172. {
  173. if (fdt)
  174. pr_info("FDT at %p\n", fdt);
  175. else {
  176. fdt = __dtb_start;
  177. pr_info("Compiled-in FDT at %p\n", fdt);
  178. }
  179. early_init_devtree(fdt);
  180. }
  181. static inline unsigned long extract_value_bits(unsigned long reg,
  182. short bit_nr, short width)
  183. {
  184. return (reg >> bit_nr) & (0 << width);
  185. }
  186. static inline unsigned long extract_value(unsigned long reg, unsigned long mask)
  187. {
  188. while (!(mask & 0x1)) {
  189. reg = reg >> 1;
  190. mask = mask >> 1;
  191. }
  192. return mask & reg;
  193. }
  194. void __init detect_unit_config(unsigned long upr, unsigned long mask,
  195. char *text, void (*func) (void))
  196. {
  197. if (text != NULL)
  198. printk("%s", text);
  199. if (upr & mask) {
  200. if (func != NULL)
  201. func();
  202. else
  203. printk("present\n");
  204. } else
  205. printk("not present\n");
  206. }
  207. /*
  208. * calibrate_delay
  209. *
  210. * Lightweight calibrate_delay implementation that calculates loops_per_jiffy
  211. * from the clock frequency passed in via the device tree
  212. *
  213. */
  214. void calibrate_delay(void)
  215. {
  216. const int *val;
  217. struct device_node *cpu = NULL;
  218. cpu = of_find_compatible_node(NULL, NULL, "opencores,or1200-rtlsvn481");
  219. val = of_get_property(cpu, "clock-frequency", NULL);
  220. if (!val)
  221. panic("no cpu 'clock-frequency' parameter in device tree");
  222. loops_per_jiffy = *val / HZ;
  223. pr_cont("%lu.%02lu BogoMIPS (lpj=%lu)\n",
  224. loops_per_jiffy / (500000 / HZ),
  225. (loops_per_jiffy / (5000 / HZ)) % 100, loops_per_jiffy);
  226. }
  227. void __init setup_arch(char **cmdline_p)
  228. {
  229. unflatten_and_copy_device_tree();
  230. setup_cpuinfo();
  231. /* process 1's initial memory region is the kernel code/data */
  232. init_mm.start_code = (unsigned long)_stext;
  233. init_mm.end_code = (unsigned long)_etext;
  234. init_mm.end_data = (unsigned long)_edata;
  235. init_mm.brk = (unsigned long)_end;
  236. #ifdef CONFIG_BLK_DEV_INITRD
  237. initrd_start = (unsigned long)&__initrd_start;
  238. initrd_end = (unsigned long)&__initrd_end;
  239. if (initrd_start == initrd_end) {
  240. initrd_start = 0;
  241. initrd_end = 0;
  242. }
  243. initrd_below_start_ok = 1;
  244. #endif
  245. /* setup memblock allocator */
  246. setup_memory();
  247. /* paging_init() sets up the MMU and marks all pages as reserved */
  248. paging_init();
  249. #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
  250. if (!conswitchp)
  251. conswitchp = &dummy_con;
  252. #endif
  253. *cmdline_p = boot_command_line;
  254. printk(KERN_INFO "OpenRISC Linux -- http://openrisc.io\n");
  255. }
  256. static int show_cpuinfo(struct seq_file *m, void *v)
  257. {
  258. unsigned long vr;
  259. int version, revision;
  260. vr = mfspr(SPR_VR);
  261. version = (vr & SPR_VR_VER) >> 24;
  262. revision = vr & SPR_VR_REV;
  263. seq_printf(m,
  264. "cpu\t\t: OpenRISC-%x\n"
  265. "revision\t: %d\n"
  266. "frequency\t: %ld\n"
  267. "dcache size\t: %d bytes\n"
  268. "dcache block size\t: %d bytes\n"
  269. "icache size\t: %d bytes\n"
  270. "icache block size\t: %d bytes\n"
  271. "immu\t\t: %d entries, %lu ways\n"
  272. "dmmu\t\t: %d entries, %lu ways\n"
  273. "bogomips\t: %lu.%02lu\n",
  274. version,
  275. revision,
  276. loops_per_jiffy * HZ,
  277. cpuinfo.dcache_size,
  278. cpuinfo.dcache_block_size,
  279. cpuinfo.icache_size,
  280. cpuinfo.icache_block_size,
  281. 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
  282. 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW),
  283. 1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
  284. 1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW),
  285. (loops_per_jiffy * HZ) / 500000,
  286. ((loops_per_jiffy * HZ) / 5000) % 100);
  287. return 0;
  288. }
  289. static void *c_start(struct seq_file *m, loff_t * pos)
  290. {
  291. /* We only have one CPU... */
  292. return *pos < 1 ? (void *)1 : NULL;
  293. }
  294. static void *c_next(struct seq_file *m, void *v, loff_t * pos)
  295. {
  296. ++*pos;
  297. return NULL;
  298. }
  299. static void c_stop(struct seq_file *m, void *v)
  300. {
  301. }
  302. const struct seq_operations cpuinfo_op = {
  303. .start = c_start,
  304. .next = c_next,
  305. .stop = c_stop,
  306. .show = show_cpuinfo,
  307. };